Registration No.

SET A

JECRC UNIVERSITY
IInd In-Sem Examination, 21 April 2020
B.Tech. (ECE), VI-Semester
VLSI DESIGN (BEE034A)
Time: 1:30 Hrs. Max Marks: 50
Instructions:
1. Attempt all the questions.
2. Illustrate your answers with suitable examples and diagrams, wherever
necessary.
3. Write relevant question numbers before writing the answer.

Course Outcomes (COs)

CO1: Able to understand and analyze sequential MOS logic circuits.
CO2: Able to understand and analyze design rules, stick diagrams, and layouts.

Q1. Answer the following questions. (10 × 1 M = 10 Marks)

1) [CO1] The only difference between a combinational circuit and a flip-flop is
that _____________ [ ]
2) [CO1] The flip-flop is only activated by _____________
a) Positive edge trigger b) Negative edge trigger
c) Either positive or Negative edge trigger d) Sinusoidal trigger
3) [CO1] In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state b) Low state
c) Toggle state d) No Change State
4) [CO1] Inverters in latch form a feedback loop which is always [ ]
a) negative b) positive c) infinite d) changing
5) [CO1] A shift register is a cascade of ________ [ ]
a) 1-bit memory b) two latches
c) two NAND gates d) none of these
6) [CO2] Which color is used for metal-1 layer? [ ]
a) red b) green c) light blue d) yellow
7) [CO2] When two or more cuts of same type cross or touch each other, that
represents ________________ [ ]
8) [CO2] Gate area can be given as [ ]
a) L/W b) 2L/W
c) L * W d) Π2(L*W)
9) [CO2] What should be the spacing between two wells at different potentials?
a) 4λ b) 6λ
c) 3λ d) 8λ
10) [CO2] When a poly crosses diffusion it represents a transistor. [True/False]
Q2. Answer the following questions. (4 × 2 M = 8 Marks)
1. [CO1] What is sequential circuit?
2. [CO1] What are the applications of T flip flop?
3. [CO2] What are the commonly used conducting layers in IC fabrication?
4. [CO2] The simplified layout of a logic circuit is shown in figure 1. Draw the
corresponding circuit diagram?

A|

B|
F
A
B
Fig. 1
A

Q3. Answer the following questions. (2 × 6 M = 12 Marks)

1. [CO1] Draw a device level circuit diagram of a depletion-load (n-MOS) latch
circuit and explain its operation.
2. [CO2] Draw a stick diagram for a CMOS circuit implementing function
F  A( B  C )  CD .

Q4. Answer the following questions. (2 × 10 M = 20 Marks)

1. [CO1] Draw a device level circuit diagram of a CMOS SR latch based on

NAND gates and explain its operation.
2. [CO2] Draw the layout for the logic function F  ( A  B  C )( D  E ) . Assume
that the circuit is implemented in a 90 nm technology and also choose
necessary data.

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