SUMMARY OF LECTURE 3(WEEK

4)
Propagation delay is the delay between the input and output. Consider t pr and tpf we can find the average
propagation time which is tp = (tpf + tpr)/2 as tf = Tn * ln (VDD/Vout) and tr = Tp ln (VDD/( VDD - Vout))

Hence we will get,

tpf = ln(2) Tn and tpr = ln(2) Tp

While

tp= = 0.35*(Tp + Tn)

As in earlier lectures we have said that

Cout = CMOS + CL

So, tf = 2.2 Rn * Cout

tf = 2.2 Rn * CMOS + 2.2 Rn * CL

2.2 Rn * CMOS shows that it’s the tf with no load in it.

tr = 2.2 Rp * CMOS + 2.2 Rp * CL

2.2 Rp* CMOS shows that it’s the tf with no load in it.

As,
αn = 2.2 Rn , αp = 2.2 Rp

So,

tf = tf0 + αn * CL

tr = tr0 + αp * CL

Now the power dissipation is

P = VDD * IDD

P= PDc + Pdyn

So we can say that Vin is stable at 0V whereas Nfet is off and Pfet is on, for the ideal condition current
will be zero as there is leakage current represented as I DDQ.
When IDD reaches at its peak then both Pmos and Nmos offers conductivity and Vin increases, hence

PDC = VDD * IDDQ

For finding dynamic power dissipation we consider a signal T having input low (pmos = on and nmos
=off) so ,

Qe = Cout*VDD

So when Vin = VDD then pmos is off while nmos will be on resulting in discharging of voltage of V out to
zero hence

Pdyn = VDD * IDD

Pdyn = VDD * Qe/T

Pdyn = VDD2 *Cout *f

As,

P= PDc + Pdyn

So,

P = VDD * IDDQ + VDD2 *Cout *f

Hence we can conclude that the power is directly proportional to f so fast circuit dissipates more power
than a slow circuit.