ASSIGNMENT # 3

Q1. Explain Junction capacitances by calculating all the capacitances involved for Source
Terminal.

ANS. Semiconductor physics reveals that the pn junction automatically exhibits capacitance
due to involvement of opposite charge polarity. This is called JUNCTION CAPACITANCE and is
found in all drain to source region of FET. It is also said that junction capacitance is the
capacitance which forms in a PN junction diode under reverse bias

Consider body of Nmos is

grounded and applied VS is
zero then there is a pn-
junction at p substrate and
𝑛+region, and a depletion
region is formed for the
junction. In n+ region
majority charge carrier are
electron wile in p region the
majority charge carrier are
holes, as negatively charge
acceptor are also present
hence this region will act
like a parallel plate
capacitor.
Above figure is the normal parallel plate capacitors yielding capacitance:
(C/A)= (esi/td)
Where esi is the permittivity constant of a silicon and td is the distance of separation (btw plates)
while A is the area between source and body.
As five sides are there which is connected to p substrate:
1. Two faces with area (2𝐴𝑓)
2. Two side walls with area (2𝐴𝑠)
3. One bottom area 𝐴𝑏𝑜𝑡
So,
Area of sidewalls (𝐴𝑠) = 2𝑊*𝑡𝑠0
Area of face is (𝐴𝑓) = 2𝑋*𝑡𝑠0
Area of bottom (𝐴𝑏𝑜𝑡) = 𝑊*𝑋

Hence,

Total area of sidewalls is

𝐴𝑠𝑤=𝐴𝑠+𝐴𝑓
𝐴𝑠𝑤=2𝑋*𝑡𝑠0+2𝑊*𝑡𝑠0
𝐴𝑠𝑤=2𝑡𝑠0*𝑊+𝑋

So,

Sidewall capacitance is

𝐶𝑠𝑤=𝜖𝑠𝑖*𝑡𝑑*𝐴𝑠𝑤
𝐶𝑠𝑤=𝜖𝑠𝑖*𝑡𝑑*2𝑡𝑠0 * 𝑊+𝑋

Bottom capacitance (𝐶𝑏𝑜𝑡) = 𝜖𝑠𝑖*𝑡𝑑*𝐴𝑏

As 𝐴𝑏 = W*X

Then,

𝐶𝑏𝑜𝑡=𝜖𝑠𝑖𝑡𝑑*𝑊*𝑋

Then,

Total capacitance is

𝐶𝑆𝐵=𝐶𝑠𝑤+𝐶𝑏𝑜𝑡
𝐶𝑆𝐵=𝜖𝑠𝑖*𝑡𝑑*2𝑡𝑠0*𝑊*𝑋+ 𝜖𝑠𝑖*𝑡𝑑

While overall drain to

capacitance is given by,
𝐶𝑆=𝐶𝐺𝑆+𝐶𝑆𝐵
𝐶𝐷=𝐶𝐺𝐷+𝐶𝐷𝐵
Q. No. 2: Derive expression for 𝐼𝐷𝑆𝑛 considering the channel mode as shown in figure below.
Also explain how channel varies
while moving from one end to
another?

ANS.

As per the diagram given we can say

that VGSn > Vtn , the current is flowing
the drain to source due to electric
field of VDSn as source is having zero
volts and drain is at positive VDSn,
hence it can be written in the form of electric charge density
Qe = - Cox * (VGS – Vtn)
Where Qe is the electric charge density and the eq. (VGS – Vtn) is known as effective voltage
equation hence Qe is effected by VDSn.
Suppose Qe be the function of y that means its non-uniform then
Qe (y) = - Cox * (VGS – Vtn – V(y))
If y = 0 then,
Qe (0) = - Cox * (VGS – Vtn)
Suppose Qe be the function of L which is VDSn then
Qe (L) = - Cox * (VGS – Vtn – VDSn)
For IDn in dR we can say that
dV = IDn * dR
The differential resistance will be,
dR= dy/(σn * An)
Here σn and An are the conductivity and cross sectional area respectively. As for the n type
region the conductivity and cross sectional area is given by,
σn * An = q*un*ne*wxe
dR = dy/(q*un*ne*W*xe)
Where ne is electron density, xe is the thickness of the channel at that point.
Hence the change density is equal to
Qe = -q * ne * xe
Now substituting all that in dV then we get,
dV= IDn * dy/(un*ne*W*Qe)
By putting value of Qe we get,
dV= IDn * dy/(un*ne*W* Cox * (VGS – Vtn – VDSn))
By taking integral of the above equation we get,
IDn = un* Cox*(W/L)*[( VGSn – Vtn)VDSn – (VDSn2/2)]
When VDSn is equal to Vsat hence the channel vanishes near drain leaving Qe is equal to zero as
well as IDn is also zero, this point is called as transition point. So at the transition point the
charge density will be zero.

Q. No. 3: Consider an nFET has a channel width W = 8𝜇𝑚, a channel length L = 0.5𝜇𝑚, and is
made in a process where 𝑘′𝑛=180 𝜇𝐴/𝑉2, 𝑉𝑇𝑛=0.70𝑉 and 𝑉𝐷𝐷=3.3 𝑉. What will be the value
of drain-source resistance? If the MOSFET is shrink to W = 5𝜇𝑚 while keep all other quantities
constant. What will be the value of the resistance now? How you would describe this change?

GIVEN:

 L = 0.5𝜇𝑚
 W = 8𝜇𝑚
 𝑘′𝑛=180 𝜇𝐴/𝑉2
 𝑉𝑇𝑛=0.70𝑉
 𝑉𝐷𝐷=VG=3.3 𝑉
TO FIND:
Resistance Rn =?
SOLUTION:
As we know that Resistance Rn is
Rn =1/ [𝛽n (𝑉𝐺 − |𝑉𝑇n|)]
So let’s find 𝛽n first which is equal to,
𝛽n= 𝑘′𝑛 * (W/L)
Hence by putting values we get,
𝛽n = (180 𝜇𝐴/𝑉2) * (8𝜇𝑚/0.5𝜇𝑚)
𝛽n = 2880
So,
Rn = 1/ [2880 * (3.3 – 0.70)]
Hence,
Rn = 133.5 ohms
As in question it is said that the MOSFET is shrink to W = 5𝜇𝑚 while keeping all other quantities
constant supposing that resistance now is Rn* so,

`
Rn*= Rn * (W/W )

Hence,
Rn*= 133.5 *(8 𝜇𝑚/5 𝜇𝑚)
Rn*= 231.6 ohms
As the Rn is inversely proportional to the channel width 𝑅𝑛∝1/𝛽𝑛 but in this case shrinking the
channel width causes increase in Rn.

Q. No. 4: Explain the phenomenon of channel creation in nMOS with the help of diagrams.

ANS. The Mosfets device passes electric current when the voltage is applied which moves from
drain to source. As drain and source are separated so the flow of charge can occur only when
the conduction path or the channel is created.
As VG is increased then the holes present in the p substrate are repelled from the gate area leaving
negative charges behind hence due to these negative charges a depletion region is created, with
increase in VG the width of depletion region also increases causing increase in the width of oxide layer so
the point of the oxide silicon interface also increases. Hence when that point is large enough then it will
result in the flowing of current through a channel which is created when the potential reaches to a
desired positive value.