DC Biasing of BJTs

Biasing

Biasing: The
T DC voltages applied to
a transistor in order to turn it on so
that it can amplify the AC signal.
 Operating Point

The DC input
establishes an
operating or
quiescent point
called the Q-point.
Q-point
 The Three States of Operation

• Active or Linear Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is reverse biased

• Cutoff Region Operation

Base–Emitter junction is reverse biased

• Saturation Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is forward biased
No matter what type of configuration a transistor
is used in, the basic relationships between the
currents are always the same, and the base-to-
emitter voltage is the threshold value if the
transistor is in the “on” state

VBE = 0.7V
I E = ( β + 1) I B ≅ I C
I C = βI B
• The operating point defines where the
transistor will operate on its characteristics
curves under dc conditions.

• For linear (minimum distortion)

amplification, the dc operating point should
not be too close to the maximum power,
voltage, or current rating and should avoid
the regions of saturation and cutoff
 DC Biasing Circuits

• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Voltage divider bias circuit
• DC bias with voltage feedback
I. Fixed Bias

• The fixed-bias configuration is the

simplest of transistor biasing
arrangements, but it is also quite unstable

•For most configurations the dc analysis

begins with a determination of the base
current

•For the dc analysis of a transistor

network, all capacitors are replaced by an
open-circuit equivalent
Fixed-bias circuit
The dc equivalent circuit of the fixed bias circuit
where the capacitor is replaced with an open-circuit
 The Base-Emitter Loop

From Kirchhoff’s voltage

law:
+VCC – IBRB – VBE = 0

Solving for base current:

VCC − VBE
IB =
RB
 Collector-Emitter Loop

Collector current:
I C = βI B

From Kirchhoff’s voltage law:

VCE + I C RC − VCC = 0

VCE = VCC − I C R C
Example: Determine the following for the fixed-bias
configuration of the figure shown:
(a) IBQ and ICQ (b) VCEQ (c) VB and VC (d) VBC

β = 75
 Saturation
• Saturation conditions are normally avoided because
the base-collector junction is no longer reverse-
biased and the output amplified signal will be
distorted
•For a transistor operating in the saturation region,
the current is a maximum value for the particular
design. Change the design and the corresponding
saturation level may rise or drop

•The highest saturation level is defined by the

maximum collector current as provided by the
specification sheet
Saturation
 VCE 0V
RCE = = = 0Ω
IC I Csat

VCC
I Csat =
RC
 Saturation

When the transistor is operating in saturation, current

through the transistor is at its maximum possible value.

VCC
I Csat =
RC

VCE ≅ 0 V

In the previous example, the saturation level for the network is

given by:
VCC 12V
I Csat = = = 5.45mA
RC 2.2kΩ
 Load Line Analysis

The variables IC and VCE are related by the equation:

VCE = VCC − I C RC
 Load Line Analysis

The end points of the load line are:

ICsat
IC = VCC / RC
VCE = 0 V
VCEcutoff
VCE = VCC
IC = 0 mA

The Q-point is the operating point:

• where the value of RB sets the value of IB
• that sets the values of VCE and IC
Circuit Values Affect the Q-Point

[Movement of the Q-point with increasing level of IB]

 Circuit Values Affect the Q-Point

[Effect of an increasing level of RC on the load line the

Q-point]
Circuit Values Affect the Q-Point

[Effect of lower values of VCC on the load line the Q-

point]
II. Emitter-Stabilized Bias Circuit

Adding a resistor
(RE) to the emitter
circuit stabilizes
the bias circuit.
 Base-Emitter Loop

From Kirchhoff’s voltage law:

+VCC - I B R B - VBE - I E R E = 0

Since IE = (β + 1)IB:
VCC - I B R B - VBE - ( β + 1)I B R E = 0

Solving for IB:

VCC - VBE
IB =
R B + (β + 1)R E
 Collector-Emitter Loop
From Kirchhoff’s voltage law:
I R +V +I R −V =0
E E CE C C CC

Since IE ≅ IC:

VCE = VCC – I C (R C + R E )

Also:

VE = I E R E
VC = VCE + VE = VCC - I C R C
VB = VCC – I R R B = VBE + VE
Example: Determine the following for the emitter bias network
of the figure shown:
(a) IB (b) IC (c) VCE (d) VC (e) VE (f) VB (g) VBC
+16 V

β = 75
 Improved Biased Stability
Stability refers to a circuit condition in which the currents
and voltages will remain fairly constant over a wide range
of temperatures and transistor Beta (β) values
Adding RE to the emitter improves the stability of a transistor
[For Emitter Bias Case]

β IB(µA) IC(mA) VCE(V)

75 30.24 2.27 9.91
100 28.81 3.63 9.11

[For Fixed Bias Case]

β IB(µA) IC(mA) VCE(V)

75 47.08 3.53 4.23
100 47.08 4.71 1.64
Saturation Level

VCC
I Csat =
RC + RE
Load-line Analysis

VCE = VCC − I C ( RC + RE )

The endpoints can be determined from the load line.

VCEcutoff: ICsat:
VCE = VCC VCE = 0 V
I C = 0 mA VCC
IC =
RC + RE
III. Voltage Divider Bias

This is a very stable

bias circuit.

The currents and

voltages are nearly
independent of any
variations in β.
Exact Analysis:
 RTh = R1 || R2 R2VCC
ETh = VR 2 =
R1 + R2

Applying Kirchhoff’s voltage law in the clockwise direction in the

Thevenin network,

ETh − I B RTh − VBE − I E RE = 0

ETh − VBE
IB = (Substituting IE = (β+1)IB)
RTh + ( β + 1) RE

VCE = VCC − I C ( RC + RE )
Approximate Analysis:
 Approximate Analysis
Where IB << I1 and I1 ≅ I2 :
R 2 VCC
VB =
R1 + R 2

Where βRE > 10R2:

VE
IE =
RE
VE = VB − VBE

From Kirchhoff’s voltage law:

VCE = VCC − I C R C − I E R E
IE ≅ IC
VCE = V CC −I C (R C + R E )
 Voltage Divider Bias Analysis

Transistor Saturation Level

V CC
I Csat = I Cmax =
RC + RE

Load Line Analysis

Cutoff: Saturation:
VCC
VCE = VCC IC =
RC + RE
I C = 0mA
VCE = 0V
IV. DC Bias with Voltage Feedback

Another way to
improve the stability
of a bias circuit is to
add a feedback path
from collector to
base.

In this bias circuit

the Q-point is only
slightly dependent on
the transistor beta,
β.
 Base-Emitter Loop
From Kirchhoff’s voltage law:
VCC – I ′C R C – I B R B – VBE – I E R E = 0

Where IB << IC:

I' = I + I ≅ I
C C B C

Knowing IC = β IB and IE ≅ IC, the loop

equation becomes:
VCC – β I B R C − I B R B − VBE − β I B R E = 0

Solving for IB:

VCC − VBE
IB =
R B + β(R C + R E )
 Collector-Emitter Loop

Applying Kirchoff’s voltage law:

IERE + VCE + I’ CRC – VCC = 0

Since I′ C ≅ IC and IE ≅ IC:

IC(RC + RE) + VCE – VCC =0

Solving for VCE:

VCE = VCC – IC(RC + RE)

 Base-Emitter Bias Analysis

Transistor Saturation Level

V CC
I Csat = I Cmax =
RC + RE

Load Line Analysis

Cutoff: Saturation:
V
VCE = VCC I = CC
C R +R
I C = 0 mA C E
VCE = 0 V
Bias Stabilization
The s ta bility of a s ys te m is a me a s ure of the
s e ns itivity of a ne twork to va ria tions in its
pa ra me te rs
In a ny a mplifie r e mploying a tra ns is tor the
colle ctor curre nt IC is s e ns itive to e a ch of the
following pa ra me te rs :
• β: incre a s e with incre a s e in te mpe ra ture
• |VBE| : de cre a s e a bout 2.5 mV pe r o C
incre a s e in te mpe ra ture
• ICO (re ve rs e s a tura tion curre nt): double s in
va lue for e ve ry 10 0 incre a s e in te mpe a rture
S hift in dc-bia s point (Q-point) due to cha nge in
te mpe ra ture : (a ) 25 0 C; (b) 100 0 C
A be tte r bia s circuit is one tha t will s ta bilize or
ma inta in the dc-bia s initia lly s e t, s o tha t the a mplifie r
ca n be us e d in a cha nging-te mpe ra ture e nvironme nt

Stability Factors: S(ICO), S(VBE), and S(β )

∆I C ∆I C ∆I C
S ( I CO ) = S (VBE ) = S (β ) =
∆I CO ∆VBE ∆β

Ne tworks tha t a re quite s ta ble a nd re la tive ly ins e ns itive

to te mpe ra ture va ria tions ha ve low s ta bility fa ctors
The highe r the s ta bility fa ctor, the more s e ns itive is the
ne twork to va ria tions in tha t pa ra me te r
S(ICO):
Emitter-Bias Configuration

1 + ( RB / RE )
S ( I CO ) = ( β + 1)
( β + 1) + ( RB / RE )

For RB/RE >> (β+1), S ( I CO ) = ( β + 1)

1
For RB/RE << 1, S ( I CO ) = ( β + 1) =→ 1
( β + 1)

For the range where RB

S ( I CO ) ≅
RB/RE ranges between RE
1 and (β+1),
[Variation of stability factor with the resistor ratio RB/RE for
the emitter-bias configuration]
Fixed-Bias Configuration:
S ( I CO ) = ( β + 1)

Voltage-Divider Bias Configuration:

1 + ( RTh / RE )
S ( I CO ) = ( β + 1)
( β + 1) + ( RTh / RE )

Feedback-Bias Configuration:

1 + ( RB / RC )
S ( I CO ) = ( β + 1)
( β + 1) + ( RB / RC )
S(VBE):
−β
Emitter-bias configuration: S (VBE ) =
RB + ( β + 1) RE

−β
Fixed-Bias Configuration: S (VBE ) =
RB
−β − β / RE
S (VBE ) = ⇒ S (VBE ) =
RB + ( β + 1) RE RB / RE + ( β + 1)

− β / RE − β / RE 1
⇒ S (VBE ) ≅ ≅ =− For (β+1)>>RB/RE
( β + 1) β RE
This shows that the larger the resistance RE, the lower is
the stability factor and the more stable is the system
S(β ):

Emitter-bias configuration:
∆I C I C 1 (1 + RB / RE )
S (β ) = =
∆β β1 (1 + β 2 + RB / RE )
Fixed-Bias Configuration:
I C1
S (β ) =
Voltage-Divider Bias Configuration: β1
I C 1 (1 + RTh / RE )
S (β ) =
β1 (1 + β 2 + RTh / RE )
Feedback-Bias Configuration:
I C 1 ( RB + RC )
S (β ) =
β1 ( RB + RC (1 + β 2 ))
Summary
The total effect on the collector current can be determined using
the following equation:

∆I C = S ( I CO )∆I CO + S (VBE )∆VBE + S ( β )∆β