MS-7144 Ver:00a Atx

5 4 3 2 1
MS-7144 VER:00A ATX Title Page

Cover Sheet 1
*AMD PGA 754 K8-Processor (DDR 400) Block Diagram 2
D D
*VIA K8M800 /K8T800 Pro GPIO SPEC 3

*VIA VT8237 (AGP 8X / VLink 8X) AMD K8 -> 754 PGA Socket 4,5,6
Clock Synthesizer 7
*Winbond 83627THF LPC I/O
System MemoryDDR DIMM 1 & 2 8
*8201CL 100/10 Bit LAN Support DDR Terminations R & C 9
DDR Damping R & Bypass Cap. 10
*USB 2.0 support (integrated into VT8237)
NB VIA K8T800Pro/K8M800 (HT) 11,12,13
*ALC655 6 channel S/W Audio K8 Vcore Power 14
AGP SLOT 8X 15
C
*DDR DIMM * 2 C
VT8237 16,17,18
*AGP SLOT * 1 ( 8X )
PCI Connectors * 4 19,20
*PCI SLOT * 4
ALCALC655 6 channel S/W Audio 21
WWW.KYTHUATVITINH.COM
IDE ATA 66/100 Connectors * 2 22
Front and Rear USB Port 23

LPC I/O W83627THF& ROM & Floppy&Fan 24
KeyBoard/Mouse/LPT/COM Connectors 25
10/100 LAN & VGA 26
B
Digitally signed by ACPI Power CONTROLLER (MS-6)
System Regulator&Front Panel

27
28
B
Nhat Tin Decoupling Cap. 29

Power Sequence 30
DN: cn=Nhat Tin, o, History 31
ou, OPTION PARTS 32
email=support@kyth
uatvitinh.com, c=VN
Date: 2010.01.08
A A
10:56:24 +07'00' Title

Cover Sheet
MS-7144
0A
Wednesday, November 10, 2004
5 4 3 2 1
5 4 3 2 1
Block Diagram
DDR400
CPUCLK+ & CPUCLK-(100/133/166/200) AMD K8 Socket 754

D D
HCLK+ & HCLK-(100/133/166/200) / GCLK(66)
HT DDR * 2
SYSTEM CLOCK A
G
Synthesizer AGPCLK(66)
P AGP 8X /Fast Write
S
L
O
T
VIA
C C
K8T800/K8T800PRO
VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)
IDE Slot
VLINK ==>ATA66,100,133 *2
Dual ATA 100/133

PCICLK[1~4] PCI-33
4 PCI Slots
B B
VT8237
LPC BUS
AC97
AC97 => S/W Audio
ALC655 / 6 channel
SUPER I/O ROM

W83627THF
USB
MII
LPC
BUS
A A
AC_14(14)
Dual USB 1.1 OHCI

SERIAL ATA *2 10/100 LAN
/2.0 EHCI 8 Ports
RTL8201CL
==> Front-Port *4 , Micro Star Restricted Secret
Back-Port *4 Title
Block Diagram
0A
MS-7144
SIOPCLK(33)/SIO48M(48)
Wednesday, November 10, 2004
2 32
5 4 3 2 1
5 4 3 2 1
GPIO FUNCTION PCI Routing

DEVICES INT# IDSEL REQ#/GNT# CLOCK
VT8237 GPIO Function Define
INT#A PREQ#6
PIN NAME Function define PIN NAME Function define PCI SLOT 1 INT#B AD16 PCICLK1
D
INT#C PGNT#6 D
INT#D
GPO0 (VSUS33) NA GPI0 NA (Exteranl Pull up to VBAT)
INT#B PREQ#3
GPO1/SUSA#(VSUS33) NA GPI1 ATADET0=>Detect IDE1 ATA100/66 PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#3
INT#A
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI#
INT#C PREQ#4
GPO3/SUSST1#(VSUS33) SUSST# GPI3/RING# RING# PCI SLOT 3 INT#D AD18 PCICLK3
INT#A PGNT#4
INT#B
GPO4/SUSCLK(VSUS33) NA (Exteranl Pull up to 3VDUAL) GPI4/LID# ATADET1=>Detect IDE2 ATA100/66
INT#D PREQ#7
GPO5/CPUSTP# NA (Exteranl Pull up to VCC3) GPI5/BATLOW# NA (Exteranl Pull up to 3VDUAL) PCI SLOT 4 INT#A AD19 PCICLK4
INT#B PGNT#7
INT#C
GPO6/PCISTP# NA (Exteranl Pull up to VCC3) GPI6/AGPBZ# POWERF3
INT#B PREQ#8
GPO7/SLP# LDTSTOP# GPI7/REQ#5 NA (Exteranl Pull up to 3VDUAL) PCI SLOT 5 INT#C AD21 PCICLK5
INT#D PGNT#8
INT#A
GPO8/GPI8/IPBIN0 NA GPI16/INTRUDER# NA (Exteranl Pull up to VBAT)
GPO9/GPI9/IPBIN1 NA GPI17/CPUMISS NA (Exteranl Pull up to 3VDUAL)

C C
GPO10/GPI10/IPBRDFR NA GPI18/AOLGP1/THRM# THRM#
GPO11/GPI11/IPBRDCK NA GPI19/IORDY NA (Exteranl Pull up to VCC3) Giga-Bit INT#A AD22 PREQ#1 GLAN_PCLK
PGNT#1
LAN
GPO12/GPI12/INTE# VSET0
S/IO GPIO Function Define
GPO13/GPI13/INTF# VSET1
PIN NAME Function define
GPO14/GPI14/INTG# VSET2
GPBX/GP13 LED#4
GPO15/GPI15/INTH# NA
GPAY/GP15 LED#2
GPO16/SA16/STRAP LDT Freq Strapping Bit0
GPAS1/GP10 LED1
GPO17/SA17/STRAP LDT Freq Strapping Bit1
GPAS2/GP17 LED4
GPO18/SA18/STRAP LDT Width (Low=8 Bit)
GPAX/GP12 LED#3
B
GPO19/SA19/STRAP Fast Command (Low=Disable) B
GPBY/GP14 LED#1
GPO20/GPI20
/ACSDIN2/PCS0#/EI POWERF1
GPBS1/GP11 LED2
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# POWERF2
GPBS2/GP16 LED3
GPO22/GPI22/IOR# NA
GPO23/GPI23/DPSLP ROMLOCK
GPO24/GPI24/GPIOA NA
GPO25/GPI25/GPIOC NA
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/
VIDSEL NA
GPO29/GPI29/
A VRDSLP NA A
GPO30/GPI30/GPIOD NA
Micro Star Restricted Secret
GPO31/GPI31/GPIOE NA Title Rev
GPIO Spec.
0A
Document Number MS-7144
MICRO-STAR INT'L CO.,LTD. Last Revision Date:
No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 32
5 4 3 2 1
5 4 3 2 1
C52 VDD_12_A
VREF routed as 40~50 mils trace wide ,
Space>25 mils C0.22U16Y X_C0.22U16Y
X_C1000P50N C156 C186 C166 C155 C174 C256 C167

U2B VTT_DDR_SUS
C64 C0.22U16Y C0.22U16Y C0.22U16Y
X_C0.22U16Y C0.22U16Y
C1000P50X
8 DDR_VREF
D D
R60 15R1% MEMZN

VDD_25_SUS
R59 15R1% MEMZP
Place near CPU in 1" , VDD_12_A

Routed => 5:10/Trace:Space , VLDT0
VLDT0 5
Same Length MCKE0
MCKE0 8,9
MCKE1
MCKE1 8,9
MD63
MD62 MEMCLK_H7 C58
MEMCLK_H7 8,9
MD61 MEMCLK_L7
MEMCLK_L7 8,9
MD60 MEMCLK_H6 C4.7U10Y0805
MEMCLK_H6 8,9
MD59 MEMCLK_L6
MEMCLK_L6 8,9
MD58 MEMCLK_H5
MEMCLK_H5 8,9
MD57 MEMCLK_L5
MEMCLK_L5 8,9
MD56 MEMCLK_H4 CADIP15 CADOP15
MEMCLK_H4 8,9 11 CADIP[0..15] CADOP[0..15] 11
MD55 MEMCLK_L4 CADIN15 CADON15
MEMCLK_L4 8,9 11 CADIN[0..15] CADON[0..15] 11
MD54 CADIP14 CADOP14
MD53 CADIN14 CADON14
MEMCLK_H1 8,9
MEMCLK_L1 8,9
MEMCLK_H0 8,9
MEMCLK_L0 8,9
MD44 CADIP9 CADOP9
C MD43 CADIN9 CADON9 C
MD42 CADIP8 CADOP8
MD41 -MCS3 CADIN8 CADON8
-MCS3 8,9
MD40 -MCS2 CADIP7 CADOP7
-MCS2 8,9
MD39 -MCS1 CADIN7 CADON7
-MCS1 8,9
MD38 -MCS0 CADIP6 CADOP6
-MCS0 8,9
MD37 CADIN6 CADON6
MD36 -MSRASA CADIP5 CADOP5
-MSRASA 8,9
MD35 -MSCASA CADIN5 CADON5
-MSCASA 8,9
MD34 CADIP4 CADOP4
-MSWEA 8,9
MD33 CADIN4 CADON4
MD32 CADIP3 CADOP3
MEMBANKA1 8,9
MD31 CADIN3 CADON3
MEMBANKA0 8,9
MD30 CADIP2 CADOP2
MD29 CADIN2 CADON2
MAA[13..0] 8,9
MD28 CADIP1 CADOP1
MD27 MAA13 CADIN1 CADON1
MD26 MAA12 CADIP0 CADOP0
MD25 MAA11 CADIN0 CADON0
MD24 MAA10
MD23 MAA9 11 CLKIP1 CLKOP1 CLKOP1 11
MD22 MAA8 CLKON1
11 CLKIN1 CLKON1 11
MD21 MAA7 CLKOP0
11 CLKIP0 CLKOP0 11
MD20 MAA6 CLKON0
11 CLKIN0 CLKON0 11
MD19 MAA5
MD18 MAA4 VLDT0 R21 49.9R1% CTLIP1
MD17 MAA3 R28 49.9R1% CTLIN1
MD16 MAA2 CTLOP0
11 CTLIP0 CTLOP0 11
MD15 MAA1 CTLON0
11 CTLIN0 CTLON0 11
MD14 MAA0
B B
MD13
MD12
-MSRASB 8,9
MD11
-MSCASB 8,9
MD10
-MSWEB 8,9
MD9
MD8
MEMBAKB1 8,9
MD7
MEMBAKB0 8,9
MD6
MD5
MAB[13..0] 8,9
MD4
MD3 MAB13
MD2 MAB12
MD1 MAB11
MD0 MAB10
MAB9
MAB8
10 MD[63..0]
DM7 MAB7
DM6 MAB6
DM5 MAB5
DM4 MAB4
DM3 MAB3
DM2 MAB2
DM1 MAB1
DM0 MAB0
-MDQS7
10 DM[7..0]
-MDQS6
-MDQS5
-MDQS4
A -MDQS3 A
-MDQS2
-MDQS1
-MDQS0
MEMORY INTERFACE
10 -MDQS[7..0]
Title Rev
K8 DDR & HT
0A
5 4 3 2 1
5 4 3 2 1
VCCA_PLL trace length from the VR1 to the

PGA must be 0.75".
Place al filters close to the PGA.

VDDIO_SENSE
Keep all power and signal trce away from

the VR1.
C53
X_C1000P50N Place a cut in the GND plane around the
VCCA_PLL regulator circuit.
D D
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
VDDA_25
traces to exit ball field) and 500 mils long.
FB1 300L700m_250_0805 CPU_VDDA_25
FB2 THERMDC_CPU
C73 C61 C71
X_120S/0603
C4.7U10Y0805 C0.22U16Y C1000P50X
U2C
THRM#
THRM# 27
C63
X_C1000P50N THERMDA_CPU
THERMDA_CPU 24
VDDA_25 THERMDC_CPU
28 -CPURST THERMDC_CPU 24
CPU_GD
27 CPU_GD
VID4
11,18 -LDTSTOP VID4 14
VID3
VID3 14
C R22 VLDT0 R20 44.2R1% L0_REF1 VID2 C
4 VLDT0 VID2 14
R19 44.2R1% L0_REF0 VID1
1KR VID1 14
VID0
VID0 14
-LDTSTOP C60
14 COREFB_H
C59 NC_AG18
14 COREFB_L
Place near CPU in 1" , C1000P50X C1000P50X NC_AH18
Routed => 5:10/Trace:Space , Differential , "10:10:5:10:10" . NC_AG17
Same Length NC_AJ18
VDDIO_SENSE
C67 C0.039U16X CLKIN_H

7 CPUCLK0_H
169R1%
Near CPU in 0.5" . R31 LAYOUT: Route
VDD_25_SUS C66 C0.039U16X CLKIN_L FBCLKOUT_H FBCLKOUT_H/L differentially
7 CPUCLK0_L
R26 820R NC_AJ23 R30
with 20/8/5/8/20 spacing and
R29 820R NC_AH23 80.6R1% trace width. ( In CPU
breakout => routed 5:5:5 )
FBCLKOUT_L
VTT_DDR_SUS Zdiff = 80 ohm
HDT Test Port Signal . DBREQ_L

DBRDY
NC_D20
NC_C21
NC_D18
TMS NC_C19
B B
TCK NC_B19
TRST_L
TDI TDO
NC_C18
NC_A19
DBREQ_L R23 X_1KR
DBRDY R24 X_1KR
TCK
TMS
TDI NC_AE23
TRST_L NC_AF23
VDDA_25
NC_AF22
NC_AF21
RN50 X_8P4R-1KR
C51
C4.7U10Y0805
RN18
X_8P4R-1KR
NC_AH18
NC_AJ18 RN20 VDDA_25 VDD_25_SUS
NC_AG18 8P4R-1KR
A NC_AG17 A
NC_D18 NC_C18
NC_B19 NC_A19
NC_C19 8P4R-1KR NC_C21 8P4R-1KR
NC_D20 TDO Micro Star Restricted Secret
RN47 RN54
Title Rev
K8 HDT & MISC
0A
5 4 3 2 1
5 4 3 2 1
U2E
D D
VCORE VDD_25_SUS
U2D
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,

2 in middle of HT link, and 12 along bottom left side of
Claw-hammer.
VCORE
<nopop>
<nopop>
<nopop>
X_C6.8P50N
X_C6.8P50N
X_C6.8P50N
X_C1U10Y
X_C1U10Y
C437
C428
C72
C70
C429
C432
C GND C
Place between DIMN1 & 2
VDD_25_SUS
C147 C138 C102 C140 C142 VDD_25_SUS C85 VTT_DDR_SUS

C0.1U25Y
C0.1U25Y C0.1U25Y C0.1U25Y C0.1U25Y
X_C0.22U16Y
<nopop>
GND
VCORE
VDD_25_SUS
B
VDD_25_SUS
LAYOUT: Place beside processor. B
C435 C431 C426

C4.7U10Y0805
C4.7U10Y0805
C1U16Y0805
X_C1U16Y0805
C0.22U16Y
<nopop>
<nopop>
C1000P50X
X_C0.22U16Y
C0.22U16Y
C1U10Y C1U10Y C1U10Y
C1U10Y
C152
C111
C164
C176
C197
C154
C33
C46
C99
C160
C178
C91
BACK
GND VTT_DDR_SUS GND
C424 C425
X_C0.1U25Y X_C0.1U25Y
In CPU.
VCORE
X_C0.22U16Y
GND
C105 C109 C114 C122 C125 C134 C108
C 0 . 2 2 U 1 6 Y C180P50N C8.2P50N X_C0.22U16Y C0.22U16Y C0.22U16Y
A A
C106 C129 C110 C115 C123 C126 C135
C180P50N C180P50N C 0 . 2 2 U 1 6 Y C8.2P50N C 0 . 2 2 U 1 6 Y X_C0.22U16Y

C8.2P50N
Title Rev
K8 POWER & GND
0A
GND GND Last Revision Date:
MICRO-STAR INT'L CO.,LTD.
5 4 3 2 1
5 4 3 2 1
VCLK C322 X_C10P50N
Clock Synthesizer GCLK_NB
GCLK_SLOT
C323
C324
C10P50N
X_C10P50N
ICS950410AF
Strapping CPU HTT PCI
FS3 FS2 FS1 FS0 MHz MHz MHz

D D
SIO48M C279 C10P50N 0 0 0 0 100.90 67.27 33.63
U9
USBCLK_SB C280 C10P50N 0 0 0 1 133.90 66.95 33.48
CLKVCC3 ICS950410AF_SSOP48 R135 33R AC_14 AC_14 21
FS0 R150 33R APICCLK AC_14 C284 X_C10P50N 0 0 1 0 168.00 67.20 33.60
APICCLK 17,18
C285 C0.1U25Y FS1 R126 33R GUICLK
GUICLK 12
For K8M800 APICCLK C321 X_C10P50N 0 0 1 1 202.00 67.33 33.67
CLK_RESET# 27,28
CLKVCC3
CLKX1 C308 C27P50N GUICLK C274 X_C10P50N 0 1 0 0 100.20 66.80 33.40
CLKX2
Y2 14.318MHZ32P_D FS1 C294 C10P50N 0 1 0 1 133.50 66.75 33.38
CLKVCC3 C305 C27P50N
MODEA VCLK For K8M800 0 1 1 0 166.70 66.68 33.34
VCLK 18
C287 C0.1U25Y MODEB GCLK_NB GCLK_NB 12
CLKVCC3 GCLK_SLOT *** 0 1 1 1 200.40 66.80 33.40
GCLK_SLOT 15
RN69 8P4R-22R
C288 X_C0.1U25Y FS2 SIOPCLK 1 0 0 0 150.00 60.00 33.00
SIOPCLK 24 CN10
LPC_PCLK
LPC_PCLK 24
CLKVCC3 PCICLK5 SIOPCLK 1 0 0 1 180.00 60.00 33.00
PCICLK5 20
RN70 8P4R-22R PCICLK4 LPC_PCLK
PCICLK4 20
C290 C0.1U25Y PCICLK5 1 0 1 0 210.00 70.00 35.00
PCICLK4
CLKVCC3 PCICLK3 1 0 1 1 240.00 60.00 30.00
PCICLK3 20
PCICLK1 8P4C-10P50N
PCICLK1 19 CN11
C310 C0.1U25Y PCICLK2 1 1 0 0 270.00 67.50 33.75
PCICLK2 19
SBPCLK PCICLK3
SBPCLK 18
CLKVCC3 RN71 8P4R-22R PCICLK1 1 1 0 1 233.33 66.67 33.33
C FS3 R127 33R SIO48M PCICLK2 C
SIO48M 24
C311 X_C0.1U25Y SEL_24 R141 33R USBCLK_SB SBPCLK 1 1 1 0 266.67 66.67 33.33
USBCLK_SB 16
CLKVCC3 SMBDATA1 8P4C-10P50N 1 1 1 1 300.00 75.00 37.50

SMBDATA1 8,17,27
SMBCLK1
SMBCLK1 8,17,27
C312 C0.1U25Y
R137 15R1% CPUCLK0_H
CPUCLK0_H 5
CLKVDDA R138 15R1% CPUCLK0_L
CPUCLK0_L 5 ModeA ModeB Pin6 Pin7 Pin8 Pin11
C286 C0.1U25Y R139 15R1% HCLK+ HCLK+ C277 C10P50N *** 0 0 HTTCLK0 HTTCLK1 HTTCLK2 PCICLK10
HCLK+ 11
R140 15R1% HCLK-
HCLK- 11
CLKVCC3 For K8T800 Pro HCLK- C278 C10P50N 0 1 ModeA In HTTCLK1 HTTCLK2 HTTCLK3
For K8T800 Pro 1 0 PCICLK7 PCICLK8 PCICLK9 PCICLK10
R151 10KR
CLKVCC3
1 1 ModeA In PCICLK8 PCICLK9 PCICLK10
"FS0~FS3" are all internal

Near CK-Gen in 0.5" .
pull-up via 100K ohm ..
VCC3 CLKVDDA CLKVCC3 CLKVCC3
VCC3 CPUCLK0_H C275 C8.2P50N
FB14 X_120S/0805 FB15 X_120S/0805 FS0 R149 10KR
CPUCLK0_L C276 C8.2P50N FS2 R152 10KR
C295 C291 CP11 C301 C289 FS1 R136 10KR
B B
C281 X_C0.1U25Y C0.1U25Y C1U16Y0805 C0.1U25Y C309 C0.1U25Y FS3 R128 10KR
VCC3
CP10 C1U16Y0805 X_COPPER
X_COPPER
Decoupling Cap for CPU Clock
ModeA,B=0:0 ( Set Pin 7,8 clock

-> 66 MHz Pin11->33Mhz )
For EMI
MODEB R166 10KR
VCC3 VCC
MODEA R165 10KR
C364 C0.1U25Y
"24_48MHZ/SEL" Freq.-Out select

pin => Low->48MHz , Hi->24MHz .
( Internal pull-up via 100K ohm )
SEL_24 R142 10KR
A A

Title Rev
Clock Synthesizer
0A

5 4 3 2 1
5 4 3 2 1
SYSTEM MEMORY
VDD_25_SUS VDD_25_SUS
DR_MD0 -MCS0 DR_MD0 -MCS2

9,10 DR_MD[63..0] -MCS0 4,9 -MCS2 4,9
DR_MD1 -MCS1 DR_MD1 -MCS3
-MCS1 4,9 -MCS3 4,9
DR_MD2 DR_MD2
D D
DR_MD3 DR_MD3
DR_MD4 DR_MD4
DR_MD5 -DR_MDQS0 DR_MD5 -DR_MDQS0
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
DR_MD12 -DR_MDQS7 -DR_MDQS7 9,10 DR_MD12 -DR_MDQS7
DR_MD13 DR_MD13
DR_MD14 DR_MD14
DR_MD15 DR_MD15
DR_MD16 DR_MD16
DR_MD17 MAA0 MAA[13..0] DR_MD17 MAB0
MAA[13..0] 4,9 MAB[13..0] 4,9
DR_MD18 MAA1 DR_MD18 MAB1
DDR DIMM
DDR DIMM
DR_MD31 DR_MD31
184
184
PIN
PIN
C DR_MD32 MEMBANKA0 4,9 DR_MD32 MEMBAKB0 MEMBAKB0 4,9 C
SOCKET
SOCKET
DR_MD33 DR_MD33 MEMBAKB1
MEMBANKA1 4,9 MEMBAKB1 4,9
DR_MD34 DR_MD34
DR_MD35 SMBCLK1 DR_MD35 SMBCLK1
SMBCLK1 7,17,27
DR_MD36 SMBDATA1 DR_MD36 SMBDATA1
SMBDATA1 7,17,27
DR_MD37 DR_MD37
DR_MD38 DR_MD38 VDD_25_SUS
DR_MD39 DR_MD39
DR_MD40 DR_MD40
DR_MD41 DR_MD41
DR_MD42 DR_MD42
DR_MD43 DR_MD43
DR_MD44 DR_MD44
DR_MD45 DR_MD45
DR_MD46 DR_MD46
DR_MD47 DR_MD47
DR_MD48 DR_MD48
DR_MD49 DR_MD49
DR_MD50 MEMCLK_H5 DR_MD50
MEMCLK_H5 4,9 MEMCLK_H4 4,9
DR_MD51 MEMCLK_L5 DR_MD51
MEMCLK_L5 4,9 MEMCLK_L4 4,9
DR_MD52 MEMCLK_H0 MEMCLK_H0 4,9 DR_MD52 MEMCLK_H1 4,9
DR_MD54 MEMCLK_H7 DR_MD54
MEMCLK_H7 4,9 MEMCLK_H6 4,9
DR_MD56 DR_MD56
DR_MD57 DR_MD57
DR_MD58 DR_MD58
DR_MD59 DR_MD59
DR_MD60 MCKE0 DR_MD60 MCKE0
MCKE0 4,9
DR_MD61 MCKE1 DR_MD61 MCKE1
B MCKE1 4,9 B
DR_MD62 -MSCASA -MSCASA 4,9 DR_MD62 -MSCASB -MSCASB 4,9
VDD_25_SUS DR_MD63 -MSRASA VDD_25_SUS DR_MD63 -MSRASB
-MSRASA 4,9 -MSRASB 4,9
R73 4.7KR WP1 DR_DM0 R74 4.7KR WP2 DR_DM0
-MSWEA DR_DM1 -MSWEB DR_DM1
4,9 -MSWEA 4,9 -MSWEB
DR_DM2 DR_DM2
DDR_VREF DR_DM3 DDR_VREF DR_DM3
DR_DM4 DR_DM4
VREF routed as 40~50 milsC 2trace
0 wide , Space>25 mils DR_DM5 DR_DM5
DR_DM6 DR_DM6
C0.1U25Y DR_DM7 DR_DM7
DDR1 DDR2
DIMM-184_green DIMM-184_green
Place 104p and 1000p Cap. near the DIMM N13-1840061-K06 N13-1840061-K06
Place near the DIMM
VREF routed as 40~50 mils trace wide , Space>25 mils DR_DM[7..0]

VDD_25_SUS DR_DM[7..0] 9,10
DIMM2 SLAVE ADDRESS
= (1010001X)B = A2
DIMM1 SLAVE ADDRESS
R13
1KR1% C423 = (1010000X)B = A0
A X_C0.1U25Y A
DDR_VREF
DDR_VREF 4

R14 C19
1KR1% Title Rev
C1U10Y System Memory : DDR DIMM 1 0A
5 4 3 2 1
5 4 3 2 1
DDR Terminations
VTT_DDR_SUS
VTT_DDR_SUS VTT_DDR_SUS
RN44 8P4R-47R0402
DR_MD44 RN26 8P4R-47R0402
DR_MD35 DR_MD23
DR_MD40 MAB8
DR_MD39 MAB7
D D
DR_MD22 VTT_DDR_SUS
RN40 8P4R-47R0402
RN64 8P4R-47R0402 DR_MD38 RN23 8P4R-47R0402
DR_MD59 DR_MD34 MAA11
DR_MD63 DR_DM4 MAB11
DR_MD62 -DR_MDQS4 MAB9
DR_MD58 DR_MD21
RN49 8P4R-47R0402
-MCS3
4,8 -MCS3
RN37 8P4R-47R0402 -MCS2
4,8 -MCS2
RN61 8P4R-47R0402 DR_MD36 RN24 8P4R-47R0402 -MSCASB
4,8 -MSCASB
-DR_MDQS7 DR_MD32 DR_MD18 -MSWEA
DR_DM7 4,8 -MSWEA
MAA7
4,8 MEMBAKB1
DR_MD57 MAA9
4,8 MEMBANKA1
DR_MD61 DR_DM2
RN59 8P4R-47R0402 RN19 8P4R-47R0402

DR_MD60 -DR_MDQS2
DR_MD56 DR_MD17
DR_MD51 MAA12
DR_MD55 MAB12
RN36 8P4R-47R0402
RN57 8P4R-47R0402 MAB0 RN17 8P4R-47R0402
C DR_MD50 MAB10 DR_MD16 C
DR_MD54 MAA10 DR_MD11
-DR_MDQS6 MAA0
4,8 MCKE0
DR_DM6
4,8 MCKE1
RN55 8P4R-47R0402 RN14 8P4R-47R0402
MAA13 DR_MD20
MAB13 DR_MD10
DR_MD53 DR_MD15
DR_MD52 DR_MD14
RN34 8P4R-47R0402
RN53 8P4R-47R0402 MAA2 RN13 8P4R-47R0402
DR_MD48 MAB2 DR_DM1
DR_MD49 DR_MD30 DR_MD13
DR_MD47 MAA3 -DR_MDQS1
DR_MD46 DR_MD12
RN29 8P4R-47R0402
RN51 8P4R-47R0402 MAA4 RN9 8P4R-47R0402
DR_MD43 MAA6 DR_MD9
DR_MD42 MAB6 DR_MD8
DR_DM5 MAB5 DR_MD3
DR_MD41 DR_MD6
B RN32 8P4R-47R0402 B
RN46 8P4R-47R0402 DR_MD26

-MCS1 DR_DM3 RN7 8P4R-47R0402
4,8 -MCS1
-MCS0 -DR_MDQS3 DR_MD7
4,8 -MCS0
-DR_MDQS5 DR_MD25 DR_MD2
-MSCASA DR_DM0
4,8 -MSCASA
-DR_MDQS0
RN31 8P4R-47R0402
RN45 8P4R-47R0402 DR_MD29
-MSWEB DR_MD28 RN5 8P4R-47R0402
4,8 -MSWEB
DR_MD45 MAB3 DR_MD1
-MSRASB MAB4 DR_MD5
4,8 -MSRASB
-MSRASA DR_MD4
4,8 -MSRASA
DR_MD0
RN28 8P4R-47R0402
RN38 8P4R-47R0402 MAA5 RN35 8P4R-47R0402
DR_MD37 MAA8 DR_MD27
DR_MD24 DR_MD31
4,8 MEMBAKB0
4,8 MEMBANKA0 DR_MD19 MAB1
DR_MD33 MAA1
DR_DM[7..0]
8,10 DR_DM[7..0]
A A
-DR_MDQS[7..0]
For DIMM2 Clock 8,10 -DR_MDQS[7..0]
For DIMM1 Clock
MEMCLK_H4 C75 X_C10P50N
MEMCLK_L4 MEMCLK_H5 C76 X_C10P50N
MEMCLK_L5 DR_MD[63..0]
4,8 MEMCLK_H4 MEMCLK_L4 4,8 4,8 MEMCLK_H5 MEMCLK_L5 4,8 8,10 DR_MD[63..0]
Title Rev
MEMCLK_L7 MAB[13..0] DDR Terminations Bank 0
4,8 MEMCLK_H1 MEMCLK_L1 4,8 4,8 MEMCLK_H7 MEMCLK_L7 4,8 4,8 MAB[13..0] 0A
MEMCLK_L0 MAA[13..0] Document Number MS-7144
4,8 MEMCLK_H6 MEMCLK_L6 4,8 4,8 MEMCLK_H0 MEMCLK_L0 4,8 4,8 MAA[13..0]

5 4 3 2 1
5 4 3 2 1
VDD_25_SUS VCC3
LAYOUT: Place on backside, LAYOUT: Locate close C462
MD38 R54 10R0402 DR_MD38
evenly spaced around VTT fill. to Clawhammer
X_C0.1U25Y
RN39 8P4R-10R0402
socket. C463
VDD_25_SUS VTT_DDR_SUS VTT_DDR_SUS

X_C0.1U25Y
DDR Terminations
MD32 DR_MD32 C193 C464
MD36 DR_MD36 VCC
MD33 DR_MD33
C1000P50X X_C0.1U25Y
<nopop>
RN41 8P4R-10R0402 C24 C465
-MDQS0 R15 1 0 R 0 4 0 2 -DR_MDQS0 MD37 DR_MD37 + +
D D
-MDQS4 -DR_MDQS4
X_C0.22U16Y X_C0.1U25Y
DM4 DR_DM4 <nopop> EC21 EC4
MD34 DR_MD34 C41 X_.CD1000U6.3EL15 .CD1000U6.3EL15 C466
RN6 8P4R-10R0402
MD0 DR_MD0
X_C0.22U16Y
MD4 DR_MD4 MD42 R55 10R0402 DR_MD42 <nopop>
X_C0.1U25Y
MD5 DR_MD5 GND C467
MD1 DR_MD1 RN43 8P4R-10R0402
MD39 DR_MD39
X_C0.22U16Y
RN8 8P4R-10R0402 MD40 DR_MD40 <nopop>
C107 X_C0.1U25Y
DM0 DR_DM0 MD35 DR_MD35 Ver:00A modify GND

MD2 DR_MD2 MD44 DR_MD44
MD7 DR_MD7 VDD_25_SUS
MD6 DR_MD6 RN48 8P4R-10R0402 VDD_25_SUS VTT_DDR_SUS VDD_25_SUS VTT_DDR_SUS V D D _ 2 5 _ S U S VDD_25_SUS
MD45 DR_MD45 C54 C181 C203 C68 C148
RN10 8P4R-10R0402 -MDQS5 -DR_MDQS5
X_C0.1U25Y X_C0.1U25Y C0.1U25Y X_C0.1U25Y C0.1U25Y
MD8 DR_MD8 DM5 DR_DM5
MD9 DR_MD9 C100 C189 C141
GND
C182
GND
C77
MD12 DR_MD12
C0.1U25Y X_C0.1U25Y C0.1U25Y C0.1U25Y
RN52 8P4R-10R0402 C0.1U25Y
MD15 R18 10R0402 DR_MD15 MD43 DR_MD43 C55 C136 C153 C34 C117
MD46 DR_MD46
RN12 8P4R-10R0402 MD47 DR_MD47
X_C0.1U25Y X_C0.1U25Y X_C0.1U25Y X_C0.1U25Y C0.1U25Y
-MDQS1 -DR_MDQS1 MD49 DR_MD49
MD13 DR_MD13 C194 C48 C120 C81 C199
DM1 DR_DM1 RN56 8P4R-10R0402
X_C0.1U25Y X_C0.1U25Y C0.1U25Y X_C0.1U25Y C0.1U25Y
C MD52 DR_MD52 C
RN21 8P4R-10R0402 MD53 DR_MD53 C149 C30 C93 C145 C188
C0.1U25Y
-MDQS2 -DR_MDQS2
X_C0.1U25Y X_C0.1U25Y X_C0.1U25Y C0.1U25Y
MD21 DR_MD21 C116
DM2 DR_DM2 MD51 R65 10R0402 DR_MD51 C42 C198 C95 C158
C0.1U25Y
C0.1U25Y X_C0.1U25Y C0.1U25Y C0.1U25Y
MD18 R27 10R0402 DR_MD18 C89
C172 C62
RN16 8P4R-10R0402 RN58 8P4R-10R0402
X_C0.1U25Y
MD10 DR_MD10 -MDQS6 -DR_MDQS6
X_C0.1U25Y C0.1U25Y
MD20 DR_MD20 MD54 DR_MD54 C206
C0.1U25Y
RN27 8P4R-10R0402 RN60 8P4R-10R0402

MD22 DR_MD22 MD56 DR_MD56 GND
RN30 8P4R-10R0402 RN62 8P4R-10R0402

VTT_DDR_SUS
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.
MD29 DR_MD29 -MDQS7 -DR_MDQS7
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
C0.1U25Y
C1U10Y
C1U10Y
C1U10Y
C1U10Y
C1U10Y
C57
C50
C177
C185
C170
C202
C139
C17
C88
C40
C45
C103
C191
C127
C200
C143
C144
C1U10Y
-MDQS3 -DR_MDQS3 MD62 DR_MD62
RN33 8P4R-10R0402
MD26 DR_MD26
B B
MD30 DR_MD30
MD31 DR_MD31
MD27 DR_MD27 MD59 R71 10R0402 DR_MD59 GND
VTT_DDR_SUS
MD63 R69 10R0402 DR_MD63
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
C0.1U25Y
C0.1U25Y
C1U10Y
C1U10Y
C1U10Y
C1U10Y
C1U10Y
C1U10Y
C32
C82
C165
C195
C146
C150
C151
C157
C209
C204
C90
C94
C27
C65
C79
C80
C36
DM3 R34 10R0402 DR_DM3
GND
LAYOUT: Locate close to

VTT_DDR_SUS
LAYOUT: Locate close to
Clawhammer socket. VDD_25_SUS
Dimm2 socket.
C0.22U16Y
-MDQS[7..0]
4 -MDQS[7..0]
C1000P50X
X_C0.22U16Y
X_C100P50N
C1U16Y0805
C1U16Y0805
-DR_MDQS[7..0] X_C4.7U10Y0805
8,9 -DR_MDQS[7..0]
C0.1U25Y
C0.1U25Y
C0.1U25Y
C0.1U25Y
C39
C31
C211
C133
DR_MD[63..0]
C47
C35
C98
C28
C23
C11
8,9 DR_MD[63..0]
C29
MD[63..0]
4 MD[63..0]
A VTT_DDR_SUS GND A
GND
X_C1000P50X
X_C1000P50N
X_C1000P50X
C1000P50X
C0.22U16Y
X_C4.7U10Y0805
X_C4.7U10Y0805

C1U16Y0805
DR_DM[7..0] C1U16Y0805
8,9 DR_DM[7..0]
Title Rev
DM[8..0]
C196
C212
DDR Terminations Bank 1

C49
C22
C13
C201
C225
C183
4 DM[8..0] 0A
C113

GND No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
5 4 3 2 1
A B C D E
VDD_12_A
C213 C0.1U25Y
VDD_12_A
VCC3 VCC3HCK Around NB

FB8 X_0R
R251 R252 R86 R253 FOR K8M800
4
C237 C233 CB16 VDD_12_A 4
0R 0R FOR K8T800A
0R 0R
X_C1000P50X C440
VCC3HCK VDD_12_A HCKGND R254 X_0R C1000P50X 5020
7 HCLK-
HCKGND C1U10Y X_C0.1U25Y
7 HCLK+
AVDD2
U4A
G21
G22
C22
C10
C11
C23
C24
C25
D10
D11
D22
D23
D24
H21
A10
A24
A25
A26
B10
B23
B24
B25
B26
E10
E11
E21
E22
E23
E24
K18
K21
To Claw Hammer
F10
F11
F15
F16
F19
F20
F21
F22
F23
L18
J10
J11
J12
J13
J14
J15
J16
J17
C9
D9
A9
B9
E9
Decoupling capacitors
at NB BGA Area (On
From Claw Hammer
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
AVDD2
Solder Layer)
CADOP0 CADIP0
4 CADOP[0..15] CADIP[0..15] 4
CADOP1 CADIP1
CADOP2 CADIP2 VDD_12_A
CADOP3 CADIP3
CADOP4 CADIP4
CADOP5 CADIP5 PNCOMP R70 49.9R1%
CADOP6 CADIP6
CADOP7 CADIP7 RTCOMP R68 100R1%
CADOP8 CADIP8
CADOP9 CADIP9 RPCOMP R72 49.9R1%
CADOP10 CADIP10
CADOP11 CADIP11
3 CADOP12 CADIP12 3
CADOP13 CADIP13
CADOP14 CADIP14
CADOP15 CADIP15
CLKOP0 CLKIP0
4 CLKOP0 CLKIP0 4
4 CLKOP1 CLKOP1 CLKIP1 CLKIP1 4
CTLOP0 CTLIP0
4 CTLOP0 CTLIP0 4
CADON0 CADIN0
4 CADON[0..15] CADIN[0..15] 4
CADON1 CADIN1
CADON2 CADIN2
CADON3 CADIN3
CADON4 CADIN4
CADON5 CADIN5
CADON6 CADIN6
CADON7 CADIN7
CADON8 CADIN8
CADON9 CADIN9
CADON10 CADIN10
CADON11 CADIN11
CADON12 CADIN12
CADON13 CADIN13
CADON14 CADIN14
CADON15 CADIN15
CLKON0 CLKIN0
4 CLKON0 CLKIN0 4
CLKON1 CLKIN1
2
4 CLKON1 CLKIN1 4 2
CTLON0 CTLIN0
4 CTLON0 CTLIN0 4
-LDTRST VDD_12_A
28 -LDTRST
-LDTSTOP
5,18 -LDTSTOP
RPCOMP
PNCOMP
RTCOMP
VDD_12_A
AGND2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J18
J21
J25
F7
F8
G25
F12
F13
F14
F17
F18
F26
C8
D6
D8
H1
H2
C21
D12
D14
D16
D18
D20
H23
L10
L11
L12
L13
L14
L15
A23
B13
B15
B17
B19
B21
B22
K10
K11
K12
K13
K14
K15
K16
K17
K23
A8
B8
E5
E6
E8
K4
J2
J3
G1
1 (VIA-K8M800-VT8380) 1

Title Rev
NORTH BRIDGE (HT)
0A
A B C D E
A B C D E
K8M800/K8T800A AGP 8X ,V-Link, Misc. Control VCC3

FOR K8T800A
VCCA3
FB13
X_0R VCC2_5
VDDQ VDD3 VCCA3 C266 C264 CB18
C1000P50X X_C1000P50X
5020
C1U10Y C227
R77
M9
M5
U1
R9
N9
N5
H5
H4
H3
D1
P9
K9
K8
K5
E4
E3
E2
E1
G5
G4
G3
G2
3KR1% C0.1U25Y
F6
F5
F4
F3
F2
F1
L9
L8
L5
4 4
J9
J5
J4
U4B
LVREF_NB
VCCQQ
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
GAD0
15 GAD[31..0] VLAD[0..7] 18
GAD1 VLAD0
GAD2 VLAD1 C229
GAD3 VLAD2 R79
GAD4 VLAD3 1KR1% C0.1U25Y
GAD5 VLAD4
GAD6 VLAD5
GAD7 VLAD6
GAD8 VLAD7
GAD9 K8M800 and K8T800A will be 0.625V(R153=1KST,R11-0102T13-Y01)
GAD10
VBE0# 18
GAD11 VPAR 18
GAD12
GAD13
UPSTB 18
GAD14
UPSTB# 18 LAYOUT: Place caps on the bottom of NB
GAD15
GAD16 DNSTB 18
GAD17 VDDQ
DNSTB# 18
GAD18
GAD19
UPCMD 18
GAD20 C450 X_C0.1U25Y
DNCMD 18
GAD21
GAD22 LVREF_NB C231
GAD23
GAD24 LCOMPP X_C1000P50N C452 X_C1U10Y
3 GAD25 3
GAD26 C443 X_C0.1U25Y

PWROK_NB# 17
GAD27
GAD28 C448 X_C1U10Y
PCIDEVRST# 24,27
GAD29
GAD30 TESTIN C454 X_C0.1U25Y
GAD31
C449 X_C1U10Y
SUSST# 17
GC/BE#0
15 GC/BE#[3..0]
GC/BE#1 DEBUG R89 10KR C451 X_C0.1U25Y
GC/BE#2
GC/BE#3
AD_STBS0
15 AD_STBS0 AR 26
AD_STBF0
15 AD_STBF0 AG 26
AB 26
15 AD_STBS1 AD_STBS1
AD_STBF1 RSET R114 84.5R1%
15 AD_STBF1
HSYNC 26
15 GFRAME VSYNC 26
15 GIRDY For K8M800.
15 GTRDY GUICLK 7
15 GDEVSEL
15 GSTOP PIRQ#A 15,16,19,20
15 GPAR
R109 1KR
15 RBF
15 WBF
15 GREQ DDCCLK 26
15 GGNT
2
15 GSERR DDCDATA 26
FOR K8M800 2
R78 100KR
7 GCLK_NB
SBA0 AGPVREF_GC C455 C1U10Y

15 SBA[7..0]
SBA1
SBA2 C228 C0.1U25Y
SBA3
SBA4
SBA5
SBA6
LAYOUT: Place caps as close NB as possible
SBA7
VCC2_5
SB_STBS
15 SB_STBS
SB_STBF TESTIN R97 4.7KR
15 SB_STBF
ST0 VPAR R82 X_8.2KR

15 ST0
ST1
15 ST1
ST2
15 ST2
VDDQ
AGPPCOMP
AGPNCOMP AGPNCOMP R130 60.4R1%
AGPVREF_GC AGPPCOMP R129 60.4R1%

15 AGPVREF_GC
LCOMPP R90 360R1%

15 AGP8XDET#
1 1
VSSQQ
DBIL
15 DBIL
DBIH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 DBIH

T1
R5
R4
R3
R2
R1
R15
R14
R13
R12
R11
R10
N25
N17
N16
N15
N14
N13
N12
N11
N10
L25
L17
L16
M23
M21
M17
M16
M15
M14
M13
M12
M11
M10
P23
P17
P16
P15
P14
P13
P12
P11
P10
P5
Title Rev
NORTH BRIDGE (AGP & VLINK)
0A
(VIA-K8M800-VT8380) No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
A B C D E
A B C D E
C240
VSUSNB
U4C
VDDQ
Power and Ground Connections For K8M800 Only
C1U10Y VDD RGBPLL
AVDD1
FB11
0R
C253 C251 CB5
VDD
4 C1000P50X C 1 U 1 0 Y C1U16Y0805 4
VDD_12_A FB9 X_0
RGBPLL C456 X_C1U10Y
C438 X_C1U10Y CP7 GND_RGBPLL
C458 X_C1000P50N X_COPPER

C442 X_C0.22U16Y
C446 X_C1U10Y VDD3 DAC_PLL
GND_RGBPLL
C457 X_C1U10Y FB10 0R
RGBPLL C444 X_C0.1U25Y
C447 X_C1000P50N C258 C267 CB6
C445 X_C1U10Y C1000P50X C1U10Y C1000P50X

FB12 X_0 5020
GND_RGBPLL VDD X_C1000P50N
CB14 C441 X_C1U10Y CP9 GND_DAC
DAC_PLL VDD_12_A
X_C1000P50N
CB15 C439 X_C0.22U16Y X_COPPER
GND_DAC R119
CB17 C10U10Y0805 0R0805
DAC_PLL VDD_12_A
VCC3 VDD3
LAYOUT : Popualte caps on the bottom side
3 of NB. RN67 3
8P4R-0R
GND_DAC
VDD
VDDQ
VDD
Note: When use K8T800,
C292
these power circuit for
C302 C314 C296
C0.1U25Y
X_C0.1U25Y
C0.1U25Y
X_C1U10Y
GFX analog power should be
NOPOPed.
VDDQ
For K8M800/K8T800 Pro Only

C316 C315 C273
C1U10Y C1U10Y C1U10Y
VCC3 AVDD1
FB6
X_0
2 CP4 C210 C207 CB13 2
X_COPPER C1000P50X C 1 U 1 0 Y X_C1000P50X

5020
VDDQ
AVDD2
C283 X_C1U10Y FB7 X_0
VCC3
CP5
C221 C220
X_COPPER
C1000P50N C1U10Y
AGND2
VDDQ
C298 C299
X_C0.1U25Y C0.1U25Y
VDDQ
1 1
C300 C297 C453

C1U10Y X_C1U10Y X_C1U10Y
Title Rev
NORTH BRIDGE (POWER/GOUND) 0A

(VIA-K8M800-VT8380) MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
ISL6568CR FOR AMD K8 939 POWER CKT
CHOK2
.CD1000U16EL20
.CD1000U16EL20
.CD1000U16EL20
.CD1000U16EL20
.CD1000U16EL20
C4.7U16Y1206
C4.7U16Y1206
+12VA VIN
C4.7U16Y1206
C1U16Y0805
VCC VCC VCC VCC CH-1.2U18A
+
C0.1U25Y
EC14
EC12
EC10
EC11
EC13
C21
C14
C12
C86
C546
X_S-1N5817_DO214AC
D1 R2
4.7R0805 +12VA
R283 R284 R285
1KR 1KR 4.7KR
U1 C2
ISL6568_QFN32 C4.7U16Y1206 R8 VIN
32PIN 5x5QFN 4.7R0805
R287
5 VID4
C532
5 VID3 C533 C4 C1U16Y0805
5 VID2
2.2R C1U16Y0805
5 VID1
5 VID0 C0.1U25X R36 Q12
27 PG_VCORE 1R0805 N-P0903BR_TO252-3 CHOK3

27 VCORE_EN
VCORE
VRM_EN > 0.6V ENABLE C534 C535
CH-1.0U40A
EC20
EC18
EC19
EC17
0.8V~1.55V/80A
.CD1500U6.3EL20
.CD1500U6.3EL20
.CD1500U6.3EL20
.CD1500U6.3EL20
C0.1U25Y C0.1U25Y R288 3KR1% R258
R43 Q14 Q13 2.2R0805
C536
R289 10KR C5600P50X 0R0805 C119
C1000P50X
N-SUR50N024-06P_TO252-3 N-SUR50N024-06P_TO252-3
C537 X_C10P50N
VIN VCORE
R290 1KR R291

VCORE C538
C539 C1U16Y0805 C549 C550
2.2R X_C100U2SP X_C100U2SP
R292 C0.1U25X R46 Q11
51R 1R0805
5 COREFB_H N-P0903BR_TO252-3 CHOK1
C540
Near CPU Socket
X_C1000P50X CH-1.0U40A
5 COREFB_L
.CD3300U6.3EL25
.CD3300U6.3EL25
.CD3300U6.3EL25
.CD3300U6.3EL25
R294 R257
3KR1% R32 Q9 Q10 2.2R0805
EC8
EC7
EC5
EC6
R295 C541
0R0805
51R X_C1000P50X N-SUR50N024-06P_TO252-3 C44
R296 N-SUR50N024-06P_TO252-3
C1000P50X
VCC
X_150KR R297 +20mV
R298 1KR1%
24KR1% OFFSET
ATX12V POWER CONNECTOR

R299 17.4KR1% JPW1
C542
R300 C543
+12VA
C544 C0.047U16X
C0.01U50X PWR-2X2M
150KR C0.01U50X C37 C16
C33P50N C 0 . 0 1 U 5 0 X
R301 39KR
R302 39KR
BOTTOM PAD CONNECT TO
GND THROUGH 10vias
PH1 PH2
HS-0500410-K08 HS-0500410-K08
MSI MICRO-STAR INT'L CO.,LTD.

Title
VRM 9.0 NIKO N2101
MS-7144 0A
Wednesday, November 10, 2004 14 32

5 4 3 2 1
AGP PRO Connector

VCC3 GAD[31..0]
VCC3 12 GAD[31..0]
VDDQ GAD31
GAD30
GAD29
VDDQ +12V GAD28
GAD27
VCC VCC AGP1 GAD26
SLOT-AGP1.5LATCH_red GAD25
N11-1240131-A10 GAD24
GAD23
C313 GAD22
D D
C0.1U25Y AGP8XDET_GC# GAD21
GAD20
GAD19
GAD18
16,19,20 PIRQ#B PIRQ#A 12,16,19,20
GAD17
7 GCLK_SLOT PCIRST# 16,27
GREQ GGNT GAD16
12 GREQ GGNT 12
GAD15
ST0 ST1 GAD14
12 ST0 ST1 12
ST2 GAD13
12 ST2
12 RBF RBF DBIH 12 GAD12
GAD11
DBIL WBF GAD10
12 DBIL WBF 12
SBA0 SBA1 GAD9
GAD8
SBA2 SBA3 GAD7
SB_STBF SB_STBS GAD6
12 SB_STBF SB_STBS 12
GAD5
SBA4 SBA5 GAD4
SBA6 SBA7 GAD3
GAD2
GAD1
GAD0
3VDUAL SBA[7..0]
12 SBA[7..0]
GAD31 GAD30
GAD29 GAD28 SBA0
SBA1
GAD27 GAD26 SBA2
GAD25 GAD24 SBA3
SBA4
C 12 AD_STBF1 AD_STBF1 AD_STBS1 AD_STBS1 12 SBA5 C
GAD23 GC/BE#3 SBA6
SBA7
GAD21 GAD22
GAD19 GAD20
GAD17 GAD18
GC/BE#2 GAD16
GC/BE#[3..0]
12 GC/BE#[3..0]
GIRDY GFRAME
12 GIRDY GFRAME 12
GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3
GDEVSEL GTRDY
12 GDEVSEL GTRDY 12
GSTOP
GSTOP 12
GPERR AGP_PME# R158 0R
PCI_PME# 17,19,20
GSERR GPAR
12 GSERR GPAR 12
GC/BE#1 GAD15
GAD14 GAD13
GAD12 GAD11
GAD10 GAD9
GAD8 GC/BE#0
AD_STBF0 AD_STBS0
12 AD_STBF0 AD_STBS0 12
GAD7 GAD6
B B
GAD5 GAD4
GAD3 GAD2
GAD1 GAD0
VREF_CG AGPVREF_GC
AGPVREF_GC 12
AGP "Vref" => 4X : 0.5*1.5V=0.75 Volt , Add-in Card Power

Imax V_Min V_Max Units
8X : 0.23*1.5 =0.345 Volt
VCC3 VDDQ 2.0A 1.425 1.575 V
VDDQ
+12V VCC3 6.0A 3.15 3.45 V
VDDQ R162
4.7KR +12V R155
3VDUAL 0.75A 3.15 3.45 V
R157 8.2KR
4X : 0.75V 1KR
VCC5 2.0A 4.75 5.25 V
8X : 0.35V R160 Q29 GPERR
A 3.32KR1% AGP8XDET_GC# N-2N7002_SOT23 R153 A
Q28 1KR
VCC12 1.0A 11.4 12.6 V
R159 N-2N7002_SOT23 AGP8XDET# Q27
1 : 4X AGP8XDET# 12
VREF_CG N-2N7002_SOT23
1.47KR1% 0 : 8X 1 : 4X R154
C318 R163 AGP8XDET_GC# Q26 Title Rev
C317 R161 10KR 0 : 8X N-MMBT3904_SOT23 AGP PRO Slot
C1U10Y C0.1U25Y 1.02KR1% 10KR R156 0A
1 : 4X 200R1% Document Number MS-7144
"AGP8XDET_GC#" 0 : 8X MICRO-STAR INT'L CO.,LTD. Last Revision Date:
=>4X=High,8X=Low Taipei Hsien, Taiwan Sheet
5 4 3 2 1
A B C D E
VCC3 RN106 RN42

USBN4 USBN2 VCC2_5
USBP4 USBP2
USBN5 USBN3
AD[31..0] USBP5 USBP3 CB22 X_C1U10Y
W10
W11
W17
W18
W19
W21
19,20 AD[31..0]
H10
H11
H12
R19
U19
V19
V21
Y21
T19
M8
W9
W8
H9
N8
R8
U8
K8
P8
V8
T8
L8
J8
U13A 3VDUAL 8P4R-15KR CB21 X_C1U10Y
AD0 8P4R-15KR RN63 8P4R-15KR
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
AD1 USBP7 CB20 X_C1U10Y
AD2 USBN7
AD3 C346 CB11 USBP6 VCC3
4 AD4 CB10 X_C0.1U25Y USBN6 CB23 X_C1U10Y 4
AD5 C0.1U25Y C10U10Y1206 3VDUAL
AD6 CB24 X_C0.01U50X
AD7 USBP0
AD8 USBN0
AD9 USBP1
AD10 USBN1
AD11
AD12
AD13 RN105 8P4R-15KR VCC
VSUS2_5
AD14 RN89 RN98 VCC3
AD15 C343 PIRQ#B 8P4R-2.7KR
AD16 C0.1U25Y PIRQ#A DEVSEL#
AD17 near SB PIRQ#C TRDY#
AD18 PIRQ#D IRDY#
AD19 VCC2_5 FRAME#
AD20 USBVCCA 8P4R-2.7KR
AD21 CB9 RN99
AD22 X_C1U10Y SERR#
AD23 PERR#
AD24 USBGNDA INTH#
AD25 STOP#
AD26 USBP0 USBP0 23
AD27 USBN0 8P4R-2.7KR
3 USBN0 23 3
AD28 USBP1 USBP1 23
AD29 USBN1 USBN1 23
AD30 USBP2 USBP2 23
C_BE#[3..0] AD31 USBN2
19,20 C_BE#[3..0] USBN2 23
USBP3 USBP3 23
C_BE#0 USBN3 USBN3 23
C_BE#1 USBP4 USBP4 23
C_BE#2 USBN4 USBN4 23
C_BE#3 USBP5 USBP5 23
USBN5 USBN5 23
FRAME# USBP6
19,20 FRAME# USBP6 23
DEVSEL# USBN6
19,20 DEVSEL# USBN6 23
IRDY# USBP7
19,20 IRDY# USBP7 23
TRDY# USBN7
19,20 TRDY# USBN7 23 VCC3
STOP# RN90
19,20 STOP#
SERR# 8P4R-2.7KR
19,20 SERR#
PAR USB_OC#1 PREQ#1
19,20 PAR USB_OC#1 23
PERR# PREQ#2
19,20 PERR#
PCIRST# PREQ#3
15,27 PCIRST#
PREQ#4
PIRQ#A USB_OC#5
12,15,19,20 PIRQ#A USB_OC#5 23
PIRQ#B
15,19,20 PIRQ#B
PIRQ#C
19,20 PIRQ#C
2 19,20 PIRQ#D PIRQ#D 2
USBCLK_SB USBCLK_SB 7
INTH# USBREXT R206 5.76KR1%
PREQ#0 R201 10KR RN88 VCC3

19 PREQ#0
PREQ#1 8P4R-4.7KR
19 PREQ#1
PREQ#2 PGNT#1
20 PREQ#2
PREQ#3 PGNT#2
20 PREQ#3
PREQ#4 PGNT#3
20 PREQ#4 KBCLK# 25
PREQ#5 PGNT#4
KBDAT# 25
MSCLK# 25
PGNT#0 RN95
19 PGNT#0 MSDAT# 25
PGNT#1 8P4R-2.7KR
19 PGNT#1
PGNT#2 PGNT#5
20 PGNT#2
PGNT#3 PREQ#5
20 PGNT#3
PGNT#4 PREQ#0
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
USBGND
20 PGNT#4
PGNT#5 PGNT#0
GND
GND
GND
GND
GND
GND
GND
GND
GND
VIA-VT8237-A2
J21
J25
F25
H23
C13
C14
C15
C16
C17
C18
C19
C20
C21
D13
D15
D17
D19
D21
H13
H14
H15
H16
H17
H18
A13
A15
A17
A19
A21
B13
B15
B17
B19
B21
E13
E15
E17
E19
E21
A1
A2
B1
B2
E8
1 1

Title Rev
VT8235 Part 1 0A
A B C D E
A B C D E
3VDUAL VSUS2_5 VT8237

VSUS2_5 VCC2_5
VCC2_5 *"ACSYNC" => LPC FWH Command *"SA[17:16]" => LDT Frequency (VD[1:0])
0 - Enable FWH 00 - 200MHz (Default) 10 - 600MHz
C461 C337 C340 C460 1 - Disable FWH(Default) 01 - 400MHz 11 - 800MHz
M18
AA4
AB4
AB5
AB6
N18
R18
U18
P18
V10
V11
V12
V13
V14
V15
V16
V17
V18
T18
L18
J10
J11
J12
M9
N9
R9
U9
U4
K9
P9
V9
X_C1U10Y C1U10Y C0.1U25Y X_C0.1U25Y ACSYNC R 2 2 3 4.7KR
T9
T4
L9
*"SA18" => LDT Width (VD[2])
J9
VCC3
U13B 0 - 8-Bit (Default)
PDD[15..0] PDD0 1 - 16-Bit
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSUS33
VSUS33
VSUS33
VSUS33
VSUS25
VSUS25
22 PDD[15..0]
PDD1 *"SA19" => Fast command (VD[3])
PDD2 GPI0 R225 4.7KR 0 - Disable (Default)
VBAT
PDD3 INTRUDER R222 1MR 1 - Enable
PDD4 AC_BITCLK
AC_BITCLK 21
PDD5 ACSDIN0 RN96
4 C551 RN101 8P4R-4.7KR 4
PDD6 AC_SDIN1
PDD7 POWERF1 X_C10P50N ACSDIN0 AC_SDIN0 GPIOA SA19 (VD[3])
AC_SDAIN0 21
PDD8 ACSYNC AC_SYNC GPIOD SA17 (VD[1])
AC_SYNC 21
PDD9 ACSYNC For EMI ACSDO AC_SDOUT GPIOB SA18 (VD[2])
AC_SDOUT 21
PDD10 ACSDO ACRST AC_RST# GPIOC SA16 (VD[0])
AC_RST# 21
PDD11 ACRST
PDD12 8P4R-22R
PDD13
PDD14 PCI_PME#
PCI_PME# 15,19,20 GPI VCC
PDD15 BATLOW#
CPUMISS
22 PDREQ
PDREQ RI# SET
PDDACK# SUSST# R227
22 PDDACK# SUSST# 12
PDIOR# THRMS# X_330R
22 PDIOR# THRMS# 24
PDIOW# EXTSMI# SUSCLK
22 PDIOW# 3VDUAL
PIORDY SMBALRT# RI# POWERF1
22 PIORDY
PDCS#1 ATADET1 CPUMISS RN103
22 PDCS#1 ATADET1 22
PDCS#3 PWRBTN# EXTSMI# 8P4R-4.7KR
22 PDCS#3 PWBTIN# 28
PDA0 PWROK_NB# SUSST# R228
22 PDA0 PWROK_NB# 12
PDA1 CLKRUN# THRMS# RN102 X_1KR
22 PDA1
PDA2 CPUSTP# BATLOW# 8P4R-4.7KR
22 PDA2
IRQ14 PCISTP# PCI_PME#
22 IRQ14
GPO1 Powerf1
SDD[15..0] SDD0 INTRUDER SMBALRT# RN100 0:10/100 LAN(Default Value)
22 SDD[15..0]
SDD1 PWROK_NB# 8P4R-4.7KR 1:GIGA LAN
SDD2 SUSCLK PWBTIN#
SDD3
SDD4 SMBCLK1 GPO0 R235 X_4.7KR
SMBCLK1 7,8,27 Strapping
3 SDD5 SMBDATA1 SUSB# R236 X_4.7KR 3
SMBDATA1 7,8,27
SDD6 SUSC# R231 X_4.7KR
SDD7 SMBCLK2 RN97 *"PDA1/SDA1" => External loop test mode
SDD8 SMBDATA2 ATADET0 0 - Disable (Default)
SDD9 ATADET1 1 - Enable
SDD10 SUSA# SUSA#
SDD11 SUSB# AC_SDIN1 *"PDA2/SDA2" => ROMSIP Select
SUSB# 24,27
SDD12 SUSC# 8P4R-4.7KR 0 - Disable
SUSC# 27
SDD13 1 - Enable(Default)
SDD14 GPI0 RN94 8P4R-4.7KR
SDD15 ATADET0 CLKRUN# *"-SDCS3" => Test Mode Select
ATADET0 22 VCC3
GPO0 PCISTP# 0 - Disable (Default)
SDREQ GPO1 CPUSTP# 1 - Enable
22 SDREQ
SDDACK# GPIOA SERIRQ
22 SDDACK#
SDIOR# GPIOB *"EEDI/-SDCS1" => EEPROM Select
22 SDIOR#
SDIOW# GPIOC TPO 0 - BIOS Porting - ACR
22 SDIOW#
SIORDY GPIOD TEST 1 - External EEPROM (On-board)(Default)
22 SIORDY
SDCS#1
22 SDCS#1
SDCS#3 SERIRQ SPKR
22 SDCS#3 SERIRQ 24
SDA0 SPKR R196 1KR PDA1 VT8237
22 SDA0 SPKR 28
SDA1 APICCLK RN93 8P4R-4.7KR (VD[5])
22 SDA1 APICCLK 7,18
SDA2
22 SDA2
22 IRQ15 IRQ15 TPO
TEST VCC2_5 R194 X_4.7KR PDA2 VT8237
VCC3
C347 X_C0.1U25Y SIDEVREF
VDDA0 (VD[6]) R181 4.7KR
Using external PHY SIDECOMP C330 *"SPKR" => CPU Freq. Adjust Setting
R171 X_360R1% C0.1U25Y
STXP_1 C361 C 1 0 0 0 P 5 0 X STXP1 1 - Disable (Default)
2 STXN_1 C360 C 1 0 0 0 P 5 0 X STXN1 SREXT 0 - Enable (VD[7]) 2
R213 R174 2.7KR PDCS#3 VT8237
SRXN_1 C359 C 1 2 0 0 P 2 5 X SRXN1 SXO 5.36KR1%
SRXP_1 C358 C 1 2 0 0 P 2 5 X SRXP1 VCC3
SXI RN104
STXP_2 C356 C 1 0 0 0 P 5 0 X STXP2 SMBCLK1
STXN_2 C352 C 1 0 0 0 P 5 0 X STXN2 VDDA33 FB17 X_601S SMBDATA1 3VDUAL
VCC3
SMBDATA2
SRXN_2 C353 C 1 2 0 0 P 2 5 X SRXN2 C362 CP15 SMBCLK2
SRXP_2 C351 C 1 2 0 0 P 2 5 X SRXP2 C0.1U25Y
near chipset SXO 8P4R-1KR

SXI
R204 X_4.7KR
VCC3
Y3 25MHZ18P_D-1 R195 4.7KR PDA0 VT8237
(VD[4])
For K8T800Pro
0:External HCLK enable
1:Internal HCLK enable
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
GNDATS
CP14 C363 C367

GNDAS
GNDAS
GNDAS
GNDAS
near chipset C15P50N C15P50N

+2.5VSATA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC2_5
FB16
X_601S SATA1 SATA2
ACSDO R224 4.7KR VT8237
F6
F7
R5
AF12
AF14
AF16
L11
L12
L13
L14
L15
L16
AC14
AD12
AD13
AD14
AD15
AD16
AC16
AC12
M11
M12
M13
M14
M15
K18
AB14
AE12
AE14
AE16
AB16
AB12
K5
P5
J5
C350 C349
C0.1U25Y 0/1:Enable/disable auto reboot
C1U10Y
GNDSATA VIA-VT8237-A2
1 1
STXP_1 STXP_2
STXN_1 STXN_2
VT8237 PDDACK# R 1 9 7 X_10KR
VCC3
1 - Disable external SATA PHY
SRXN_1 SRXN_2 Title Rev
SRXP_1 SRXP_2
VT8235 Part 2 0A
VT8237 PDCS#1 R180 10KR
VCC3
R179 X_10KR
SATA master/slave mode No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
1 - Disable 0 - Enable CONN-SATA_white CONN-SATA_white Taipei Hsien, Taiwan Sheet
A B C D E
A B C D E
RN91
VCC2_5 VSUS2_5 3VDUAL MTXD0 C0.1U25Y CB7
MIITXD0 26
MTXD1 MIITXD1 26 VCC3
MTXD3 MIITXD3 26
MTXD2 MIITXD2 26
M21
M22
M23
M24
M25
M19
N21
N22
N23
N24
N25
N26
N19
D12
K21
P22
P23
P24
P25
P26
P19
E12
E10
E11
L23
L21
L19
D9
E9
12 VLAD[0..7] U13C 8P4R-33R
VLAD0
MIIVCC
MIIVCC
MIIVCC
MIIVCC
MIISUS25
MIISUS25
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VCCVK
VLAD1 MIIMDIO R216 X_1.5KR
MIICRS 26 3VDUAL
VLAD2
4 MIICOL 26 4
VLAD3
VLAD4 MIITXEN R212 X_1KR
MIITXEN 26
VLAD5 MTXD0
VLAD6 MTXD1
VLAD7 MTXD2
MTXD3 EEDI R210 4.7KR
VCC3
MIITXCLK 26
VCC3
MIIRXER 26 "EEDI"=>Eliminate Lan EEPROM 1/0:ENABLE/DISABLE
MIIRXCLK 26
MIIRXDV 26
FERR# R205 1KR
MIIRXD0 26
MIIRXD1 26
APICD0# R203 330R
MIIRXD2 26
VBE0# APICD1# R173 330R
12 VBE0# MIIRXD3 26
APICCLK R193 X_4.7KR
UPCMD ROMLOCK R169 4.7KR
12 UPCMD MIIMDC 26
DNCMD GHI# R170 4.7KR
12 DNCMD MIIMDIO 26
UPSTB AGPBZ#
12 UPSTB
UPSTB# VGATE
12 UPSTB#
EECS VRDSLP
DNSTB EEDO VT8237
12 DNSTB
DNSTB# EEDI
3 12 DNSTB# 3
EECK RN92
VCC2_5 8P4R-4.7KR
VPAR +2.5VRAM R219 X_2.2R
12 VPAR CB12
VLREF_SB X_C1U10Y
GND_RAM
R172 360R1% VCOMPP_SB
FERR#
VCLK A20M#
7 VCLK
IGNNE#
CPUINIT#
INTR R249 1KR
5VSB VBAT
NMI_SB
1
SMI# R248 2.7KR
STPCLK# VIA AN258 JBAT1
D12
-LDTSTOP 5,11
LPC_AD0 GHI# S-BAT54C_SOT23
24 LPC_AD0
LPC_AD1 ROMLOCK
24 LPC_AD1
LPC_AD2 C419
24 LPC_AD2
2
LPC_AD3 VGATE VBAT1 XX
24 LPC_AD3 BAT-2P_SO41 X_C10U10Y1206
SATALED 28
VRDSLP R250
AGPBZ# R247 1KR
1KR
2 LPC_FRAME# 2
24 LPC_FRAME#
LPC_REQ#
24 LPC_REQ#
SBPCLK SBPCLK 7
ALL_PWRGD APICCLK VBAT
27,28 ALL_PWRGD APICCLK 7,17
RSMRST# APICD0# C420
26,27 RSMRST#
APICD1#
CP12 C0.01U50X
VBAT +2.5VSBPLL VCC2_5
CB8
X1 GND_SBPLL C0.1U25Y
X2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC2_5
VLREF_SB =>
K8T800= 0.625V,
W22
W25
T11
T12
T13
T14
T15
T16
T21
R11
R12
R13
R14
R15
R16
R21
AC18
P11
P12
P13
P14
P15
P16
K19
AA21
AB19
AB22
AB25
AE17
AE19
AE22
AE25
AB18
AA10
AA9
VIA-VT8237-A2 K8M800= 0.45V,

Y4 K8T800A= 0.45V
32.768KHZ12.5P_D R192
C339 360R1%
1 C0.1U25Y 1
VLREF_SB Micro Star Restricted Secret
C377 C376 Title Rev
C10P50N C10P50N
Under SB Bottom
CB19 C338
R191 VT8235 Part 3 0A
49.9R1%
X_C0.1U25Y Document Number
V-Link -> MS-7144
C0.1U25Y
LVREF=0.625 No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
Volt http://www.msi.com.tw 18 of 32
A B C D E
5 4 3 2 1
AD[31..0]
PCI Connectors
16,20 AD[31..0]
C_BE#[3..0]
VCC3 VCC3 16,20 C_BE#[3..0] VCC3 VCC3
VCC VCC +12V VCC VCC +12V
-12V -12V
PCI1 PCI2
D D
PIRQ#A PIRQ#B
PIRQ#A 12,15,16,20
PIRQ#B PIRQ#C PIRQ#C PIRQ#D
15,16,20 PIRQ#B PIRQ#C 16,20
PIRQ#D PIRQ#A
16,20 PIRQ#D
3VDUAL 3VDUAL
PCISLOTRST# PCISLOTRST#
PCISLOTRST# 20,27 PCISLOTRST# 20,27
PCICLK1 PCICLK2
7 PCICLK1 7 PCICLK2
PGNT#0 PGNT#1
PGNT#0 16 PGNT#1 16
PREQ#0 PREQ#1
16 PREQ#0 16 PREQ#1
PCI_PME# PCI_PME#
PCI_PME# 15,17,20
AD31 AD30 AD31 AD30
AD29 AD29
AD28 AD28
AD27 AD26 AD27 AD26
AD25 AD25
AD24 AD24
C_BE#3 R183 100R AD19 C_BE#3 R184 100R AD20
AD23 AD23
AD22 AD22
AD21 AD20 AD21 AD20
C AD19 AD19 C
AD18 AD18
AD17 AD16 AD17 AD16
C_BE#2 C_BE#2
FRAME# FRAME#
FRAME# 16,20
IRDY# IRDY#
16,20 IRDY#
TRDY# TRDY#
TRDY# 16,20
DEVSEL# DEVSEL#
16,20 DEVSEL#
STOP# STOP#
STOP# 16,20
PLOCK# PLOCK#
20 PLOCK#
16,20 PERR# PERR# SDONE SDONE 20 PERR# SDONE
SBO# SBO#
SBO# 20
SERR# SERR#
16,20 SERR#
PAR PAR
PAR 16,20
C_BE#1 AD15 C_BE#1 AD15
AD14 AD14
AD13 AD13
AD12 AD11 AD12 AD11
AD10 AD10
AD9 AD9
AD8 C_BE#0 AD8 C_BE#0

AD7 AD7
AD6 AD6
AD5 AD4 AD5 AD4
AD3 AD3
AD2 AD2
AD1 AD0 AD1 AD0
B B
20 ACK64# ACK64# REQ64# REQ64# 20 ACK64# REQ64#
SLOT-PCI SLOT-PCI
N11-1200031-A10 N11-1200031-A10
VCC
3VDUAL
PLOCK# R211 2.7KR
C389
ACK64# R221 2.7KR X_C0.1U25Y
A REQ64# R220 2.7KR A
SDONE R185 2.7KR
SBO# R186 2.7KR

Title Rev
PCI Connector 1 & 2
0A
5 4 3 2 1
5 4 3 2 1
PCI Connectors 16,19 AD[31..0]

AD[31..0]
VCC3 VCC3
C_BE#[3..0] VCC3 VCC3
16,19 C_BE#[3..0]
5VDUAL 5VDUAL
VCC VCC +12V
VCC +12V
-12V
D -12V D
PCI3
PCI4
16 PREQ#4
PGNT#4 16
PIRQ#C
PIRQ#C 16,19
PIRQ#D PIRQ#A PIRQ#D
16,19 PIRQ#D PIRQ#A 12,15,16,19 PIRQ#D 16,19
PIRQ#B PIRQ#A PIRQ#B
15,16,19 PIRQ#B 12,15,16,19 PIRQ#A PIRQ#B 15,16,19
16,19 PIRQ#C PIRQ#C VCC
3VDUAL R232 100R AD23
21 AUXL
21 AUXR
PCISLOTRST#
PCISLOTRST# 19,27 7 PCICLK5 3VDUAL
PCICLK3 PCISLOTRST#
7 PCICLK3
PGNT#2
PGNT#2 16 7 PCICLK4
PREQ#2 PGNT#3
16 PREQ#2 PGNT#3 16
PCI_PME# PCI_PME# 15,17,19 16 PREQ#3 PREQ#3
AD31 AD30 PCI_PME#
AD29 AD31 AD30
AD28 AD29
AD27 AD26 AD28
AD25 AD27 AD26
AD24 AD25
C_BE#3 R214 100R AD21 AD24
AD23 C_BE#3 R233 100R AD22
AD22 AD23
C AD21 AD20 AD22 C
AD19 AD21 AD20
AD18 AD19
AD17 AD16 AD18
C_BE#2 AD17 AD16
FRAME# C_BE#2
FRAME# 16,19
IRDY# FRAME#
16,19 IRDY#
TRDY# IRDY#
TRDY# 16,19
DEVSEL# TRDY#
16,19 DEVSEL#
STOP# DEVSEL#
STOP# 16,19
19 PLOCK# PLOCK# STOP#
PERR# SDONE PLOCK#
16,19 PERR# SDONE 19
SBO# PERR#
SBO# 19
SERR#
16,19 SERR#
PAR SERR#
PAR 16,19
C_BE#1 AD15 PAR
AD14 C_BE#1 AD15
AD13 AD14
AD12 AD11 AD13
AD10 AD12 AD11
AD9 AD10
AD9
AD8 C_BE#0
AD7 AD8 C_BE#0
AD6 AD7
AD5 AD4 AD6
AD3 AD5 AD4
AD2 AD3
AD1 AD0 AD2
B B
AD1 AD0
ACK64# REQ64#
19 ACK64# REQ64# 19
ACK64# REQ64#
SLOT-PCI
N11-1200031-A10 SLOT-PCI_orange
N11-1200161-K06
3VDUAL
VCC3
C334
C325 C263 C332 X_C0.1U25Y
A A
X_C0.1U25Y X_C0.1U25Y X_C0.1U25Y

Title Rev
PCI Connector 3 & 4
0A
5 4 3 2 1
5 4 3 2 1
AUDIO CODEC LINE_NEXT_R
LINE_OUT
LINE_NEXT_L
C216 C215
VCC3 AUDIO1A
C402 C1000P50X C1000P50X JACK-EARX3-13P
CODEC VCC3_3 NEED CAP
AS CLOSE AS POSSIBLE.
C0.1U25Y
D D
+5VR
C405
LINE_IN_R
C0.1U25Y
U15 LINE_IN
LINE_IN_L
C218 C217
AUDIO1B
C399 C1000P50X C1000P50X JACK-EARX3-13P
X_C10P50N C 4 0 3 C10U10Y0805 LINE_OUT_R
C404 C10U10Y0805 LINE_OUT_L

7 AC_14
C401 FR_MICIN
C1U10Y
17 AC_SDOUT VREFOUT
17 AC_BITCLK R234 33R R76 4.7KR
17 AC_SDAIN0
VREFOUT MICIN2
17 AC_SYNC MIC_IN
17 AC_RST#
MICIN1
+ EC33 C387 C392 C388 C394 C396 C400
C397
C1U10Y X_C1U10Y C214 C219
C386 C10U16EL C1U10Y C1U10Y C1000P50X VREFOUT R75 4.7KR AUDIO1C
C0.1U25Y C1000P50X C1000P50XC1000P50X JACK-EARX3-13P
C X_COPPER C
For EMI CP25
ALC655 X_C4.7U10Y0805
C383 LINE_IN_R
C1U16Y0805
C382
20 AUXL
C1U16Y0805 C384 LINE_IN_L
C552
X_C0.1U25Y C1U16Y0805
20 AUXR C381
C1U16Y0805
C553
X_C0.1U25Y
C370 MICIN2
C1U16Y0805
C371 MICIN1
C1U16Y0805
C372
C1U16Y0805 J1
AUDIO-CDIN1X4
C373
C1U16Y0805
B B
C374 JCD
C1U16Y0805
FR_MICIN R244 X_0R S
+5VR
C414
C413 X_C1000P50N
JAUDIO
R246 C1000P50N JAUD1
FR_MICIN
+12V +5VR 4.7KR
S
+5VR
U17
R245 LINE_OUT_R LINE_NEXT_R
CP26 X_COPPER
X_4.7KR CUT 8
C555
C554 C556
X_C0.1U25Y X_C0.1U25Y R307 X_0R LINE_OUT_L LINE_NEXT_L
C10U10Y0805
MC78L05ACP_TO92 C418 C415
A R308 X_0R XX A
C416 C417
X_C1000P50N
X_C1000P50N X_C1000P50N
X_C1000P50N
Title Rev
C-MEDIA 9739A CODEC
0A
5 4 3 2 1
5 4 3 2 1
ATA 33/66/100 Connector 17 PDD[15..0]

PDD[15..0]
SDD[15..0]
17 SDD[15..0]
PRIMARY IDE CONN.

R64
HDDRST#
27 HDDRST# RN77 8P4R-22R0402 RN74 8P4R-22R0402
IDE1
33R SDA0 SDA0_R IRQ14 IRQ14_R
17 SDA0 17 IRQ14
PDD_7 PDD_8 17 SDA2 SDA2 SDA2_R 17 PDDACK# PDDACK# PDDACK#_R
D D
PDD_6 PDD_9 SDCS#1 SDCS#1_R PIORDY PIORDY_R
17 SDCS#1 17 PIORDY
PDD_5 PDD_10 SDCS#3 SDCS#3_R PDIOR# PDIOR#_R
17 SDCS#3 17 PDIOR#
PDD_4 PDD_11
PDD_3 PDD_12
PDD_2 PDD_13 RN80 8P4R-22R0402
PDD_1 PDD_14 SIORDY SIORDY_R RN78 8P4R-22R0402
17 SIORDY
PDD_0 PDD_15 SDDACK# SDDACK#_R PDIOW# PDIOW#_R
17 SDDACK# 17 PDIOW#
IRQ15 IRQ15_R PDREQ PDREQ_R
17 IRQ15 17 PDREQ
PDREQ_R SDA1 SDA1_R PDD0 PDD_0
17 SDA1
PDIOW#_R PDD15 PDD_15
PDIOR#_R R52
PIORDY_R RN82 8P4R-22R0402
PDDACK#_R SDD15 SDD_15
IRQ14_R 470R SDD0 SDD_0
PDA1_R ATADET0 SDD14 SDD_14
PDA0_R PDA2_R SDD13 SDD_13
PDCS#1_R PDCS#3_R
IDEACTP#
28 IDEACTP# RN85 8P4R-22R0402 PDCS#1 R176 2 2 R 0 4 0 2 PDCS#1_R
17 PDCS#1 R175 2 2 R 0 4 0 2 PDCS#3_R
CONN-IDE(20)_yellow SDD9 SDD_9 PDCS#3
17 PDCS#3
N32-2201091-H06 SDD6 SDD_6
SDD8 SDD_8
SDD7 SDD_7
SECONDARY IDE CONN. RN75 8P4R-22R0402

PDD14 PDD_14
PDD1 PDD_1
R143
HDDRST# PDD13 PDD_13
27 HDDRST#
C IDE2 PDD7 R200 22R0402 PDD_7 PDD2 PDD_2 C
33R
PDD8 R199 22R0402 PDD_8
SDD_7 SDD_8
SDD_6 SDD_9
SDD_5 SDD_10
SDD_4 SDD_11
SDD_3 SDD_12 RN81 8P4R-22R0402
SDD_2 SDD_13 PDD10 PDD_10
PDD6 PDD_6
SDREQ_R RN84 8P4R-22R0402
SDIOW#_R SDD11 SDD_11
SDIOR#_R R81 SDD4 SDD_4
SIORDY_R SDD10 SDD_10
SDDACK#_R SDD5 SDD_5 RN76 8P4R-22R0402
IRQ15_R 470R PDD12 PDD_12
SDA1_R ATADET1 PDD3 PDD_3
SDA0_R SDA2_R RN79 8P4R-22R0402 PDD11 PDD_11
SDCS#1_R SDCS#3_R PDD4 PDD_4
IDEACTS# 17 SDIOR# SDIOR# SDIOR#_R
28 IDEACTS#
SDIOW# SDIOW#_R
17 SDIOW#
CONN-IDE(20)_yellow SDREQ SDREQ_R
17 SDREQ
N32-2201091-H06
RN83 8P4R-22R0402
SDD1 SDD_1 RN73
VCC SDD2 SDD_2
SDD12 SDD_12 PDA2 PDA2_R
17 PDA2
SDD3 SDD_3 PDA0 PDA0_R
B 17 PDA0 B
IDEACTP# R35 10KR PDA1 PDA1_R
17 PDA1
IDEACTS# R66 10KR 8P4R-22R0402
ATADET1
17 ATADET1
Near SB < 1" ( or Damping Rs) ATADET0
17 ATADET0
PIORDY_R R53 4.7KR PDREQ_R R198 5.6KR
SIORDY_R R108 4.7KR SDREQ_R R115 5.6KR
IRQ14_R R48 10KR PDD7 R202 10KR
IRQ15_R R105 10KR SDD7 R209 10KR
A A

Title Rev
ATA 33/66/100 Connector
0A
5 4 3 2 1
5 4 3 2 1
V_FUSB1
5VDUAL FS1 F-MINISMDC110
V_FUSB2
FRONT USB PORT +

FS2 F-MINISMDC110
C409
EC36
.CD1000U6.3EL15 R238 X_C0.1U25Y
47KR
USB_OC#5
D 16 USB_OC#5 D
C408 R239
56KR
C0.1U25Y
L8 JUSB2
X_CMC-L02-9008014-T34
USBN4 <Priority> USB_D4- USB_D5-
16 USBN4
16 USBP4 USBP4 USB_D4+ USB_D5+
USBN5 USB_D5-
16 USBN5
USBP5 USB_D5+ USB_OC#5
16 USBP5
L9 H2X5(9)_yellow
X_CMC-L02-9008014-T34 N31-2051131-P05
<Priority>
USB 2.0 PIN HEADER

(BLUE)
L6 JUSB1
X_CMC-L02-9008014-T34 V_FUSB1
USBN1 <Priority> USB_D1- USB_D0-
16 USBN1
USBP1 USB_D1+ USB_D0+
16 USBP1
USBN0 USB_D0-
16 USBN0
USBP0 USB_D0+ USB_OC#5
16 USBP0
C L7 H2X5(9)_yellow C
X_CMC-L02-9008014-T34 N31-2051131-P05
<Priority> USB 2.0 PIN HEADER
(BLUE)
KBVCC
STACKED USB CONNECTOR
REAR USB PORT 5VDUAL KBVCC
C171 R255 0R1206

R58 + EC16 R256 0R1206
47KR X_C0.1U25Y
USB_OC#1 .CD1000U6.3EL15
16 USB_OC#1
CP17 X_COPPER FS3 X_F-MINISMDC150
R61
C180 56KR CP16 X_COPPER R56
C162
C0.1U25Y
C0.1U25Y X_47KR
_CONN-RJ45_USBX2_LEDX2-20-30u-in
B L5 B
X_CMC-L02-9008014-T34 USB_D6- USB1

<Priority> USB_D6+
16 USBN6
16 USBP6 UP
16 USBN7
USB_D7- L3
16 USBP7
USB_D7+ X_CMC-L02-9008014-T34
L4 DOWN USBN3 <Priority> USB_D3- USB_D2-
16 USBN3
X_CMC-L02-9008014-T34 USBP3 USB_D3+ USB_D2+
16 USBP3
<Priority> LAN_USB1A USB_D2-
16 USBN2
CP23 X_COPPER USB_D2+
16 USBP2
CP24 X_COPPER L2
X_CMC-L02-9008014-T34
<Priority>
CONN-USBX2
X_COPPER
For EMI CP22
A CP21 A
X_COPPER

CP3
X_COPPER Title Rev
USB Port
0A
PGND MICRO-STAR INT'L CO.,LTD. Last Revision Date:
5 4 3 2 1
5 4 3 2 1
Super I/O SYSTEM ROM

VCC3
VCC3
FLOPPY DISK HEADER
U12
VCC3
PCIDEVRST# LPC_PCLK
LPC_PCLK 7
FDD1 PRES3 PRES4
R168 U10 PRES2
4.7KR DRVDEN0 PRES1
12,27 PCIDEVRST#
PRES0
7 SIOPCLK
INDEX# BIOS_WP#
17 SERIRQ
18 LPC_REQ# MOA# TBL#
D D
LPC_INIT#
18 LPC_FRAME#
DSA# LPC_FRAME#
18 LPC_AD0
DIR#
18 LPC_AD1
STEP# LPC_AD0
18 LPC_AD2
WRDATA# LPC_AD1
18 LPC_AD3
WE# LPC_AD2
TRACK0# LPC_AD3
WP#
RDDATA#
HEAD# PLCC-32
DSKCHG# <Priority>
default is high RN86 8P4R-1KR
PD0 CONN-FDD(4)(5)(6)V PRES4 PRES0
VCC3 VCC3
PD1 N32-2173021-H06 PRES3 BIOS_WP#
PD2 PRES2 TBL#
R190 X_10KR PD3 PRES1 LPC_INIT#
VCC
PD4
VREF PD5 RN87 8P4R-1KR
SIO
PD6
THERMDA_CPU PD7
Hardware Monitor
5 THERMDA_CPU
VTIN1
RSLCT 25
RPE 25 PD[7..0] 25
RBUSY 25
RACK# 25 SYSTEM Thermal RT1
RSLIN# 25 R178
VREF
RINIT# 25
VCC3 RERR# 25 VCC3
10KR1% 10KRT1%
RAFD# 25
C VCC SMD C
VCORE RSTB# 25
C328
RN72 8P4R-4.7KR VTIN1 C0.1U25Y
CTSB#
DSRB# R187
GP40 DCDB# THERMDA_CPU
RIB#
30KR1%
DCDA# 25
CPU_FAN_PWM
DSRA# 25
FANIO1
SINA 25
RTSA# +12VA
RTSA# 25
FANIO2 SOUTA
SOUTA 25
R188 0R
17 THRMS# CTSA# 25
DTRA#
DTRA# 25
RIA# 25
Q3
CHASISS DCDB# N-P3055LD_TO252
DCDB# 25
DSRB#
DSRB# 25
SINB 25
R259
RTSB# 25
SOUTB C469 X_0R0805
SOUTB 25
CTSB#
CTSB# 25
X_C0.01U50X
DTRB# 25
RIB#
RIB# 25 U16
CPU_FAN_PWM
R260 CPU_FAN_CTRL
5VSB
+12VA
C470 C0.1U25Y 10KR
17,27 SUSB#
R261
B 7 SIO48M B
6.49KR1%
BEEP C472
C306 C0.1U25Y C471
VBAT
BIOS_WP#
C0.1U25Y C0.1U25Y W83391TS
VCC3
C319
X_C0.1U25Y
C320
Fan Connector
C0.1U25Y
+12VA
THERMDC_CPU +12V
THERMDC_CPU 5
W83627THF
VCC
CP13
X_COPPER
Power-on strap, enable 48MHz SYSTEM FAN R3

R80
4.7KR
4.7KR
CPU FAN
VCC
R5
R167 R84 27KR FANIO2 FANIO1
SOUTB
27KR
R83
4.7KR SFAN1 CFAN1 R6
10KR
10KR
CPU_FAN_CTRL
Distribute near the VCC VCC Chasiss Intrusion Header + EC1

power pin of the LPC SOUTA L: Disable KBC H: Enable KBC + FAN1X3_white X_C10U16EL FAN1X3_white
SOUTB L: 24MHZ H: 48MHZ VBAT EC24 N32-1030011-H06 N32-1030011-H06
A VCC RTSA# L: CFAD=2E H: CFAD=4E C10U16EL A
DTRA# L: PNP Default H: PNP no Default R148
10KR R164
RN68 8P4R-4.7KR 2MR
ALARM 28
RTSA# Micro Star Restricted Secret
DTRA#
C307 C333 C326 SOUTA BEEP Q25 CHASISS Title Rev
X_C0.1U25Y VCC
GP40 N-MMBT3904_SOT23 JCASE1 LPC I/O & ROM & Floppy&Fan
0A
X_C0.1U25Y X_C0.1U25Y Document Number MS-7144
H1X2_black MICRO-STAR INT'L CO.,LTD. Last Revision Date:
5 4 3 2 1
5 4 3 2 1
LPT / COM PORTS VCC

For EMI
CN4
Keyboard/Mouse Ports
RACK#
RBUSY
RPE
D4 RSLCT
KBVCC
1N4148_SOD123 8P4C-180P50N
CN7
RSTB# R33 4.7KR RAFD#
24 RSTB#
RINIT#
RN11 RERR#
D D
RACK# RSLIN# STACKED PS2 CONNECTOR
24 RACK#
RBUSY EC3 +
24 RBUSY
RPE 8P4C-180P50N C18 C5 JKBMS1
24 RPE
RSLCT X_C10U16EL X_C0.1U25Y C0.1U25Y
24 RSLCT
CN6
8P4R-4.7KR PD0
PD1
RN25 PD2 PGND PGND PGND
RAFD# PD3
24 RAFD# For EMI
24 RINIT# RINIT#
RERR# 8P4C-180P50N
24 RERR#
RSLIN#
24 RSLIN#
CN5
8P4R-4.7KR PD4 R303 X_0R
16 KBDAT#
PD5
RN22 PD6
8P4R-4.7KR PD7
PD0
PD1 8P4C-180P50N
PD2
PD3 RSTB# R304 X_0R
16 KBCLK#
PD4
PD5 C84 C180P50N PGND PGND
PD6 CONN-KB_MS
PD7 N56-12F0031-F02
PGND
RN15
PD[7..0] 8P4R-4.7KR R305 X_0R
24 PD[7..0] 16 MSCLK#
C CP18 X_COPPER C
CP19 X_COPPER
C304 R306 X_0R
16 MSDAT#
C0.1U25Y
D11 U7
+12V +12VCOM CP20 X_COPPER
VCC
1N4148_SOD123
RTSA# NRTSA
24 RTSA#
DTRA# NDTRA PGND
24 DTRA# KBVCC
24 SOUTA SOUTA NSOUTA
RN4 CN1
RIA# NRIA# LPT1 MSDAT# KBCLK#
24 RIA#
24 CTSA# CTSA# NCTSA# KBDAT# MSCLK#
DSRA# NDSRA# MSCLK# KBDAT#
24 DSRA#
24 SINA SINA NSINA KBCLK# MSDAT#
24 DCDA# DCDA# NDCDA# R11
8P4R-4.7KR X_330R 8P4C-180P50N
D10
-12V -12VCOM PGND
1N4148_SOD123 GD75232_SSOP20
C272 I95-7523212-T07 RSLCT
X_C0.1U25Y
RPE SERIAL PORT 2
B Multiple RS232 Drivers and Receivers RBUSY B
U8 C303 C0.1U25Y
RACK# +12VCOM
VCC
PD7
CN3 RTSB# NRTSB
PD6 24 RTSB#
COM1 NRTSA DTRB# NDTRB
24 DTRB#
NDSRA# SOUTB NSOUTB
PD5 24 SOUTB
NDCDA# NDSRA# NCTSA#
NSINA NRTSA NRIA# RIB# NRIB#
PD4 24 RIB#
NSOUTA NCTSA# 24 CTSB# CTSB# NCTSB#
NDTRA NRIA# 8P4C-180P50N 24 DSRB# DSRB# NDSRB#
PD3 SINB NSINB
24 SINB
PGND RSLIN# DCDB# NDCDB#
24 DCDB#
CONN-COM PD2
N51-09M0021-F02 RINIT#
CN2 PD1 -12VCOM
NDCDA# RERR# C282 C0.1U25Y
NSINA PD0
PGND NSOUTA RAFD# GD75232_SSOP20
NDTRA RSTB#
8P4C-180P50N JCOM1
RESVD NDCDB# NSINB
NSOUTB NDTRB
L1 X_80S/1206 NDSRB#
NRTSB NCTSB#
NRIB#
A COM-D9-GN A
PGND
CONN-LPT NRTSB
N51-25F0041-F02 NDSRB# CN9 Micro Star Restricted Secret
NCTSB# 8P4C-180P50N
CP1 X_COPPER NRIB# Title Rev
KeyBoard/Mouse/LPT/COM
NDCDB# 0A
PGND NSOUTB CN8 Document Number MS-7144
NSINB 8P4C-180P50N
NDTRB MICRO-STAR INT'L CO.,LTD. Last Revision Date:
5 4 3 2 1
A B C D E
REALTEK 8201CL MII PHY

VDD25
C239
C0.1U25Y
RN65 U5
MIIRXD3 RXD3 MX1+
18 MIIRXD3
MIIRXD2 RXD2 MIIMDC MX1-
18 MIIRXD2 18 MIIMDC
MIIRXD1 RXD1 MIIMDIO MX0-
18 MIIRXD1 18 MIIMDIO VDD33
4
18 MIIRXD0 MIIRXD0 RXD0 18 MIITXD0 MIITXD0 MX0+ 4
MIITXD1 C238
18 MIITXD1
8P4R-33R MIITXD2 C244 R92 R94
18 MIITXD2
MIITXD3 C0.1U25Y R91
18 MIITXD3
MIITXEN C10U10Y1206 R93
18 MIITXEN
MIITXCLK R111 X_22R 49.9R1% 49.9R1%
18 MIITXCLK
MIIRXDV 49.9R1% 49.9R1%
18 MIIRXDV
RXD0
RXD1
MIIRXCLK R104 X_22R RXD2 GND shielding
18 MIIRXCLK
RXD3
MX1+
EMI X_C0.1U25Y Near C259 C250 MIICOL MX1- C234 C235
18 MIICOL
C406 X_C10P50N MIICRS
VCC3 VCC Controler X_C10P50N
18 MIICRS C0.01U50X
MIIRXER C0.01U50X
18 MIIRXER
MX0-
MX0+
Y1 R112 5.1KR ACTLED

VDD33 NET1 R95
NET2 2KR
C248 C249 AAA SPDLED NET3
C20P50N 25MHZ18P_D-1C20P50N SPDLED AAA NET4 VDD25
RN66 8P4R-4.7KR NET5
NET6
VDD25
NET7 _CONN-RJ45_USBX2_LEDX2-20-30u-in
DVDD33 NET8 SPDLED R57 330R AMBER+
PHY address to C260 AMBER-
RSMRST# 18,27
NC
00001b. C0.1U25Y 3VDUAL NC
3
MX1- RDN 3
NC
RTL8201CL NC
VDD33 R63 C179 MX1+ RDP
X_COPPER NET3 330R MX0- TDN
X_C0.1U25Y
CP8 NET4 MX0+ TDP
3VDUAL
NET5 GREEN+
VDD33 NET6 ACTLED
GREEN-
C261
C0.1U25Y C252 C257 NET8 ACT FAIL WHEN 2 PC Connect C187 C192 LAN_USB1B
VDD33
C243 C241 X_C1U10Y X_C10U10Y1206 NET2
C10U10Y0805 X_C0.1U25Y NET7 C1000P50X X_C1000P50X
GND
Use K8T800Pro remove all

components
VCC
VGA CONNECTOR
F1
VCC
D6 F-MICROSMD110
2
POLY SWITCH 2
VCC
AB
AG VVSYNC
AR VHSYNC CB4 JVGA1
_Z-PACDND006M_MSOP8 C0.1U25Y
R44 R37
FB5 30L500m_200 1.8KR 1.8KR
12 AR
FB4 30L500m_200
12 AG DDCDATA 12
FB3 30L500m_200
12 AB
R49 R50 R51 C130 C131 C132 C124 C118 C112

75R 75R 75R X_C22P50N
DDCCLK 12
X_C22P50N
X_C22P50N C33P50N C22P50N C22P50N
CONN-VGA
VCC
R39
4.7KR
R40 22R VVSYNC R38 0.082U300m

1 12 VSYNC 1
R42 Micro Star Restricted Secret

4.7KR
VCC Rev
Title
12 HSYNC
R45 22R VHSYNC R41 0.082U300m REALTEK 8201BL MII PHY
0A
C101 C96 Document Number MS-7144
Trace Note:
1.The 5V traces should be 20 mils to VGA/DFP C22P50N C22P50N MICRO-STAR INT'L CO.,LTD. Last Revision Date:
A B C D E
8 7 6 5 4 3 2 1
5VSB
R120
5VSB LINEAR MODE
330R
R132
28 PLED1
3VSB MODE SELECT R131 X_1KR
3VSB MODE 3VDLDEC# Q20 3VDLDEC#
N-MMBT3904_SOT23
SINGLE MOSFET PULL HIGH 4.7KR VCC2_5 3VDUAL 3VDUAL
D D
R123
DUAL MOSFET PULL LOW 10KR THESE OUTPUT AND INPUT PIN MUST
BE PULL HIGH
R106 R122
R121
330R 330R
5VSB 10KR
CPU PWR_GD OUTPUT
CPU_GD 5
CHIP PWR_GD OUTPUT
ALL_PWRGD 18,28
5VSB I2C BUS
SMBCLK1 7,8,17
R134 I2C BUS
SMBDATA1 7,8,17
CONNECT TO SOUTH BRIDGE RSMRST# SIGNAL
330R RSMRST# 18,26
SOUTH BRIDGE POWER CONTROL(SLP_S4# OR SUSB#) SIGNAL
SUSC# 17
R133 SOUTH BRIDGE POWER CONTROL(SLP_S3# OR SUSC#) SIGNAL
28 SUSLED SUSB# 17,24
ATX POWER OK INPUT 5VSB
X_1KR PW_OK 28
R125
Q21 EXTRAM
.CD1000U6.3EL15
N-MMBT3904_SOT23
VDIMM LINEAR OR PWM SELECT 4.7KR 5VSB +
EC35
VDIMM MODE EXTRAM R124 VCC Q32
10KR
LINEAR REGULATOR PULL LOW
VCC
PWM REGULATOR PULL HIGH C271 5VDUAL
C0.1U25Y NN-P07D03LV_SO8
.CD1000U6.3EL15
+
PCISLOTRST# PCIDEVRST#
EC32
C C
C255 C265 VCC VCC3 U6
C22P50N C33P50N
R118
R117 CHARGE PUMP
330R 220R0805 VOLTAGE
C270 9VSB OUTPUT
FRONT PANEL RESET BUTTON C421 X_C22P50N
7,28 FP_RST#
PCIRST# INPUT C268 VCC3
15,16 PCIRST#
C0.1U16X C422 X_C22P50N
22 HDDRST#
PCIRST# BUFFER OUTPUT 12,24 PCIDEVRST#
5VSB_DRV C1U16Y0805
14 PG_VCORE
5V_DRV Q16
14 VCORE_EN
1.25VREF
N-P3055LD_TO252
VCC
PCI SOLT PCIRST# BUFFER OUTPUT R110 33R
19,20 PCISLOTRST#
VCC3 VDDQ
VDD
VDDA_25
THRM# 5
1.25VREF EC29 C269 C254C262 Q15
+
(MS-6-RBF)
.CD1000U6.3EL15
CONNECT TO CPU +
5VSB 5VSB X_.CD100U16EL11
C4.7U10Y0805 N-APM2054N_SOT89
C0.1U25Y
C 0 . 1 UC205. Y
1U25Y R107 R116 R113
C468
EC28
CLOSE TO CHIP 10KR X_10KR 10KR
VDD_12_A
R102 R101
4.7KR 10KR
VCC2_5 5VSB +
B 28 PS_OUT# B
EC23
WATCHING DOG TIMER SELECT .CD1000U6.3EL15
C246 C0.22U10X WD_DET TIMER
C247 PULL LOW OFF

5VSB THE TWO MODE ONLY ONE MODE PRESENT
C0.1U25Y
C242 PULL HIGH ON
SINGLE MODE DUAL MODE
C0.1U25Y
CONNECT TO SOUTH BRIDGE SUSB# SIGNAL R103

C245
X_C10U10Y1206 THIS MODE SELECT BY PIN THIS MODE SELECT BY

17,24 SUSB#
Q19 47 PULL HIGH 5VSB PIN 47 PULL LOW
4.7KR N-MMBT3904_SOT23
3VSB REGULATE BY 5VSB AND VCC3
THE VDIMM_HSEN IN LINEAR MODE
THE TWO BLOCK CHOICE ONE R100 4.7KR
DDRTYPE VDIMM_HSEN VCC3
SUPPORT SYSTEM POWER CONTROL VCC3 VREF
DDR AND DDR II VOLT SELECT EC25 .CD1000U6.3EL15
N-P3055LD_TO252
+
DDR 2.0V
DDRTYPE VDIMM Q17 3VDUAL Q30 5VSB
DDR II 1.7V
PULL LOW 2.5V 5V_DRV
DDR TERMINATION
PULL HIGH 1.8V 3VSB_DRV
R99 R98
R87 100R1%
VDD_25_SUS NN-P07D03LV_SO8
3VDUAL 2.2KR1% 1KR1%
.CD1000U6.3EL15
+
U3 R85 100R1%
VTT_DDR_SUS Q18
EC34
A VDD_25_SUS A
N-P3055LD_TO252
C1U16Y0805
EC27
W83310DS_SOIC8 Micro Star Restricted Secret

EC9
EC2
.CD1000U6.3EL15
.CD1000U6.3EL15
.CD1000U6.3EL15
.CD1000U6.3EL15
.CD1000U6.3EL15
C230
+ + + + +
EC22
EC26
C236 C232 Title Rev

C0.1U25Y C0.1U25Y ACPI POWER CONTOLLER (MS-6) 0A
THIS POINT VOLT CAN'T SETTING
BELOW 2.9V Document Number MS-7144
8 7 6 5 4 3 2 1
5 4 3 2 1
FRONT PANEL System Voltage Regulator

VCC
330R HDD+
R243 VCC VCC2_5

D D
U11
LT1087S_SOT89
For MSI / Intel Front Panel
JFP1
H2X5(10)_black-N31-2051231
C329
N31-2051231-H06 +
VCC3 X_C0.1U25Y
R182 EC31
PLED1 .CD1000U6.3EL11.5
360R1%
HDDLED SUSLED
R240
4.7KR PWRSW R242 100R
PWBTIN# 17
R241 100R C411 R177
7,27 FP_RST#
C0.1U25Y
390R1%
C410
X_C0.1U25Y
7,27 CLK_RESET#
D5
SUSLED VCC3
27 SUSLED IDEACTP# 22
PLED1 EC30
27 PLED1 1N4148_SOD123
+
C VCC C
.CD1000U6.3EL15
D8
JFP2 HDDLED
IDEACTS# 22
H2X4(7)_color-N31-2041101
N31-2041101-H06 1N4148_SOD123 3VDUAL 3VDUAL
D9
R229 VSUS2_5
SATALED 18
R208
24 ALARM
1N4148_SOD123 49.9R1% R96
220R0805
R67 4.7KR 200R1% VSUSNB
VCC
VDDQ VDD
R230
Q31
17 SPKR
N-MMBT3904_SOT23
1KR C395 R88
X_C0.1U25Y R207 C342 390R1%
200R1% C10U10Y0805
B
ATX Power Connector POWER OK Circuits B
VCC3
3VDUAL VSUS2_5
VCC
VCC3 R146
JWR1 R145
4.7KR
4.7KR
-12V -CPURST 5
R62
PS_OUT# VCC 4.7KR Q24
27 PS_OUT#
N-MMBT3904_SOT23
R144
Q22
18,27 ALL_PWRGD
PW_OK
-5V PW_OK 27 1KR
C205 N-MMBT3904_SOT23
5VSB
X_C1000P50N
VCC +12V
PWR-ATX20 R147
C173 Q23
11 -LDTRST
C190
C0.1U25Y C0.1U25Y 1KR N-MMBT3904_SOT23
A A

Title Rev
System Regulator&Front Panel
0A
5 4 3 2 1
5 4 3 2 1
BULK / Decopuling ATX VIA-Hole * 9

VCC
VCC3
Place on CPU Solder side
VCORE MH2
C137 C208 C169 C331 C407 C355
C226 C368 C345 C390 MH5
X_C0.1U25Y C1000P50X C0.1U25Y X_C0.1U25Y C 0 . 1 U 2 5 Y C1000P50X
C433 C69 C0.1U25Y X_C0.1U25Y C0.1U25Y X_C0.1U25Y
D D
X_C0.22U16Y C0.01U50X
VCC VCC
C559 C560
VCC3 X_150 Drill / 300 Pad-0

X_C1000P50X X_C1000P50X
X_150 Drill / 300 Pad-0
VCC3
MH4
C341
C558 MH3
C0.1U25Y
C380 C223 C336 C344
C0.1U25Y C0.1U25Y X_C0.1U25Y C0.1U25Y

X_C0.1U25Y
VCC
X_150 Drill / 300 Pad-0

VCC3
VCC
MH6 X_150 Drill / 300 Pad-0

VCC3
C557
C412 C26 C327
C C0.1U25Y C0.1U25Y C0.1U25Y C
X_C0.1U25Y
MH1
CPU VCC2_5
X_150 Drill / 300 Pad-0
Place on inside of CPU Cavity ( 10 * EMI

C459
0.22uF/0603 X7R high-freq decoupling Cap. )
VCC3 VCC2_5
For EMI X_C0.1U25Y

X_150 Drill / 300 Pad-0
PGND
SYSTEM
5VSB
VCC
B B
C175 C378
C385 C293
X_C0.1U25Y X_C0.1U25Y
C0.1U25Y X_C0.1U25Y
Buck-decoupling Mid-Freq. decoupling Cap.

( 7 * 4.7uF / 0805 , 4*10uF/1206)
VCC3
VCORE
C10U10Y1206
C10U10Y1206 X_C10U10Y1206 X_C10U10Y1206 C357
C335 C379 C375 C224 C391
C83 C97 C92 C78 C427 C430 C434
X_C0.1U25Y C0.1U25Y X_C0.1U25Y X_C0.1U25Y
C10U10Y1206 C104 X_C0.1U25Y C0.1U25Y
X_C1U25Y1206
X_C10U10Y1206 X_C10U10Y1206
+12V
3VDUAL
+12V -12V -5V VCC3
C168
C398 C348 C354 C222 C184 C393
X_C0.1U25Y X_C0.1U25Y C0.1U25Y C0.1U25Y C0.1U25Y

A X_C0.1U25Y C0.1U25Y A
VCC

FM3 FM2 FM8 FM4 FM1 FM6 FM7 FM5
Impedance Test Title Rev
VCC BULK / Decopuling
T2 T1 0A
X_FM X_FM X_FM X_FM X_FM X_FM X_FM X_FM
F_PAD_M120 X_YJ102 X_YJ102 No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
5 4 3 2 1
5 4 3 2 1
K8 CPU Power NB & SB & AGP Power Other Power

CPU Side DDR Side
NB & SB Core-Power
K8 Vcore ->
DDR Power -> -> "VCC2_5" (?A)
"VCORE" (60A) 5VDUL DDR_3VDUAL
"VDD_25_SUS"
D (9.5A) NB & SB Core-Suspend D
VDDA_2.5 Power ->

Power -> "VSUS2_5" (?A)
"VDDA_25" (0.11A)
DDR-VTTPower -> 3VDUL 9VSB
"VTT_DDR_SUS" NB AGP8X Power ->
HT Power ->
(5.21A) "VDDQ" (1.5A)
"VDD_12_A"&"VLDT0"
(2A)
ATX Power
Supply
C +5VSB VSUS2_5 C
5VDUAL 3VDUAL
-> SB
( Q36.5) ( Q35.3 ) ( Q22/S )
VCC
Charge Pump
-> 9VSB
MS-6.34
VCORE ->
+12V K8 CPU
B ( CHOK2/2 ) DDR_25_SUS B
+5VR -> -> DDR

( Q13/S )
Audio
( U21/2 )
VCC1_8 ->
SATA VTT_DDR_SUS
( VR1/2 )
-> DDR
VDDA_25 -> ( Q8/4 )
VCC3 K8 CPU(I/O)
FB2
VDDQ ->
A A
AGP
( Q28/S )
VCC1_5 -> Title Rev
VDD_12_A Power Generation
-12V NB & SB 0A
-> HT Document Number MS-7144
( VLINK ) ( Q19/1 ) MICRO-STAR INT'L CO.,LTD. Last Revision Date:
( Q21/S ) No. 69, Li-De St, Jung-He City, Wednesday, November 10, 2004
5 4 3 2 1
5 4 3 2 1
Ver. 00A 2004/06/27

New SPEC(Copy from 7032-10A)
D D
C C
B B
A A

Title Rev
History
0A
5 4 3 2 1
5 4 3 2 1
U4-F U4-H
PCB1
MSI MSI
VBAT1_X
D D
7144-00A BAT-BCR2032P
DDR DDR
D06-0100101-P01
P50-071440A-T53 _E31-0400310
X_NB-HEATSINK-W/Fan
? E31-0400310-K08
U12_X
_W39V040A
M31-39V0418-W03
U2_1 U2_2
C C
CPU_RM CPU_RM
B B
A A

Title Rev
OPTION PART
0A
5 4 3 2 1

MS-7144 Ver:00a Atx

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MS-7144 Ver:00a Atx

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5 4 3 2 1

MS-7144 VER:00A ATX Title Page

*VIA K8M800 /K8T800 Pro GPIO SPEC 3

Front and Rear USB Port 23

System Regulator&Front Panel

Nhat Tin Decoupling Cap. 29

ou, OPTION PARTS 32

10:56:24 +07'00' Title

Wednesday, November 10, 2004

CPUCLK+ & CPUCLK-(100/133/166/200) AMD K8 Socket 754

HCLK+ & HCLK-(100/133/166/200) / GCLK(66)

Dual ATA 100/133

SUPER I/O ROM

Dual USB 1.1 OHCI

GPIO FUNCTION PCI Routing

GPO9/GPI9/IPBIN1 NA GPI17/CPUMISS NA (Exteranl Pull up to 3VDUAL)

GPO10/GPI10/IPBRDFR NA GPI18/AOLGP1/THRM# THRM#

X_C1000P50N C156 C186 C166 C155 C174 C256 C167

R60 15R1% MEMZN

Place near CPU in 1" , VDD_12_A

VCCA_PLL trace length from the VR1 to the

Place al filters close to the PGA.

Keep all power and signal trce away from

C67 C0.039U16X CLKIN_H

VTT_DDR_SUS Zdiff = 80 ohm

HDT Test Port Signal . DBREQ_L

LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,

C147 C138 C102 C140 C142 VDD_25_SUS C85 VTT_DDR_SUS

C435 C431 C426

GND VTT_DDR_SUS GND

C 0 . 2 2 U 1 6 Y C180P50N C8.2P50N X_C0.22U16Y C0.22U16Y C0.22U16Y

C106 C129 C110 C115 C123 C126 C135

C180P50N C180P50N C 0 . 2 2 U 1 6 Y C8.2P50N C 0 . 2 2 U 1 6 Y X_C0.22U16Y

VCLK C322 X_C10P50N

Clock Synthesizer GCLK_NB

Strapping CPU HTT PCI

FS3 FS2 FS1 FS0 MHz MHz MHz

CLKVCC3 SMBDATA1 8P4C-10P50N 1 1 1 1 300.00 75.00 37.50

"FS0~FS3" are all internal

ModeA,B=0:0 ( Set Pin 7,8 clock

"24_48MHZ/SEL" Freq.-Out select

SEL_24 R142 10KR

Micro Star Restricted Secret

Document Number MS-7144

DR_MD0 -MCS0 DR_MD0 -MCS2

Place near the DIMM

VREF routed as 40~50 mils trace wide , Space>25 mils DR_DM[7..0]

Micro Star Restricted Secret

RN59 8P4R-47R0402 RN19 8P4R-47R0402

RN46 8P4R-47R0402 DR_MD26

MICRO-STAR INT'L CO.,LTD. Last Revision Date:

VDD_25_SUS VTT_DDR_SUS VTT_DDR_SUS

DM0 DR_DM0 MD35 DR_MD35 Ver:00A modify GND

RN27 8P4R-10R0402 RN60 8P4R-10R0402

RN30 8P4R-10R0402 RN62 8P4R-10R0402

MD63 R69 10R0402 DR_MD63

LAYOUT: Locate close to

Micro Star Restricted Secret

DDR Terminations Bank 1

Document Number MS-7144

VCC3 VCC3HCK Around NB

Micro Star Restricted Secret