MOSFET & IC Basics – GATE Problems (Part - II)

1. In MOSFET devices the N-channel type is better than the P – Channel

type in the following respects.
(a) It has better immunity (d) It has better drive
(b) It is faster capability
(c) It is TTL compatible
[GATE 1988: 2 Marks]
Soln. In N – Channel MOSFETs the charge carriers are electrons while in
P – channel MOSFETs holes are the charge carriers.
The mobility of electrons is always greater than the mobility of holes.
i.e. 𝝁𝒏 > 𝝁𝒑
Thus, N – Channel MOSFETs are faster
Option (b)
2. In a MOSFET, the polarity of the inversion layer is the same as that of the
(a) Charge on the GATE – EC – electrode
(b) Minority carries in the drain
(c) Majority carriers in the substrate
(d) Majority carries in the source
[GATE 1989: 2 Marks]
Soln. In a MOSFET the polarity of inversion layer is the same as that of
majority carriers in the source.
For example, for N – MOSFETs the source is of N – type and
inversion layer formed is of electrons.
Option (d)

3. Which of the following effects can be caused by a rise in the

temperature?
(a) Increase in MOSFET current (IDS)
(b) Increase in BJT current (IC)
(c) Decrease in MOSFET current (IDS)
(d) Decrease in BJT current (IC)
[GATE 1990: 2 Marks]
Soln. The current equation for BJT is
𝑰𝑪 = 𝜷 𝑰𝒃 + (𝟏 + 𝜷)𝑰𝑪𝑶
As temperature increases, the leakage current ICO increases, so the
current IC increases in BJT.
Since mobility decreases as temperature increases. So in MOSFETs
current IDS decreases with rise in temperature
Option (b) and (c)

4. When the gate – to – source voltage (VGS) of a MOSFET with threshold

voltage of 400 mV, working in saturation is 900 mV, the drain current is
observed to be 1 mA. Neglecting the channel width modulation effect and
assuming that the MOSFET is operating at saturation, the drain current
for an applied VGS of 1400 mV is
(a) 0.5 mA (c) 3.5 mA
(b) 2.0 mA (d) 4.0 mA
[GATE 2003: 2 Marks]
Soln. Given,
𝑽𝑻 = 𝟒𝟎𝟎 𝒎𝑽 = 𝟎. 𝟒 𝑽
Voltage applied at gate
𝑽𝑮𝑺 = 𝟗𝟎𝟎 𝒎𝑽 =0.9 V
𝑰𝑫𝑺 = 𝟏 𝒎𝑨
Find the drain current for
𝑽𝑮𝑺 = 𝟏𝟒𝟎𝟎 𝒎𝑽
MOSFET is operating in saturation
𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐
𝒐𝒓, 𝟏 × 𝟏𝟎−𝟑 = 𝑲 (𝟎. 𝟗 − 𝟎. 𝟒)𝟐
𝟏𝟎−𝟑 𝑨
𝒐𝒓, 𝑲 = (𝟎.𝟓)𝟐 = 𝟒 × 𝟏𝟎−𝟑
𝑽𝟐

For VGS = 1.4 V

𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐
= 𝟒 × 𝟏𝟎−𝟑 (𝟏. 𝟒 − 𝟎. 𝟒)𝟐
 𝑰𝑫𝑺 = 𝟒 𝒎𝑨
Option (d)

5. The drain of an n – channel MOSFET is shorted to the gate so that

𝑉𝐺𝑆 = 𝑉𝐷𝑆 . The threshold voltage (VT) of MOSFET is 1 V. If the drain
current (ID) is 1 mA for VGS = 2 V, then for 𝑉𝐺𝑆 = 3 𝑉, ID is
(a) 2 mA (c) 9 mA
(b) 3 mA (d) 4 mA
[GATE 2004: 2 Marks]
Soln. Given,
𝑽𝑮𝑺 = 𝑽𝑫𝑺
Then the device is in saturation.
So, 𝑰𝑫𝑺 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐
For 𝑰𝑫𝑺 = 𝟏 𝒎𝑨 , 𝑽𝑮𝑺 = 𝟐𝑽 , 𝑽𝑻 = 𝟏𝑽
𝟏 = 𝑲 (𝟐 − 𝟏)𝟐
𝒐𝒓, 𝑲 = 𝟏 𝒎𝑨⁄𝑽𝟐
Again,
𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐
For 𝑽𝑮𝑺 = 𝟑 𝑽
𝑰𝑫 = 𝟏 × (𝟑 − 𝟏)𝟐
𝑰𝑫 = 𝟒 𝒎𝑨
Option (d)

6. An n – channel depletion MOSFET has following two points on its

𝐼𝐷 − 𝑉𝐺𝑆 curve
(i) 𝑉𝐺𝑆 = 0 𝑎𝑡 𝐼𝐷 = 12 𝑚𝐴 𝑎𝑛𝑑
(ii) 𝑉𝐺𝑆 = −6 𝑉 𝑎𝑡 𝐼𝐷 = 0
Which of the following Q point will give the highest transconductance
gain for small signals?
 (a) 𝑉𝐺𝑆 = −6 𝑉 (c) 𝑉𝐺𝑆 = 0 𝑉
(b) 𝑉𝐺𝑆 = −3 𝑉 (d) 𝑉𝐺𝑆 = 3 𝑉
[GATE 2006: 2 Marks]
𝜹 𝑰𝑫
Soln. Transconductance (𝒈𝒎 ) = for 𝑽𝑫𝑺 = 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝜹 𝑽𝑮𝑺

The characteristics is plotted.

𝑰𝑫 (𝒎𝑨)

12mA

VGS
-6V 0

As ID increases VGS also increases Larger VGS will have high

transconductance
Thus, Option (d)

7. In the C MOS inverter circuit shown if the transconductance parameters

of N MOS and P MOS transistor are
𝑊𝑛 𝑊𝑝
𝐾𝑛 = 𝐾𝑝 = 𝜇𝑛 𝐶𝑂𝑋 = 𝜇𝑝 𝐶𝑂𝑋 = 40 𝜇𝐴⁄𝑉 2
𝐿𝑛 𝐿𝑝
and threshold voltages are 𝑉𝑇 = 1𝑉 the current I is

5V

PMOS

2.5V

NMOS
 (a) 0 A (c) 45 µA
(b) 25 µA (d) 90 µA
[GATE 2007: 2 Marks]
Soln. Given
𝑲𝒏 = 𝑲𝒑 = 𝟒𝟎 𝝁𝑨⁄𝑽𝟐
𝑽𝑻 = 𝟏 𝑽
The device is in saturation. So the current is given by
𝑲𝒏
𝑰𝑫𝑺 = (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐
𝟐
𝟒𝟎
(𝟐. 𝟓 − 𝟏)𝟐 = 𝟐𝟎 × (𝟏. 𝟓)𝟐 = 𝟒𝟓 𝝁𝑨
𝟐

Option (c)

8. Two identical N MOS transistors M1 and M2 are connected as shown

below. 𝑉𝑏𝑖𝑎𝑠 Chosen so that both transistor are in saturation. The
𝜕 𝐼𝑜𝑢𝑡
equivalents 𝑔𝑚 of the pair is defined to be at constant𝑉𝑜𝑢𝑡 . The
𝜕 𝑉𝑖
equivalent 𝑔𝑚 of the pair is
𝑽𝒐𝒖𝒕
𝑰𝒐𝒖𝒕

𝑽𝒃𝒊𝒂𝒔 M2

𝑽𝒊 M1

(a) The sum of individual 𝑔𝑚 of two transistors.

(b) The product of individual 𝑔𝑚 of the transistors.
(c) Nearly equal to the 𝑔𝑚 of M1
(d) Nearly equal to 𝑔𝑚 ⁄𝑔0 of M2
[GATE 2008: 2 Marks]
Soln. As per the principle of transconductance
𝟏 𝟏 𝟏
=𝒈 =𝒈
𝒈𝒎 𝒎𝟏 𝒎𝟐

𝒈𝒎 𝒈𝒎
𝟏 𝟐
𝒐𝒓, 𝒈𝒎 = ≅ 𝒈𝒎
𝒈𝒎 +𝒈𝒎 𝟏
𝟏 𝟐

Option (c)

9. The measured Transconductance 𝑔𝑚 of an NMOS transistor operating in

the linear region is plotted against voltage VG at a Constant drain voltage
VD. Which of the following figures represents the expected dependence
of 𝑔𝑚 on VG .

gm gm
(a) (b)

V VG VG

gm gm
(c) (d)

VG VG

[GATE 2008: 2 Marks]

Soln. Drain current ID in the linear region is given by
𝑽𝟐𝑫𝑺
𝑰𝑫 = 𝑲𝒏 [(𝑽𝑮𝑺 − 𝑽𝑻 )𝑽𝑫𝑺 − ]
𝟐
𝝏 𝑰𝑫
𝒂𝒏𝒅 𝒈𝒎 = = 𝑲𝒏 (𝑽𝑮𝑺 − 𝑽𝑻 )𝑽𝑫𝑺
𝝏 𝑽𝑮𝑺

𝑺𝒐, 𝒈𝒎 ∝ 𝑽𝑮𝑺
So, linear characteristic
Option (c)
 10. Consider the following two situations about the internal conditions in an
n – channel MOSFET operating in the active region.
S1: The inversion charge decreases from source to drain
S2 : The channel potential increases from source to drain
Which of the following is correct?
(a) Only S2 is true
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true but S2 is not a reason for S1
(d) Both S1 and S2 are true and S2 is reason for S1
[GATE 2009: 2 Marks]
Soln. MOSFET is also considered as gate – controlled resistor.
When +ve gate voltage in an n – channel MOSFET exceeds VT,
electrons are induced in p – type substrate. This channel is also
connected to n+ source and drain regions. Channel looks like induced
n – type resistor. With increase in gate voltage the channel becomes
more conducting. The drain current increase (linear region). When
more drain current flows, there is more ohmic voltage drop along the
channel. The channel potential varies near zero from source to the
potential at drain end.
The voltage difference between gate and channel reduces from VG
(near source) to (𝑽𝑮 − 𝑽𝑫 ) near drain. When drain bias is increased
(𝑽𝑮 − 𝑽𝑫 ) = 𝑽𝑻 , the channel is piched off. When VD increase further
the drain current is in saturation.
So, S1 & S2 are true and S2 is reason for S1

Option (d) (Refer: Streetman)

11. The source of a silicon (𝑛𝑖 = 1010 𝑝𝑒𝑟 𝑐𝑚3 ) n – channel MOS transistor
has an area 1 sq µm and a depth of 1 µm. If the dopant density in the
source is 1019 /𝑐𝑚3 the no. of holes in the source region with above
volume is approx.
(a) 107 (c) 10
(b) 100 (d) 0
[GATE 2012: 2 Marks]
Soln. Given,
𝒏𝒊 = 𝟏𝟎𝟏𝟎 ⁄𝒄𝒎𝟑
𝑨𝒓𝒆𝒂 (𝑨) = 𝟏 × 𝟏𝟎−𝟏𝟐 /𝒎𝟐
𝒅𝒆𝒑𝒕𝒉 (𝒅) = 𝟏𝟎−𝟔 𝒎
𝑽𝒐𝒍𝒖𝒎𝒆 = 𝑨 . 𝒅 = 𝟏 × 𝟏𝟎−𝟐 × 𝟏𝟎𝟔 𝒎𝟑
= 𝟏𝟎−𝟏𝟖 /𝒎𝟑
= 𝟏𝟎−𝟏𝟐 /𝒄𝒎𝟑
𝑵𝑫 = 𝒏 = 𝟏𝟎𝟏𝟗 /𝒄𝒎𝟑
𝒏𝟐𝒊 𝟏𝟎𝟐𝟎
𝒑= = = 𝟏𝟎⁄𝒄𝒎𝟑
𝑵𝑫 𝟏𝟎𝟏𝟗

So,
Holes in volume V is
𝑯 = 𝒑 . 𝑽 = 𝟏𝟎−𝟏𝟐 × 𝟏𝟎
= 𝟏𝟎−𝟏𝟏
Since not integer number ≅ 𝟎
Option (d)

12. A depletion type N – channel MOSFET in biased in its linear region for
use as a voltage controlled resistor . Assume threshold voltage 𝑉𝑇𝐻 =
0.5𝑉 , 𝑉𝐺𝑆 = 2.0𝑉 , 𝑉𝐷𝑆 = 5𝑉 , 𝑊 ⁄𝐿 = 100, 𝐶𝑂𝑋 = 10−8 𝐹/𝑐𝑚2 and
𝜇𝑛 = 800 𝑐𝑚2 ⁄𝑉 − 𝑠. The value of the resistance of the voltage
controlled resistor (𝑖𝑛 Ω) is __________
[GATE 2014: 2 Marks]
Soln. Given,
Depletion type MOSFET (N – Channel)
In linear region
𝑽𝑻𝑯 = 𝟎. 𝟓𝑽
𝑽𝑮𝑺 = 𝟐. 𝟎𝑽
𝑽𝑫𝑺 = 𝟓𝑽
 𝑾/𝑳 = 𝟏𝟎𝟎
𝑪𝑶𝑿 = 𝟏𝟎−𝟖 𝑭⁄𝒄𝒎𝟐
The value of voltage controlled resistor is given by

𝟏
𝒓𝒅𝒔 =
𝑾
𝝁𝒏 𝑪𝑶𝑿 (𝑽 − 𝑽𝑻 )
𝑳 𝑮𝑺

𝟏
𝒓𝑫𝑺 =
𝟖𝟎𝟎 × 𝟏𝟎−𝟖 × 𝟏𝟎𝟎[𝟐 − (−𝟎. 𝟓)]

𝒓𝑫𝑺 = 𝟓𝟎𝟎 𝛀
Answer: 𝟓𝟎𝟎 𝛀

13. For the n – channel MOS transistor shown in figure, the threshold
voltage VTH is 0.8V. Neglect channel length modulation effects. When
the drain voltage VD = 1.6, the drain current ID was found to be 0.5 mA. If
VD is adjusted to be 2V by changing the values of R and VDD, the new
value of ID (in m A) is
𝑽𝑫𝑫

G S

(a) 0.625 (c) 1.125

(b) 0.75 (d) 1.5
[GATE 2014: 2 Marks]
Soln. Given,
𝑽𝑻𝑯 = 𝟎. 𝟖 𝑽
𝑽𝑫 = 𝟏. 𝟔 𝑽
𝑰𝑫 = 𝟎. 𝟓 𝒎𝑨
For the given figure we notice that Gate is connected to drain
So, 𝑽𝑮𝑺 = 𝑽𝑫𝑺 = 𝑽𝑫
In saturation ID is given by
𝑰𝑫𝑺 = 𝑲(𝑽𝑮𝑺 − 𝑽𝑻 )𝟐

𝟐
𝑰𝑫𝟐 [𝑽𝑮𝑺𝟐 − 𝑽𝑻 ]
𝑺𝒐, = 𝟐
𝑰𝑫𝟏 [𝑽
𝑮𝑺𝟏 − 𝑽𝑻 ]

𝑰𝑫𝟐 (𝟐 − 𝟎. 𝟖)𝟐
𝑺𝒐, = = 𝟐. 𝟐𝟓
𝑰𝑫𝟏 (𝟏. 𝟔 − 𝟎. 𝟖)𝟐
𝒐𝒓, 𝑰𝑫𝟐 = 𝟐. 𝟐𝟓 × 𝟎. 𝟓
= 𝟏. 𝟏𝟐𝟓 𝒎𝑨
Option (c)

14. For the MOSFET shown in the figure the threshold voltage |𝑉𝑡 | = 2𝑉
1 𝑊
and 𝐾 = 𝜇𝑐 ( ) = 0.1𝑚𝐴/𝑉 2 . The value of ID (in mA) is ________
2 𝐿
𝑽𝑫𝑫 = +𝟏𝟐𝑽

𝑹𝟏 𝟏𝟎 𝑲𝛀

𝑹𝟐 𝟏𝟎 𝑲𝛀 𝑰𝑫

𝑽𝑺𝑺 = −𝟓𝑽
 [GATE 2014: 2 Marks]
Soln. The two MOSFET are in series so, same current will be flowing. For
the bottom MOSFET it is easier to find VGS
𝑽𝑮𝑺 = 𝑽𝑮 − 𝑽𝑺 = 𝟎— 𝟓
= 𝟓𝑽
VGS is greater than threshold voltage,
So, MOSFET is in saturation
𝟏 𝑾
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 [𝑽𝑮𝑺 − 𝑽𝑻 ]𝟐
𝟐 𝑳

= 𝟎. 𝟏 𝒎𝑨/𝑽𝟐 [𝟓 − 𝟐]𝟐
𝟎. 𝟏 𝒎𝑨/𝑽𝟐 [𝟑]𝟐
𝑰𝑫 = 𝟎. 𝟗 𝒎𝑨
Answer: 0.9 mA

15. The slope of the 𝐼𝐷 𝑣𝑠 . 𝑉𝐺𝑆 curve of an n – channel MOSFET in linear

region is 10−3 Ω−1 at 𝑉𝐷𝑆 = 0.1𝑉 . For the same device, neglecting
channel length modulation, the slope of the √𝐼𝐷 𝑣𝑠 𝑉𝐺𝑆 curve
(𝑖𝑛 √𝐴⁄𝑉 ) under saturation region is approximately ________
[GATE 2014: 2 Marks]
Soln. Given,
Slope of 𝑰𝑫 𝒗𝒔 . 𝑽𝑮𝑺 curve for N – MOSFET in linear region is
𝟏𝟎−𝟑 𝛀−𝟏

𝝏 𝑰𝑫
𝒊. 𝒆. = 𝟏𝟎−𝟑
𝝏 𝑽𝑮𝑺
In linear region the drain current is given by

𝟏 𝟐
𝑰𝑫 = 𝑲𝒏 [(𝑽𝑮𝑺 − 𝑽𝑻 )𝑽𝑫𝑺 − 𝑽 ]
𝟐 𝑫𝑺
𝑾
𝒘𝒉𝒆𝒓𝒆 𝑲𝒏 = 𝝁𝒏 𝑪𝑶𝑿
𝑳
 𝝏 𝑰𝑫
= 𝑲𝒏 𝑽𝑫𝑺
𝝏 𝑽𝑮𝑺
𝝏 𝑰𝑫
𝝏 𝑽𝑮𝑺 𝟏𝟎−𝟑
𝒐𝒓, 𝑲𝒏 = = = 𝟏𝟎−𝟐
𝑽𝑫𝑺 𝟎.𝟏

For saturation region

𝟏
𝑰𝑫 = 𝑲 [𝑽 − 𝑽𝑻 ]𝟐
𝟐 𝒏 𝑮𝑺

𝑲𝒏
𝒐𝒓, √𝑰𝑫 = √ [𝑽𝑮𝑺 − 𝑽𝑻 ]
𝟐

𝝏 √𝑰𝑫 𝑲𝒏
=√
𝝏 𝑽𝑮𝑺 𝟐

𝝏 √𝑰𝑫 𝟏𝟎−𝟐
𝒐𝒓, =√ = 𝟎. 𝟎𝟕𝟎𝟕 √𝑨 / 𝑽
𝝏 𝑽𝑮𝑺 𝟐

Answer: 𝟎. 𝟎𝟕𝟎𝟕 √𝑨 / 𝑽

16. An ideal MOS capacitor has boron doping concentration of 1015 𝑐𝑚−3
in the substrate. When a gate voltage is applied, a depletion region of
width 0.5 𝜇𝑚 is formed with a surface (channel) potential of 0.2 V. Given
that ∈0 = 8.854 × 10−14 F/cm and the relative permittivity of silicon and
silicon dioxide are 12 and 4 respectively the peak electric filed in 𝑉 ⁄𝜇𝑚
in the oxide region is _____________
[GATE 2014: 2 Marks]
Soln. Dopant is Boron, so p – type substrate
Thus device is n MOSFET. Peak electric field in Si substrate

𝟐𝚿𝒔
𝑬𝒔𝒊 =
𝑾𝒅
 Where, 𝚿𝒔 − 𝒔𝒖𝒓𝒇𝒂𝒄𝒆 𝒑𝒐𝒕𝒆𝒏𝒕𝒊𝒂𝒍
𝑾𝒅 − 𝒅𝒆𝒑𝒍𝒆𝒕𝒊𝒐𝒏 𝒓𝒆𝒈𝒊𝒐𝒏 𝒘𝒊𝒅𝒕𝒉

𝟐 × 𝟎. 𝟐
𝑬𝒔𝒊 = = 𝟎. 𝟖⁄𝝁𝒎
𝟎. 𝟓𝝁𝒎
Electric field in oxide

∈𝒔
𝑬𝑶𝑿 = .𝑬
∈𝑶𝑿 𝒔𝒊
𝟏𝟐
= × 𝟎. 𝟖𝑽⁄𝝁𝒎
𝟒
= 𝟐. 𝟒 𝑽⁄𝝁𝒎
Answer: 𝑬𝑶𝑿 = 𝟐. 𝟒𝑽⁄𝝁𝒎

17. For the MOSFET M1 shown in figure, assume

𝑊 ⁄𝐿 = 2, 𝑉𝐷𝐷 = 2.0𝑉, 𝜇𝑛 𝐶𝑂𝑋 = 100 𝜇𝑚⁄𝑉 2 𝑎𝑛𝑑 𝑉𝑇𝐻 = 0.5𝑉. The
transistor M1 switches from saturation region to linear region when 𝑉𝑖𝑛
(in volts) is ___________
𝑽𝑫𝑫

R = 𝟏𝟎 𝑲𝛀

𝑽𝒐𝒖𝒕

𝑽𝒊𝒏 M1

[GATE 2014: 2 Marks]

Soln. For saturation region drain current is given by
𝑰𝑫 = 𝑲𝒏 [𝑽𝑮𝑺 − 𝑽𝑻 ]𝟐

𝟏 𝑾
= 𝝁𝒏 𝑪𝑶𝑿 [𝑽𝑮𝑺 − 𝑽𝑻 ]𝟐
𝟐 𝑳
 𝟏 𝑾
= 𝝁𝒏 𝑪𝑶𝑿 [𝑽𝟎 ]𝟐
𝟐 𝑳
𝒔𝒊𝒏𝒄𝒆, 𝑽𝑮𝑺 − 𝑽𝑻 = 𝑽𝑫𝑺 = 𝑽𝟎
𝟏
𝑺𝒐, 𝑰𝑫 = × 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 × 𝟐 × 𝑽𝟐𝟎
𝟐

𝒐𝒓, 𝑰𝑫 = 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 𝑽𝟐𝟎 − − − − − − − (𝟏)

Applying KVL in outer loop
𝑽𝑫𝑫 = 𝑰𝑫 × 𝟏𝟎𝑲 + 𝑽𝟎 − − − − − −(𝟐)
From equation (1) and (2) we get
𝟐 = 𝟏𝟎𝟎 × 𝟏𝟎−𝟔 𝑽𝟐𝟎 + 𝑽𝟎
𝒐𝒓, 𝟐 = 𝑽𝟐𝟎 + 𝑽𝟎
𝒐𝒓, 𝑽𝟐𝟎 + 𝑽𝟎 − 𝟐 = 𝟎

−𝟏 ± √𝟏 + 𝟒 × 𝟏 × 𝟐 −𝟏 ± 𝟑
𝑽𝟎 = =
𝟐×𝟏 𝟐
𝑺𝒐, 𝑽𝟎 = 𝟏𝑽 𝒐𝒓 − 𝟐𝑽
Taking 𝑽𝟎 = 𝟏𝑽
𝑽𝑫𝑺 = 𝑽𝑮𝑺 = 𝑽𝑻
𝒐𝒓, 𝑽𝟎 = 𝑽𝒊𝒏 − 𝑽𝑻
𝒐𝒓, 𝑽𝒊𝒏 = 𝟏 + 𝟎. 𝟓 = 𝟏. 𝟓𝑽
Answer: 1.5V

18. In a MOS capacitor with an oxide layer thickness of 10 nm, the

maximum depletion layer thickness is 100 nm. The permittivities of the
semiconductor and the oxide layer are 𝜀𝑠 𝑎𝑛𝑑 𝜀𝑂𝑆 respectively.
Assuming 𝜀𝑠 /𝜀𝑂𝑋 = 3, the ratio of the maximum capacitance of the
minimum capacitance of this MOS capacitor is .
[GATE 2015: 2 Marks]
Soln. Given,
Oxide layer thickness (𝒕𝑶𝑿 ) = 𝟏𝟎 𝒏𝒎
Depletion layer thickness (𝒕𝒅𝒆𝒑 ) = 𝟏𝟎𝟎 𝒏𝒎

𝜺𝒔
=𝟑
𝜺𝑶𝑿

Metal
tOX (10nm)

tdep =100

Si

Both oxide layer capacitance (𝑪𝑶𝑿 ) and depletion layer capacitances

are coming in series, so the maximum capacitance will be when
depletion layer capacitance (𝑪𝒅𝒆𝒑 ) will be absent
Maximum capacitance (𝑪𝒎𝒂𝒙 ) = 𝑪𝑶𝑿
Minimum capacitance (𝑪𝒎𝒊𝒏 ) is
Given by

𝑪𝑶𝑿 𝑪𝒅𝒆𝒑
𝑪𝒎𝒊𝒏 =
𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑
Where 𝑪𝑶𝑿 𝒂𝒏𝒅 𝑪𝒅𝒆𝒑 are capacitances per unit area

𝑪𝒎𝒂𝒙 𝑪𝑶𝑿 𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑

= =
𝑪𝒎𝒊𝒏 𝑪𝑶𝑿 𝑪𝒅𝒆𝒑 𝑪𝒅𝒆𝒑
𝑪𝑶𝑿 + 𝑪𝒅𝒆𝒑

𝜺𝑶𝑿
𝑪𝑶𝑿 𝒕
=𝟏+ = 𝟏 + 𝜺𝑶𝑿
𝑪𝒅𝒆𝒑 𝑺
𝒅
 𝜺𝑶𝑿 𝒅
=𝟏+ .
𝜺𝒓 𝒕𝑶𝑿

𝑪𝒎𝒂𝒙 𝟏 𝟏𝟎𝟎
= 𝟏+ × = 𝟒. 𝟑𝟑
𝑪𝒎𝒊𝒏 𝟑 𝟏𝟎
Answer: 4.33

19. In the circuit shown both enhancement mode NMOS transistor have the
following characteristics: 𝐾𝑛 = 𝜇𝑛 𝐶𝑂𝑋 (𝑊 ⁄𝐿) = 1𝑚𝐴/𝑉 2 ; 𝑉𝑇𝑁 = 1𝑉.
Assume that the channel length modulation parameter λ is zero and body
is shorted to source. The minimum supply voltage VDD (in volts) needed
to ensure that transistor M1 operates in saturation mode of operation is __
𝑽𝑫𝑫

M2

2V M1

[GATE 2015: 2 Marks]

Soln. In the given circuit
M1 is to operate in saturation. Both MOSFETs are NMOS
𝑲𝒏 = 𝝁𝒏 𝑪𝑶𝑿 (𝑾⁄𝑳) = 𝟏 𝒎𝑨/𝑽𝟐
𝑽𝑻𝒏 = 𝟏 𝑽
Both MOSFETs are in series so same current will flow through then
For M1 : 𝑽𝑮𝑺𝟏 = 𝟐𝑽 (As per figure)
If M1 is assumed in saturation, then

𝟏 𝟐
𝑰𝑫𝟏 = 𝑲𝒏 [𝑽𝑮𝑺𝟏 − 𝑽𝑻 ]
𝟐
 Minimum VDS required for M1 to operate in saturation
𝑽𝑫𝑺𝟏 = 𝑽𝑮𝑺𝟏 − 𝑽𝑻 = 𝟐 − 𝟏 = 𝟏𝑽
For M2 : 𝑽𝑮𝑺𝟐 − 𝑽𝑫𝑫 − 𝑽𝑫𝑺𝟏 = 𝑽𝑫𝑫 − 𝟏

𝟏 𝟐
𝑰𝑫𝟐 = 𝑲𝒏 [𝑽𝑮𝑺𝟐 − 𝑽𝑻 ]
𝟐
Since 𝑰𝑫𝟏 = 𝑰𝑫𝟐

𝟏 𝟐 𝟏 𝟐
𝑲𝒏 [𝑽𝑮𝑺𝟏 − 𝑽𝑻 ] = 𝑲𝒏 [𝑽𝑮𝑺𝟐 − 𝑽𝑻 ]
𝟐 𝟐
𝒐𝒓, 𝑽𝑽𝑮𝟏 − 𝑽𝑻 = 𝑽𝑮𝑺𝟐 − 𝑽𝑻
𝑽𝑮𝑺𝟏 = 𝑽𝑮𝑺𝟐
𝒐𝒓, 𝑽𝑮𝑺𝟏 = 𝑽𝑫𝑫 − 𝟏
𝒐𝒓, 𝑽𝑫𝑫 = 𝟐 + 𝟏 = 𝟑𝑽
Answer: 𝑽𝑫𝑫 = 𝟑𝑽

20. The current in an enhancement mode NMOS transistor biased in

saturation mode was measured to be 1 mA at a drain source voltage of
5V. When the drain source voltage was increased to 6V while keeping
gate source voltage same. The drain current increased to 1.02 mA.
Assume that drain to source saturation voltage is much smaller than the
applied drain source voltage. The channel length modulation parameter λ
(𝑖𝑛 𝑉 −1 ) is ______________.
[GATE 2015: 2 Marks]
Soln. Given,
N MOS transistor
Biased in saturation 𝑰𝑫 = 𝟏𝒎𝑨 , 𝑽𝑫𝑺 = 𝟓𝑽
Drain current in saturation including the effect of channel length
modulation parameter
𝟏 𝑾
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 (𝑽𝑮𝑺 − 𝑽𝑻 )𝟐 (𝟏 + 𝝀 𝑽𝑫𝑺 )
𝟐 𝑳
 So, we can write the ratio of two current

𝑰𝑫𝟐 𝟏 + 𝝀 𝑽𝑫𝑺𝟐
=
𝑰𝑫𝟐 𝟏 + 𝝀 𝑽𝑫𝑺𝟏
𝟏. 𝟎𝟐 𝟏 + 𝟔𝝀
𝒐𝒓, =
𝟏 𝟏 + 𝟓𝝀
𝒐𝒓, 𝟏. 𝟎𝟐 + 𝟓. 𝟏𝝀 = 𝟏 + 𝟔𝝀
𝒐𝒓, 𝟎. 𝟗 𝝀 = 𝟎. 𝟎𝟐
𝟎. 𝟎𝟐
𝒐𝒓, 𝝀 = = 𝟎. 𝟎𝟐𝟐𝑽−𝟏
𝟎. 𝟗

21. Consider an n – channel metal oxide semiconductor field effect transistor

(MOSFET) with gate to source voltage of 1.8V. Assume that
𝑊
= 4, 𝜇𝑛 𝐶𝑂𝑋 = 70 × 10−6 𝐴𝑉 −2
𝐿
The threshold voltage is 0.3V, and the channel length modulation
parameter is 0.09𝑉 −1 . In the saturation region, the drain conduction (in
micro Siemens) is ________
[GATE 2016: 2 Marks]
Soln. Given,
N – MOSFET
𝑾
𝑽𝑮𝑺 = 𝟏. 𝟖𝑽 , = 𝟒 , 𝝁𝒏 𝑪𝑶𝑿 = 𝟕𝟎 × 𝟏𝟎−𝟔 𝑨𝑽−𝟐
𝑳

𝑽𝑻𝑯 = 𝟎. 𝟑𝑽 , 𝝀 = 𝟎. 𝟎𝟗𝑽−𝟏
Drain current in saturation including the effect of channel length
modulation is

𝟏 𝑾
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 ( ) (𝑽𝑮 − 𝑽𝑻 )𝟐 (𝟏 + 𝝀𝑽𝑫 )
𝟐 𝑳
Channel conductance (𝒈𝒅 )
 𝝏 𝑰𝑫
(𝒈𝒅 ) =
𝝏 𝑽𝑫 𝑽 = 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝑮

𝝏 𝑰𝑫 𝟏 𝑾
𝒈𝒅 = = 𝝁𝒏 𝑪𝑶𝑿 ( ) (𝑽𝑮 − 𝑽𝑻 )𝟐 . 𝝀
𝝏 𝑽𝑫 𝟐 𝑳
So,
𝟏
𝒈𝒅 = × 𝟕𝟎 × 𝟏𝟎−𝟔 × 𝟒 × (𝟏. 𝟖 − 𝟎. 𝟑)𝟐 × 𝟎. 𝟎𝟗
𝟐

= 𝟏𝟒𝟎 × 𝟏𝟎−𝟔 × 𝟐. 𝟐𝟓 × 𝟎. 𝟎𝟗
= 𝟐𝟖. 𝟑𝟓 × 𝟏𝟎−𝟔
𝒈𝒅 = 𝟐𝟖. 𝟑𝟓 𝝁 𝑺𝒊𝒆𝒎𝒆𝒏𝒔
Drain conductance 𝒈𝒅 = 𝟐𝟖. 𝟑𝟓 𝝁 𝐒𝐢𝐞𝐦𝐞𝐧𝐬

22. A voltage VG is applied across the MOS capacitor with metal Gate and
p – type silicon substrate at 𝑇 = 300 𝐾. The inversion carrier density (in
number of units per unit area) for
𝑉𝐺 = 0.8𝑉 𝑖𝑠 2 × 1011 𝑐𝑚−2 𝑓𝑜𝑟 𝑉𝐺 = 1.3𝑉, the inversion carrier density
is 4 × 1011 𝑐𝑚−2 . What is value of inversion carrier density of VG = 1.8V
(a) 4.5 × 1011 𝑐𝑚−2 (c) 7.2 × 1011 𝑐𝑚−2
(b) 6.0 × 1011 𝑐𝑚−2 (d) 8.4 × 1011 𝑐𝑚−2
[GATE 2016: 2 Marks]
Soln. Given,
For VG = 0.8V
Inversion layer carrier density = 𝟐 × 𝟏𝟎𝟏𝟏 𝒄𝒎−𝟐
𝑭𝒐𝒓 𝑽𝑮 = 𝟏. 𝟑𝑽 , 𝑰𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏 𝒍𝒂𝒚𝒆𝒓 𝒄𝒂𝒓𝒓𝒊𝒆𝒓 𝒅𝒆𝒏𝒔𝒊𝒕𝒚 = 𝟒 ×
𝟏𝟎𝟏𝟏 𝒄𝒎𝟐
Find for VG = 1.8 V
For MOS capacitor
Charge (𝑸) ∝ (𝑽𝑮 − 𝑽𝑻 )
Charge 𝑸𝟏 = 𝑲. (𝑽𝑮 − 𝑽𝑻 )
 Or, 𝑸𝟏 = 𝒒𝑨 × 𝒊𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏 𝒄𝒂𝒓𝒓𝒊𝒆𝒓 𝒅𝒆𝒏𝒔𝒊𝒕𝒚
So,

𝟐 × 𝟏𝟎𝟏𝟏 . 𝒒𝑨 (𝟎. 𝟖 − 𝑽𝑻 )
=
𝟒 × 𝟏𝟎𝟏𝟏 . 𝒒𝑨 (𝟏. 𝟑 − 𝑽𝑻 )
Or, VT = 0.3V
𝑵𝒐𝒘 𝒇𝒐𝒓 𝑽𝑮 = 𝟏. 𝟖𝑽 , 𝑸𝟏 = 𝒒𝑨 𝝆𝒊
Where 𝝆𝒊 is inversion carrier density

𝝆𝒊 𝒒 . 𝑨 (𝟏. 𝟖 − 𝟎. 𝟑)
=
𝟐 × 𝟏𝟎𝟏𝟏 𝒒 . 𝑨 (𝟎. 𝟖 − 𝟎. 𝟑)
𝒐𝒓, 𝝆𝒊 = 𝟔 × 𝟏𝟎𝟏𝟏 /𝒄𝒎𝟐
Option (b)

23. Consider long channel N MOS transistor with source and body
connected together.
Assume that the electron mobility is dependent of VGS and VDS. Given,
𝑔𝑚 = 0.5 𝜇 𝐴⁄𝑉 𝑓𝑜𝑟 𝑉𝐷𝑆 = 50 𝑚𝑉 𝑎𝑛𝑑 𝑉𝐺𝑆 = 2𝑉
𝑔𝑑 = 8 𝜇 𝐴⁄𝑉 𝑓𝑜𝑟 𝑉𝐺𝑆 = 2𝑉 𝑎𝑛𝑑 𝑉𝐷𝑆 = 0𝑉
Where
𝜕 𝐼𝐷 𝜕 𝐼𝐷
𝑔𝑚 = 𝑎𝑛𝑑 𝑔𝑑 =
𝜕 𝑉𝐺𝑆 𝜕 𝑉𝐷𝑆
The threshold voltage (in volts) of the transistor is _________
[GATE 2016: 2 Marks]
Soln. Given long channel N MOS, it means it does not have the effect of
channel length modulation. Since VDS is 50 mV (small) it is operating
in linear region. The drain current is given by

𝑾 𝟏
𝑰𝑫 = 𝝁𝒏 𝑪𝑶𝑿 ( ) [(𝑽𝑮𝑺 − 𝑽𝑻 )𝑽𝑫𝑺 − 𝑽𝟐𝑫𝑺 ]
𝑳 𝟐

𝝏 𝑰𝑫 𝑾
𝒈𝒎 = = 𝝁𝒏 𝑪𝑶𝑿 ( ) . 𝑽𝑫𝑺
𝝏 𝑽𝑮𝑺 𝑳
 𝑾 𝒈𝒎 𝟎. 𝟓 × 𝟏𝟎−𝟔
𝒐𝒓, 𝝁𝒏 𝑪𝑶𝑿 = = −𝟑
= 𝟏𝟎 × 𝟏𝟎−𝟔
𝑳 𝑽𝑫𝑺 𝟓𝟎 × 𝟏𝟎
Now,

𝝏 𝑰𝑫 𝑾
𝒈𝒅 = = 𝝁𝒏 𝑪𝑶𝑿 [𝑽𝑮 − 𝑽𝑻 ]
𝝏 𝑽𝑫𝑺 𝑳
𝒐𝒓, 𝟖 × 𝟏𝟎−𝟔 = 𝟏𝟎 × 𝟏𝟎−𝟔 [𝑽𝑮𝑺 − 𝑽𝑻 ]
𝟖 × 𝟏𝟎−𝟔
𝒐𝒓, 𝑽𝑮𝑺 − 𝑽𝑻 =
𝟏𝟎 × 𝟏𝟎−𝟔
𝒐𝒓, 𝑽𝑻 = 𝑽𝑮𝑺 − 𝟎. 𝟖
= 𝟐 − 𝟎. 𝟖 = 𝟏. 𝟐𝑽
𝐀𝐧𝐬𝐰𝐞𝐫: 𝑽𝑻 = 𝟏. 𝟐𝑽

24. Figure I and II show two MOS capacitors of unit area. The capacitor in
Figure I has insulator material X of (thickness t1 = 1 nm and dielectric
constant ∈1 = 4) and y (of thickness 𝑡2 = 3𝑛𝑚 and dielectric
constant∈1 = 20). The capacitor in figure II has only insulator material X
of thickness 𝑡𝑒𝑞 . If the capacitors are of equal capacitance, then the value
of 𝑡𝑒𝑞 (in nm) is________
Metal Metal
t2 Ԑ2 Ԑ1 teq
t1 Ԑ1

Si
Si

Figure II
Figure I

[GATE 2016: 2 Marks]

Soln. MOS structure is like a parallel plate capacitor
The capacitance per unit area for this geometry is
 ∈
𝑪′ =
𝒅

Where ∈ is permittivity of insulator

d is distance between plates
For area A,
∈𝑨
𝑪=
𝒅
As per figure I the two capacitors formed by the two dielectrics are in
series

𝑪𝟏 𝑪𝟐
𝑪=
𝑪𝟏 + 𝑪𝟐

𝟒 𝟐𝟎
−𝟗 ×
= [𝟏 × 𝟏𝟎 𝟑 × 𝟏𝟎−𝟗 ] ∈
𝟒 𝟐𝟎 𝟎
+
𝟏 × 𝟏𝟎−𝟗 𝟑 × 𝟏𝟎−𝟗
𝑪 = 𝟐. 𝟓 × 𝟏𝟎𝟗 ∈𝟎
For the II case

∈𝒓 ∈𝟎
𝑪=
𝒕𝒆𝒒

∈𝒓 ∈𝟎
𝒐𝒓, 𝒕𝒆𝒒 =
𝑪

∈𝒓 ∈𝟎 𝟒
= =
𝟐. 𝟓 × 𝟏𝟎𝟗 ∈𝟎 𝟐. 𝟓 × 𝟏𝟎𝟗
= 𝟏. 𝟔 × 𝟏𝟎−𝟗 𝒎
𝒕𝒆𝒒 = 𝟏. 𝟔 𝒏𝒎

Ans.1.6 nm