IETE Journal of Research

ISSN: 0377-2063 (Print) 0974-780X (Online) Journal homepage: http://www.tandfonline.com/loi/tijr20

Asymmetric H-Bridge Single-Phase Seven-Level

Inverter Topology with Proportional Resonant
Controller

P. A. Salodkar, P. S. Kulkarni, Manoj A. Waghmare, P. C. Chaturvedi &

Sandeep N

To cite this article: P. A. Salodkar, P. S. Kulkarni, Manoj A. Waghmare, P. C. Chaturvedi

& Sandeep N (2017): Asymmetric H-Bridge Single-Phase Seven-Level Inverter
Topology with Proportional Resonant Controller, IETE Journal of Research, DOI:
10.1080/03772063.2017.1396934

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Published online: 06 Dec 2017.

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 IETE JOURNAL OF RESEARCH, 2017
https://doi.org/10.1080/03772063.2017.1396934

Asymmetric H-Bridge Single-Phase Seven-Level Inverter Topology with

Proportional Resonant Controller
1 2 3
P. A. Salodkar , P. S. Kulkarni , Manoj A. Waghmare , P. C. Chaturvedi2 and Sandeep N 4

1
Electrical Engineering Department, Shri Ramdeobaba College of Engineering and Management, Nagpur, India; 2Electrical Engineering
Department, Visvesvaraya National Institute of Technology, Nagpur, India; 3Electrical Engineering Department, Yeshwantrao Chavan College of
Engineering, Nagpur, India; 4Electrical Engineering Department, NIT, Surathkal, India

ABSTRACT KEYWORDS
This paper presents an asymmetrical H-bridge single-phase seven-level inverter topology with Asymmetric source
modified gating scheme for reducing the number of high-frequency switches. Due to configuration; Current
controller; Multilevel
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shortcomings like steady-state error and problems in removing low-order harmonics associated
with proportional integral controller, proportional resonant controller is used for grid-connected inverters; Power quality;
Pulse-width modulation
converter current control. A practical application of proportional resonant current controller is
developed using a low-cost dsPIC33EP256MC202 microcontroller to keep the current injected in to
the grid. The validity of proposed inverter and control scheme is verified through simulation and
implemented for low-voltage laboratory prototype.

1. INTRODUCTION applications like flexible AC transmission systems FACTS,

electric drives, and renewable energy integration to grid
The recent advancement in power electronics is the multi-
[9–11].
level inverter and its suitability for grid connection. The
most industrial recommended topologies are the cascaded
Multilevel inverters has a limitation – for increased
H-bridge (CHB), neutral-point-clamped (NPC), modular
number of output voltage levels, they require large num-
multilevel converter (MMC), flying capacitor (FC), and its
ber of power semiconductor devices. So the topologies
variants [1–4]. The installed capacities of wind and PV
with reduced switch count are presented [12–15].
systems have witnessed an exponential growth over the
last decade. This quick growth has created an arena in
A hybrid operation of power semiconductor switches
view to exploit the wind and PV energy fully, wherein
with few operating at switching frequency with lower
many expeditious technologies in the field of converter
blocking voltage and remaining switches at line fre-
structures for enabling the integration of renewable-
quency with higher blocking voltage is found to be
energy-based system for electric power generation have
attractive at high power levels [16–18]. The topology
emerged. In the recent years, many efforts have been put
which is best suited for application and cost consider-
by the researchers to develop innovative topologies and
ation is more advantageous. A new power multilevel
pulse-width-modulation techniques, and this has led to
inverter with two power switches and one DC input
the advent of several structures with a claim of reduced
source named as “Packed U-cells” offers high energy
part count. Cascaded multilevel inverters produce a
conversion quality using small number of active and
medium output voltage based on a series connection of
passive devices is presented in [19,20]. A real-time
power cells to achieve high-quality output voltages and
implementation of seven-level packed U-cell Inverter
input currents. Therefore, the cascaded multilevel inverter
with a low switching frequency voltage regulator and
has been recognized as an important alternative in the
model predictive control (MPC) has been proposed
medium-voltage inverter market [5,6]. The current trends
[21,22]. Seven-level CHB inverter with a single isolated
and challenges faced by energy applications, such as
DC source and one capacitor with its voltage regulated
renewable power conversion and distributed generation
at the half of the DC source is presented [23]. Similarly,
systems, together with the recent developments in multi-
a DC source and one capacitor DC link are applied to
level converter technology, are opening a new vast area of
seven-level PUC inverter [24]. The application of seven-
applications. The recent advancement in multilevel con-
level PUC inverter as an active power filter is presented
verters and modulation strategies is presented in [7,8]. The
[25]. A hybrid multilevel inverter integrating half- and
multilevel converters are found useful in widespread
© 2017 IETE
 2 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER

full-bridge converter to generate seven-level output volt- illustrate its practicality, and the experimental results
age is detailed in [26]. obtained are included.

Neutral point potential (NPP) regulator for a three-level

diode-clamped inverter employing a sine-triangle regu-
lator in conjunction with a closed-loop controller with
reduced switching losses and comparison of total har-
monic distortion (THD) and switching losses in conven-
tional two-level inverters with multilevel inverters
(three-level and five-level) at different switching fre-
quencies is presented in [27,28].
Due to the development of distributed power generation
with renewable energy source, the research is more
focused on grid interface systems. The multilevel inverter
topology suitable for grid interface is presented in [29,30].
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2. PROPOSED TOPOLOGY
2.1 Working Structure
The proposed inverter structure is developed by consid-
ering a single-phase H-bridge inverter as a fundamental
building block, wherein, the two H-bridges are cascaded
to form a seven-level inverter. Unlike conventional CHB
inverter, all the power switches do not operate at high
frequency. Figure 1 shows the circuit of the proposed
multilevel inverter. As it can be observed, it requires
eight switches and two isolated sources.

Among which, the external switches S4 and S4 are

DC offset current problem is more critical in the case of responsible for polarity reversal of voltage across the
photovoltaic inverters connected to grid. So, control load and will operate only once in a half cycle of funda-
strategy of suppressing dc current injection to the grid mental voltage.
for PV inverters is required [31].
The magnitude of the inner source voltage is half of that
The generalized solution for grid converter is PWM cur- of the outer one such that
rent-controlled voltage source converter used in
single-phase and three-phase grid-connected system. Vdc1 ¼ 2Vdc2 (1)
Generally, PI controller with voltage feed forward is
For simplicity, Vdc2 ¼ Vdc =2 and Vdc1 ¼ Vdc are consid-
used for single-phase grid-connected system. However,
ered. This requirement of isolated sources makes it very
the major drawback of PI controller is stationary error
attractive for an application like photovoltaic power gen-
in stationary frame control. Hence proportional reso-
eration and it also obviates the need for an external bal-
nant current controller is used in single-phase grid-con-
ancing circuit of dc-link. The proposed topology is
nected system [32,33,34].
modular in nature and can be easily extended to a higher
number of levels by cascading additional inner
In this paper, an attempt is made to devise a novel topol-
H-bridges. From the reliability point of view, if the inner
ogy with reduced-part-count suitable for renewable
H-bridge fails, it can be bypassed, and the inverter can
energy integrations to the power system. Structurally, it
be operated with the three-level output voltage at its full-
consists of eight power switches split into two H-bridges.
rated power. Thus the proposed inverter exhibits an
These bridges are fed with an isolated source of magni-
improved reliability. Output voltage with seven-level
tude Vdc and Vdc/2, respectively. A logic-gate-based
including (3Vdc =2; Vdc ; Vdc =2; 0; Vdc =2; Vdc ;3Vdc =2)
PWM technique is developed for the generation of the
can be synthesized with proper switching sequence. Table 1
output voltage with seven levels. The notable feature of
shows the valid switching combination for generation of
the proposed PWM method is that half of the total
number of switches operate at line frequency (50 Hz)
and hence is more efficient. Generally, PR controller is
used in renewable applications or active filters. In all
the applications, the grid converter has to control the
current, dc voltage, and synchronization with the grid.
As the reference is always sinusoidal, PR controller can
be easily adopted. The PR controller is used to check
the suitability of proposed inverter topology for grid
integration. To validate and verify the concept, MAT-
LAB/SIMULINK-based simulations have been carried
out, and the results are presented. Also, the hardware Figure 1: Asymmetrical H-bridge single-phase seven-level inverter
implementation of proposed inverter is carried out to topology
 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER 3

Table 1: Switching sequence for seven-level inverter nal b is connected to the positive; the voltage applied
S1 S2 S3 S4 Vinv across the load is 3Vdc =2 as shown in Figure 2(f).
1
1
0
0/1
1
0/1
0
0
3Vdc/2
Vdc
(7) Maximum negative output (3Vdc =2): S2, S4 from
0 0 1 0 Vdc/2 the upper half and S1, S3 from the lower half are
0/1 0/1 0/1 0/1 0 ON, connecting the two sources in series. All other
1 1 0 1 ¡Vdc/2
0 0/1 0/1 1 ¡Vdc switches are OFF. The load terminal b is connected
0 1 0 1 ¡3Vdc/2 to the positive dc rail and a to the negative dc rail;
the voltage across the load is Vdc as shown in
Figure 2(g).
seven-level output voltage. In Table 1, the entry with “0”
represents the particular switch is OFF and “1” represents 2.2.1. Output Voltage
the particular switch is ON, respectively. As mentioned in modes of operation, four switches are
conducting in each mode. For the structure shown in
2.2 Modes of Operation Figure 1, switchesðSp; Sp Þfp ¼ 1; 2; 3; 4g are complimen-
tary. So the switching function associated with the
The operating mode throughout the generation of each switch S is given as
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level is as follows.
tðtÞ ¼ 1 S is ON
(1) Maximum positive output (3Vdc =2): S1, S3 from (2)
¼ 0 S is OFF
the upper half and S2, S4 from the lower half are
ON, connecting the two sources in series. All other Then the load voltage VL ðtÞ can be expressed in terms of
switches are OFF. The load terminal a is connected nodal voltage g p ðtÞ as
to the positive dc rail and b to the negative dc rail;
the voltage applied across the load is 3Vdc =2 as X
4
shown in Figure 2(a). VL ðtÞ ¼ g p ðtÞ (3)
p¼1
(2) Two-third maximum positive output (Vdc ): S1
from the upper half and S2, S3, S4 from the lower
half are ON. All other switches are OFF. The load Nodal voltage
terminal a is connected to positive dc rail and b to
the negative dc rail; the voltage applied across the g p ðtÞ ¼ ð1Þp f1  tðtÞgðVdc;p þ Vdc;p1 Þ (4)
load is Vdc as shown in Figure 2(b).
(3) One-third maximum positive output (Vdc =2): S1, whereas p ¼ f1; 2; 3; 4g and Vdc;0 ¼ Vdc;3 ¼ Vdc;4 ¼ 0
S2, S4 from the lower half and S3 from the upper
half, are ON. All other switches are OFF. The load From (3) and (4), the voltage across the load
terminal a is connected to the positive dc rail of
X
4    
the inner source and b to the negative dc rail; the VL ðtÞ ¼ ð1Þp ð1  tp Þ ðVdc;p þ Vdc;p1 Þ (5)
voltage applied across the load is Vdc =2 as shown p¼1
in Figure 2(c).
(4) Zero output: S1, S2, S3, S4 from the lower half This simplifies to
are ON. All other switches are OFF. Both the
load terminals a and b are short-circuited; the volt- VL ðtÞ ¼ f1  t2 ðtÞgðVdc2 þ Vdc1 Þ (6)
age applied across the load is 0 as shown in
Figure 2(d). The output voltage expressed in terms of input dc volt-
(5) One-third maximum negative output (Vdc =2): age and switching function is shown in Equation (6).
S1, S2, S4 from the lower half and S3 from the upper
half are ON. All other switches are OFF. The load 2.2.2. Output Current
terminal a is connected to the negative dc rail of Source current IpðtÞ through the source Vdc ; pfp ¼ 1; 2g
the inner source and b to the positive dc rail; the can be presented in terms of switching function and load
voltage applied across the load is Vdc =2 as shown current:
in Figure 2(e).
(6) Two-third maximum negative output (Vdc ): S1, S2, IpðtÞ ¼ ð1Þpþ1 ðt p  t pþ1 ÞIL ðtÞ (7)
S3 from the lower half and S4 from the upper half
are ON. All other switches are OFF. The load termi- For p ¼ 1; I1 ðtÞ ¼ IL ðtÞ and p ¼ 2; I2 ðtÞ ¼ IL ðtÞ
 4 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER

(a)

(e)
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(b)

(f)

(c)

(g)

(d)
Figure 2: Switching sequence required to obtain the seven-level output voltage (Vinv). (a) Vinv = 3Vdc/2, (b) Vinv = Vdc, (c) Vinv = Vdc/2, (d)
Vinv = 0, (e) Vinv = ¡Vdc/2, (f) Vinv = ¡Vdc, (g) Vinv = ¡3Vdc/2

2.2.3. Voltage Across Blocking Switches
Voltage stress Vstress;p for the switch pair (SP ; SP ) can be
given as
Vstress;p ¼ ðVdc;p1 þ Vdc;p Þ
where p ¼ f1; 2; 3; 4g and Vdc;0 ¼ Vdc;3 ¼ Vdc;4 ¼ 0
It shows that the four switches (S2 ; S2 and S3 ; S3 ) need to
block the voltage of Vdc =2 and four switches (S1 ; S1 and
S4 ; S4 S4 ; S 4 ) are to withstand the voltage Vdc .
(8)
From the above analysis, the significant features of the
proposed topology are as follows:
 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER 5

(a) Equal load sharing is possible with symmetrical

sources.
(b) Additive combination is possible but subtractive
combination is not possible, hence cannot be
used for trinary combination of DC sources.
(c) Number of switches conducting simultaneously
to synthesis various voltage level is the same, i.e.
4, so conduction losses and switching losses are
the same.
(d) Four switches are operated at fundamental fre-
quency, so the switching loss is comparatively
reduced.
(e) In this topology, inner four switches have to
block Vdc voltage and outer four switches have to
withstand 2Vdc.
(f) This topology is modular, by duplicating the
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inner bridge; it can work for higher level.

(g) The use of isolated DC sources makes the topol-
ogy suitable for renewable application.

2.3 Modified Gating Scheme (MGS)

Unlike multicarrier-based PWM, a modified gating
scheme (MGS) is presented in this paper. A logic-form-
equation for each junction is developed using the tech-
nique proposed in [17,18]. Three reference signals
(Vref1(t), Vref2(t), and Vref3(t)) are compared with a car-
rier signal (Vcarrier(t)). These reference signals are in
phase, and have the same frequency and amplitude. But
they differ only in terms of an offset added. The value of
the offset added is equal to the maximum amplitude of
the Vcarrier(t). Since the proposed inverter uses three ref-
erence signals, the modulation index is described in
Equation (9) as follows:

Vm
ma ¼ (9)
3Vc

where Vm is the peak value of the reference signal

and Vc is the peak-to-peak value of the carrier signal.
Figure 3 demonstrates the arrangement of these refer-
ence and carrier signals. Each of these reference sig-
nals is compared with the high-frequency carrier.
The outputs of this comparison are termed as com-
parator output C1, C2, and C3. Further to distinguish
the level transition, three region signals (R1, R2, and Figure 3: From top: multilevel PWM reference and carrier signals,
R3) are generated as expressed mathematically in comparator output signals, region signals
(10). R1 = 1 designates the level to be generated
either zero or Vdc/2; similarly, R2 = 1 indicates the cycle of the fundamental voltage. Once the region
voltage swing between Vdc/2 and Vdc; and R3 = 1 and decision signals are ready, the PWM signal gen-
indicates the voltage swing between Vdc and 3Vdc/2. eration for each power switch is carried out in the
These region signals repeat themselves for every half following way:
 6 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
R1 ¼ 1 u1  vt  u2 and u3  vt  u4
¼ 0 elsewhere
R3 ¼ 1 u2  vt  u3
(10)
¼ 0 elsewhere
R3 ¼ 1 u2  vt  u3
¼ 0 elsewhere
where
Vc 2Vc
u1 ¼ sin1 ; u2 ¼ sin1 ; u3 ¼ P  u2
Vm Vm
u4 ¼ P  u1
At a distinct instant of time, if the load voltage is Vdc,
then switches S1 ; S1 ; S3 and S4 are ON and the remaining
Downloaded by [University of Connecticut] at 01:22 18 December 2017
switches are OFF. If the load voltage is 0, then switches
S1 ; S2 ; S3 and S4 are ON and the remaining switches are
OFF. Repeating this process for the whole cycle will lead
to multilevel stepped output waveform. In this manner,
the gating signal for each switch is determined. The
redundancy in some of the levels (§Vdc and 0) is
selected such that the number of switching transitions is
minimum.
However, to express and implement the PWM technique
in real time, a mathematical relation defining the gating
signals is required. Difficulty mentioned above is
achieved by constructing the PWM signals through
appropriate logic operation among region and decision
signals.
Using the Boolean operation, the gating pulses for each
power switch are derived as expressed in (11). During
the implementation stage, signals C1, C2, and C3 come
from the respective comparators; while the region signals
are obtained from a look-up table approach. The gating
signals are generated after passing these signals through
appropriate logic gates built using (11). Another advan-
tage of the proposed logic-gate-based PWM is that it can
be implemented using a low-cost digital signal processor
(DSP) since it does not involve any complex computa-
tion to be performed. Once the gating signals are gener-
ated, using suitable gate drive circuit, the power switches
are to be triggered:
S1 ¼ ð½ðR2 C2 Þ þ R3 V þ Þ þ ð½R1 þ ðR2 C2 ÞV  Þ
S2 ¼ ½ðR1 þ R2 þ R3 V þ
S3 ¼ ð½ðR1 C1 Þ þ ðR3 C3 ÞV þ Þ þ ð½ðR2 C2 Þ
þðR3 þ C3 Þ þ R1 V  Þ
S4 ¼ S2 (11)
where V+ and V¡are defined as follows:
Vþ ¼ 1 f or Vref > 0
¼0
elsewhere
(12)

V ¼1 f or Vref > 0
¼0 elsewhere
The PWM signals generated using utilizing the proposed
technique mentioned above is illustrated in (11) and
(12). Except for gate signal for S1  S1 and S3  S3 ; the
remaining four devices operate only once in half cycle,
i.e. zero-voltage crossings. It is significant that the num-
ber of power switches conducting the load current at
any instant plays a vital role in determining the overall
inverter efficiency. For example, in seven-level inverter
topology, the number of power devices that conduct the
load current in each instance is six in number. Also, all
these six switches operate at high frequency. However,
in the proposed topology, half of the total number of
power devices, i.e. four switches, conducts the load cur-
rent at any given instance. Among which two operate at
50 Hz frequency. Therefore, the MGS and simplified
logic-gate-based (LGB) PWM are the main contribu-
tions; i.e. a new efficient PWM for reducing the number
of high-frequency switches is proposed. The proposed
inverter has a better efficiency as the number of active
switches is less at any instance in comparison to well-
established topologies available in the literature
[11,14,16].
3. PROPORTIONAL RESONANT CONTROLLER
For grid connection, it is important to select the cur-
rent controller that provides a high-quality sinusoidal
output with minimal distortion to avoid creating har-
monics. Generally, proportional integral (PI) control-
lers are used to control the current of grid-connected
converters. But it is not able to follow a sinusoidal ref-
erence without steady-state error due to the dynamics
of the integral term. Hence PI controller with voltage
feed-forward term is necessary to get good dynamic
response. The proportional resonant (PR) controller is
a good alternative in the case of single-phase grid-con-
nected system. It provides gain at only one frequency
(resonant frequency) and no gain at other frequencies.
It easily follows the sinusoidal reference without the
use of voltage feed-forward term. Hence, in this paper,
PR current controller is used for grid interface. It has
an advantage over conventional PI controller to
remove the stationary error and lower order harmon-
ics in current.
 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
Downloaded by [University of Connecticut] at 01:22 18 December 2017
Figure 4: Bode plot for PI controller
The performance of PI and PR controllers is verified
using frequency-domain analysis.
The transfer function of PI controller is defined as
Ki
GI ðsÞ ¼ KP þ (13)
s controller.
whereas the transfer function of PR current controller is
defined as
Ki s
GI ðsÞ ¼ KP þ
s2 þ v2
whereas Kp is the proportional gain term, Ki is the inte-
gral gain term, and v is the resonant frequency.
The bode plots of PI and PR controllers for Kp = 1, Ki =
1, 10, and 100 at v ¼ 2p50 are shown in Figures 4
and 5, respectively.
PR controller provides an infinite gain at the ac frequency
v and no phase shift and gain at the other frequencies.
Hence it has very high gain in a narrow frequency band
centred at the resonance frequency, whereas PI controller
mentioned in (13) has wide range of band for high values
of integral constant as shown in Figure 4.
Figure 5 shows bode plot for PR current controller,
which attains very high gain in narrow frequency band
centred on the resonance frequency v. For grid interfac-
ing, the grid frequency is almost constant but 1% varia-
tion is allowed. Hence appropriate value of v for PR
7
current controller can be calculated using frequency-
domain analysis. It concludes that PR controller can be
easily tuned for the desired frequency.
Figure 6 shows that single-phase asymmetric seven-level
PV inverter is connected to grid with PR current
In normal practice, PI controller is used, but it leads to
stationary error in tracking sinusoidal input and inability
to remove lower order harmonics in current. Hence PI
(14)
controller is replaced with PR controller to reduce the
complexity and to get desired output.
4. SIMULATION RESULTS
To verify the feasibility of the proposed inverter, MAT-
LAB/SIMULINK is used to simulate the power circuit
along with the proposed MGS and simplified LGB PWM
technique, wherein the characteristics of power devices
are assumed ideal. The voltages of the outer dc-source
and inner dc-source are set to 30 and 15 V, respectively.
A carrier frequency of 2 kHz at modulation index set to
one is employed. The system parameters used for simu-
lation are listed in Table 2. The inverter output voltage
and current waveforms with DC link voltage are shown
in Figure 7. It is clearly inferred that the output voltage
is made up of seven levels (¡45, ¡30, ¡15, 0, 15, 30,
and 45 V). The THD for the inverter current is found to
be 2.1% and the inverter output voltage is 18.03% for the
load considered.
 8 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
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Figure 5: Bode plot for PR controller

Figure 6: Block diagram of single-phase seven-level inverter con-

nected to grid

Table 2: System parameter used for simulation

Parameters Range/Ratings
Load voltage frequency 50 Hz
Inductive filter (Lf) 2.5 mH
DC voltage source (Vdc1) 30 V Figure 7: Simulated waveforms of inverter output voltage and
DC voltage source (Vdc2) 15 V current at RL load applied to filter
Switching frequency 2 kHz
AC grid voltage 25 V RMS
RL load 70 V, 10 mH
TLP250-based driver circuit. It is worth mentioning that
isolated dc power supply for each driver circuitry was
employed.
5. EXPERIMENTAL RESULTS
A down-scaled prototype shown in Figure 8 was devel- A low-cost dsPIC33EP256MC202 microcontroller is
oped in the laboratory to validate the performance of the programmed with MGS and simplified LGB PWM tech-
proposed inverter and its PWM control. A modular- nique to generate the necessary gating signals. Hioki
integrated PCB was developed housing both the switches 3196 power quality analyser is used to measure the THD
and drivers on the same board to reduce the effect of of current waveform. The values of the switching fre-
parasitic loop inductance between the gate driver and quency, load, and dc source voltage employed for experi-
the power devices. IRFP250N (200 V, 30 A) MOSFET is mental verification are the same as that of the simulation
employed as switching power devices gated with as listed in Table 3.
 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER 9

Figure 8: Laboratory prototype of single-phase seven-level inverter

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Table 3: Comparison of the proposed inverter with other

inverter topology
Inverter type [1] [3] [11] [14] [16] Proposed
Power switches HF HF 6HF + 2LF 6HF + 2LF 6HF + 4LF 4HF + 4LF
Clamping 0 30 0 0 0 0
diodes
DC bus 3 6 3 3 3 2
capacitors
Flying 0 0 0 0 0 0
capacitors

In this part, an asymmetrical H-bridge seven-level

inverter has been tested as a stand-alone supplier, which Figure 9: (a) PWM signals for S1 ; S1 and S2 ; S2 : (b) PWM signals
is connected to RL load with a small-size filter. The out- for S3 ; S3 and S4 ; S4
come of the PWM technique: after proper logic opera-
tions on the comparison of reference and carrier signals
resulting in the switching patterns of Figure 9(a) 9(b)
were obtained from the microcontroller which clearly
shows that the switches S2 ; S 2 and S4 ; S 4 are operating at
fundamental frequency, S3 ; S 3 at high switching fre-
quency, and S1 ; S 1 are operating at moderately high
switching frequency. So out of eight power electronic
switches, four switches are operating at fundamental fre-
quency. DC link voltage is supplied through rectifiers.
Figure 10 depicts the experimental output of the inverter
with seven-level voltage and load current while the
inverter is feeding a resistive and inductive load. The
voltage stress of each power switches is demonstrated in
Figure 11. One can notice that four switches (S2 ; S 2 and
S3 ; S 3 ) need to block a voltage of 15 V and only the
remaining four switches are to withstand 30 V. Figure 12 Figure 10: Measured waveforms of inverter voltage (Vinv) and
shows the steady-state operation of the seven-level current (Iinv) at RL load applied to filter terminal
asymmetrical inverter in grid-connected mode. Grid
voltage and current are synchronized, and the unity
power factor mode is successfully achieved. Figure 13 Experimental results show that grid current follows the
shows the THD of grid current which is found to be reference with the desired value without voltage feed-
2.88% when the inverter is connected to grid with PR forward term. Hence the practicability of the proposed
current controller. inverter with PR current controller is verified.
 10 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
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Figure 11: Measured experimental waveforms of voltage across active switches of inverter
 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
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Figure 12: Steady-state voltage and current waveforms for grid-
connected inverter
Figure 13: Total harmonic distortion of grid current measured
with power quality analyser
6. COMPARATIVE STUDY
To clearly illustrate the distinctive features of the proposed
inverter topology, a comparison of the number of compo-
nents among the proposed inverter and some of the classi-
cal multilevel and recent topologies is carried out and
tabulated in Table 3. Considered are some of the essential
and critical contributors in determining the overall inverter
cost and reliability. As mentioned earlier, the very promis-
ing feature of the proposed inverter is the significant
decrease in power switches and the number of high-
11
frequency components. Power electronic devices with high
frequency are the weakest link in comparison to low-fre-
quency switches from the system reliability point view.
Among the total eight switches, half of them operate twice
in full cycle (50 Hz) of the output voltage. This feature ele-
vates the overall efficiency since the average switching
power loss (Psw) in the device due to transition is given by
VDS IO ðton þ toff Þ
Psw ¼ (15)
2Ts
where ton and toff are the turn-on and turn-off delay time,
respectively; VDS is the blocking voltage across the switch;
and Io is the total current flowing through the switch; Ts is
the switching time interval. From (15), considering equal
turn-on and turn-off time, the average power loss is pro-
portional to the VDS and fsw ¼ 1=Ts . From Table 3, it is
seen that the proposed inverter has the maximum number
of devices operating at low frequency, indicating a signifi-
cant reduction in switching power loss (Psw ) compared to
other topologies. The outcome of the comparison results
indicates a significant reduction in overall components
requirement for the proposed inverter topology; therefore,
emerging as a potential candidate for high-power applica-
tions like HVDC and FACTS. Wherein, the use of pro-
posed inverter obviates the need for phase-shifting
transformer to generate a higher number of voltage levels.
It also suits as a custom power device like STATCOM,
thereby eliminates the need of multiple configurations
required in the conventional system to comply with the
stringent IEEE 1547 std. Currently, large-scale integration
of renewable has opened up a new platform for the advent
of innovative topologies. For which, the proposed inverter
appears to be a qualified candidate among the current
converter structures due to reduced size, cost, and control
complexity.
7. CONCLUSIONS
Applications urging a higher number of voltage levels
escalate the number of overall power components
required. In this paper, a new seven-level inverter is pro-
posed with superior characteristics over conventional
inverters regarding the number of power devices
required, isolated dc source, and reliability. A significant
reduction in the number high-frequency switching devi-
ces is an important merit of the proposed topology.
It requires only eight power switches among which four
operates at low frequency for generating the seven-level
output voltage. Moreover, an MGS and simplified LGB
PWM are the main contributions. The injected current to
grid was successfully controlled with PR current controller
 12 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
to have synchronized waveform with grid voltage at unity
power factor. A comparative study furnished at tests the
merit of the proposed topology over conventional inverters,
qualifying the proposed topology as a potential candidate
for power applications such as FACTS, HVDC, PV sys-
tems, etc. Simulation and experimental results obtained on
a laboratory-scale prototype presented depict a clear agree-
ment confirming the ability of proposed inverter in gener-
ating the multilevel waveform.
ACKNOWLEDGEMENTS
The authors are grateful to the authorities of VNIT, Nagpur,
and SRCOEM, Nagpur, for providing facilities to carry out the
research work.
Downloaded by [University of Connecticut] at 01:22 18 December 2017
ORCID
P. A. Salodkar http://orcid.org/0000-0002-9809-1064
P. S. Kulkarni http://orcid.org/0000-0001-6843-4399
Manoj A. Waghmare http://orcid.org/0000-0003-4151-
0122
Sandeep N http://orcid.org/0000-0002-2670-2049
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 14 P. A. SALODKAR ET AL.: ASYMMETRIC H-BRIDGE SINGLE-PHASE SEVEN-LEVEL INVERTER TOPOLOGY WITH PROPORTIONAL RESONANT CONTROLLER
Authors
Prachi Salodkar (S’09) was born in Nag-
pur, India, in 1981. She received the BE
degree in Electrical Engineering in 2002
from Shri Ramdeobaba College of Engi-
neering, RTM Nagpur University, Nag-
pur, India. She received her MTech
degree in Integrated Power System, RTM
Nagpur University, Nagpur, India, in
2009. She is currently working towards
the PhD degree in Department of Electrical Engineering, Vis-
vesvaraya National Institute of Technology, Nagpur, India.
She has total teaching experience of 10 years. Her research
interests include application of power electronics in power sys-
tem and renewable energy systems.
E-mail: salodkarpa@rknec.edu
Downloaded by [University of Connecticut] at 01:22 18 December 2017
P. S. Kulkarni graduated in Electrical
Engineering from the Walchand College
of Engineering, Sangli, Maharashtra, in
1987, He received his ME degree in Elec-
trical Power System from Government
College of Engineering, Amravati, in
1994 and his PhD degree for his thesis
on “Emission Constrained Economic
Dispatch”, from RTM Nagpur Univer-
sity, Nagpur, in 2002. He has total teaching experienced of
30 years at diploma, degree, and post-graduate level. He is
presently working as an associate professor in Electrical Engi-
neering Department of VNIT, Nagpur. His fields of interest
are AI applications in power operation and control, renewable
energy system including wind and PV systems.
E-mail: pskulkarni@eee.vnit.ac.in
Manoj A. Waghmare (S’16) graduated in
Electrical Engineering from B. D. College
of Engineering, Wardha, Maharashtra.
He received his MTech degree from Shri
Ramdeobaba College of Engineering,
Nagpur, in 2016. Currently, he is work-
ing with Yeshwantrao Chavan College of
Engineering, Nagpur, Maharashtra. His
research interests include application of
power electronics and drive.
E-mail: manoj10waghmare@gmail.com
CONTACT P. A. Salodkar
Pradyumn Chaturvedi received the BE,
ME, and PhD degrees in 1996, 2001, and
2010, respectively. He is currently work-
ing as an assistant professor in the
Department of Electrical Engineering,
Visvesvaraya National Institute of Tech-
nology, Nagpur, India. He is having
more than 15 years of teaching experi-
ence. He has published more than 70
research papers in international refereed journals and refereed
international/national conferences. He is Sr. Member IEEE
USA, Life Member ISTE India, and Member IET UK. He is
holding the position of Chair, Joint Chapter of Power Electron-
ics, Industrial Electronics & Industry Applications of IEEE Nag-
pur Sub-Section. He is also actively involved in IEEE
conferences as Track Chair, Technical Program Committee
and Advisory Committee. He is regular Reviewer of research
articles for IEEE Transaction on Power Electronics, IEEE
Transaction on Industrial Informatics, Electrical Engineering
(Springer’s), International Journal of Electronics (Taylor &
Francis), International Journal of Power Electronics (Inder-
science Publisher), Electric Power Components & Systems, IEEE
Student Conference SCEECS. His research interests include
power electronics, improved power factor converter, power
quality improvement, multilevel converters, electric drives,
and renewable energy harvesting.
E-mail: pc220774@gmail.com
Sandeep N. was born in Bengaluru,
India, in 1991. He received the diploma
and the BE degree in electrical and elec-
tronics engineering from the Sri Jayacha-
marajendra (Government) Polytechnic
and B. M. S. College of Engineering, Ben-
galuru, and the MTech degree in power
electronics and drives from the Visves-
varaya National Institute of Technology
Nagpur, Nagpur, India, in 2009, 2012, and 2014, respectively.
He is currently working towards the PhD degree with the
Department of Electrical and Electronics Engineering,
National Institute of Technology Karnataka, Surathkal, Man-
galuru, India. His research interests include multilevel power
converters and grid-connected photovoltaics. He received the
Best Poster Presentation Award for his paper at the 18th IEEE
National Power Systems Conference 2014, Indian Institute of
Technology Guwahati, Guwahati, India.
E-mail: sandeepbabu28@gmail.com
salodkarpa@rknec.edu