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Electronic Design II
(EE124‐01) Lecture 20
HIU‐YUNG WONG
APR. 13, 2020
hiuyung.wong@sjsu.edu, Office: ENG363
http://www.sjsu.edu/people/hiuyung.wong/index.html
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Outline
Frequency Response (The technique used here is a part of the mid‐term review!)
◦ Frequency response of single stage amplifier
Review
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Announcements
Assignment 4 solution will posted later today.
Mid‐term 2: Apr 15, Ch 9, 10, 11 (cascode, differential amplifier, frequency response)
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Article of the Day
IC fabrication involves the addition and removal
of many patterned layers of different materials to
create a functional semiconductor device. During
the manufacturing process, it is critical that each
patterned layer is precisely aligned to the
previous layer to ensure electrical contact and
produce a functioning device.
overlay error budget is approaching the sub‐2 nm threshold
Advanced DRAM and 3D NAND memory devices – with their
complex design features, high aspect ratio structures, opaque
materials, and thick film stacks that produce high wafer stress –
introduce a new set of challenges to overlay metrology
systems.
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About Mid‐term – Everyone
The format of mid‐term is similar to mid‐term 1 but
1. online
2. it will be broken down into many small steps. You need to enter only the final answer for each step.
There will be no partial score for the steps (and it is no need because each step bears only a few
points).
3. You can have your own draft paper. Not need to submit. However, I encourage you to take photos
on them within 5 mins after the exam and keep the time stamps. This is just in case you failed the
submission. Any photos taken 5 mins after the exam will not be accepted.
4. No cheat sheet
5. Show your draft paper are blank during inspection
6. Remember to submit your paper before the end of the
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About Midterm – for Zoom users
Those who use Zoom – You can only take the midterm through zoom if you have contacted me
and got my approval.
◦ I have sent an email (not announcement) about which zoom url to use to take midterm 2 online exam. If
you have not received, please let me know.
◦ Do not use the url in the previous slides for Zoom exam. Use the one I sent you in email.
◦ Make sure your Webcam is working
◦ Join Zoom 10mins early
◦ Please go to restroom before the exam
◦ This is closed book. And you are NOT allowed to use any resources including cell phone. To avoid cheating,
you should not have cell phone and other electronic devices.
◦ You need to turn on your video all the time. Have the video facing you and your workspace. But don’t
show your answer.
◦ You should have minimal use of computer. You need to close all other apps except the browser to access
Canvas. After the exam starts, I will request each of you share your screen in turn to show that you only
open the browser. During the exam, I might request some of you to share randomly.
◦ Whenever I suspect you are not only reading the exam paper, I will request you to share the screen
immediately.
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There are only 3
questions but
Format and Cheat Sheet broken into many
parts
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4
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What did we learn in the last lecture?
PMOS version?
HW4, Q10C
Transit Frequency
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Frequency Response of CS stage
Now we combine bias capacitors (important for low
frequency, short for high frequency) and MOSFET intrinsic
capacitors together (open for low frequency, important for
Chapter 11 high frequency)
Frequency Response
Our goal is to plot the Bode plot of the amplifier
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Frequency Response Analysis
No worry, this is a map, refer to it when needed
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LF Response of CS Amplifier
This is how we usually bias CS Amplifier
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Midband Gain of CS Stage
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High Frequency Response of CS
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High Frequency Response of CS
Include Voltage Source Resistor (Rs’)
CS stage suffers Miller Effect!
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Input Impedance
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CG Amplifier (LF response)
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Example: CG Amplifier (HF Response)
1. Draw the relevant circuit: 2. Simply the circuits (lump the caps) 3. Find the poles
Any Miller Effect?
How large is input pole frequency?
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Some Fundamental Definitions
Av = ‐ Gm Rout
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Cascode Output Impedance
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Cascode Gm
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Current Mirror
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Differential Amplifier
Concept of Virtual ground
and
Half Circuit Technique
How much current goes through each branch?
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Pen and Paper Time
What is the Vp‐p for Vout=Vx‐Vy?
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Input CM Noise with Ideal Tail Current
RSS=infinity RSS is finite
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CM to DM Conversion, ACM‐DM
Why the loading resistance are different?
What happens to Vout1‐Vout2 when there is VCM?
Therefore, common mode input (VCM) is converted
to differential mode output
Vout R D
ACM -DM
VCM 2 RSS
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Common Mode Rejection Ratio (CMRR)
ADM
CMRR
ACM DM
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CMRR Example
M3
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