Decoder design

Cu Rebeca, Gutiérrez José, Ventura Adriana, Yerbes Pablo

Digital Signal Processing
Universidad Autónoma de Yucatán, Facultad de Ingeniería
Mérida, México

Abstract — FPGA is a digital reconfigurable ASIC. Today, it As we can see, the outputs of the device are the ratio of the
is being used in many industries for a variety of reasons. This mini terms, where only one output terminal is activated at a
document is a report on Laboratory 3 and how to use logical time in relation to each of the input combinations.
functions.

I. INTRODUCTION
A decoder is a combinational circuit that converts a binary
input code of n bits into m output lines, where m is the number
of combinations of the input code, m = 2n. Its operational
function is based on the introduction of a binary code number
in its inputs and converting it into an equivalence pattern. For
example, Figure 3.1 illustrates the internal diagram of decoder
7447 composed of several logical elements. The decoder is
internally formed by logic gates and its internal connections Figure 2. Truth table
are a system predefined by the designer so that its operational
function has a perfect and effective coupling. By using the above truth table, for every output function, the
Boolean expression can be written: a = F1 (X, Y, Z, W) = ∑m
(0, 2, 3, 5, 7, 8, 9)

In relation to the truth table in Figure 2, only the output 𝐷! is

equal to 1 when the input variables are equal to the
combination 𝐴 "= 0, 𝐴! = 0, the output 𝐷" is equal to 1 when
the input variables have the combination 𝐴 "= 0, 𝐴! = 1, and
thus As a consequence, the decoder circuit implements the four
possible mini terms of two variables, a mini term for each
output. In the logical diagram of Figure 3, each mini term is
implemented by an AND gate with two input terminals.

Figure 3. Decoder function

Figure 1. Schematic circuit of a decoder
II. METODOLOGY
Another function of the decoder is presented in Figure 2, this In this laboratory, the design of a 7-segment BCD decoder is
figure illustrates a truth table that describes its functionality. implemented, which can be carried out following the
procedure described in the following example. To achieve the
above, in this laboratory we will rely on the diagram presented
in Figure 4.
A. How a seven segment display should work
Figure 4. Seven segment display
Figure 5. Testbench simulation
Figure 6. Functions generated by blocks
As a result of the code implemented in Verilog, the code of the
test bench and the simulations, we can verify that the behavior
is what we expected from the logic diagram.
III. RESULTS
A. Testbench waveform for BCD to 7 Segment Display
Decoder
Figure 7. Testbench waveform
IV. CONCLUSIONS
One of the characteristics that we must take into account is that
a logic circuit does not have to be represented in a standardized
and common way. There are several ways for this to occur as
alternative factors to the ones and zeros presented by the binary
information that has been loaded into a digital component. For
example, we can see it with the balance that exists between the
on and off function or in which you simply resort to a switch
that is open or closed with respect to the transmission of
energy. Therefore, depending on the position occupied by a
switch, a digital device can act or not without a major change
in its internal processes. To count and manage these variables,
truth tables are used.
V. REFERENCES
Viewpoint Systems (2019). FPGA Basics for Industrial
Applications. IEEE Communications Spectrum.