Professional Documents
Culture Documents
• Bi-positional switch
• PWM and duty ratio
• Cycle-by-cycle averaging
• Concept of DC steady-state
• Volt-sec balance
• Current-sec balance
• Power balance
+ +
1 iA ( t )
iA Vd
A
Vd A +
v AN ( t )
2 −
−
- N
Pulse Width
Modulator SPST
SPDT vc A ( t ) q A ( t ) implementation
(single pole double throw)
+ 1
D1
S1 Which devices conduct?
iA (t)
A
qA= 1 qA= 0
D2 + iA > 0 S1 D2
S2 vA (t) iA < 0 D1 S2
_ 2 _
q A (t ) 0 t
TS
Example:
Switching frequency, fS = 200 kHz
Period, TS = 1/ fS = 5 us
q A (t ) 0 t
TON
duty ratio, d A =
TS
• Duty ratio is the main control variable
Vd 0 T
ON t
vA(t) TS
Vd
Avg(vA)
0
0
vA (t)
d = 0.75
12V
v A 9V
0 t
0
vA (t) d = 5/14
14V
v A 5V
0 t
⇒ vA (t ) =
0
Vd TON t
vcA < vramp ⇒ q A ( t ) =
0 ⇒ bottom switch ON TS =1/fs
⇒ vA (t ) =
0
TON
Duty ratio, d A =
Ts
Raja Ayyanar, ASU
Relationship between duty ratio and control voltage
vramp
V̂ramp
1
+ vc A
Vd
+
0
vA
− qA t1 t
−
1
vc A 0
qA t
vvAN
A
Vd
Vˆramp Vˆramp = 1
vramp ( t ) = t 0 ≤ t < Ts
Ts avg (vvAN
A)
0
Vˆramp Vˆramp t
vramp ( t1 ) =
TON
t1 = TON = vcA
Ts Ts TS =1/fs
TON
= dA
Ts For Vˆramp = 1, d A ( t ) = vc A ( t )
1 0 ≤ vc A ( t ) ≤ 1
d A (t ) = vc A ( t )
Vˆramp 0 ≤ vc A ( t ) ≤ Vˆramp For this course we will assume Vˆramp = 1
iL +
Vd = Vo
+ Rload
Vin vA −
• Bi-positional switch
• PWM and duty ratio
• Cycle-by-cycle averaging
• Concept of DC steady-state
• Volt-sec balance
• Current-sec balance
• Power balance
Cycle-by-cycle averaging (CCA)
1 t
x t x d
Ts t Ts
x (t )
x (t )
TS =1/fs t
qA(t) 1 qA d
0T (t)
ON
TS t
vAN (t)
Vd v AN ( t ) = Vd q A ( t )
v A d Vd
0 t
1 t TON t
q A t q A t dt d t
TS t Ts TS
1 t 1 t
v AN v AN
t dt Vd q A t dt Vd d t
TS t Ts TS t Ts
v A (t )
v A (t )
iL (t )
iL (t )
f m : 50 Hz f s : 5 kHz
v AN ( t )
(V)
Ts
v AN ( t )
(V)
Time (s)
i1 ( t ) i3 ( t ) i1 t i2 t i3 t 0
Integrating both sides and dividing by TS
i2 ( t ) 1 t 1 t 1 t
i1 t dt i2 t dt i3 t dt 0
TS tTs TS tTs TS tTs
i1 i2 i3 0
io
x
+ vL − iC
y = vo
iL − iC − io =
0 −v A + vL + vo =
0
v t R i t v t R i t
d d
vL t L iL t vL t L iL t
dt dt
d d
iC t C vC t iC t C vC t
dt dt
d 1
()
x=
t x ( t ) − x ( t − Ts )
dt Ts
• Bi-positional switch
• PWM and duty ratio
• Cycle-by-cycle averaging
• Concept of DC steady-state
• Volt-sec balance
• Current-sec balance
• Power balance
DC steady state in power converters
In non-switching circuits,
Transient Steady state DC steady state can be defined
iL as a condition when all the
(A)
variables (voltages, currents)
are CONSTANT in time
vC
(V)
vA (t)
(V)
iL (t)
(A)
Time (s)
v A (t )
v A (t )
iL (t )
iL (t )
• Bi-positional switch
• PWM and duty ratio
• Cycle-by-cycle averaging
• Concept of DC steady-state
• Volt-sec balance
• Current-sec balance
• Power balance
diL t dvC t
vL t L iC t C
dt dt
X
X X
X
Raja Ayyanar, ASU
Volt-sec balance in inductors
vL = 0
d iL
vL = L
dt iL
since, iL should beconstant +
d iL vL
in steadystate, =0 -
dt
d iL
∴ vL = L =
0
dt
Raja Ayyanar, ASU
Volt-sec balance in inductors
vL (t)
V1 Area A = Area B
A
0
t
B V2
d Ts (1 − d )Ts
Ts
V1 d + V2 (1 − d ) =
0
Raja Ayyanar, ASU
Volt-sec balance in inductors
vL = 0 iL ( t0 + Ts ) =
iL ( t0 )
vL
(V), (A)
iL
Time (s)
vL
(V), (A)
iL
Time (s)
vL
(V), (A)
iL
Time (s)
Ideal diode
Invalid
(with ideal diode and
ideal inductor)
iC = 0
d vC
iC = C =0
dt
(since, vC should beconstant
in steadystate)
iC (t)
I1 Area A = Area B
A
0
t
B I2
d Ts (1 − d )Ts
I1 d + I 2 (1 − d ) =
0
Raja Ayyanar, ASU
Current-sec balance in capacitors
iC = 0 ⇒ vC remains constant
vC
iC
(V), (A)
Time (s)
iC
(V), (A)
vC
Time (s)
Invalid
(with ideal diode and
ideal capacitor)
• Bi-positional switch
• PWM and duty ratio
• Cycle-by-cycle averaging
• Concept of DC steady-state
• Volt-sec balance
• Current-sec balance
• Power balance
Power balance
• Neglecting all losses, and in an average (CCA) sense
and under steady state, input power equals output power
iin
pin = po
+ pin iint io
vin A
+
- +
vint p vo
int po
-
-
N
_______ _______
p=
in ( vin iin=) p=
o ( vo io )
px ≠ vx ix
• But, normally for dc-dc converters with dc input voltage source
and regulated dc output voltage and smooth dc output current,
=pin V=
in iin ; po Vo I o
iin
=
pin p=
int po +
vin
pin
A
iint io
+
- +
in steady-state and with no losses vint p vo
int po
-
-
N
px ≠ vx ix
• Need to be careful in writing
_______
pint = ( vint iint )
Raja Ayyanar, ASU
Power balance
• Power balance is NOT valid in an instantaneous sense
even in steady-state
• Power balance is NOT valid during transients
even in CCA sense
• Both the above because of storage elements – L and C
• In general,
dE ( t )
in ( t )
p= po ( t ) +
dt
E is the total stored energy (in all L and C)
+
D = 0.4 Valid 5Ω
Vo
− 24V network
−
iin
6 A−
4 A−
0
4 10 14 t (µs)