Quiz – 2

1) We will be requiring 8 flip-flop as we required flip-flop when

always @(posedge clk/negedge clk) is used as they produce
synchronous output and for every single bit assigning through
non-blocking assignment in this always block we need 1 flip-
flop hence we here require 8 flip-flop as here we are assigning
8 bits through non-blocking assignment in always @(posedge
clk) block .Hence ans is 8 Flip-Flop.
2) Code of top_comp module :
module top_comp(
input [1:0] A,
input [1:0] B,
output res
);

compare in1(.A(A[1]),.B(A[0]),.C(B[1]),.D(B[0]),.out(res));
endmodule

Code of compare module :

module compare(
input A,
input B,
input C,
input D,
output wire out
);

assign out =(A&(~C))|((B & (~C))&(~D))|((~D & A)&B);

endmodule
Truth Table of the code :
A B C D Output
0 0 0 0 0
0 1 0 0 1
1 0 0 0 1
1 1 0 0 1
0 0 0 1 0
0 1 0 1 0
1 0 0 1 1
1 1 0 1 1
0 0 1 0 0
0 1 1 0 0
1 0 1 0 0
1 1 1 0 1
0 0 1 1 0
0 1 1 1 0
1 0 1 1 0
1 1 1 1 0
A[1] = A
A[0] = B
B[1] = C
B[0] = D
K-Map :
 From KMap we get the logic of gates to be written
which is : AC’+BC’D’+ABD’
Hence from this logic I have implemented the the compare
module and hence made the comparator of 2 bit inputs A
and B.
3) FSM state diagram :
Present Bump_le Bump_rigth Next Walk_left walk_righ
State ft State t
S0 1 0 S1 0 1
S0 1 1 S1 0 1
S0 0 1 S0 1 0
S0 0 0 S0 1 0
S1 0 0 S1 0 1
S1 0 1 S0 1 0
S1 1 0 S1 1 0
S1 1 1 S0 0 1
S1 Areset==1 S0 1 0
S0 Areset==1 S0 1 0

From question we know that default state is s0 and when

bump_left is equal to 1 then the state changes to s1 and if
bump_right is equal to one after that we get to s0 again and if
bump_left not equal to 1 then state is s0 and if in case of s1 if
bump_right not equal to 1 then the state is s1 again.

Code of lemings module :

module lemings(
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);

reg present_state, next_state;

parameter s0 = 1'b0,s1 = 1'b1;

always @(*)
begin
present_state<=next_state;
end

always @(posedge clk or posedge areset)

begin
if(areset==1)
next_state<=s0;
else
begin
case (present_state)
s0 : if(bump_left==1)
next_state<=s1;
else
next_state<=s0;
s1 : if(bump_right==1)
next_state<=s0;
else
next_state<=s1;
 default :
next_state<=s0;
endcase
end
end
assign walk_left = (present_state==s0);
assign walk_right = (present_state==s1);
endmodule

I have written the code from the basic state diagram of the
machine I know that as the next state is changed my present
state must also change hence we have define it in always @(*)
block and then for calculating next state I have made a always
@(posedge clk or posedge areset) as if areset is 1 then next
state is s0 and we are checking first that after that we are
checking that if state is s0 and we have got input that
bump_left==1 then state changes to s1 otherwise it is s0 only
and for the case if state is s1 and input is bump_right==1 then
we change state to s0 otherwise it remain same default state of
the machine is given to be s0. At last we know that if present
state is s0 then we are moving left hence we are assigning
walk_left equal to Boolean of present state == s0 and similarly
for the walk_right we have assigined. We consider a case that
your state was s0 and the walk_left==1 then we have
bump_left and bump_right both equal to 1 in that case as we
know that bump_right is 1 hence its state will change to s1 and
we will get walk_left inversed as present state changed to s1
and walk_right will also get inversed as the present state
changed to s1 hence walk_left would we 1(In this case only the
if statement of the state is processed as if is true then we never
 run else and also it is given after passing from this it will run
agiain at the posedge of clk or posedge of areset).

4) (a) The given code is of 32 bit shift register as we can see from
code because here we can see that serial input from SI is
concatenated with first 31 bits of the value present in data. SEL
acts as a register which holds 32 address the bit value
corresponding to the address is passed to DO which is our
output. As if reset =1 at posedge of clock then data will become
0 else if reset is not 1 we assign data = data[30:0] hence we
conclude it is a 32 bit shift register.
Output size = 32 bit
Input size = 1 bit
No of address = 32
As we have used 32 flip-flop in this because it is a 32 bit shift
register hence there will be a latency(delay from input to
output)is of 32 clock cycle.

(b)As we are using 32 flip-flop so we are here using 2 clb as 1

clb has 16 flip-flop. Here we are using 32 flip-flop.

(c)As we only have 32 1 bit address and the shift register

chaining and F7AMUX F7BMUX and F8MUX multipliers allow
upto 128 bit shift register with addressable access to one
SLICEM and hence we can have one sliceM to store 32 address
and as 1 clb contain 1 SLICEM hence we can decrease the need
of use of 2 clb to 1 clb hence decreasing the need by 50%.
Instead of using 32 flip-flop we are using 1 SliceM to decrease
the number of clb.