CSE 675.

02: Introduction to Computer Architecture

Arithmetic / Logic Unit – ALU

Design

Presentation F

Reading Assignment: B5, 3.4 Slides by Gojko Babi

32-bit ALU
ALU Control

A 32

32 Result
32-bit
ALU Zero
Overflow
Carry out
B 32

•
Our ALU should be able to perform functions:

– logical and function
– logical or function
– arithmetic add function
– arithmetic subtract function
– arithmetic slt (set-less-then) function
– logical nor function
•
ALU control lines define a function to be performed on A and B.
g. babic Presentation F 2

1
 Functioning of 32-bit ALU
ALU Control
ALU Control lines 4
Function Ainvert Binvert Operation
32
and 0 0 00 A
32 Result
or 0 0 01 32-bit
add 0 0 10 ALU Zero
Overflow
subtract 0 1 10 Carry out
B 32
slt 0 1 11
nor 1 1 00

•
Result lines provide result of the chosen function applied to values of

A and B
•
Since this ALU operates on 32-bit operands, it is called 32-bit ALU
•
Zero output indicates if all Result lines have value 0
•
Overflow indicates integer overflow of add and subtract functions;
for unsigned integers, this overflow indicator does not provide any useful
information
•
Carry out indicates carry out and unsigned integer overflow
g. babic Presentation F 3

Designing 32-bit ALU: Beginning

1.
Let us start with and function Operation = 0  and
2.
Let us now add or function = 1  or

a0
0 Result0
b0
1

a1 Result1
0
b1
1

a2
0 Result2
b2
1

a31
0 Result31
b31
1

g. babic 4

2
 Designing 32-bit ALU: Principles
•
A number of functions Operation = 0  and
are performed inter- = 1  or
nally, but only one
a0
result is chosen for and
0 Result0
b0
the output of ALU or 1

a1 and Result1
0
b1
•
32-bit ALU is built or 1
out of 32 identical
a2
1-bit ALU’s and
Result2
0
b2
or 1

a31 and
0 Result31
b31
or 1

g. babic 5

Designing the Adder

•
32-bit adder is built out of 32 1-bit adders

1-bit Adder 1-bit Adder Truth Table

Input Output
a b Carry Sum Carry
Figure B.5.2 In Out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0

From the truth 0 1 1 0 1

table and after 1 0 0 1 0
minimization, we 1 0 1 0 1
can have this 1 1 0 0 1
design for CarryOut
1 1 1 1 1
Figure B.5.5 Figure B.5.3
g. babic Presentation F 6

3
 32-bit Adder
“0”

a0 Cin
sum0
b0
+
Cout

This is a ripple carry adder.

a1 Cin
sum1
b1
+
Cout
The key to speeding up addition
is determining carry out in the
Cin
a2 sum2 higher order bits sooner.
+
b2
Cout Result: Carry look-ahead adder.

a31 Cin
sum31
b31
+
Cout

Carry out
g. babic Presentation F 7

32-bit ALU With 3 Functions

=0

1-bit ALU

Operation = 00  and
= 01  or
= 10  add

Figure B.5.6

Figure B.5.7
CarryOut
+ carry out

g. babic Presentation F 8

4
 32-bit Subtractor
“0”
“1”

a0 Cin A – B = A + (–B)
Result0
b0
+
Cout =A+B+1

a1 Cin
Result1
b1
+
Cout

a2 Cin
Result2
b2
+
Cout

a31 Cin
Result31
b31
+
Cout

CarryOut

g. babic Presentation F 9

32-bit Adder / Subtractor

binvert
“0”

a0 Cin
Result0
b0
0 +
Cout
1

a1 Cin
Result1
b1 0
+
Cout

a2 Cin Binvert = 0  addition

Result2
b2 0
+ = 1  subtraction
Cout

a31 Cin
Result31
b31 0
+
Cout

1 0 CarryOut

g. babic 1 10

5
 32-bit ALU With 4 Functions
1-bit ALU B in v e r t O p e r a tio n

B in ve rt O pe ra tion
C a r r y In
a0 C a rryI n
b0 ALU0 R e s u l t0
a
0
C a rryO u t
1
R e s u lt

a1 C a rryI n
b 0 2 b1 ALU1 R e s u l t1
1
C a rryO u t
Figure B.5.8
C a r ry O u t
a2 C a rryI n
b2 ALU2 R e s u l t2

Control lines C a rryO u t

Function Binvert Operation

(1 line) (2 lines)
C a rr y In
and 0 00
or 0 01 a3 1 C a rryI n R e s u l t3 1
b3 1 A L U 31
add 0 10
subtract 1 10
0 Carry Out
g. babic Presentation F 1 11

2’s Complement Overflow

B in v e r t O p e r a tio n
•
2’s complement overflow C a r ry In

happens:
– if a sum of two positive a
0

numbers results in
a negative number 1

– if a sum of two negative R e s u lt

numbers results in b 0
+ 2

a positive number 1

L e ss 3

Carry Out

O v e r f lo w
O v e rflo w
d e te c tio n

1-bit ALU for the most significant bit

Other 1-bit ALUs, i.e. non-most significant bit ALUs, are not affected.

g. babic Presentation F 12

6
 32-bit ALU With 4 Functions and Overflow
B in v e r t O p e r a tio n

a0 C a rryI n
b0 ALU0 R e s u l t0

C a rryO u t

Control lines
a1 C a rryI n
Function Binvert Operation b1 ALU1 R e s u l t1
(1 line) (2 lines) C a rryO u t
and 0 00

or 0 01 a2 C a rryI n
b2 ALU2 R e s u l t2
add 0 10
C a rryO u t
subtract 1 10

C a rr y In

a3 1 C a rryI n R e s u l t3 1
b3 1 A L U 31
O v e r flo w
Missing: slt & nor functions and Zero output
Carry Out
g. babic Presentation F