Ultra High CMR, Small Outline,

5 Lead, High Speed Optocoupler

Technical Data

HCPL-M454

Features Applications • Line Receivers - High com-

• Function Compatible with • Inverter Circuits and mon mode transient immunity
HCPL-4504 Intelligent Power Module (>15 kV/µs for a TTL load/
• Surface Mountable (IPM) Interfacing - Shorter drive) and low input-output
propagation delays and capacitance (0.6 pF).
• Very Small, Low Profile
guaranteed (tPLH - tPHL) • Replace Pulse Trans-
JEDEC Registered
specifications. (See Power formers - Save board space
Package Outline
Inverter Dead Time section). and weight
• Compatible with Infrared
Vapor Phase Reflow and • High Speed Logic Ground • Analog Signal Ground
Wave Soldering Processes Isolation - TTL/TTL, TTL/ Isolation - Integrated photon
LTTL, TTL/CMOS, TTL/ detector provides improved
• Short Propagation Delays
LSTTL linearity over phototransistors
for TTL and IPM
Applications
• Very High Common Mode Outline Drawing (JEDEC MO-155)
Transient Immunity:
Guaranteed 15 kV/ µ s at
VCM = 1500 V
ANODE 1 6 VCC
• High CTR: >25% at 25°C
MXXX 7.0 ± 0.2 5 VOUT
• Guaranteed Specifications 4.4 ± 0.1
(0.173 ± 0.004)
XXX (0.276 ± 0.008)
for Common IPM CATHODE 3 4 GND
Applications
• TTL Compatible
TYPE NUMBER (LAST 3 DIGITS)
• Guaranteed ac and dc 0.4 ± 0.05
(0.016 ± 0.002) DATE CODE
Performance Over
Temperature: 0°C to 70°C 3.6 ± 0.1*
(0.142 ± 0.004)
• Open Collector Output
0.102 ± 0.102
• Recognized Under the 2.5 ± 0.1 (0.004 ± 0.004) 0.15 ± 0.025
(0.098 ± 0.004) (0.006 ± 0.001)
Component Program of
U.L. (File No. E55361) for
Dielectric Withstand Proof 1.27 BSC
(0.050)
0.71 MIN.
(0.028)
Test Voltage of 3750 Vac. 1
MAX. LEAD COPLANARITY
Minute DIMENSIONS IN MILLIMETERS (INCHES) = 0.102 (0.004)
• Lead Free Option “-000E” * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's
susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken
in handling and assembly of this component to prevent damage and/or degradation which may be induced by
ESD.
 2

Description The HCPL-M454 CTR, propaga- the light emitting diode and an
The HCPL-M454 is similar to tion delays, and CMR are integrated photon detector to
Agilent’s other high speed specified both for TTL load and provide electrical insulation
transistor output optocouplers, drive conditions and for IPM between input and output.
but with shorter propagation (Intelligent Power Module) load Separate connections for the
delays and higher CTR. The and drive conditions. Specifica- photodiode bias and output
HCPL-M454 also has a tions and typical performance transistor collector increase the
guaranteed propagation delay plots for both TTL and IPM speed up to a hundred times over
difference (tPLH - tPHL). These conditions are provided for ease that of a conventional photo-
features make the HCPL-M454 of application. transistor coupler by reducing the
an excellent solution to IPM base-collector capacitance.
inverter dead time and other This diode-transistor optocoupler
switching problems. uses an insulating layer between

Absolute Maximum Ratings

(No Derating Required up to 85°C)
Storage Temperature .................................................... -55°C to +125°C
Operating Temperature ................................................ -55°C to +100°C
Average Input Current - IF ......................................................... 25 mA[1]
Peak Input Current - IF .............................................................. 50 mA[2]
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - IF ................................................... 1.0 A
(≤1 µs pulse width, 300 pps)
Reverse Input Voltage - VR (Pin 3-1) .................................................. 5 V
Input Power Dissipation ........................................................... 45 mW[3]
Average Output Current - IO (Pin 5) ............................................... 8 mA
Peak Output Current .................................................................... 16 mA
Output Voltage - VO (Pin 5-4)............................................ -0.5 V to 20 V
Supply Voltage - VCC (Pin 6-4) .......................................... -0.5 V to 30 V
Output Power Dissipation ....................................................... 100 mW [4]
Infrared and Vapor Phase Reflow Temperature ....................... see below

Solder Reflow Thermal Profile

300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
PEAK
TEMP.
TEMP.
245°C
240°C
PEAK
TEMP.
230°C
TEMPERATURE (°C)

200
2.5°C ± 0.5°C/SEC.
SOLDERING
30 TIME
160°C 200°C
150°C SEC.
140°C
30
3°C + 1°C/–0.5°C SEC.

100
PREHEATING TIME
150°C, 90 + 30 SEC. 50 SEC.

TIGHT
TYPICAL
ROOM
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)
 3

Recommended Pb-Free IR Profile

TIME WITHIN 5 °C of ACTUAL

PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

Schematic Land Pattern Recommendation

ICC
6 4.4
VCC (0.17)

+ IF
ANODE 1.3
1 (0.05)
2.5
VF (0.10)
IO 5
– VO
CATHODE
3

4
SHIELD GND 2.0
(0.080) 0.64
(0.025)
8.27
(0.325)

DIMENSION IN MILLIMETERS (INCHES)

Insulation Related Specifications

Parameter Symbol Value Units Conditions
Minimum External Air Gap L(IO1) ≥ 5 mm Measured from input terminals
(Clearance) to output terminals
Minimum External Tracking Path L(IO2) ≥ 5 mm Measured from input terminals
(Creepage) to output terminals
Minimum Internal Plastic Gap 0.08 mm Through insulation distance
(Clearance) conductor to conductor
Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109
 4

DC Electrical Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. (See note 11)
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Current CTR 25 32 60 % TA = 25°C VO = 0.4 V IF = 16 mA 1,2,4 5
Transfer
Ratio 21 34 VO = 0.5 V VCC = 4.5 V
Current CTR 26 35 65 % TA = 25°C VO = 0.4 V IF = 12 mA 1,2,4 5
Transfer
Ratio 22 37 VO = 0.5 V VCC = 4.5 V
Logic Low VOL 0.2 0.4 V TA = 25°C IO = 3.0 mA IF = 16 mA
Output
Voltage 0.2 0.5 IO = 2.4 mA VCC = 4.5 V
Logic High IOH 0.003 0.5 µA TA = 25°C VO = VCC = 5.5 V IF = 0 mA 5
Output
Current 0.01 1.0 TA = 25°C VO = VCC = 15 V

50
Logic Low ICCL 50 200 µA IF = 16 mA VCC = 15 V VO = open 11
Supply
Current
Logic High ICCH 0.02 1 µA TA = 25°C IF = 0 mA VCC = 15 V 11
Supply VO = open
Current 0.02 2
Input VF 1.5 1.7 V TA = 25°C IF = 16 mA 3
Forward
Voltage 1.5 1.8
Input BVR 5 V IR = 10 µA
Reverse
Breakdown
Current
Tempera- ∆VF /∆TA -1.6 mV/°C IF = 16 mA
ture Co-
efficient of
Forward
Voltage
Input CIN 60 pF f = 1 MHz VF = 0 V
Capacitance
Input- VISO 3750 VRMS RH < 50% t = 1 min 6,12
Output TA = 25°C
Insulation
Voltage
Resistance RI-O 10[12] Ω VI-O = 500 Vdc 6
(Input-
Output)
Capacitance CI-O 0.6 pF f = 1 MHz 6
(Input-
Output)
 5

Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified
Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note
Propagation tPHL 0.2 0.3 µs TA = 25°C Pulse: f = 20 kHz 8, 9 9
Delay Time Duty Cycle = 10%
to Logic 0.2 0.5 IF = 16 mA VCC = 5.0 V
Low at RL = 1.9 kΩ CL = 15 pF
Output VTHHL = 1.5 V

0.2 0.5 0.7 TA = 25°C Pulse: f = 10 kHz 10- 10

Duty Cycle = 50% 14
0.1 0.5 1.0 IF = 12 mA VCC = 15.0 V
RL = 20 kΩ CL = 100 pF
VTHHL = 1.5 V
Propagation tPLH 0.3 0.5 µs TA = 25°C Pulse: f = 20 kHz 8, 9 9
Delay Time Duty Cycle = 10%
to Logic 0.3 0.7 IF = 16 mA VCC = 5.0 V
High at RL = 1.9 kΩ CL = 15 pF
Output VTHLH = 1.5 V

0.3 0.8 1.1 TA = 25°C Pulse: f = 10 kHz 10- 10

Duty Cycle = 50% 14
0.2 0.8 1.4 IF = 12 mA VCC = 15.0 V
RL = 20 kΩ CL = 100 pF
VTHLH = 2.0 V
Propagation tPLH- -0.4 0.3 0.9 µs TA = 25°C Pulse: f = 10 kHz 10- 13
Delay tPHL Duty Cycle = 50% 14
Difference -0.7 0.3 1.3 IF = 12 mA VCC = 15.0 V
Between RL = 20 kΩ CL = 100 pF
Any 2 Parts VTHHL = 1.5 V VTHLH = 2.0 V
Common |CMH| 15 30 kV/µs TA = 25°C VCC = 5.0 V RL = 1.9 kΩ 7 7,9
Mode CL = 15 pF IF = 0 mA
Transient VCM = 1500 VP-P
Immunity
at Logic 15 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10
High Level CL = 100 pF IF = 0 mA
Output VCM = 1500 VP-P
Common |CML| 15 30 kV/µs TA = 25°C VCC = 5.0 V RL = 1.9 kΩ 7 7,9
Mode CL = 15 pF IF = 16 mA
Transient VCM = 1500 VP-P
Immunity
at Logic 10 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10
Low Level CL = 100 pF IF = 12 mA
Output VCM = 1500 VP-P

15 30 TA = 25°C VCC = 15.0 V RL = 20 kΩ 7 8,10

CL = 100 pF IF = 16 mA
VCM = 1500 VP-P
 6

Notes: pulse, VCM, to assure that the output common mode pulse signal,VCM, to
1. Derate linearly above 70°C free-air will remain in a Logic High state assure that the output will remain in
temperature at a rate of 0.8 mA/°C. (i.e., VO > 2.0 V). Common mode a Logic Low state (i.e., VO < 1.0 V).
2. Derate linearly above 70°C free-air transient immunity in a Logic Low 9. The 1.9 kΩ load represents 1 TTL
temperature at a rate of 1.6mA/°C. level is the maximum tolerable unit load of 1.6 mA and the 5.6 kΩ
3. Derate linearly above 70°C free-air (negative) dVCM/dt on the trailing pull-up resistor.
temperature at a rate of 0.9 mA/°C. edge of the common mode pulse 10. The RL = 20 kΩ, CL = 100 pF load
4. Derate linearly above 70°C free-air signal, VCM, to assure that the output represents an IPM (Intelligent Power
temperature at a rate of 2.0 mA/°C. will remain in a Logic Low state (i.e., Mode) load.
5. CURRENT TRANSFER RATIO in VO < 0.8 V). 11. Use of a 0.1 µF bypass capacitor
percent is defined as the ratio of 8. Under IPM (Intelligent Power connected between pins 4 and 6 is
output collector current (IO), to the Module) load and LED drive recommended.
forward LED input current (IF), conditions: Common mode transient 12. In accordance with UL 1577, each
times 100. immunity in a Logic High level is the optocoupler is proof tested by
6. Device considered a two-terminal maximum tolerable dVCM /dt on the applying an insulation test voltage
device: Pins 1 and 3 shorted together leading edge of the common mode ≥4500 VRMS for 1 second (leakage
and Pins 4, 5 and 6 shorted together. pulse, VCM, to assure that the output detection current limit, Ii-e ≤ 5 µA).
7. Under TTL load and drive conditions: will remain in a Logic High state 13. The difference between tPLH and
Common mode transient immunity (i.e., VO > 3.0 V). Common mode tPHL, between any two HCPL-M454
in a Logic High level is the maximum transient immunity in a Logic Low parts under the same test condition.
tolerable (positive) dVCM /dt on the level is the maximum tolerable (See Power Inverter Dead Time and
leading edge of the common mode dVCM /dt on the trailing edge of the Propagation Delay Specifications
section).
NORMALIZED CURRENT TRANSFER RATIO

1.5 1000
TA = 25°C 40 mA
10 VCC = 5.0 V

IF – FORWARD CURRENT – mA
IO – OUTPUT CURRENT – mA

35 mA 100
IF
TA = 25°C
30 mA +
1.0 10
VF
25 mA –
1.0
5
20 mA
0.5 NORMALIZED 0.1
15 mA IF = 16 mA
10 mA VO = 0.4 V
0.01
VCC = 5.0 V
IF = 5 mA TA = 25°C
0 0.0 0.001
0 10 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 1.1 1.2 1.3 1.4 1.5 1.6

VO – OUTPUT VOLTAGE – V IF – INPUT CURRENT – mA VF – FORWARD VOLTAGE – VOLTS

Figure 1. DC and Pulsed Transfer Figure 2. Current Transfer Ratio vs. Figure 3. Input Current vs. Forward
Characteristics. Input Current. Voltage.
NORMALIZED CURRENT TRANSFER RATIO

IOH – LOGIC HIGH OUTPUT CURRENT – nA

1.1 10 4

1.0 10 3
IF = 0 mA
VO = VCC = 5.0 V
10 2
0.9
NORMALIZED
IF = 16 mA 10 1
0.8 VO = 0.4 V
VCC = 5.0 V 10 0
TA = 25°C
0.7 10 -1

0.6 10-2
-60 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120
TA – TEMPERATURE – °C TA – TEMPERATURE – °C

Figure 4. Current Transfer Ratio vs. Figure 5. Logic High Output Current
Temperature. vs. Temperature.
 7

HCPL-M454
IF
PULSE IF VCC
GEN.
0 1 6
ZO = 50 Ω
tr = 5 ns RL
VCC
VO
5 VO
0.1µF
VTHHL VTHLH
VOL IF MONITOR 3 4
CL

RM
tPHL tPLH

Figure 6. Switching Test Circuit.

HCPL-M454
10 V
VCM 90% 90% IF
10% 10% 1 6 VCC
0V
tr A RL
tf
B 5 VO

VO 0.1µF
VCC
SWITCH AT A: IF = 0 mA 3 4
VFF CL
VO VOL VCM
SWITCH AT B: IF = 12 mA, 16 mA + –

PULSE GEN.

Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.

0.50 1.4 2.6

VCC = 5.0 V VCC = 5.0 V VCC = 5.0 V
2.4
tp – PROPAGATION DELAY – µs
tp – PROPAGATION DELAY – µs

TA = 25° C
tp – PROPAGATION DELAY – µs

0.45 RL = 1.9 kΩ T = 25° C

1.2 A 2.2
CL = 15 pF CL = 15 pF CL = 100 pF
0.40 V 2.0 VTHHL = 1.5 V
THHL = VTHLH = 1.5 V tPLH 1.0 VTHHL = VTHLH = 1.5 V
10% DUTY CYCLE 10% DUTY CYCLE 1.8 VTHLH = 2.0 V
0.35 tPLH 1.6
0.8 50% DUTY CYCLE
t PHL 1.4 t PLH
0.30
0.6 1.2
0.25 IF = 10 mA 1.0
IF = 10 mA
0.4 t PHL 0.8
IF = 16 mA t PHL IF = 16 mA
0.20 0.6
IF = 10 mA 0.2 0.4
0.15
IF = 16 mA 0.2
0.10 0.0 0.0
-60 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20

TA – TEMPERATURE – °C RL – LOAD RESISTANCE – kΩ RL– LOAD RESISTANCE – kΩ

Figure 8. Propagation Delay Time vs. Figure 9. Propagation Delay Time vs. Figure 10. Propagation Delay Time vs.
Temperature. Load Resistance. Load Resistance.
 8

1.1 1.8 3.5

VCC = 15.0 V IF = 10 mA VCC = 15.0 V VCC = 15.0 V
t PLH

tp – PROPAGATION DELAY – µs
1.6 TA = 25° C
tp – PROPAGATION DELAY – µs

tp – PROPAGATION DELAY – µs
1.0 RL = 20 kΩ IF = 16 mA
3.0 TA = 25° C
CL = 100 pF CL = 100 pF RL = 20 kΩ
1.4
0.9 V VTHHL = 1.5 V
THHL = 1.5 V t PLH 2.5 VTHHL = 1.5 V
VTHLH = 2.0 V 1.2 VTHLH = 2.0 V VTHLH = 2.0 V
0.8 t PLH
50% DUTY CYCLE 50% DUTY CYCLE
1.0 2.0 50% DUTY CYCLE
0.7 t PHL
0.8 1.5
0.6 t PHL
0.6
1.0
0.5 0.4
tPHL IF = 10 mA
0.4 IF = 10 mA 0.5
0.2 IF = 16 mA
IF = 16 mA
0.3 0.0 0.0
-60 -40 -20 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 40 45 50 0 200 400 600 800 1000

TA – TEMPERATURE – °C RL – LOAD RESISTANCE – kΩ RL – LOAD CAPACITANCE – pF

Figure 11. Propagation Delay Time vs. Figure 12. Propagation Delay Time vs. Figure 13. Propagation Delay Time vs.
Temperature. Load Resistance. Load Capacitance.

1.2
TA = 25° C
1.1
tp – PROPAGATION DELAY – µs

RL = 20 kΩ
1.0 CL = 100 pF
VTHHL = 1.5 V
0.9
VTHLH = 2.0 V
0.8 50% DUTY CYCLE
t PLH
0.7
0.6
0.5
t PHL
0.4
IF = 10 mA
0.3 IF = 16 mA
0.2
10 11 12 13 14 15 16 17 18 19 20
VCC – SUPPLY VOLTAGE – V

Figure 14. Propagation Delay Time vs.

Supply Voltage.
 9

+HV
+
HCPL-M454
6

1
LED 1

5 BASE/GATE
Q1
3 OUT 1 DRIVE CIRCUIT

+
HCPL-M454
6

1
LED 2

5 BASE/GATE Q2
3 OUT 2 DRIVE CIRCUIT

–HV

Figure 15. Typical Power Inverter.

LED 1

OUT 1

tPLH MIN.
(tPLH MAX. – tPLH MIN.)

tPLH MAX.

TURN ON DELAY
(tPLH MAX. – tPLH MIN.)

LED 2

OUT 2

tPHL MIN.
(tPHL MAX. – tPHL MIN.)
tPHL MAX.

MAXIMUM DEAD TIME

Figure 16. LED Delay and Dead Time Diagram.


Power Inverter Dead
Time and Propagation
Delay Specifications
The HCPL-M454 includes a
specification intended to help
designers minimize “dead time” in
their power inverter designs. The
new “propagation delay
difference” specification (tPLH -
tPHL) is useful for determining not
only how much optocoupler
switching delay is needed to
prevent “shoot-through” current,
but also for determining the best
achievable wort-case dead time
for a given design.
When inverter power transistors
switch (Q1 and Q2 in Figure 15),
it is essential that they never
conduct at the same time.
Extremely large currents will flow
if there is any overlap in their
conduction during switching
transitions, potentially damaging
the transistor and even the
surrounding circuitry. This
“shoot-through” current is
eliminated by delaying the turn-on
of one transistor (Q2) long
enough to ensure that the
opposing transistor (Q1) has
completely turned off. This delay
introduces a small amount of
“dead time” at the output of the
inverter during which both
transistors are off during
switching transitions. Minimizing
this dead time is an important
design goal for an inverter
designer.
The amount of turn-on delay
needed depends on the propa-
gation delay characteristics of the
optocoupler, as well as the
characteristics of the transistor
base/gate drive circuit. Consider-
ing only the delay characteristics
of the optocoupler (the
characteristics of the base/gate
drive circuit can be analyzed in
the same way), it is important to
know the minimum and maximum
turn-on (tPHL) and turn-off (tPLH)
propagation delay specifications,
preferably over the desired
operating temperature range. The
importance of these specifications
is illustrated in Figure 16. The
waveforms labeled “LED1”,
“LED2”, “OUT1”, and “OUT2” are
the input and output voltages of
the optocoupler circuits driving
Q1 and Q2 respectively. Most
inverters are designed such that
the power transistor turns on
when the optocoupler LED turns
on; this ensures that both power
transistors will be off in the event
of a power loss in the control
circuit. Inverters can also be
designed such that the power
transistor turns off when the
optocoupler LED turns on; this
type of design, however, requires
additional fail-safe circuitry to
turn off the power transistor if an
over-current condition is
detected. The timing illustrated in
Figure 16 assumes that the power
transistor turns on when the
optocoupler LED turns on.
The LED signal to turn on Q2
should be delayed enough so that
an optocoupler with the very
fastest turn-on propagation delay
(tPHLmin) will never turn on before
an optocoupler with the very
slowest turn-off propagation delay
(tPLHmax) turns off. To ensure this,
the turn-on of the optocoupler
should be delayed by an amount
no less than (tPLHmax - tPHLmin),
which also happens to be the
maximum data sheet value for the
propagation delay difference
specification, (tPLH - tPHL). The
HCPL-M454 specifies a maximum
(tPLH - tPHL) of 1.3 µs over an
operating temperature range of 0-
70°C.
10
Although (tPLH - tPHL)max tells the
designer how much delay is
needed to prevent shoot-through
current, it is insufficient to tell the
designer how much dead time a
design will have. Assuming that
the optocoupler turn-on delay is
exactly equal to (tPLH - tPHL)max,
the minimum dead time is zero
(i.e., there is zero time between
the turn-off of the very slowest
optocoupler and the turn-on of
the very fastest optocoupler).
Calculating the maximum dead
time is slightly more complicated.
Assuming that the LED turn-on
delay is still exactly equal to (tPLH
- tPHL)max, it can be seen in Figure
16 that the maximum dead time is
the sum of the maximum
difference in turn-on delay plus
the maximum difference in turn-
off delay,
[(tPLHmax-tPLHmin) + (tPHLmax-
tPHLmin)],
This expression can be
rearranged to obtain
[(tPLHmax-tPHLmin) - (tPHLmin-
tPHLmax)],
and further rearranged to obtain
[(tPLH-tPHL)max - (tPLH-tPHL)min],
which is the maximum minus the
minimum data sheet values of
(tPLH - tPHL). The difference
between the maximum and
minimum values depends directly
on the total spread of

propagation delays and sets the
limit on how good the worst-case
dead time can be for a given
design. Therefore, optocouplers
with tight propagation delay
specifications (and not just
shorter delays or lower pulse-
width distortion) can achieve
short dead times in power
inverters. The HCPL-M454
specifies a minimum (tPLH - tPHL)
of -0.7 µs over an operating
temeprature range of 0-70°C,
resulting in a maximum dead time
of 2.0 µs when the LED turn-on
delay is equal to (tPLH - tPHL)max,
or 1.3 µs.
11
It is important to maintain
accurate LED turn-on delays
because delays shorter than (tPLH
- tPHL)max may allow shoot-
through currents, while longer
delays will increase the worst-case
dead time.
www.agilent.com/semiconductors
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5989-0793EN
December 28, 2004
5989-2116EN