An improved fast acquisition phase

frequency detector for high speed phase-

locked loops
Cite as: AIP Conference Proceedings 1955, 040030 (2018); https://doi.org/10.1063/1.5033694
Published Online: 18 April 2018

Lei Zhang, Zongmin Wang, Tieliang Zhang, and Xinmang Peng

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AIP Conference Proceedings 1955, 040030 (2018); https://doi.org/10.1063/1.5033694 1955, 040030

© 2018 Author(s).
An Improved Fast Acquisition Phase Frequency Detector for
High Speed Phase-Locked Loops
Lei Zhang a), Zongmin Wang, Tieliang Zhang and Xinmang Peng

Beijing Microelectronics Technology Institute, Beijing 100076, China.

a)
Corresponding author: rightzhanglei@163.com

Abstract. Phase-locked loops (PLL) have been widely applied in many high-speed designs, such as microprocessors or
communication systems. In this paper, an improved fast acquisition phase frequency detector for high speed phase-locked
loops is proposed. An improved structure based on dynamic latch is used to eliminate the non-ideal effect such as dead
zone and blind zone. And frequency dividers are utilized to vastly extend the phase difference detection range and enhance
the operation frequency of the PLL. Proposed PFD has been implemented in 65nm CMOS technology, which occupies an
area of 0.0016mm2 and consumes 1.5mW only. Simulation results demonstrate that maximum operation frequency can be
up to 5GHz. In addition, the acquisition time of PLL using proposed PFD is 1.0us which is 2.6 times faster than that of the
PLL using latch-based PFD without divider.

Key words: Phase-locked Loops; Phase Frequency Detector; Fast Acquisition.

INTRODUCTION

Due to the circuit complexity and operation frequency rising up, phase-locked loops (PLL) [1] have been widely
applied in many high-speed designs, such as microprocessors or communication systems. PLL embedded in these
high-performance integrated circuits plays an important role in clock management, and is commonly used as jitter
filter or frequency synthesizer [2] to provide high-quality clock signal for the high-speed systems.

CLKin CLKout
PFD CP LF VCO
CLKfb

Divider
FIGURE 1. Block diagram of a typical PLL.

The block diagram of a typical phase-locked loop, as shown in Fig.1, mainly consists of five parts: phase frequency
detector (PFD), charge pump (CP), loop filter (LF), voltage-controlled oscillator (VCO) and frequency divider. Phase
frequency detector is a key building block that can detect both phase and frequency difference between the input
reference signal and the feedback signal, and then generate outputs voltage pulses whose width is proportional to the
phase difference [3]. As a result, an accurate measurement [4] and a wide detection range of the phase difference of a
PFD is a critical factor that affects the overall performance of PLL, such as jitters, phase noise and lock time. For a
non-ideal PFD, there might be a fact that PFD does not respond correctly in the presence of a phase difference which

Advances in Materials, Machinery, Electronics II

AIP Conf. Proc. 1955, 040030-1–040030-8; https://doi.org/10.1063/1.5033694
Published by AIP Publishing. 978-0-7354-1654-3/$30.00

040030-1
will lead to cycle-to-cycle jitter in PLL output signal [5], and even the failure of locking phase. Thus, the demand of
high performance PFD with high detection precision, wide detection range, zero dead zone, minimal blind zone and
wide input frequency range is a tendency and a big challenge.
The conventional PFD has the drawbacks of limited operating speed, large dead zone or blind zone, high power
consumption and undesired output glitches [6]. In recent years, various types of PFD and many strategies to reduce
non-ideal effects in PFD have been presented, in which a popular approach was to modify the structures of the
conventional PFD to make PFDs work more efficiently. The reported precharge-type PFD, ncPFD and latch-based
PFD are made on simplifying the circuit, eliminating the dead zone and reducing the blind zone [7]-[9]. Among those
published PDFs, the latch-based PFD is the most commonly used one for its high operation speed, wide phase
detection range, low power consumption, and independence from the input duty cycle.
In this paper, we considered the non-ideal factor in conventional phase frequency detector and proposed an
improved structure with extended detection range for fast-locking PLL. The remaining of the paper is organized as
follows. Section II analyses the principle of PFD. Section III describes the design of the proposed PFD circuit.
Simulation results and relevant discussion are introduced in section IV. Section V concludes the paper.

PRINCIPLE ANALYSIS OF PFD

Fig.2 (a) illustrates the basic structure of the typical phase frequency detector which usually consists of a pair of
edge-triggered resettable D flip-flops (DFF) and a two-input NAND gate to provide a reset path when both outputs
UP and DN go high at the same time. And the output UP or DN of PFD would generate a certain width pulse signal
indicating lead or lag relationship of two input signals CLKin and CLKfb, which would make it feasible to allow the
pulse width of UP or DN signal is linearly proportional to the phase difference between the input reference clock and
feedback clock.

V
Vd

2
2


(a) Schematic of PFD (b) Transfer characteristics

FIGURE 2. (a) Basic schematic of PFD, (b) Transfer characteristics of an ideal PFD.

The transfer characteristics of an ideal PFD is shown in Fig.2(b) which is ideally linear for the entire range of input
phase difference ∆ϕ from −2π to 2π, and the gain of PFD can be expressed as,

Vd
K PFD  (1)
2

Where V is the conversion of the pulse width of UP minus the pulse width of DN.
As is well known, the main problem with conventional PFD is the presence of the dead zone which is defined as
the maximum phase difference between the two inputs that cannot be detected by a PFD. The dead zone make the
PFD fail to detect the phase error when the phase difference reaches a certain value small enough, which will make
the loop essentially open and increase the phase noise of the PLL. Fig.3 (a) illustrates the phase difference versus
output voltage characteristics of the PFD suffered from dead zone that is a region of very low or zero gain of PFD
near the zero input phase difference from −ϕ toϕ .

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 Vd

2 DZ
DZ 2 

(a) Transfer characteristics (b) Waveform of a PFD with dead zone

FIGURE 3. (a) Transfer characteristics with dead zone, (b) Waveform of a PFD with dead zone.

The waveform in Fig.3 (b) shows the PFD operating in the dead zone. Due to a certain delay existing in the NAND
gate, the UP and DN output of PFD would still generate pulse signals theoretically when the rising edges of CLKin
and CLKfb are very close. However, such a narrow pulse namely a short time cannot make the output reach a
understand voltage V to open or close the switch because of the load capacitance in the fan-out of PFD.
The optimal PFD has the characteristic of zero dead zone, which contributes to improving the phase noise
performance and reducing the spurious tones. As shown in Fig.2(a), to eliminate the dead zone, a buffer is employed
in the reset path as a deliberate delay cell, which ensures the output pulses with a constant width to turn on the switch
transistors of the CP sufficiently when the phase of the inputs are aligned. And the waveform in Fig.4 (a) shows the
PFD operating with zero dead zones.

(a) Waveform of a PFD with zero dead zones (b) Finite state machine of PFD
FIGURE 4. (a) Waveform of a PFD with zero dead zones, (b) Finite state machine of PFD.

The traditional PFD is a sequential circuit which can be depicted in a finite state machine consisted of three states:
N state (UP=0, DN=0), U state (UP=1, DN=0) and D state (UP=0, DN=1). Due to the inserting delay cell used to
eliminate the dead zone, the finite state machine adds an extra transition state shown in Fig.4 (b) which consists of
four states driven by the rising edges of the input signals: CLKin and CLKfb.
Initially, both the outputs UP and DN are zero, the PFD stays in N state until either input appears a rising edge.
When a rising edge of the input CLKin arrives, the PFD will transfer to U state where the outputs signals UP=1, DN=0,
predicate the phase of CLKin leading the CLKfb. If a rising edge appears on input CLKin again, the PFD still stays
in U state. Only a rising edge of the input CLKfb arrives, the PFD will transfer to R state where the outputs signals
UP=1, DN=1. The PFD enters a reset state and returns to initial N state after a delay. Similarly if a rising edge of the
input CLKfb arrives, the PFD will transfer to D state where the outputs signals UP=0, DN=1, predicate the phase of
CLKin lagging the CLKfb. If a rising edge appears on input CLKfb again, the PFD still stays in D state. Only a rising

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edge of the input CLKin arrives, the PFD will transfer to R state where the PFD enters a reset state and returns to
initial N state after a delay.
However, while solving the dead zone problem, the existence of the reset delay brings about a detrimental side
effect called blind zone. Fig.5 (a) shows the diagram of the production of blind zone.

Vd

BZ

2
2

BZ

(a) Effect of blind zone production (b) Transfer characteristics with blind zone
FIGURE 5. (a) Effect of blind zone production, (b) Transfer characteristics with blind zone.

When the phase difference goes near 2π, the leading rising edge of the input reference clock CLKin triggers the
UP signal until the lagging rising edge of the feedback clock CLKfb comes, which triggers the DN signal and resets
both the UP and DN signal to low a short while later. Due to presence of finite delay of the reset signal, the next
coming rising edge of the CLKin which is supposed to trigger the UP to go high would be missed. As a result, the
effect of blind zone occurs. As shown in Fig.5 (a), if the rising edge of the CLKin signal falls at blind zone, it would
not be detected and lead to phase detection error.
We assume T is the minimum pulse duration of the output signal that makes the PFD with zero dead zone,

Tmin  TRST  td (2)

Where t is the delay of the two input NAND gate and the delay cell used to eliminate the dead zone, and T is
the reset delay of the DFF. And the blind zone T can be expressed as,

TBZ  TDFF  Tmin  t d (3)

Where T is the response time of the edge-triggered DFF. As T is usually a constant value for zero dead zone,
the minimum blind zone can be achieved by decreasing the response time of the DFF.
Ideal characteristic of PFD is perfectly linear for the input phase difference from −2π to 2π. However, as the result
of the existence of the blind zone, the phase difference detection range is lower than 4π, and the actual transfer
characteristics of PFD suffered from blind zone problem as shown in Fig.5 (b). ϕ Is the phase range of blind zone,

TBZ
BZ  2  (4)
Tref

And the maximum phase detection range can be presented as follows

 T 
max  4  2BZ  4 1  BZ  (5)
 Tref 

Where T the time of blind zone is, T is the period of the input reference clock.

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 Moreover, if the phase difference falls into the blind zone during the frequency acquisition, the PFD delivers the
wrong polarity for large phase difference information leading to shift the phase toward the opposite direction, which
aggravates cycle slips and deteriorates the frequency acquisition time significantly.
Formula (4) indicates that the blind zone will become wider with the increase of the input reference frequency. In
the worst case scenario, when the phase range of blind zone ϕ reaches π, namely the time of blind zone T is as
much as half the period of input reference signal, the PFD outputs wrong information half the time fails to acquire
frequency lock unconditionally. So, the maximum operating frequency can be expressed as

1
f max  (6)
2  TBZ

To sum up, PFDs mainly have non-ideal effects such as dead zone and blind zone which will bring about a
reduction in phase detection range and a problem with missing edges, consequently resulting in a large phase noise
and a long frequency acquisition time in the steady state in PLL.

PROPOSED CIRCUIT DESIGN

After analyzing the principle and non-ideal effects of the conventional PFD, A new structure of latch-based PFD
is proposed as shown in Fig.6 (a).

(a) Proposed PFD design (b) Loop filters for PFD

FIGURE 6. (a) Proposed PFD design, (b) Loop filters for PFD.

The proposed PFD is designed by fully symmetrical structure to eliminate the static phase offset caused by the
delay mismatch or parasitic delays. The dynamic pulsed latches are adopted owing to the advantages of high speed
and low power consumption, and which fundamentally changes the dependence on the reset delay. And the reset
circuit includes a two-input NAND gate, a delay cell and two inverters. When the rising edge of input reference signal
CLKin arrives during the reset, the edge information propagates to the output as long as the CLKin pulse driven by
two-input NOR is still high when the reset period ends. As a result, the PFD no longer miss edge which makes the
PFD has a faster frequency acquisition and twice maximum operation frequency. Because of the frequency dividers
are used to lower the signal frequency involved in frequency detection. Just because of this, the phase difference
detection range has been extended and the operation frequency of the PLL adopting our proposed PFD has been
enhanced vastly.
As the output of the PFD is a voltage pulse signal (UP and DN), but for the voltage-controlled oscillator actually
an analog voltage is needed, the signal is converted by a charge pump to a pulse-modulated current output or by a
low-pass filter works like an integrator averaging the output voltage pulse of PFD. The low-pass filter applied to the
proposed PFD is an active filter as shown in Fig.6(b), and the transmission function can be expressed as,

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 1  sR1C 1
VO   UP  DN  (7)
s R 0C 0R1C 1  sR 0 C 0  C 1 
2

There is a tradeoff on bandwidth of filter between the frequency locking range, acquisition time and superior jitter
characteristics.

SIMULATION RESULTS

FIGURE 7. Layout of proposed PFD.

The proposed PFD has been implemented in 65nm SMIC CMOS technology with a 1.2V supply voltage. Fig.7
shows the chip layout of proposed PFD circuit, which occupies an area of only 0.0016mm2 and consumes 1.5mW.

(a)

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 (b)
FIGURE 8. (a) Maximum operation frequency of PFD, (b) Frequency acquisition of PLL with the proposed PFD.

Maximum operation frequency is delineated by the shorted period conveying function characteristics with correct
phase detection information united with same frequency and 90o phase difference on the input signals [10]. As shown
in Fig.8 (a), the proposed PFD has an excellent performance of operation frequency. And the maximum operation
frequency can be up to 5GHz.
Simulated frequency acquisition characteristics of the PLL using proposed have been presented in Fig.8 (b). To
analyze the frequency acquisition, an input reference clock of 2.5GHz is supplied. In this figure we can see that the
acquisition time of PLL using proposed PFD is 1.0us which is 2.6 times faster than that of the PLL using latch based
PFD without divider.

CONCLUSION
An improved fast acquisition phase frequency detector for high speed phase-locked loops is proposed in this paper.
An improved structure based on dynamic latch is used to eliminate the non-ideal effect such as dead zone and blind
zone. And frequency dividers are utilized to vastly extend the phase difference detection range and enhance the
operation frequency of the PLL. Proposed PFD has been implemented in 65nm CMOS technology, which occupies
an area of 0.0016mm2 and consumes 1.5 mW only. Simulation results demonstrate that maximum operation frequency
can be up to 5GHz. In addition, the acquisition time of PLL using proposed PFD is 1.0us which is 2.6 times faster
than that of the PLL using latch-based PFD without divider.

ACKNOWLEDGMENTS

This work was supported by the Pre-Research Program of Beijing Microelectronics Technology Institute.

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