GGNMOS as ESD Protection in Different Nanometer

CMOS Process
Weihuai Wang, Shurong Dong, Senior Member, IEEE, Zhiwei Liu
Lei Zhong, Jie Zeng, Zhihui Yu School of Microelectronics and Solid-State Electronics,
ESD Lab, Department ofInformation Sciences and Electronic University of Electronics Science and Technology of China,
Engineering, 310027 610054, Chengdu, China
Zhejiang University, Hangzhou, China

Abstract-Grounded-gate NMOS (GGNMOS) plays a more Fig. I Cross-section and layout sketch of the GGNMOS structure.

important role in electrostatic discharge (ESD) protection

2. J Channel width (W)
because of its simple structure and low trigger voltage. Various
GGNMOS based on 90nm, 65nm and 40nm CMOS process are Channel width (W) is key parameter to change the ESD
compared to investigate its ESD characteristic changes with metrics of GGNMOS. Fig. 2 shows the TLP test results of
process advancing. Results show that the key parameters, GGNMOS in 90 nm CMOS process with various W. As
including channel width and length, have great influence on its comparison, ESD characteristics of GGNMOS with same
ESD metrics. structure under 40nm process are also tested and shown in
Table. 1.
Keywords-GGNMOS; channel width; ESD metrics
Results show that the W has great effects on 1t2/W under
90nm process. With the W increasing, GGNMOS's 1t2IW
I. Introduction decreases greatly. The reason is its uniformity of current under
With the advance of the CMOS process, the electrostatic ESD stress becomes poor with the W increasing. So, widen
discharge (ESD) protection design becomes much harder [1]. GGNMOS can reduce its ESD robustness and area efficiency.
GGNMOS has low trigger voltage and simple structure, The same effect is not obvious under 40nm process.
therefore GGNMOS and GGNMOS triggered ESD protection GGNMOS under 40nm process turns on faster than that under
devices are widely used in ESD protection field [2-4]. With 90nm, so the non uniformity of current cannot exacerbate in
the process advance, same structure GGNMOS implemented time.
in 90nm as an excellent ESD protection, maybe is not fit to
40nm process. So Investigation its ESD metrics change of
GGNMOS with different process is very important. In this
paper, the GGNMOS key parameter effects are tested and
analyzed under 90nm, 65nm and 40nm CMOS process by
Barth 4002 transmission line pulse system (TLP).

II. RESULTS AND DISCUSSION

GGNMOS are fabricated under 90nm, 65nm and 40nm
CMOS process. The key parameters of GGNMOS include
channel width (W), channel length (L), drain contact to ploy
(DCP) and source contact to ploy (SCP), shown in Fig. 1.

Anode Cathode Fig. 2 TLP results of GGNMOS in 90nm CMOS process with different W
values.

Table. I Key ESD metrics with different values of W in 90nm and 40nm
CMOS process for lOOns TLP measurements
P·SUB Vtl-
Process Whim) Vt1(V) Vh(V) Vh(V) lt2(A) lt21W(mAhtm)
�L� 120 6.71 4.71 2 0.67 5.58
90nm
240 6.59 4.52 2.07 1.1 4.58
• • •
• • • 60 6.73 4.92 1.81 0.43 7.16
• •
w· 40nm 240 6.31 4.49 1.82 1.77 7.38
• • •
• • • 3 60 6.19 4.2 1.99 2.65 7.3 6
� !II •

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 The results also show that with the W increasing, trigger
voltage, holding voltage decrease and width of ESD windows
ahnost has no change under both 90nm and 40nm process. It
maybe also relate to the uniformity of current.
So, GGNMOS is applied as ESD protection. Under 40nm
process, the impact of W on trigger voltage and holding
voltage should be mainly considered because 40nm process
has a very narrow ESD window. However,
process the impact of W on the uniformity of current should
be mainly considered.
2. 2 Channel length (L)
Fig. 3 shows the TLP test results of GGNMOS in 65 nm
CMOS process with various L. As comparison, GGNMOS
ESD characteristics with same structure under 90nm and
40nm process are also tested and shown in Table. 2.
smaller under 40nm process. It is supposed that the thin oxide
thickness becomes the constraint under 40nm process, and L is
no longer the main factor to affect the failure current.
So, it is better to set small L for an excellent failure current,
while large L for a higher holding voltage. The L should be
trade off when designing GGNMOS under 90nm and 65nm. L
is no longer the main factor to affect the failure current under
under 90nm 40nm process.
2. 3 DCP and SCP
From the TLP results under each process, both DCP and
SCP have a little effect on the trigger voltage and holding
voltage. As DCP increases, the failure current increase when
DCP is small. This is caused because the uniformity of current
must decrease when DCP is small, therefore the failure current
decreases. As a result, DCP should be appropriate, and the
best DCP for an excellent ESD protection is different under
each process. SCP is less strict to set because it is minor
compared to DCP.

III. CONCLUSION
This paper gives the relationship between the key layout
parameter and ESD metrics of GGNMOS. The impact of W
on trigger voltage and holding voltage is mainly considered as
well as the impact of L on holding voltage when designing
GGNMOS under 40nm process. The impact of W on the
uniformity of current and the impact of L on the failure current
are also under consideration under 90nm process.

Fig. 3 TLP results of GGNMOS in 65nm CMOS process with different L

Acknowledgment
values. This work was supported by the National Natural Science
Foundation of China (Nos. 61171038 and 61204124 and
Table. 2 Key ESD metrics with different values of L in 90nm, 65nm and
61106105).The authors thank the Innovation Platform for
40nm CMOS process for lOOns TLP measurements
MicrolNano Device and System Integration and Cyrus Tang
Vtl-
Process L(llm) Vtl(V) Vh(V) Vh(V) It2(A) Centre for Sensor Materials and Applications at Zhejiang
University.
0.35 6.46 4.64 1.82 2.57
90nm 0.4 6.46 4.68 1.78 2.54

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