DATA ACQUISITION

SEPTEMBER 2014
circuitcellar.com ISSUE 290

circuit cellar
Engineer a Data
Acquisition System
^ LED Pul^e Current
& Duration countermove
om logic tree J

Position Coordinates

f t
force data
$ 9 . QOUS $ 1 0 . 0 0C AN Electrical Engineering Tips (Update) |Q&A: FPGA Enthusiast DIY Force-
0 9>
Sensing System |Build a Camera Stabilization Platform |Update to a Classic
Electronic Game Pooling Microarchitectural Resources |Variable Resistors |
Improved PWM MOSFET Gate Driver |IR Transmissions
Q 74470 75349 o
3-D Printed Electronics
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l2C • SPI • CAN • eTPU (for I/O handling, serial communications, *
m otor/tim ing/engine control applications)
> MOD54415
250 MHz processor w ith 32MB flash & 64MB RAM ■42 GPIO • 8 UARTs
5 l2C • 3 SPI • 2 CAN • SSI ■8 ADC • 2 DAC • 8 PWM • 1-Wire8 interface ,

> NAN054415
250 MHz processor w ith 8MB flash & 64MB RAM • 30 GPIO • 8 UARTs
4 l2C ■3 SPI • 2 CAN ■SSI ■6 ADC • 2 DAC • 8 PWM • 1-Wire8 interface

S Add Ethernet connectivity to an existing product, or use it as your product's core processor

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• 1x m icroS D Socket ■ 16x ADC, 4x DAC Ports ■ 1x m icroS D Socket - 24 VAC o r 8 - 24 VDC Power

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B e n e fits: Benefits:
■ P rovides a v a rie ty o f e le c tric a lly is o la te d IO ■ L ow p o w e r a n d lo w co st in d u s tria l g ra d e SBC

■ M e ta l e n clo su re w ith ru g g e d screw c o n n e c to rs ■ R u g g ed 24-P in screw te rm in a l c o n n e c to r

■ C o n v e n ie n t P o w e r o v e r E th e rn e t (PoE) p o w e rs SBC ■ F le xib le p o w e r in p u ts in c lu d in g AC a n d DC

■ C u sto m iza b le w ith p ro g ra m m a b le 5 K Lut FPGA ■ W ireless d a ta a q u is itio n via WiFi a n d B lu e to o th

■ -40 to 85 °C in d u s tria l te m p e ra tu re ra nge ■ 30 V to le ra n t DIO, a n a lo g IO, 3 A relays, a n d m o re

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We've never Embedded Support every Unique em bedded

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product in 30 are built to open for our
years endure source vision customers
2 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

EDITOR'S LETTER

INNOVATIVE DATA ACQUISITION SYSTEMS

I s s u e 2 9 0 S e p te m b e r 2014 | ISSN 1 5 2 8 -0 6 0 8

C IR C U IT C E L LA R ® (ISSN 1 5 2 8 -0 6 0 8 ) is p u b lis h e d m o n th ly by: It never fails. Each month, I find myself telling someone—sometimes it's a reader, other
times it's a client—that the latest edition of Circuit Cellar is the most diverse to date. And each
C irc u it C ellar, In c.
111 F o u n d e rs Plaza, S u ite 300
time I do, I truly believe it. Well, I'm doing it again. Why? In this issue we cover a variety of
East H a r tfo r d , CT 06108 topics ranging from a DIY data acquisition system to a video camera stabilization system to an
upgraded classic electronic game to 3-D printed electronics. By publishing articleson so many
P erio dic al ra te s p aid a t East H a r tfo rd , CT, a nd a d d itio n a l o ffic e s .
O n e -y e a r (12 issues) s u b s c r ip tio n ra te US and posse ssio n s
different topics, we're sure to pique your interest more than once.
$ 50 , C a na da $6 5, F o re ig n / ROW $75. All s u b s c r ip tio n o rd e rs We start the issue with an in-depth interview with Chris Zeh, a young hardware design
p a y a b le in US f u n d s o n ly v ia V isa , M a s te rC a rd , in te rn a tio n a
engineer at STMicroelectronics who blogs about his interests and considers himself an FPGA
p o s ta l m o n e y o rd e r, o r c h e c k d ra w n on US bank.
aficionado (p. 6). Chris tell us about some of his most innovative projects, including the
S U B S C R IPT IO N S
"HyperSniffer," which is an FPGA-based, application-specific logic analyzer.
On page 22, two Camosun College graduates explain how they engineered sensor-to-
C ir c u it C ellar, PO. B ox 4 6 2 2 5 6 , E sco n d id o , CA 9 2 0 4 6
human data acquisition system. They built it to monitor the forces exerted by rowers on a crew
E-m ail: c ir c u itc e lla r@ p c s p u b lin k .c o m
team, but you can build a similar system for measuring, displaying, and logging force data for
Phone: 8 0 0 .2 6 9 .6 3 0 1
any number of other applications.
In te rn e t: c irc u itc e lla r.c o m
Next, a group of Cornell University students present their well-designed, microcontroller-
A d d re s s C h a n g e s /P ro b le m s : c irc u itc e lla r@ p c s p u b lin k .c o m
based video camera stabilization platform (p. 32). After providing a high-level overview, they
P o s tm a s te r: S end a d d re s s c h a n g e s tc delve into the details about the project's hardware and software. They includeinformation
C ir c u it C ellar, P.O. B ox 4 6 2 2 5 6 , E sco n d id o , CA 9 2 0 4 6 about how the system reads and processes data.
In "DIY RGB Game Design," Mitch Matteau details an upgrade to a classic electronic tic­
A D VE R TIS IN G
tac-toe game system (p. 40). He describes his original design and then explains his recent
S tr a te g ic M edia M a rk e tin g , Inc. upgrades.
2 M ain S tre e t, G lo u c e s te r, M A 01930 USA
Turn to page 48 for columnist Ayse Coskun's article on the topic of pooling microarchitectural
Phone: 9 7 8 .2 8 1 .7 7 0 8
resources. She explains how pooling your resources across applications can improve overall
Fax: 9 7 8 .2 8 1 .7 7 0 6
energy efficiency.
E -m ail: c ir c u itc e lla r @ s m m a rk e tin g .u s
A d v e r tis in g ra te s a n d t e r m s a va ila b le on re q u e s t
On page 54, George Novacek continues his series on resistors. In this installment, he takes
N e w Produ cts:
a close look at variable resistors and covers their power ratings and different styles.
N e w P ro d u c ts , C irc u it C ellar, 111 F o u n d e rs Plaza, S u ite 300 Mitch Matteau isn't the only engineer in this issue who revisits a previous design. This
East H a r tfo r d , CT 0610 8, E -m a il: n e w p ro d u c ts @ c irc u itc e lla r.c o m month, columnist Ed Nisley returns to his Arduino PWM MOSFET gave drive (p. 58).
Turn to page 66 for the second part in Jeff Bachiochi's article series on IR remotes. In
HEAD OFFICE
this article, he tackles the topics of identifying,
C irc u it C ellar, In c . 111 F o u n d e rs Plaza, S u ite 300
decoding, and reproducing IR transmissions.
East H a r tfo r d , CT 06108
P hone: 8 6 0 .2 8 9 .0 8 0 0
Dr. Martin Hedges wraps up the issue with an
essay on the future of one of the most exciting
COVER PH O TO G R A PH Y developments in our industry—3-D printed
C h ris R akoczy, w w w .ra k o c z y p h o to .c o m
electronics (p. 80). As you'll see, this promising new
field is poised to revolutionize the way engineers
C O P Y R IG H T NOTICE design and manufacture electrical systems.
E n tire c o n te n ts c o p y r ig h t © 2014 by C irc u it C ellar, In c . All
r ig h ts re s e rv e d . C ir c u it C e lla r is a re g is te re d tr a d e m a r k o f
C. J. Abate
3-D chip packaging (Courtesy o f F raunhofer IKTS)
C irc u it C ellar, In c . R e p ro d u c tio n o f th is p u b lic a tio n in w h o le
o r in p a r t w ith o u t w r itt e n c o n s e n t fr o m C ir c u it C ellar, In c. is
cabate@ circuitcellar.com
p r o h ib ite d .

D IS C LA IM E R

C irc u it C e lla r ® m a k e s no w a r r a n tie s a nd a s s u m e s no

r e s p o n s ib ility o r lia b ility o f a n y k in d fo r e r r o r s in these
p r o g r a m s o r s c h e m a tic s o r f o r th e co n s e q u e n c e s o f any
THE TEAM
s u c h e r r o r s . F u r th e r m o r e , b e c a u s e o f p o s s ib le v a ria tio n ir
th e q u a lity a n d c o n d itio n o f m a te ria ls a nd w o rk m a n s h ip o f
EDITOR-IN-CHIEF PRESIDENT FOUNDER
re a d e r-a s s e m b le d p r o je c ts , C ir c u it C e lla r ® d is c la im s an y
re s p o n s ib ility f o r th e s a fe a n d p ro p e r fu n c tio n o f re a d e r-
C. J. Abate Hugo Van haecke Steve Ciarcia
a s s e m b le d p r o je c ts base d u p o n o r fr o m p la n s, d e s c rip tio n s , o r
in fo r m a tio n p u b lis h e d by C ir c u it C e lla r ® . MANAGING EDITOR PUBLISHER PROJECT EDITORS
T h e in fo r m a tio n p ro v id e d by C irc u it C e lla r ® is f o r e d u c a tio n a l
Mary Wilson Don Akkermans Chris Coulston,
p u rp o s e s . C irc u it C e lla r ® m a k e s no c la im s o r w a r r a n ts th a t
Ken Davidson,
re a d e rs have a r ig h t to b u ild th in g s based upon th e s e ideas ASSOCIATE EDITOR ASSOCIATE PUBLISHER
u n d e r p a te n t o r o th e r re le v a n t in te lle c tu a l p r o p e r ty la w in
Nan Price Shannon Barraclough David Tweed
t h e ir ju r is d ic t io n , o r th a t re a d e rs have a r ig h t to c o n s tru c t o r
o p e ra te a n y o f th e d e v ic e s d e s c rib e d h e re in u n d e r th e re le v a n t
p a te n t o r o th e r in te lle c tu a l p r o p e r ty la w o f th e re a d e r's ART DIRECTOR COLUMNISTS CUSTOMER SERVICE
ju r is d ic tio n . T h e re a d e r a s s u m e s a n y ris k o f in fr in g e m e n t
KC Prescott Debbie Lavoie
lia b ility f o r c o n s tr u c tin g o r o p e ra tin g such devices.
Jeff Bachiochi, Ayse K.

ADVERTISING COORDINATOR Coskun, Bob Japenga, Robert

© C irc u it C e lla r 2014 P rin te d in th e U n ite d S tates

Kim Hopkins Lacoste, Ed Nisley, George

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4 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

CONTENTS

circuit cellar

SEPTEMBER 2014 • ISSUE 290

DATA ACQUISITION

DATA ACQUISITION SYSTEM PROVIDES FEEDBACK VIA 15 LEDs

CC COMMUNITY FEATURES
06 i CC WORLD 20 : Engineer a Force-Sensing System
Sensor-to-User Data Acquisition Made Simple
OS i QUESTIONS & ANSWERS By Steven Liu and Albert Ruskey
Engineer, Blogger, & FPGA Enthusiast Build a sensor-to-user data acquisition system for
By Nan Price measuring, displaying, and logging information
San Jose, CA-based engineer Chris Zeh on working
with FPGA dev boards and a variety of projects 32 : Position Control
Build a Microcontroller-Based Stabilization Platform
By Evan Chen, Zequn Huang, and Geo Xu
INDUSTRY & ENTERPRISE A DIY, hand-held, microcontroller-based stabilization
14 i PRODUCT NEWS system for camera control

21 i CLIENT PROFILE 40 : DIY RGB Game Design

Logic Supply (South Burlington, VT) An Upgrade for a Classic Platform
By Mitch Matteau
The most recent iteration of an engineer's electronic
Tic-tac-toe game system

COLUMNS
48 : GREEN COMPUTING
Pooling Microarchitectural Resources
Towards Flexible Heterogeneity
By Ayse K. Coskun
How pooling microarchitectural resources across
applications improves energy efficiency
FPGA-BASED "HYPERSNIFFER"—AN APP-SPECIFIC LOGIC ANALYZER
 c ircu itce lla r.co m s

CONTENTS

A MAX4544 EPOXIED ON A MOSFET

UPGRADED TIC-TAC-TOE GAME SYSTEM IR RECEIVER DEMODULATOR & LED TRANSMITTER

54 : THE CONSUMMATE ENGINEER TESTS & CHALLENGES

The Humble Resistor (Part 2)
Variable Resistors 74 : CROSSWORD
By George Novacek
A close look at variable resistors, including different 75 : TEST YOUR EQ
styles and power ratings

58 : ABOVE THE GROUND PLANE TECH THE FUTURE

Improved Arduino PWM MOSFET Gate Drive 80 : The Future of 3-D Printed Electronics
By Ed Nisley By Dr. Martin Hedges
Reworked Hall-effect LED current control circuitry and An analysis of the potential for 3-D printed electronics to
firmware change the tech landscape and revolutionize production

66 : FROM THE BENCH

IR Remotes (Part 2)
IR Transmissions Explained
By Je ff Bachiochi
Tips on how to identify, decode, and reproduce IR
transmissions

3-D PRINTED ELECTRONICS DEMO (SOURCE: NEOTECH)

@editor_cc n
VARIOUS POTENTIOMETERS AND TRIMMERS @circuitcellar circuitcellar
 6 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

CC WORLD

EE TIPS UPDATE
By CC & EIM Staff (US & Netherlands)
1 1

A few months ago, the Circuit Cellar and Elektor team

started posting electrical engineering (EE) tips on CircuitCellar.
com. There are now several dozen on the site, and more
are scheduled fo r the coming weeks. The EE Tips have been
generating a lot of positive feedback. Two tips that have been
shared the most during the past several weeks are "Embedded
Security" (EE Tip #139) and "D on't Trust Connectors, Solder, or
Wires" (EE Tip #138).

EMBEDDED SECURITY
Embedded security is one of the most im portant topics
in our industry. You could build an amazing m icrocontroller-
based design, but if it is vulnerable to attack, it could
COMMUNITY

become useless or even a liability.

Virginia Tech professor Patrick Schaumont explains,
"perfect embedded security cannot exist. Attackers have a
wide variety of techniques at their disposal, ranging from
analysis to reverse engineering. When attackers get their
hands on your embedded system, it is only a m atter of
tim e and sufficient eyeballs before someone finds a flaw
and exploits it."
So, w hat can you do? In CC25, Patrick Schaumont
provided some tips:
As design engineers, we should understand
what can and what cannot be done. I f we
understand the risks, we can create designs
that give the best possible protection at a given
level o f complexity. Think about the following
four observations before you start designing an
embedded security implementation.
First, you have to understand the threats that
you are facing. I f you don't have a threat model, it
makes no sense to design a protection—there's no
threat! A threat model for an embedded system
will specify what can attacker can and cannot do.
Can she probe components? Control the power
supply? Control the inputs o f the design? The
more precisely you specify the threats, the more
robust your defenses will be. Realize that perfect
security does not exist, so it doesn't make sense
to try to achieve it. Instead, focus on the threats
you are willing to deal with.
Second, make a distinction between what
you trust and what you cannot trust. In terms of
building protections, you only need to worry about
what you don't trust. The boundary between what
you trust and what you don't trust is suitably called
the trust boundary. While trust boundaries were
originally logical boundaries in software systems,
they also have a physical meaning in embedded
context. For example, let's say that you define the
trust boundary to be at the chip package level of
a microcontroller. (Go to http://bit.ly/1xXTx71 for
the rest o f his tips.)
Using the w rong p in o u t fo r a connector is a com m o n e rro r, especially on RS-232 ports
w h ere it's a p p ro x im a te ly 50% probable th a t you'll have the w rong RX/TX m apping.
S w apping the row s o f a connector (as you see here) is also q u ite c o m m o n .
DON'T TRUST CONNECTORS, SOLDER, OR WIRES
Engineer Robert Lacoste is one of our go-to
resources fo r engineering tips and tricks. When we
asked him fo r a few bits of general engineering advice,
he responded w ith a list of more than 20 invaluable
electrical engineering-related insights. One our team's
favorite "Lacoste tip s" is this: don't tru s t connectors,
solder, or wires. Read on to learn more.
One o f my colleagues used to say that 90%
o f design problems are linked either to power
supplies or to connector-related issues. It's often
the case. Never trust a wire or a connector. If
you don't understand what's going on, use your
ohmmeter to check if the connections are as
planned. (Do this even i f you are sure they are.) A
connector might have a broken pin, a wire might
have an internal cut, a solder joint might be dry
and not conductive, or you might simply have a
faulty wiring scheme. (Go to http://bit.ly/UNpUZk
for the rest o f his tips.)
We're always looking fo r new EE tips. If you have any
tips, tricks, or suggestions, please send them to our editorial
d epartm ent. Thanks!
Send us your EE tips!
I E -m a il y o u r tips and advice
to editor@circuitcellar.com
^0 Tweet y ou r tip and advice to
@circuitcellar. #eetips
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8 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

QUESTIONS & ANSWERS

Engineer, Blogger, and

FPGA Enthusiast
An Interview with Chris Zeh
San Jose, CA-based hardware design engineer and blogger Chris Zeh enjoys work­
ing with FPGA development boards, application-specific integrated circuits, and
logic analyzers. We recently discussed some of the projects he is involved with at
STMicroelectronics and on his own.—Nan Price, Associate Editor

NAN: Tell us about Idle-Logic.com. Why and
when did you decide to start a blog?
CHRIS: I started blogging in the winter of 2009, a
little more than a year after I graduated Colorado
State University with a BSEE. I realized that after
graduating it was important to continue working
on various projects to keep my mind and skills
sharp. I figured the best way to chronicle and
show off my projects was to start a blog—my

a — Chris's S a turn board prototype

includes an A lte ra Cyclone I I FPGA anc
JTAG FPGA p ro g ra m m e r, tw o linear
regulato rs, a 5-V breadb oard pow er
supply, and a 24-M Hz clock. b—A side
vie w o f the board

little corner of the Internet. Initially, I didn't really
expect many people to visit the site, thus the main
purpose was to act as a personal journal for the
projects I was working on.
During the summer of 2009, Katie, who
was then my girlfriend and is now my wife,
was finishing her Master's degree in Biomedical
Science and about to start four more years of
schooling to get her DVM. I figured a good way to
be a supportive significant other was to join her in
the library. While she furiously studied cardiology,
oncology, and all the other "ologies," I was busy
putting together my website and working on
projects (at the same time I also started University
of California Berkeley Extension's Integrated Circuit
Design and Techniques certificate program).
NAN: What types of projects do you feature on
your site?
CHRIS: I like working on a wide range of
different types of projects, varying from software
development to digital and analog design. I've
found that most of my projects highlighted on
Idle-Logic.com have been ones focusing on FPGAs.
I find these little reprogrammable, multipurpose
ICs both immensely powerful and fascinating to
work with.
My initial plan for the blog was to start a
development project to create an FPGA equivalent
to the Arduino. I wanted to build a main board with
all the basic hardware to run an Altera Cyclone II
FPGA and then create add-on PCBs with various
sensors and interfaces. My main FPGA board was
to be named the Saturn board, and the subsequent
add-on "wings" were to be named after the various
moons of Saturn.
The project proceeded nicely. I spent some time
brushi ng up on my Photoshop skills to put together a
Chris is w o rkin g w ith a Terasic Technologies DE0-Nano evaluation board to s u p p o rt a fu ll-c o lo r TFT LCD touchscreen display.
c ircu itce lla r.co m 9
QUESTIONS & ANSWERS
Chris used a USB-to-UART technique
to b it bang an FPGA configuration
file.
logo and came up with a minimized BOM solution to
provide power to the nine different voltage supplies,
both linear regulators and switched-mode supplies.
One aspect of FPGAs that can make them costly for
COMMUNITY
hobbyist is that the programming JTAG cable was
on the order of $300. Fortunately, there are a few
more affordable off-brand versions, which I used at
first. After many weeks of work, I finally had the
total solution for the main FPGA board. The total
cost of the prototype system was about $150.
Eventually I came up with a way to bit bang the
FPGA's programming bitstream using a simple
$15 UsB-to-UART IC breakout board driven by a
tiny Python application, eliminating the need for
the pricey cable. This Future Technology Devices
International FT232RL USB-to-UART IC also
provided a clock output enabling me to further
reduce the component count.
The project was a success in that I was
compelled to completely digest the FPGA's 470-
page handbook, giving me a solid grasp of how to
work with FPGAs such as the Cyclone II. The project
was a failure in that the FPGA breakout board I
wanted to use for the project was discontinued by
 10 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
QUESTIONS & ANSWERS
COMMUNITY
Chris designed the HyperSniffer logic analyzer, w hich is shown w ith the HyperDrive m ain board. (The PCB was designed by Vincent
Himpe and Albino Miglialo.)
the manufacturer. Creating and fabricating my
own four-layer board and hand soldering the 208-
pin package was both prohibitively expensive and
also a little daunting.
Fortunately, at that time Terasic Technologies
introduced its DE0-Nano, a $79 commercial, $59
academic, feature-packed FPGA evaluation board.
The board comes with two 40-pin general I/O
plus power headers, which has become a perfect
alternative base platform for FPGA development.
I now intend to develop add-on "wings" to work
with this evaluation board.
NAN: What do you enjoy most about working
with FPGAs?
CHRIS: The FPGA is such an amazing invention.
The possibility to create a digital design using
hardware description language (HDL) and
immediately see your creation working on your
bench is fantastic. The ability to create multiple
functional blocks that operate in parallel all in one
device is so powerful.
I can recall how perplexed I was when first
learning about the FPGA. The idea of creating
various tasks that operated in parallel seemed
so foreign compared to a microprocessor's more
familiar sequential operation. The ability to create
complex digital designs without having to fabricate
an application-specific integrated circuit (ASIC)
unlocked a whole world of possibilities. Working
with an FPGA comes with a steep learning curve,
but I believe it is definitely worth the time and
effort.
NAN: Tell us more about how you've been using
Terasic Technologies's DE0-Nano development
and education board.
CHRIS: The main project I've been working on
lately with the DE0-Nano is creating and adding
support for a full-color 4.3" (480 x 272 pixel) thin-
film transistor (TFT) touchscreen LCD. Because of
the large pin count available and reconfigurable
logic, the DE0-Nano can easily support the display.
I used a Waveshare Electronics $20 display, which
includes a 40-pin header that is almost but not
quite compatible with the DE0-Nano's 40-pin
header. Using a 40-pin IDC gray cable, I was
able to do some creative rewiring (cutting and
swapping eight or so pins) to enable the two to
mate with minimal effort. Eventually, once all the
features are tested, I'll fabricate a PCB in place of
the cable.
There are many libraries available to drive the
display, but for this project I want to develop the
hardware accelerators and video pipeline from the
ground up, purely though digital logic in the FPGA.
I recently picked up an SD card breakout board
and a small camera breakout board. Using these
I would like to start playing around with image
processing and object recognition algorithms.
NAN: What is your title at STMicroelectronics.
What types of projects are you working on?
CHRIS: My official title is Senior Hardware Design
Engineer. This title mainly comes thanks to the
first project I worked on for the company, which is
ongoing—an FPGA-based serial port capture and
decoding tool named the HyperSniffer. However,
my main role is that of an application engineer.
I spend most of my tim e testing and
debugging our prototype mixed-signal ASICs
prior to mass production. These ASICs are built
for the hard disk drive industry. They provide
several switch-mode power supplies, linear
regulators, brushless DC motor controllers, voice
coil motor actuation, and a shock sensor digital
processing chain, along with the various DACs,
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 12 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

QUESTIONS & ANSWERS

ADCs, and monitoring circuits all integrated into
a single IC.
Our ASIC's huge feature set requires me to stay
sharp on a wide variety of topics, both analog and
digital. A typical day has me down in the lab writing
scripts in Python or Visual Studio, creating stimuli,
and taking measurements using my 1-GHz, 10-
GSPS LeCroy WavePro 7100A oscilloscope, several
6.5-digit multimeters, dynamic signal analyzers,
and noise injection power supplies among other
instruments. I work closely with our international
COMMUNITY
design team and our customers to help discover
and document bugs and streamline the system
integration.
A few years back I was able to join my
colleagues in writing "Power Electronics Control
to Reduce Hard Disk Drive Acoustics Pure
Tones," an Institute of Electrical and Electronics
Engineers (IEEE) paper published for the Control
and Modeling for Power Electronics (COMPEL)
2010 conference. I presented the paper, poster,
and demonstration at the conference discussing

For Chris's senior design project, he

w orked w ith a team at Colorado State
University to design a prototype
engine calibration controller. a—
This inside view shows th e te rm in a l
blocks and video graphics array
(VGA) connector, w hich enabled
the team to quickly swap different
encoders and displays. b— The
top view shows the 5 .7 " th in -film
tra n sisto r (TFT) LCD and various
ro ta ry encoders on th e custom
acrylic enclosure, w hich swings
open to reveal a D igi Inte rn a tion a l
ConnectCore 9 evaluation board.

a novel technique to reduce acoustic noise
generated by a spindle motor.
NAN: Tell us more about the HyperSniffer
project.
CHRIS: The HyperSniffer project is an FPGA-
based digital design project I first created right
out of college. (My colleagues Vincent Himpe and
Albino Miglialo did the board design and layout.)
The tool is basically an application-specific logic
analyzer. It enables us to help our customers
troubleshoot problems that arise from serial port
transmissions between their system-on-a-chip
(SoC) and our ASIC. Through various triggering
options it can collect and decode the two or
three wire data transmissions, store them on on­
board memory, and wait for retrieval and further
processing by the application running on the PC.
One of this tool's nice features is that it is capable
of synchronizing and communicating with an
oscilloscope, enabling us to track down problems
that happen in the analog domain that arise due
to commands sent digitally.
NAN: Tell us about your software developer
internship at Nestle Purina. Can you share any
interesting experiences?
CHRIS: I took this internship right out of high
school, in the summer before starting at Colorado
State University. Initially, I was hired to help
convert 300 database-backed web applications
from an old programming language to a new one.
I've been programming since I was very young,
so I had a talent and a knack for writing software
to make life easier. I was able to automate the
conversion process and finished a full two months
early. After demonstrating my abilities, the scope
of my internship was expanded to include a full
redesign of the internal website. I continued to
work for Nestle Purina for the following two
summers and holiday breaks, writing applications
to process manufacturing data and help automate
report generation. It was a fun introduction to
the working world. I had a lot of autonomy and
they really let me take on any project I wanted.
I spent a lot of time learning how to write clean,
reliable, and professional code—an experience
that benefits me to this day.
NAN: You also did an internship at Xilinx. Can you
elaborate on the FPGA research you conducted?
CHRIS: This was a short internship for a few
months between semesters. My research mainly
focused on evaluating the accuracy of the power
planning tools integrated into the Xilinx ISE
design suite, comparing the projected power
consumption vs the actual. Additionally, I was
tasked to compare the power performance of
several designs on hardware from the various
c ircu itce lla r.co m 13
QUESTIONS & ANSWERS
FPGA manufactures. Much of the work was
spent creating tools to collect data and generate
visualizations for comparisons and marketing
purposes.
NAN: How long have you been designing
embedded systems? When did you become
interested?
CHRIS: The first real embedded system I worked
on was during my senior design project at
Colorado State University. I was the project leader
for a group of four students. Our goal was to
develop an embedded system that would provide
a clean user interface to assist in the calibration
of the internal combustion engine. The device
was developed to communicate with an engine
controller to modify parameters such as fuel
quantity and spark timing.
COMMUNITY
The team built a prototype enclosure that
housed a Digi International ConnectCore9
evaluation board, a 5.7" TFT LCD, several
quadrature encoders, and various buttons. The
ARM microprocessor ran Digi International's
NET+OS RTOS. We were able to quickly develop a
GUI using the wxWidgets cross-platform library.
The project was a success and we placed third in
a year-end competition among all the other senior
design project groups.
NAN: What do you consider to be the "next big
thing" in the industry?
CHRIS: Judging by the number of people I see
walking down hallways or sidewalks staring down
at their smartphones, I have to believe that optical
head-mounted displays (e.g., Google Glass) are
going to be ubiquitous one day soon. In my opinion,
the biggest drawback to these types of wearable
computers, aside from cost, is the interface. Not
only do you stand out in a crowd just by wearing
the glasses, but you further alienate yourself by
having to verbally control the hardware. I would
imagine that adding small tactile remote control
would be a big improvement. Maybe even just
adding a few buttons (up/down/left/right, enter,
and back) on the reverse side of a smartphone—
which you could use without having to look down—
would improve the head-mounted display's
usability and reduce the awkwardness factor.
The market for wearable embedded systems
for fitness really seems to be taking off. The ability
to track and monitor fitness goals using motion­
tracking armbands seems to be a real hit. I think
the gamification of fitness using these wearables
really helps to encourage healthy habits. For
many, the desire to achieve their target step count
or distance each day while having their
accountability literally strapped to them is quite
motivating. Some of the new technologies on the
horizon capable of tracking even more metrics
(e.g., heart rate) are really intriguing. O
 14 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

PRODUCT NEWS

DUAL-PHASE BOOSTS STEP-

UP EFFICIENCY
Linear Technology Corp. recently introduced
the LTC3124 tw o-phase, 3-MHz current-m ode
synchronous boost DC/DC converter. It features
outp ut disconnect and inrush cu rre n t lim iting.
Dual-phase operation has the benefit of reducing
peak inductor and capacitor ripple currents. This
allows equivalent perform ance to be achieved
in the power supply design w ith sm aller valued
inductors and capacitors.
The LTC3124 incorporates low resistance
MOSFETs w ith an RDS(ON) of 130 m fi (N-channel)
and 200 mQ (P-channel) to deliver efficiencies
as high as 95%. The ou tp u t disconnect feature
allows the outpu t to be com pletely discharged
INDUSTRY & ENTERPRISE

at shutdown and reduces sw itch-on inrush. An

in put pin can be used to configure the LTC3124
fo r continuous frequency mode to give low-noise
operation. A dditional features include external
synchronization, output overvoltage protection,
and robust sh o rt-c irc u it protection.
The LTC3124's main features include: • O utput Overvoltage Protection
• Internal s o ft-s ta rt
• VIN Range: 1.8 V to 5.5 V, 500 mV a fte r sta rt-u p • Less than 1 |j A IQ in shutdown
• A djustable ou tp u t voltage: 2.5 V to 15 V
• 1.5-A O utput cu rre n t fo r VIN = 5 V and VOUT = 12 V The LTC3124EDHC and LTC3124EFE are both available
• Dual-phase control reduces o utput voltage ripple fro m stock in 16-lead 3 mm x 5 mm DFN and the rm a lly
• O utput disconnects fro m in p u t when shut down enhanced TSSOP packages, respectively. One-thousand-
• Synchronous rectification: up to 95% efficiency piece pricing s ta rts at $3.26 each.
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• Selectable Burst Mode operation: 25- j A IQ

EIGHT-CORE, 64-BIT PROCESSOR TARGETS MOBILE DEVICES

MediaTek re c e n tly announced the MT6795 , w hich A ccording to MediaTek, we can expect to see 4G
the com pany is ta rg e tin g a t the h ig h -e n d A n d ro id 4G sm a rtp h o n e s using MT7695 chips before the end o f 2014.
sm a rtp h o n e s and ta b le t segm ent. A ccording to the
com pany, the e ig h t-c o re processor also s u p p o rts 2560 MediaTek, Inc.
x 1600 re so lu tio n d isp la ys, FDD/TDD LTE technology, w w w .m ediatek.com
802.11ac W i-F i, B lu e to o th , GPS, FM Radio, and 2G and 3G
w ire le ss n e tw o rks.
The chip also su p p o rts video re c o rd in g and playback at
U ltra HD (4K2K) re so lu tio n using the H.265, H.264 and VP9
fo rm a ts , s u p p o rtin g h igh-speed 1080p video re co rd in g
a t up to 480 fra m e s per second a llo w in g s lo w -m o tio n
playback on screens w ith 120 Hz re fre s h . An in te g ra te d
16-MP cam era im age signal processor handles vid e o in p u t
and MediaTek's C learM otion te c h n o lo g y e lim in a te s m otion
j it t e r to ensure sm ooth vid e o playback a t 60fps.
The MT6795 uses e ig h t ARM C ortex-A 53 processors,
based on a 28 -n m process th a t clocks a t 2.0 GHz and a
M ali-T 760 GPU to handle d isp la y co n tro l. MediaTek also
supplies its C oreP ilot te ch n o lo g y, w hich pro vid e s m u ltic o re
processor p e rfo rm a n c e and th e rm a l c o n tro l of th e chip.
The MT6795 also su p p o rts d u a l-ch a n n e l LPDDR3 m e m o ry
a t 933 MHz.
 c ircu itce lla r.co m 15

PRODUCT NEWS

EMBEDDED SOM WITH LINUX-BASED RTOS

N ational In s tru m e n ts has in tro d u ce d The LabVIEW FPGA gra p h ica l
an em bedded system-on-module (SOM) d e ve lop m e n t p la tfo rm e lim in a te s the need
development board w ith in te g ra te d Linux- fo r e x p e rtis e in the design a p proach using
based re a l-tim e o p e ra tin g syste m (RTOS). a h a rd w a re d e s c rip tio n language.
Processing pow er in the 2 " x 3"
SOM comes fro m a X ilin x Zync-7020 all National Instrum ents
p ro g ra m m a b le SOC ru n n in g a dual core w w w .ni.com
ARM C ortex-A 9 a t 667 MHz. A b u ilt-in ,
lo w -p o w e r A rtix -7 FPGA o ffe rs 160 s in g le ­
ended I/O s and Its dedicated processor
I/O include G igab it E th e rn e t USB 2.0 host,
USB 2.0 h o st/d e vice , SDHC, RS-232, and
Tx/R x. The SOM's pow er re q u ire m e n ts are
ty p ic a lly 3 to 5 W.
The SOM in te g ra te s a va lid a te d board

INDUSTRY & ENTERPRISE

s u p p o rt package (BSP) and device d riv e rs
to g e th e r w ith the N ational In s tru m e n ts
Linux re a l-tim e OS. The SOM board is
supplied w ith a fu ll s u ite of m id d le w a re
fo r developing an em bedded OS, custom
s o ftw a re d riv e rs , and o th e r com m on
s o ftw a re com ponents.

RASPBERRY PI MODEL B+
The Raspberry Pi foundation announced what it calls "an long as there's demand for it.
evolution" of the Raspberry Pi SBC. Compared to the previous At $35, the new model B+ is the same price as the older model
model, the new Raspberry Pi Model B+ has more GPIO, and B and is already available fromFarnell/element14/Newark and RS/
more USB ports. In addition, it uses Micro SD memory cards and Allied Components.
improved power consumption.
The GPIO header is now 40 pins, with the same pinout for Raspberry Pi Foundation
the first 26 pins as the Model B. The B+ also has four USB 2.0 www.raspberrypi.org
ports (compared to two on the Model B) and better hotplug and
overcurrent behavior. In place of the old frictio n -fit SD card socket
is a better push-push micro SD version.
In line with today's electronic concepts, the
new board also lowers power consumption.
By replacing linear regulators with switching
ones, the power requirements are reduced
by between 0.5 W and 1 W. The audio circuit
incorporates a dedicated low-noise power
supply, enabling better audio applications.
The new board is well organized. The USB
connectors are aligned with the board edge,
and the composite video now has a 3.5-mm
jack. The corners are rounded with four
squarely placed mounting holes.
The Raspberry Pi Model B+ uses the same
BCM2835 application processor as the Model
B. It runs the same software and still has 512­
MB RAM.
If you want to adapt a current project to
the new platform, be sure to study the new
GPIO pins and mechanical specs. To ensure
continuity of supply for industrial customers,
the Model B will be kept in production for as
 16 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
PRODUCT NEWS
JANSR+ 100KRAD TRANSISTORS FOR RADIATIVE ENVIRONMENTS
STMicroelectronics recently announced it is bringing into
the JANS system the innovation released last year w ith in the
European Space Components Coordination (ESCC) program .
Called JANSR+, the innovation consists of a series of 100krad
JANSR high-dose-rate bipolar tra n sisto rs w ith an additional
100krad low -dose-rate (100 mrad/s) te st perform ed on each
wafer.
Furtherm ore, ST has announced it w ill complete its
JANSR+ offer w ith data fro m ve ry-lo w -d o se -ra te (10 mrad/s)
tests, dem onstrating the outstanding robustness to radiation
effect of its technology.
As a result, ST's JANSR+ series gives access to products
w ith superior perform ance in radiative environm ents, w ith
complete test data to support the claim. These products
INDUSTRY & ENTERPRISE
NEW DUAL-CHANNEL FUNCTION/ARBITRARY WAVEFORM GENERATORS
B&K Precision recently launched its new 4060 Series line
of dual channel fu n c tio n /a rb itra ry w aveform generators. The
series includes three models th a t generate sine waveform s
up to 80 MHz (4063), 120 MHz (4064), and 160 MHz (4065).
Featuring an advanced pulse generator and high-perform ance
512k-point a rb itra ry w aveform generator on one channel,
these instrum ents are ideal fo r use in applications requiring
high signal fid e lity w ith extensive m odulation and a rb itra ry
w aveform capabilities at a value price point.
Unique to the 4060 Series are its advanced pulse
generation capabilities. The instrum ents can generate pulses
w ith low jit te r less than 100 ps and ou tp u t 12 ns w idth pulses
at frequencies as low as 0.1 Hz-a feature not typ ica lly found
in DDS generators. Rise and fall tim es are also adjustable
w ith in a large range, e.g. users can ou tp u t pulses w ith 6 ns
rise tim es combined w ith 6 s fall tim es.
All models provide tw o independent o utput channels w ith
a large 4.3" color LCD display, ro ta ry control knob, numeric
keypad, and in tuitive function keys to make waveform
adjustm ents quick and easy. Other standard features
include a b uilt-in counter, Sync output, trig g e r I/O term inal,
and external 10 MHz reference clock input and o utput fo r
synchronization of the in stru m e n t to another generator.
The 4060 Series offers linear and lo garithm ic sweep
function and a wide v a rie ty of m odulation schemes fo r
modulated signal applications: am plitude and frequency
can be used w ith o u t any up-screen cost and lead tim e , thus
d ram atically raising the bar in the industry.
All parts are housed in advanced herm etic UB packages
and are available in sample and volume quantities.
STMicroelectronics
www.st.com
m odulation (AM/FM), double sideband am plitude m odulation
(DSB-AM), am plitude and frequency s h ift keying (ASK/FSK),
phase m odulation (PM), and pulse w idth m odulation (PWM).
Equipped w ith a high perform ance 14-bit, 500 MSa/s,
512k-point a rb itra ry w aveform generator, the 4060 Series
provides users 36 b uilt-in a rb itra ry w aveform s and the ab ility
to create and load up to 32 custom a rb itra ry waveform s using
the included w aveform editing softw are via standard USB
interface on the rear. A fro n t panel USB host p o rt is available
fo r users to conveniently save waveform s and setups on a USB
flash drive or to connect the optional USB-to-GPIB adapter for
GPIB connectivity.
Available im m ediately, B&K Precision's 4060 Series
products are backed by a standard th ree-year w a rra n ty at
the following list prices:
• 4063 - 80 MHz - $1,350
• 4064 - 120 MHz - $1,670
• 4065 - 160 MHz - $1,990
For additional technical specifications, accessories, photos,
and su p p o rt documents, v is it B&K Precision's website.
B&K Precision Corp.
www.bkprecision.com
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 18 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

PRODUCT NEWS

USB-230 SERIES: NEW LOW-

COST 16-BIT DAQ
Measurement Computing Corporation recently
announced the release of tw o, 1 6-bit, m ultifunction
USB DAQ devices w ith sample rates up to 100
ksps. The USB-230 Series includes low-cost 16-bit
m ultifunction USB devices. Each device features eight
single-ended/four differential analog inputs, eight
digital I/O, one counter input, and tw o 16 -b it analog
outputs. Removable screw -term inal connectors make
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The USB-231 costs $249 and has a 50-ksps
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rate and is available fo r only $424.
Included softw are options fo r the USB-230
Series include out-of-th e -b o x TracerDAQ fo r quick-
INDUSTRY & ENTERPRISE

and-easy logging and displaying of data, along w ith

comprehensive support fo r C, C++, C#, Visual Basic,
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DASYLab and NI LabVIEW.

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SDK FOR OPENCL DEV FLOW

Altera Corp. has simplified a programmer's ability to accelerate
algorithms in FPGAs. The Altera SDK for OpenCL version 14.0
includes a program m er-fam iliar rapid prototyping design flow
that enables users to prototype designs in minutes on an FPGA
accelerator board. Altera, along with its board partners, further
accelerate the development of FPGA-based applications by offering
reference designs, reference platforms and FPGA development
boards that are supported by Altera's OpenCL solution. These
reference platforms also streamline the development of custom
FPGA accelerators to meet specific application requirements.
Altera is the only company to offer a publicly available, OpenCL
conformant software development kit (SDK). The solution allows
programmers to develop algorithms with the C-based OpenCL
language and harness the performance and power efficiencies
of FPGAs. A rapid prototyping design flow included in the Altera
SDK for OpenCL version 14.0 allows OpenCL kernel code to be
emulated, debugged, optimized, profiled and re-compiled to a
hardware implementation in minutes. The re-compiled kernels can
be tested and run on an FPGA immediately, saving programmers
weeks of development time.
Altera and its board partners further sim plify the experience
of getting applications up and running using FPGA accelerators
by offering a broad selection of Altera-developed reference
platforms, reference designs and FPGA accelerator boards. Altera
provides a variety of design examples that demonstrate how to
describe applications in OpenCL, including OPRA FAST Parser for
finance applications, JPEG decoder for big data applications and
video downscaling for video applications.
Design teams that want to create custom solutions that
feature a unique set of peripherals can create their own custom
FPGA accelerators and save significant development time by
using Altera-developed reference platforms. The reference
platforms include an SoC platform for embedded applications, a
high-performance computing (HPC) platform and a low-latency
network-enabled platform that utilizes IO Channels.
One notable enhancement is production support for I/O
Channels that allow streaming data into and out of the FPGA
as well as kernel channels allowing the result reuse from one
kernel to another in a hardware pipeline for significantly higher
performance and throughput with little to no host and memory
interaction. Another enhancement is production support for
single-chip SoC solutions (Cyclone V SoC and Arria V SoC), where
the host is an embedded ARM core processor integrated in the
FPGA accelerator.
Altera's SDK for OpenCL allows programmers to take OpenCL
code and rapidly exploit the massively parallel architecture of an
FPGA. Programmers targeting FPGAs achieve higher performance
at significantly lower power compared to alternative hardware
architectures, such as GPUs and CPUs. On average, FPGAs deliver
higher performance at one-fifth the power of a GPU. Altera's
OpenCL solutions are supported by th ird-party boards through
the Altera Preferred Board Partner Program for OpenCL. Visit
www.altera.com/opencl.
The Altera SDK for OpenCL is currently available for download
on Altera's website (www.altera.com/products/software/opencl/
opencl-index.html). The annual software subscription for the SDK
for OpenCL is $995 for a node-locked PC license. For additional
information about the Altera Preferred Board Partner Program for
OpenCL and its partner members, or to see a list of all supported
boards and links to purchase, visit the OpenCL section on Altera's
website.
Altera Corp.
www.altera.com
 c ircu itce lla r.co m 19

PRODUCT NEWS

NEW BRUSHLESS DC MOTORS

Maxon's new brushless drive w ith a diam eter of 19 mm has been specially designed fo r high
speeds and features low heat developm ent and extrem ely quiet and low -vibration running. This
little powerhouse has applications in centers fo r m iniaturized processing, hand-held tools and
medical technology. When combined w ith planetary gearheads, many possible variations are
available for applications in these key markets.
With its m odular construction, this new brushless DC m otor is available in three perform ance
classes: the cost-optim ized EC 19 at 60 W, the strong and high-speed EC 19 at 120 W and the
sterilizable high-end version EC 19 at 120 W. The internals of the drives are responsible fo r their
individual characteristics:

• The EC 19 at 60 W is equipped w ith

a m agnetic circu it th a t is designed
fo r speeds of up to 80,000 rpm . The
m axim um continuous torque is 12
mNm and the m otor contains no

INDUSTRY & ENTERPRISE

Hall sensors.
• The EC 19 at 120 W has been designed
fo r speeds of up to 100,000 rpm and
delivers a high continuous torque of
24 mNm. Versions w ith and w ith o u t
Hall sensors are available.
• The EC 19 Sterilizable at 120 W may
be sterilized in an autoclave 1000
tim es. With a m axim um perm issible
speed of 100,000 rpm and 24 mNm
continuous torque, this drive also
w ithstands high tem peratures
and harsh steam cycles. This is
achieved through careful selection
of m aterials and through protection
of the components such as in the
herm etically sealed ro to r magnet.

With Maxon's winding technology, it is

possible to offer various voltage versions.
The sta to r has been designed w ith o u t
slots. Therefore, no cogging torque occurs
resulting in excellent control properties and
e xtra o rd ina rily smooth running. Together
w ith an optim ally balanced rotor, low-noise
and low -vibration operation is easily achieved.
Maxon's new sterilizable planetary
gearhead, the GP 19 M is ideal fo r applications
requiring very high speeds - input speeds
of up to 40,000 rpm . To accomm odate such
high speeds, the toothing and m aterials have
been especially designed to m inim ize frictio n .
A key demand placed on the m aterial is 1000
sterilization cycles. The gearhead contains
a special shaft seal. W orth noting is the no­
need to disassemble the drive unit fo r the
sterilization process.
The new 19-m m drives are p a rticu la rly
suitable fo r surgical and dental devices, such
as arthroscopic shavers and bone drills. There
is also a focus on respirators and CAD/CAM
spindle drives.

Maxon P recision M otors, Inc.

w w w .m axonm otorusa.com
 20 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

PRODUCT NEWS

KERNEL RTOS EVALUATION KIT

eSOL has started offering the eT-
Kernel Evaluation Kit fo r Xilinx's
Zynq-7000 All Program mable SoC,
w hich combines the dual-core ARM
Cortex-A9 MPCore processor w ith
X ilinx's 28-nm program m able logic
fabric. The Evaluation Kit integrates
eSOL's eT-Kernel M ulti-Core Edition
real tim e operating system (RTOS),
its dedicated eBinder integrated
developm ent environm ent (IDE),
m iddleware components, and device
drivers. This com plim entary 30-day
Evaluation Kit perm its developers
to easily and quickly evaluate the
INDUSTRY & ENTERPRISE
HDMI display driver, all of which are
integrated and im m ediately run on
the Zynq-7000 All Programmable
SoC Evaluation Board. The eBinder
IDE is available fo r eT-Kernel
M ulti-Core Edition-based softw are
development. Besides ARM's genuine
compiler, eBinder offers various
developm ent tools and functions to
stro n g ly support m u lti-p ro g ra m m in g ,
debugging, and analysis fo r complex
m u lti-co re softw are development.
Zynq-7000 All Program m able SoC
tig h tly integrates tw o ARM Cortex-A9
MPCore processors and FPGA
Program m able SoC and the eT-Kernel
Platform are an ideal com bination for
advanced embedded systems in the
autom otive, industrial, and medical
arenas, including A utom otive Driver
Assistance Systems (ADAS), high­
resolution graphic system s, machine
vision system s, and n etw ork systems.
eSOL Co., Ltd
www.esol.com

perform ance and qu a lity of Xilinx
Zynq-7000 All Program m able SoC and
eT-Kernel. Since eT-Kernel inherited
the functions and a rchitecture of
ulTRON, the m ost popular RTOS in
Japan and Asian countries, developers
can reuse th e ir uITRON-based
so ftw are assets w ith o u t fu rth e r work.
Runtime softw are in the Evaluation
Kit includes the eT-Kernel M ulti-core
Edition, eSOL's PrFILE2 FAT file system,
the SD m em ory card driver, and the
fabric. The hardware and softw are
p ro g ra m m a b ility of Zynq-7000 AP
SoC enables system developm ent
w ith high perform ance, fle xib ility,
and scalability, w hile achieving lower
power consum ption and cost. The eT-
Kernel/Zynq-7000 All Programmable
SoC Evaluation Kit allows developers
to ju m p -s ta rt th e ir evaluation
using packaged device drivers,
w hich saves the tim e and money
of developing them . Zynq-7000 All

24-CHANNEL DIGITAL I/O INTERFACE FOR ARDUINO & COMPATIBLES

SCIDYNE Corp. recently expanded its product line by
developing a digital I/O interface fo r A rduino hardware.
The DIO24-ARD makes it easy to connect to solid-state I/O
racks, switches, relays, LEDs, and many other comm only
used peripheral devices. Target applications include industrial
control system s, robotics, IoT, security, and education.
The board provides 24 nonisolated I/O channels across
three 8 -b it ports. Each channel's direction can be individually
configured as either an In p u t or O utput using standard SPI
lib ra ry functions. Outputs are capable of sinking 85 mA at 5
V. External devices attach by means of a 50 position ribbon-
cable style header.
The DIO24-ARD features stack-through connectors w ith
long-leads allowing systems to be b u ilt around m ultiple
Arduino shields. It costs $38 .
SCIDYNE Corp.
www.scidyne.com
 c ircu itce lla r.co m 21

CLIENT PROFILE

Logic Supply
www.logicsupply. com

35 Thompson St., South Burlington, VT 05403

CONTACT: Erika Austin (erika.austin@ logicsupply.com)

PRODUCTS/SERVICES: Logic S upply is an in d u s tria l and

embedded com puter provider offering end-to-end hardware
s o lu tio n s and OEM services to a w ide range of in d u s trie s
in c lu d in g Data A c q u is itio n , D ig ita l S ig n a g e , In d u s tria l
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INDUSTRY & ENTERPRISE

solution fo r data collection applications in any environm ent.
Logic Supply DAQ h ardw are is well suited fo r rem ote data
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FEATURES

Need a data acquisition system for gathering and sending analog data to
a user in real time? This article details the process of building a sensor-to-
user data acquisition system. Although this project is intended to monitor
forces exerted by rowers, you can use it as a guide to build a system for
measuring, displaying, and logging forces for a variety of applications.

By Steven Liu and Albert Ruskey (Canada)

ou have p ro b a b ly stood on a d ig ita l th a t w o rk s ? " The s e e m in g ly s im ple a b ility

Y b a th ro o m scale w here your fir s t
th o u g h t w as, "T h a t m u st be w ro n g !" Maybe
to ta ke a m e a su re m e n t, d ig itiz e it, and
p re se n t it to a user can be q u ite a m y s te ry
y o u r second th o u g h t w as, " I w o n d e r how to the u n in itia te d . We set o u t to not only

PHOTO 1
This is the finished force-sensing
u n it m ounted and attach ed to row ing
m achine for d e m o n s tra tio n . You can
see the LED and A n dro id displays.
 c ircu itce lla r.co m 23

u n d e rsta n d how such a system PHOTO 2

We m ounted s tra in gauges on a
w o rks, b u t also to ta ilo r it to our own
row ing footplate. They w ere attached
a p p lica tio n .
to steel bars w ith cyanoacrylate glue
W hile stu d yin g a t Camosun College
and soldered on 30-gauge w ire.
in Canada, we w ere in tro d u c e d to a
physics p ro fe sso r w ith close tie s to

FEATURES
the V ic to ria row ing p ro g ra m s. She
tu rn e d us on to the idea th a t system s
fo r m o n ito rin g force s exerted by
ro w e rs —and then re la tin g th a t data
to th in g s like a c c e le ra tio n —w ere
e x tre m e ly lim ite d . The idea was to
develop a system to m o n ito r forces
in re a l-tim e and p ro vid e fee d b a ck to
ro w e rs fo r e ffic ie n c y a nalysis. To do
so, we w anted to m o n ito r the force
a t a ro w e r's fe e t and re la te it to the
b o at's a cce le ra tio n . A d d itio n a lly , we
w anted tra c k the ro w e r's balance
of m o tio n to the rig h t or to the le ft.
Our e n d -to -e n d , s e n s o r-to -u s e r
data a c q u is itio n system was b u ilt
s p e c ific a lly w ith row in g in m in d ,
b u t you could easily m o d ify it to
m easure, display, and log forces
fo r any num b e r of a p p lic a tio n s (see
Photo 1).

GAUGING THE SITUATION

Our f ir s t p r io r ity was to
d e te rm in e how we w ou ld d e te c t the
fo rce s being ap p lie d by a row er.
We w e n t th ro u g h several o p tio n s
fo r fo rc e sensing w h ich included
s tra in g a u g e s, co n d u ctive fo a m , and w ould be fle x io n on the bar as the user
p ize o e le ctrics. A fte r te s tin g each op tio n row ed. Photo 2 shows o u r fin a l m o u n tin g
and w e ig h in g th e b e n e fits a g a in s t the s tra te g y . We used som e of the fo o tp a d 's
cost fo r each o p tio n , we d e te rm in e d th a t e x is tin g s u p p o rt a rc h ite c tu re to a p p ly even
s tra in gauges w ould p ro v id e the best p ressure across th e s tra in gauges.
m ix of lin e a rity , re p e a ta b ility , p re c is io n , Since the ele m e n ts are th in m etal
and s ta b ility fo r ou r purposes. Camosun film th a t changes w ith com pression and
College g e n e ro u sly d onated several V ishay/ te n s io n , th e y are p a rtic u la rly su sce p tib le
M icro -M e a su re m e n ts CEA-13-240UZ-120 to te m p e ra tu re . To avoid any possible
120-Q s tra in gauges to o u r p ro je c t. These issues, e specially because th is system
gauges are th in - film re s is tiv e e lem ents was designed w ith an o u td o o r ro w in g scull
th a t change th e ir resista n ce when
p u t u nd er te n sio n or co m p re ssio n .
FIGURE 1
These gauges are th in - film
F u ll-b ridg e strain g au ge circuit Here you see the bridg e config u ra tio n
re s is tiv e e lem en ts th a t change th e ir
fo r te m p e ra tu re com pensation and
re sista n ce when p u t u n d e r te n sio n
lin e a rity in data. As the s tra in gauges
or com pressio n. stretch and com press, th e ir electrical
The physical m o u n tin g of s tra in resistance changes, w hich produces
gauges can be qu ite a challenge in an o u tp u t voltage th a t relates to a r
and of its e lf. I t is im p o rta n t th a t it applied force.
p ro p e rly bonds to th e su rfa ce as any
unexpected tension or com pression
can g re a tly skew the re su lts. We used
a th in steel bar sanded down w ith
fin e , 8 0 0 -g r it san dpap e r and bonded
w ith G orilla c y a n o a c ry la te glue.
The m o u n tin g bar then had to be
o rie n te d in such a fash io n th a t th e re
 24 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

FIGURE 2 b rid g e c o n fig u ra tio n (see Figure 1).

The con d itio n in g c irc u it is designee
The v e ry th in e lem ents in the s tra in
to a m p lify sm all signal inputs using
gauge do not pass a v e ry large c u rre n t.
an LT1167 in s tru m e n ta tio n am p lifie r.
In o rd e r to produce a m e a su re m e n t th a t
This was used to a m p lify the m in o r
voltage changes com ing fro m our
we could read on o u r STM32F4 bo ard , we
stra in gauge c irc u its to the ARM
had to do som e signal c o n d itio n in g . This
FEATURES

board. c o n d itio n in g was done w ith an LT1167

in m in d , we had to create te m p e ra tu re
com p e n sa tio n . F o rtu n a te ly , th is was
accom plished w ith o u t m uch d iffic u lty by
p la c in g the s tra in gauges in a W heatstone
o p -a m p c irc u it shown in ( Figure 2). The
a m p lifie r uses a p o te n tio m e te r as a tu n in g
re s is to r in o rd e r to a d ju s t the s e n s itiv ity of
the s tra in gauge. This tu n in g allow s fo r a
w ide range of forces to be m easured.
ACQUIRING ANSWERS
W ith the strain gauges mounted in place,

v o id A D C _ C o n f ig u r a t io n ( v o id )
{
A D C _C o m m o n In itT y p e D e f A D C _ C o m m o n In itS tr u c tu re ;
A D C _ In itT y p e D e f A D C _ I n i t S t r u c t u r e ;

/* ADC Common I n i t */
A D C _ C o m m o n In itS tru c tu re .A D C _ M o d e = A D C _ M o d e _ In d e p e n d e n t;
A D C _ C o m m o n In itS tr u c tu re .A D C _ P r e s c a le r = A D C _ P re s c a le r _ D iv 2 ;
A D C _ C o m m o n In itS tru c tu re .A D C _ D M A A c c e s s M o d e = A D C _D M A A cce ssM o d e _D isa b le d ;
A D C _ C o m m o n In itS tru c tu re .A D C _ T w o S a m p lin g D e la y = A D C _ T w o S a m p lin g D e la y _ 5 C y c le s ;
A D C _ C o m m o n In it(& A D C _ C o m m o n In itS tru c tu re );

A D C _ I n itS tr u c tu r e . A D C _ R e s o lu tio n = A D C _ R e s o lu tio n _ 1 2 b ;

A D C _ In itS tru c tu re .A D C _ S c a n C o n v M o d e = ENABLE;
A D C _ In itS tr u c tu re .A D C _ C o n tin u o u s C o n v M o d e = ENABLE;
A D C _ In itS tr u c tu r e . A D C _ E x t e r n a lT r ig C o n v E d g e = A D C _ E x te rn a lT rig C o n v E d g e _ N o n e ;
/ / A D C _ I n it S t r u c t u r e . A D C _ E x t e r n a lT r ig C o n v = 0;
A D C _ In itS tr u c tu r e . A D C _ D a t a A lig n = A D C _ D a ta A lig n _ R ig h t;
A D C _ In itS tr u c tu r e .A D C _ N b r O fC o n v e r s io n = 4 ;
A D C _ In it(A D C 1 , & A D C _ I n it S t r u c t u r e ) ;

/* ADC1 r e g u l a r channel c o n fig u r a t io n s * /

A D C _ R e g u la rC h a n n e lC o n fig (A D C 1 , A D C _ C h a n n e l_ 1 1 , 1, A D C _ S a m p le T im e _ 4 8 0 C y c le s );
A D C _ R e g u la rC h a n n e lC o n fig (A D C 1 , A D C _ C h a n n e l_ 1 2 , 2, A D C _ S a m p le T im e _ 4 8 0 C y c le s );
A D C _ R e g u la rC h a n n e lC o n fig (A D C 1 , A D C _ C h a n n e l_ 1 4 , 3, A D C _ S a m p le T im e _ 4 8 0 C y c le s );
A D C _ R e g u la rC h a n n e lC o n fig (A D C 1 , A D C _ C h a n n e l_ 1 5 , 4, A D C _ S a m p le T im e _ 4 8 0 C y c le s );

A D C _ D M A R e q u e s tA fte rL a s tT ra n s fe rC m d (A D C 1 , ENABLE);

/* E n a b le ADC1 DMA * /
ADC_DMACmd(ADC1, ENABLE);

/* E n a b le ADC1 * /
ADC_Cmd(ADC1, ENABLE);
}

LISTING 1
This setup is fo r the ARM boa rd's b u ilt-in ADCs. I t was created for continuous 1 2 -b it conversions on data acquired fro m fo u r d iffe re n t GPIO pins.
 Messe München
International

Connecting Global Competence

Welcome to Planet e.
The entire em bedded universe at a single location!

2 6 th In te rn a tio n a l Trade Fair fo r

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w w w . e le ctro n ica .d e
 26 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

s ta t ic v o id D M A _ C o n f ig u r a t io n ( v o id )
{
D M A _ In itT y p e D e f D M A _ I n it S t r u c t u r e ;
FEATURES

D M A _ In itS tru c tu re .D M A _ C h a n n e l = D M A _C hannel_0;

D M A _ In itS tru c tu re .D M A _ M e m o ry 0 B a s e A d d r = ( u in t 3 2 _ t ) & A D C C o n v e r t e d V a lu e s [0 ] ;
D M A _ In itS tr u c tu r e .D M A _ P e r ip h e r a lB a s e A d d r = (u in t3 2 _ t)& A D C 1 - > D R ;
D M A _ In itS tru c tu re .D M A _ D IR = D M A _ D IR _ P e rip h e ra lT o M e m o ry ;
D M A _ In itS tr u c t u r e . D M A _ B u ff e r S iz e = 4 ; // C ount o f 1 6 - b i t w o rd s
D M A _ I n it S t r u c t u r e . D M A _ P e r ip h e r a lI n c = D M A _ P e r ip h e r a lIn c _ D is a b le ;
D M A _ In itS tru c tu re .D M A _ M e m o ry In c = D M A _ M e m o ryIn c_E n a b le ;
D M A _ In itS tr u c t u r e . D M A _ P e r ip h e r a lD a ta S iz e = D M A _ P e r ip h e ra lD a ta S iz e _ H a lfW o rd ;
D M A _ In itS tru c tu re .D M A _ M e m o ry D a ta S iz e = D M A _ M e m o ry D a ta S iz e _ H a lfW o rd ;
D M A _ In itS tru c tu re .D M A _ M o d e = D M A _ M o d e _ C irc u la r;
D M A _ I n it S t r u c t u r e . D M A _ P r io r it y = D M A _ P r io r ity _ H ig h ;
D M A _ In itS tru c tu re .D M A _ F IF O M o d e = D M A _FIFO M ode_E nable;
D M A _ In itS tr u c tu r e .D M A _ F IF O T h r e s h o ld = D M A _ F IF O T h re s h o ld _ H a lfF u ll;
D M A _ In itS tru c tu re .D M A _ M e m o ry B u rs t = D M A _ M e m o ry B u rs t_ S in g le ;
D M A _ In it S t r u c t u r e . D M A _ P e r ip h e r a lB u r s t = D M A _ P e r ip h e r a lB u r s t_ S in g le ;
D M A _ In it(D M A 2 _ S tre a m 0 , & D M A _ I n it S t r u c t u r e ) ;

/* DM A2_Stream0 e n a b le * /
DMA_Cmd(DMA2_Stream0, ENABLE);
}

LISTING 2 we w ere fin a lly ready to s ta r t reading G P IO _ In itS tru c tu r e .G P IO _ M o d e =

This setup is fo r the ARM boa rd's DMA
con tro lle r. I t was created w ith a base
address in m e m o ry fo r s to rin g ADC
conversion values. The DMA c o n tro lle r
enabled us to p e rfo rm m u ltip le ADC
conversions.
some values. We knew th a t we w ould need
a m ic ro c o n tro lle r to co lle ct and process
the data before passing it o u t fo r display.
To accom plish th is , we decided to use
a board th a t we had some experience
w ith , the S T M icro e le ctro n ics STM32F4
D iscovery Board (see Figure 3). I t includes
all of the in te rfa c e s we needed: tw o ADCs
w ith m u ltip le channels, tw o USARTs, and
m u ltip le g e n e ra l-p u rp o s e in p u t-o u tp u t
(GPIO) p o rts . This w ould enable us to
co lle ct data fro m the toe and heel o f each
fo o t, and then tra n s m it o u t to a M icrochip
Technology PIC18F1330 m ic ro c o n tro lle r
and a B luetooth m odule.
To c o n fig u re th e ADCs, we had to ta ke
a n u m b e r o f ste p s . The ADCs can c o n v e rt
va lu e s fro m e ith e r th e GPIO p in s o r fro m
o n -b o a rd p e rip h e ra ls . We w e re in te re s te d
o n ly in a c q u irin g d a ta on fo u r p in s fro m
o u r s tra in gau g e c irc u its ; we had no
in te re s t in th e p e rip h e ra ls . T h is m e a n t
th a t th e f i r s t s te p w as to c o n fig u re th e
GPIO p in s fo r a n a log use.
G P I O _ I n itS tr u c tu r e .G P IO _ P in =
G P IO _P in _1 | G P IO _ P in _ 2 |
G P IO _ P in _ 4 | G P IO _ P in _ 5 ;
GPIO _M ode_AN ;
S pecial c a re had to be ta k e n en su re
th e c o rr e c t p in s w e re s e le c te d fo r use.
We used PC1, 2, 4, 5, b u t it is easy to
m is ta k e n ly use PC3, w h ic h is n o t an
a v a ila b le ADC p in . Once we had th e GPIO
code s e tu p , we needed to e n a b le th e
ADC it s e lf to s ta r t re a d in g v a lu e s. M o st
o f th e ADC c o n fig u ra tio n is s im ila r to
th e s e tu p fo r a s in g le ADC, b u t w ith a
fe w im p o r t a n t d iffe re n c e s . We k n e w we
w e re g o in g to s e t up th e D ire c t M e m o ry
Access (D M A ) to h a n d le th e m u ltip le
c o n v e rs io n s and we had to s e t up th e
ADC w ith th a t in m in d . We had to s e t the
m odes to e n a b le m u ltip le c o n v e rs io n s
and th e n s e t th e n u m b e r o f c o n v e rs io n s
we w a n te d to p e rfo rm on each s e rv ic in g
o f th e ADC. Lines 146 to 149 in Listing 1
p o in t th e ADC a t th e c o rr e c t GPIO pins
and a lso d e te rm in e th e o rd e r in w h ic h th e
c o n v e rs io n s w ill be m a d e . A fte r a ll th is ,
we a lm o s t had u sa b le d a ta !
The fin a l ste p fo r o u r ADC c o n fig u ra tio n
w as h a n d lin g w h e re it w o u ld be sto re d
in m e m o ry . T h a t's w h e re th e DMA came
in to play. The DMA e n abled us to assign
The new EAGLE has landed!

e information, visit www.cadsoftusa.com

 28
FEATURES C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

FIGURE 3
This is the com plete p roje ct featu rin g
the ARM and PIC circu its. The ARM
b oa rd and co nd itioning c irc u its are
located a t the top. The PIC and LEDs
are displayed a t the bo tto m .

a lo c a tio n in m e m o ry to s to re all o u r
c o n v e rte d values. F inally, we had o u r
d a ta in a usable fo rm . B u t it s till seem ed
to a p p e a r as a valu e b e tw e e n 0 and
4 0 9 6 (see Listing 2). T h is va lu e a p p e a rs
because o f how th e ADC w o rk s . In o u r ADC
c o n fig u ra tio n , we chose a 1 2 -b it re s o lu tio n
so o u r rang e o f value s w as fro m 0 to 2 12.
To in te rp r e t th is as a v o lta g e , we to o k
o u r m a x im u m know n v o lta g e o f 5 V and
d iv id e d by 2 12, w h ich gave us o u r le a st
s ig n ific a n t b it and a w ay to re la te back to
o u r analog u n it.
TALK TO US!
A fte r we a c q u ire d o u r d a ta , we
needed to c o m m u n ic a te w ith th e w o rld .
We p ro v id e d tw o w a y s fo r a u s e r to see
fe e d b a c k fro m th e ir d a ta . We c re a te d
an A n d ro id a p p lic a tio n th a t a ccepted
in fo rm a tio n via B lu e to o th , and we also
c re a te d a 15-LED a rra y c o n tro lle d by a
P IC18F1330 m ic ro c o n tro lle r th a t received
c ircu itce lla r.co m 29
in fo rm a tio n o v e r a s e ria l c o n n e c tio n .
To c o n fig u re the USART on the STM32F4
D iscovery Board, we again had to set up
the GPIO pin th a t we w anted to use, but
th is tim e in A lte rn a te F unction (AF) mode.
FEATURES
G P IO _ In itS tru c tu re .G P IO _ M o d e =
G PIO_M ode_AF;
G P IO _ P in A F C o n fig (G P IO D ,
G P IO _ P in S o u rc e 8 , GPIO_AF_
USART3);
Next was to se tu p the USART its e lf. We
used s ta n d a rd s e ttin g s fo r an 8 - b it s e ria l
c o m m u n ic a tio n w ith o u r data ra te selected
depending on w hich device we were
c o m m u n ic a tin g w ith . To tra n s m it o u t via
B lu e to o th , we used an S T M icro e le ctro n ics
SPBT2632C2A B luetooth m odule. We were
able to p o rt our s e ria l c o m m u n ic a tio n
d ire c tly o u t over B lu e to o th . The m odule
comes p re c o n fig u re d to accept s e ria l in at
1 1 5 ,2 0 0 bps (data ra te ), so c o n fig u rin g our
PHOTO 3
Here you see ARM and PIC PCB boards
w ith o p -a m p cond itio n in g c ircu its
and MUX included. The overall system
on separate ARM-based (b o tto m )
and PIC-based (top ) PCB boards. We
used A ltiu m D esigner to create the
schem atics and PCB layouts.
 30 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
The end goal for our project was to see our data.
FEATURES
There are numerous options for communicating
with the user, such as LCDs, buzzers, and LEDs
... We implemented an array o f 15 LEDs that
would move back and forth in order to provide
additional information to the row er...
PROJECT FILES
c irc u itce lla r.co m /ccm a te ria ls
To d o w n lo a d th e code, go to
c irc u itc e lla r.c o m /c c m a te ria ls .
USART to the c o rre c t data ra te and then
passing data o u t was dead sim p le . Creating
A n d ro id a p p lic a tio n s is a broad to p ic th a t's
o u tsid e the scope of th is a rtic le . W e'll leave
it to you to in v e s tig a te it fu rth e r.
PIC US
Much s im p le r th a n cre a tin g an
A n d ro id a p p lic a tio n fro m scra tch was
o u r second USARTc o n fig u re d to be used
fo r c o m m u n ic a tin g w ith o u r PIC18F1330
m ic ro c o n tro lle r. The PIC18F1330 is lim ite d
to a data ra te of 9,600 bps a t the given
in te rn a l o s c illa to r speed. This lim ita tio n
m e a n t th a t, u n fo rtu n a te ly , we w ere not
able to d riv e both the PIC18F1330 and the
B luetooth u n its fro m a single pin on the
ARM.
When cre a tin g these c h ip -to -c h ip
co n n e ctio n s, we also had to pay special
a tte n tio n to our tim in g . They say th a t in
com edy tim in g is e v e ry th in g , b u t we th in k
SOURCES
A ltiu m D e s ig n e r s o ftw a re
A ltiu m | w w w .a ltiu m .c o m
PIC 18F1330 M ic ro c o n tro lle r
M ic ro c h ip T e chno lo gy, In c . | w w w .m ic ro c h ip .
com
SPBT2632C2A B lu e to o th M o dule and STM32F4
D is c o v e ry Board
S T M ic ro e le c tro n ic s | w w w .s t.c o m
C E A -13-2 40U Z -12 0 120-Q S tra in g a uge
V is h a y /M ic ro -M e a s u re m e n ts | w w w .v is h a y p g .
c o m /m ic ro - m e a s u re m e n ts /
it's even m ore im p o rta n t in e lectro nics!
Due to the d iffe re n c e in p ro ce ssor speed,
8 MHz fo r o u r PIC18F1330 com pared to 180
MHz fo r th e ARM, we have to be v e ry aw are
of o v e rflo w e rro rs when co m m u n ica tin g
betw een o u r chips. O ve rflo w occurs when
new data a rriv e s before the receive re g is te r
has had a chance to clear. To get around
th is , we in tro d u c e d a delay betw een each
USART co m m u n ic a tio n . A 10-m s delay was
m ore th a n enough to slow o u r system down
to avoid any chance of o v e rflo w , w hile s till
g ivin g us a high enough sam ple rate fo r
our data to be useful.
SHOW US THE WORLD
The end goal fo r our p ro je c t was to see
our data. There are n u m e ro us option s fo r
co m m u n ic a tin g w ith the user, such as LCDs,
buzzers, and LEDs. We needed som ething
th a t could p ro vid e in s ta n t fee d b a ck w ith o u t
re q u irin g th e user to focus too long. To this
end, we im p le m e n te d an a rra y of 15 LEDs
th a t w ould move back and fo rth in o rd e r
to p ro vid e a d d itio n a l in fo rm a tio n to the
ro w e r a b o u t th e ir p e rfo rm a n c e so th a t th ey
could c o rre c t th e ir le ft- r ig h t balance (see
Photo 3). The LEDs w ould a c t as a bubble
level and w ould be co lo r coded to ind ica te
ju s t how in or out of sync the ro w e r's fe e t
w ere.
The PIC18F1330 c o n fig u ra tio n was not
too d iffic u lt to fig u re out using the b u ilt-
in USART lib ra ry . The PIC18F1330 had a
m a xim u m in te rn a l o s c illa to r speed of 8
MHz, and as a re s u lt a m a xim u m data rate
of 9,600 bps. The setup fo r the PIC18F1330
USART is:
OpenUSART(USART_TX_INT_OFF
& USART_RX_INT_OFF
& USART_ASYNCH_MODE
& USART_EIG HT_BIT
& USART_CONT_RX
& USART_BRGH_HIGH, 5 1 );
Once we had the data on the
PIC18F1330, it was tim e to do som e thin g
w ith it. Processing the raw data was done
on the ARM board f ir s t to c o n v e rt the value
in to a s m a lle r num ber. This processing was
done f ir s t on the ARM due to the seria l
co m m u n ic a tio n o n ly being 8 b it and our
data being a 1 2 -b it value. The PIC18F1330
s im p ly receives a value th a t is easily
parsed to betw een 0 and 14, w hich then
runs a fu n c tio n to sw itc h on an LED. This of
course creates som e c o m p lic a tio n s as the
PIC18F1330 does not come equipped w ith
enough I/O pins to handle 15 LEDs!
The fin a l piece of th is puzzle was to add
in a m u ltip le x e r to add to o u r usable I/O
 c ircu itce lla r.co m 31

ABOUT THEAUTHORS
A lb e r t R uskey (a ru s k e y @ sh a w .ca ) s t u d ie d a t C a m osu n College in V ic to r ia , BC,
w h e re he an e a rn e d E le ctro n ics a nd C o m p u te r E n g in e e rin g T echnology d ip lo m a .
He is p u rs u in g fo r a d e g re e in C o m p u te r E n g in e e rin g , w ith a fo cu s on e m b e d ­
ded syste m s, a t th e U n iv e rs ity o f B ritis h C o lu m b ia . P reviously, A lb e rt w o rk e d as

FEATURES
a m a rin e te c h n o lo g is t fo r Ocean N e tw o rks C anada and an e le c tro n ic s te c h n ic ia n
fo r th e D e p a rtm e n t o f N a tio n a l Defense.

Steven Liu (s te v e n liu 2 0 @ h o tm a il.c o m ) e a rne d an E le ctro n ics and C o m p u te r En­

g in e e rin g T ech n o lo g y d ip lo m a fro m C a m osu n C ollege in V ic to ria , BC. Steven is
p u rs u in g an E le ctrica l E n g in e e rin g d e g re e a t th e U n iv e rs ity o f V ic to ria and plans
to sp e c ia liz e in m e c h a tro n ic s . He is also C o m pT IA A + c e rtifie d .

pins. Using an 8 -to -1 m u ltip le x e r as a lo w -sid e s w itc h , we w ere able to

get fo u r a d d itio n a l I/O pins fo r c o n tro llin g LEDs. Then all th a t was le ft was
to set up the ro u tin e th a t w ould tu rn on and o ff each LED. F o rtu n a te ly,
c o n tro llin g d ig ita l I/O on the PIC18F1330 re q u ire s less w o rk than on the
STM 32F4Discovery. S im p ly by s e ttin g the in d iv id u a l b its on each p o rt, you
are able to assign a logic hig h , w hich is enough to d rive an LED.
The last challenge was to ensure th a t only the sp e cifie d LED was on. To
th a t end, e ve ry tim e we called the LED fu n c tio n , we fir s t tu rn e d o ff all of the
LEDs and then lit the a p p ro p ria te one.
Now if you are th in k in g th a t you could d rive LEDs fro m th e STM32F4
b oard's GPIO pins and get rid of th e PIC18F1330 e n tire ly , y o u 're a b so lu te ly
c o rre c t! However, fo r o u r a p p lic a tio n , we w anted a so lu tio n th a t w ould give Project articles and
us the fle x ib ility to add a d d itio n a l fe a tu re s la te r, such as m aking the display design applications
w ire le ss or perhaps adding a d d itio n a l gauges to the STM32F4 board. We
fe lt it w ould be advanta g e o u s to be able to m ake m o d ific a tio n s w h ile only Embedded industry
cre a tin g a m in im u m a m o u n t of e x tra w o rk in itia lly . news and announcements
W ith th e PIC18F1330 c ir c u it in place, we a c c o m p lis h e d an e n d -to -e n d ,
s e n s o r-to -u s e r s y s te m . As an added b o n u s, due to th e w a y th a t th e d ata 12 issues annually
is a c q u ire d in d iv id u a lly and p ro ce sse d , it w o u ld be easy to ch a n g e o r add
fu n c tio n a lity . For e x a m p le , c h a n g in g th e LED d is p la y to d is p la y th e o ve ra ll CC.Post e-newsletter
fo rc e b e in g a p p lie d w o u ld s im p ly re q u ire c h a n g in g a s m a ll a m o u n t o f m a th
in th e ARM code. And th a t a c tu a lly w o u ld be s im p le r th a n w h a t's re q u ire d
fo r th e le ft- r ig h t balance fu n c tio n .

TURN IT ON
The only th in g le ft to do is tu rn it on and push off. T u rn in g it on m ig h t o
G
r c u it ce n Qr
be a pro b le m th o u g h because a lth o u g h e le c tric ity o fte n feels like m agic,

ügggasL m
it does in fa c t re q u ire a source of pow er to w o rk. For o u r a p p lic a tio n in a
ro w ing scull to be e ffe c tiv e , we could not increase the w e ig h t o f the scull
by m ore than a b o u t 1 lb. This ruled o u t th in g s like bu lky b a tte ry packs and
m u ltip le pow er sources. W ith th a t in m in d , all of o u r co m p o n e n ts—the ARM,
op -a m p s, PIC18F1330, and the MUX—w ere chosen to be able to run o ff of 5 V.
To keep the w e ig h t down fu rth e r, we decided to use an LM7805 lin e a r voltage
re g u la to r to re g u la te 9 V, w hich p rovides the g re a te s t vo lta g e fo r th e lig h te s t
w e ig h t of any sta n d a rd a lka lin e b a tte ry available.
H opefully, th is a rtic le has as p rovided some in s ig h t in to w h a t is re q u ire d
to create a data a c q u is itio n syste m . B u ilding a system to m easure w o rld
aroun d you can be both easy and inexpensive. I f we ig n o re the s tra in gauges,
w hich w ere do nated, the e n tire cost of the p ro je c t was close to $50!
We created our setup w ith ro w in g in m in d , b u t y o u 'll fin d it an excellent
s ta rtin g p o in t fo r any data a c q u is itio n system in w hich the end goal is to get
analog data back to a user in real tim e . It's easy. S im p ly re m e m b e r yo u r
drcuitcellor.com /
a cronym s: ARM to GPIO to ADC to DMA to USART to PIC to MUX to LED! O subscriptions
 32 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

Position Control
Build a Microcontroller-Based
Stabilization Platform
FEATURES

You can engineer a way to taking better

videos. This handheld self-stabilizing camera
system consists of a gyroscope and an
accelerometer mounted on a platform. When
sensors detect a change in the platform's
position, a microcontroller controls the
motors to counteract the disturbance.

By Evan Chen, Zequn Huang, Geo Xu (US)

s avid outdoor enthusiasts, we often on a p ro je ct fo r our m icro co n tro lle r design

A find ourselves taking action shots of our
adventures, only to discover a ve ry shaky
and nauseating video of our endeavors at the
end of the day. So, when we had to decide
course (ECE 4760) at Cornell University, we
chose to build a handheld camera stabilizing
p la tfo rm . While idea of a handheld camera
stabilizer is not new, this p ro je c t proved to be
a challenge when it came to both the softw are
and hardware. With a budget cap of $100, we
had to make design-related tradeoffs to keep
costs down yet retain overall perform ance.
In this a rticle , w e'll present our final design.
We'll detail the specific hardware, softw are,
and m athem atics we used to complete the
project.

HIGH-LEVEL OVERVIEW
As you can see in Photo 1 at the core of
our design are tw o servo m otors, a main
board containing an Atmel ATmega1284p
m icrocontroller, a three-axis accelerometer,
and a three-axis gyroscope. The
m icrocontroller board and servo m otor are
attached to an L-shaped wooden fram e th a t
enables you to hold the apparatus in different
ways. A b a tte ry pack is on the other side of the
wooden fram e. The servo m otor attached to
the main L-shaped wooden fram e controls the
pla tfo rm 's roll. Its sh a ft is d irectly screwed
into a wooden support fram e, which supports
the second servo m otor th a t controls the
pitch of the p latform . The sh a ft of the second
servo m otor is connected to a metal bracket
supporting the actual p la tfo rm th a t contains
the test camera, three-axis accelerometer,
PHOTO 1
and three-axis gyroscope.
This is the basic setup fo r o u r self-sta bilizin g p la tfo rm . The m a in board contains an ATmega1284p
When the device is switched on, the
m icro co n tro lle r w ith an AA b a tte ry pack m ounted behind the handle. A servo m o to r controls the roll o f the
pla tfo rm is initialized to the neutral position
p la tfo rm . The servo m o to r controls the pitch o f p la tfo rm . Also included are a trip le -a x is gyroscope, a trip le ­
axis accelerom eter, and a w ebcam attached to the p la tfo rm fo r testing.
(level to the ground). Using specific algorithm s
 c ircu itce lla r.co m 33

in the softw are section (we'll describe them FIGURE 1

Here you see the cam era's pitch,
later), the m icrocontroller detects any
roll, and yaw . The device controls the
changes to the platform 's pitch and roll based
p la tfo rm ’s pitch and roll.
on the outputs of both the accelerom eter and
gyroscope (see Figure 1). Upon detection of
a disturbance, the m icro co n tro lle r adjusts

FEATURES
tw o separate pulse-w idth m odulation (PWM) P itch
outputs th a t control the servo m otors'
positions, bringing the p la tfo rm back to the
neutral position.

HARDWARE DESIGN
Configuring the mechanical fram e was
one of the most challenging aspects of the
hardware design process. Since we have to
control both the platform 's pitch and roll, the
fram e has to allow a platform to freely rotate
along tw o different axes. The servo motors are
able to rotate ±90° from a neutral position, so
we make sure we have adequate clearance in all
directions. To reduce the torque and load on the
servo motors and frame, ideally, the platform
should be at the center of the system, with the
servo motors attached on different sides of the
platform . However, this is difficult to achieve
w ith our given resources. So, the servo motor
that is currently connected to the main frame
supports both the platform and the second
servo m otor (see Photol).
To connect the electronic components, we
started with soldering the gyroscope and the
accelerometer to a board on the platform. From
there, we used headers and a ribbon header cable
to connect the sensors to the main microcontroller
board (see Figure 2). Since the accelerom eter
uses the SPI protocol, is it connected to the
SPI pins in the ATmegea1284p's Port B (see
Figure 3). Since the gyroscope uses the I 2C
protocol, it is connected to the SDA and SCL
pins of Port C. The control lines of the servo
m otor are connected to the PWM outputs
of Port D, which correspond to the PWM
generated fro m Timer3.
To supply power to both the servo
m otors and the m icrocontroller board, we
used a circu it to reduce the noise between
the diffe re n t power lines through the use
of capacitors. In particular, a b a tte ry pack
containing fo u r AA batteries in series supplies
the power. The operating voltage fo r our servo
m otors was 4.8 to 6 V, while the operating
voltage fo r the ATmega1284P m icrocontroller
is 1.8 to 5.5 V. Since the b a tte ry pack outputs a
voltage of 6 V, the servo m otors could use the
power directly. From there, we added a diode
to safely supply power to the m icrocontroller,
bringing the voltage to a little more than 5 V.
W ithout the capacitors added between
the power and servo m otor control lines, the
m icrocontroller resets when the servo m otors
attem pted to make large and sudden changes
upon large p erturbations. We deduce th a t this
is the result of noise along the power lines.
So, we cu rre n tly have capacitors between the
power lines, as shown in Figure 3, to reduce
noise between the power lines of the servo
m otor, the m icrocontroller, and the control

8888888888nnnm m m n8888i

Q 0 V V V v & v Q v V v V Y V V ¥ V V V V Y V ' V Í r V v j& ' ® l^ !@, '*

m i m m n m m n n n m n n ;

FIGURE 2
The m ain m ic ro c o n tro lle r board is
m ounted on an L-shaped wooden
fra m e . The board was designee
by Professor Bruce Land a t Cornell
University.
 34 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
FIGURE 3
Take a look a t the com plete circ u it.
The accelerom eter is connected tc
the SPI in p u t pins. The gyroscope is
connected to the m ic ro c o n tro lle r's I2C
in put pins.
FEATURES
lines to the servo motor. As a result, the device
now functions sm oothly w ith o u t ever having
the m icrocontroller reset unintentionally.
SOFTWARE OVERVIEW
Our m icro co n tro lle r program is w ritte n
using the m ultitasking kernel called
TinyRealTime (TRT), which was w ritte n by Dan
Henriksson and Anton Cervin. This enables us
to achieve the concurrent execution of several
necessary tasks fo r our design.
TRT Task 1 interacts w ith the PC keyboard
to take user input. I t then set up proportional
integral derivative (PID) controller param eters
to control the servo motors.
TRT Task 2 runs the PID control loop about
50 tim es per second using x-axis and y-axis
tilt angles measured fro m another task. It
then assigns the PID calculation result to the
PWM o u tp u t to drive the servo motors.
TRT Task 3 acquires the data fro m the
gyroscope and the accelerometer. It then
calculates the corresponding x-axis and y-axis
tilt angles at about 50 Hz.
To im plem ent TRT Task 1, we used
predefined function f s c a n f ( ) to get the
input strin g fro m the UART p o rt, which is
the PC keyboard in this case. Also, tw o TRT
sem aphores, SEM_RX_IS R _SIGNAL and
SEM_STRING_DONE, are required fo r serial
com m unication. The fo rm e r is used in UART
receiving in te rru p t service routine (ISR). The
la tte r is fo r detecting w hether or not the user
typed <enter> key. A fte r getting a valid input,
we assign the input value to corresponding
variable such as PID param eters.
While this task is not necessary fo r the
actual function of the device, this enabled us
to fine-tune the default PID param eters, and
it allows the user to fine tune how fast and
steady the user wants the device to respond to
perturbations. For example, the proportional
te rm and derivative te rm can be increased
to make the design respond faster, although
this results in less s ta b ility as the m otors may
overshoot the ta rg e t position.
PID & MOTOR CONTROL
To im plem ent TRT Task 2, w hich drives
the servo m otors, we tried tw o approaches to
control the servo m otors. The firs t was direct
angle control and other was PID control, which
we u ltim a te ly settled upon. The d irect angle
control method sim ply involved changing the
PWM ou tp u t to make the servo m otor rotate
a certain angle th a t was equal in m agnitude
to the cu rre n t tilt angle and but opposite in
direction. This, however, provided less user
control than using a PID.
Our p ro g ra m 's PID co n tro l a lg o rith m is
a standard a lg o rith m provided by Cornell
Professor Bruce Land (ECE 4760: Laboratory
4 —"T achom eter and M otor C ontroller,"
2013). The m o to r is m odeled as a second-
o rd e r system w hen it's powered and a fir s t­
o rd e r system when it's c o a stin g. In th is
a lg o rith m , we use the calculated p itch and
roll angles as the feedback to the PID. The
a lg o rith m 's core is the fo llo w in g line o f code
in the pro g ra m :
m _ in p u t = p i d _p * c _ e r r o r + p i d _i
* p id _ in t e g r a l / 1000 + p i d_d *
(c _ e rro r - c _ e rro r_ p re v );
P id _p, p i d _i , and p i d _d are the
PID param eters fo r the proportional term ,
integral term , and derivative term . C _ e r r o r
 c ircu itce lla r.co m 35

is the difference between cu rre n t tilt angle m axim um 180° rotation.

and desired angle, w hich is level. c _ e r r o r _
p r e v is the previous tilt angle fro m the last
PID cycle. p i d _ i n t e g r a l is the integral of
the previous e rro r term s.
To achieve sm oother leveling of the
READING DATA
For TRT Task 3, we obtained data fro m the
accelerom eter and gyroscope. We used is an
Analog Devices ADXL345 low-power, three-

FEATURES
p la tfo rm , we made some m odifications to the axis accelerometer. We used the standard
original algorithm . First, we put a lim it on the SPI protocol to com m unicate between the
integral te rm 's m axim um value to prevent accelerom eter and the m icrocontroller. To
instabilities when the integral changes sign. read and w rite to the ADXL345 accelerom eter's
We also scaled the integral te rm by 1,000- registers, we utilized and modified code
fold sm aller to make the p i d _i param eter provided by SparkFun. To convert the raw
easier to input. In addition, we introduced data to angular acceleration, we use the
an additional variable, SCALE, to scale the follow ing equation:
m axim um value of the to ta l PID calculation
result m _ in p u t to control the change rate of
the control PWM signal. Finally, the calculation
result is mapped to the PWM o u tp u t control
registers OCR1A and OCR1B, w hich output
to the m icrocontroller's pin D4 and D5,
respectively.
To d e te rm in e the e xa ct value fo r the
PWM o u tp u t, we had to vie w the specs
fo r o u r p a rtic u la r servo m o to rs , FEETECH
m odel FS5106B servo m o to rs purchased
fro m S parkFun. In p a rtic u la r, the c irc u itry
o f the servo e xpects a c o n sta n t 50-H z PWM
signal (p eriod o f 20 ms). The actual in p u t
we send the servo is th e w id th o f the high
sig n a l d u ra tio n in the w hole p e rio d . As
show n in Figure 4 , the w id th o f the high
sig n a l d e te rm in es the p o sitio n o f the servo
co rrespo nd ing ly.
Since th e p ro p e r fre q u e n c y fo r the PWM
signal is 50 Hz, we could n o t use the fa s t
PWM m ode, w hich generates a v e ry h ig h -
fre q u e n cy signal. So, we decided to use
th e Phase and Frequency C orrect m ode o f
T im e r1. Only T im er1 and T im er3 s u p p o rt
th e Phase and Frequency C orrect m ode and
have 1 6 -b it tim e rs . Since T im e r3 o u tp u ts
its PWM to Ports B3 and B4, w hich the
a ccelerom eter needed fo r the SPI pro to co l,
we use T im er1 fo r the Phase and Frequency
C o rrect m ode. T im er3, in the m e a n tim e , is
used fo r the TRT kernel.
In Phase and Frequency Correct mode,
we firs t set the Prescaler value, N, to 8, and
we then calculated our ICR1 (In p u t Capture
Register 1 = TOP) register value fro m the
equation below.

f PW M
2 x N x TOP

A fte r we set the ICR1 (TOP) value to

20000, the PWM frequency is 50 Hz. The
OCR1A register value determ ines the w idth
of the high signal. We can v a ry OCR1A from
1000 to 2000, which should correspond to 10-
and 20-m s signal w idths, respectively. For our
p a rticu la r servo m otor, we use m ore extrem e
values fro m 770 and 2300 in order to get the
e$>resspcb.com
 36 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

I 2C protocol to com m unicate between the

gyroscope and m icrocontroller. Once again, to
read and w rite to registers of the ITG-3200
gyroscope, we utilized and m odified code
provided by SparkFun.
The gyroscope's ou tp u t is degrees per
FEATURES

second. To translate this into degrees, we

can integrate the gyroscope data over tim e
provided the frequency is high enough. So,
we used the following equation to convert the
raw data to angular acceleration:

14.375 LSBs per (

AngularAcc = rawData x
s

To fu rth e r reduce noise in our

FIGURE 4
This is a servo m o to r PWM tim in g 8 LSBs
dia g ra m and the corre sponding angle Acc = raw Data x —— -------
2 g
o f shaft position. The period is 20 ms
and pulses v a ry fro m around 1 to 2
In addition, to determ ine the pitch and
ms.
roll of the p la tfo rm , we used the following
equations:
0X = tan 1
While the accelerom eter alone can
determ ine these angles w ith o u t the aid of
a gyroscope, it is ra th e r noisy when used
to measure the gravitational acceleration,
especially when the pla tfo rm moves back
and fo rth . So, we also decided to include
a gyroscope, which, if used by itself, will
produce readings th a t d rift over tim e.
We used an InvenSense ITG-3200 trip le ­
axis gyroscope. We used the standard
ABOUT THEAUTHORS
Evan Chen (e c 4 8 8 @ c o rn e ll.e d u ) s t u d ie s E le c tric a l a nd C o m p u te r E n g in e e r­
ing a t C ornell U n iv e rs ity . M ost o f his w o r k e x p e rie n c e has been fo cu sed on
d ig ita l e le c tro n ic s , b u t he re ta in s a b ro a d in te re s t in a v a rie ty o f e n g in e e r­
in g -re la te d areas.
Zequn Huang (h u a n g z e q u n .c h in a @ g m a il.c o m ) s t ud ie d E le ctrica l E n g in e e rin g
a t P ennsylvania S ta te U n iv e rs ity and is c u rre n tly p u rs u in g a M a ste r's degree
a t C ornell U n iv e rs ity . A lth o u g h Zequn m a in ly focuses on e m b e d d e d syste m s
d e sig n , he has c o m p le te d m a n y d ig ita l and an a lo g c ir c u it designs.
Jia n g lu (G eo ra ld ) Xu (g e o x x u @ g m a il.c o m ) is p u rs u in g a M a s te r's d e g re e a t
C o rn e ll U n iv e rs ity . He is c u r r e n tly fo cu se d on e m b e d d e d a p p lic a tio n s and
c o m p u te r a rc h ite c tu re . He is also w o rk in g on a s ta r t- u p p ro je c t focused on
a W i-F i re m o te c o n tro lle r a nd is se eking co o p e ra tio n .
m easurem ents, we also sample m ultiple
readings fro m the gyroscope and the
accelerom eter. However, w ith our initial
tests, we were sam pling too m any readings,
w hich negatively im pacted the speed of our
device. In particular, we were averaging eight
samples of the gyroscope m easurem ents and
eight samples of the accelerometer. With this
am ount of in te g ra tio n , we observed th a t the
m otors w ere visib ly a djusting at discrete
intervals, resulting in a v e ry jitte r y response.
The m otors seemed to a d ju st about tw ice
a second. This occurred since our TRT Task
3 was unable to meet the deadline th a t we
set. In particular, to com pute the angles
fro m the gyroscope, the m icro co n trolle r runs
many com putations on long integers, so we
reduced the num ber of samples to tw o for
the gyroscope and fo u r fo r the accelerometer.
W ith these new values, functions were able to
be executed much m ore frequently, resulting
in sm oother transitions.
In order to combine the data fro m the
gyroscope and the accelerom eter, we looked
into tw o d iffe re n t m ethods—using a Kalman
filte r and using a com plem entary filte r.
The Kalman filte r operates by producing a
s ta tis tic a lly optim al estim ate of the system
state based upon the m easurem ents. To do
th is it needs to know the noise of the input
to the filte r, w hich is called the m easurem ent
noise, and it needs the noise of the system
itself, w hich is called the process noise. To do
this, the noise has to be Gaussian distrib uted
and have a mean of zero. For us, m ost of the
random noise in our m easurem ents has this
characteristic.
The a lg o rith m fo r the Kalman filte r is
ra th e r com plicated, but the code fo r the
Kalman filte r fun ctio n can be broken down
into the follow ing fo u r steps in a loop:
■ Update estim ation e rro r covariance and
project the e rro r covariance ahead.
■ Calculate discrete Kalman filte r
measurem ent update equations and
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 38 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

calculate Kalman gain.

■ Calculate angle and bias and update estim ate w ith m easurem ent in k state.
■ Calculate and update estim ation e rro r covariance.

The original Kalman filte r code we used was fro m SparkFun. We modified it to suit our
m icrocontroller and sensors.
FEATURES

COMPLEMENTARY FILTER
The com plem entary filte r provides another way to combine diffe re n t sensor data and it is
much easier and more intuitive. In fa ct, this filte r manages both high-pass and low-pass filte rs
sim ultaneously. The low pass filte r filte rs high frequency signals (such as the accelerom eter in
the case of vibration) and low pass filte rs th a t filte r low frequency signals (such as the d rift of
the gyroscope). In its sim plest fo rm , the filte r looks as follows:

filte rA n g le = 0 .9 8 x (previousA ngle + gyrD ata x d t )

+ 0 .0 0 2 x accData

The com plem entary filte r we used in our program is a second order filte r w hich is more
complicated. The a lg o rith m looks like PID and is given as follows:

e r r o r T e r m = (n e w A n g le - p r e v io u s A n g le ) * k * k
i n t e g r a lT e r m = in t e g r a lT e r m + e r r o r T e r m * d t
PIDTerm = i n t e g r a lT e r m + (n e w A n g le - p r e v io u s A n g le ) * 2 * k + n e w R a te
f i l t e r A n g l e = PIDTerm * d t + p r e v io u s A n g le

PROJECT FILES
circ u itce lla r.co m /ccm a te ria ls
RESOURCES
S. C o lto n , "T h e B alance
F ilte r,” 20 07, h t t p : / / b i t .
ly /1 jL r9 O Z .
B. Land, "A P re e m p tiv e Kernel
fo r A tm e l M e ga12 84 M ic ro ­
c o n tro lle rs ,” C orn ell U n iv e r­
s ity , 20 13, h ttp ://p e o p le .e c e .
c o rn e ll.e d u /la n d /c o u rs e s /
e c e 4 7 6 0 /T in y R e a lT im e /in d e x .
h tm l
---------, "ECE4760: Laboratory 4 -
Tachom eter an d M o to r C on­
tro lle r,” C orn ell U n iv e rs i­
ty , 2 0 1 3 , h ttp ://p e o p le .e c e .
c o rn e ll.e d u /la n d /c o u rs e s /
e c e 4 7 6 0 /la b s /f2 0 1 3 /la b 4 .
h tm l.
k is the tim e constant. d t is the derivative constant. n e w A n g le is the tilt angle calculated
Le tsM a ke R o b o ts.co m , "K a lm a n f ilt e r vs C o m p le ­
m e n ta r y F ilte r,” 20 11, h ttp ://le ts m a k e r o b o ts .
c o m /n o d e /2 9 1 2 1 .
S p a rkF u n , " T rip le A x is A c c e le ro m e te r B re a k o u t
- A D XL345,” 20 13, h ttp s ://w w w .s p a r k fu n .c o m /
p ro d u c ts /9 8 3 6 .
--------- , "T rip le -A x is D ig ita l- O u tp u t G yro -
scop e— IT G -3 2 0 0 ,” h ttp s ://w w w .s p a r k fu n .c o m /
p ro d u c ts /9 7 9 3 .
SOURCES
ADXL345 A c c e le ro m e te r
A nalog D evices, In c . | w w w .a n a lo g .c o m
A T m ega1284p M ic ro c o n tro lle r
A tm el Corp. | w w w .a tm e l.c o m
ITG -3200 T rip le -A x is D ig ita l-O u tp u t G yroscope
S ervo— G eneric High Torque (S tandard Size)
SparkFun (d is trib u to r) | h ttp s ://w w w .s p a rk fu n .
c o m /p ro d u c ts /9 7 9 3
fro m the accelerometer. n e w R a te is the
angular acceleration calculated from the
gyroscope. In our code, we made several
m odifications to this a lg o rith m to make the
tilt recovery process faster. We introduced a
variable to control the p ro portion of n e w R a te
in P ID Term . We also scaled e r r o r T e r m in
i n t e g r a lT e r m to make it proportional to
the n e w R a te .
We cu rre n tly use the com plem entary
filte r to calculate the tilt angles because
the result fro m the com plem entary filte r
was v e ry close to the one calculated by the
Kalman filte r. Also, the com plem entary filte r
is m ore m icro p ro ce sso r-frie n d ly because it
requires a small num ber of flo a tin g -p o in t
operations.
PERFORMANCE
With our default PID settings, we see
relatively fa st and smooth transitions. The
m otors can tra n sitio n fro m -9 0 ° to 90°
w ith in 1.2 s. We can decrease the tra nsition
tim e by increasing the proportion term and
the derivative term . However, this results
in rougher tra n sitio n s, and the platform
w ill som etim es oscillate as a result of
overshooting the ta rg e t position. In any case,
it is possible to reduce the response tim e,
and the theoretical m inim um response tim e
seems to be lim ited by the slew rate of the
motors.
While the p la tfo rm rem ains in a relatively
neutral position, the p la tfo rm occasionally
oscillates back and fo rth . This e rro r seems
to be caused by m ultiple sources. On the

softw are side, since we had to reduce the
num ber of samples taken fro m the gyroscope
and accelerometer, accuracy suffered where
we saw variations in angles of about a degree
or two. In addition, on the hardw are side, the
bearings on the m otor th a t controls the roll of
the platform became a b it loose. In particular,
its sha ft is directly connected to a wooden
support th a t holds the w eight of the second
m otor and the entire platform . A fte r many
tria ls and tests, the rather heavy loads that
we had placed on it have probably caused the
bearings to loosen. Combined, these sources
of e rro r make the pla tfo rm v a ry at around
±2.5° from the neutral position.
When tested w ith a webcam, the platform
kept the video oriented in the landscape
position as we tilted the apparatus to the
extrem es of ±90° in both roll and pitch.
However, when the device was held in place
w ith o u t any perturbations, due to the sources
of e rro r mentioned previously, the platform
would continue to adjust its position up to
±2.5° fro m the neutral position.
Overall, the self-stabilizing pla tfo rm works
as expected. However, while it is able to keep
a camera oriented in a relatively neutral
4 lk
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c ircu itce lla r.co m 39
position, it experiences slight vibrations. So,
while it can be suited to taking steadier action
video shots, it is not as suited to taking still
pictures, and many im provem ents can be
made, especially on the hardware side.
For example, to reduce the load on the
FEATURES
shaft of the m otor controlling the roll, we can
distrib u te the load by adding another support
panel having a second point of contact on the
opposite end of the motor. In addition, instead
of m ounting the gyroscope and accelerom eter
on top of tw o separate pin socket connectors,
we can tr y placing both together flush against
the platform . This may help increase accuracy
in the angle calculations. Of course, if budget
was not an issue, m otors w ith b etter torque
and slew rates can be used instead. A larger
and more refined p la tfo rm can also be
attached so th a t it can hold a larger v a rie ty of
cameras and objects.
Authors' Note: Full code is available on Circuit
Cellar's FTP site. The code and further details
are also available at http://bit.ly/1mLH4MX. A
video demonstration o f our camera stabilizing
platform is also available at http://bit.
ly/lqRYtZJ.
 40 C IR C U IT CELLAR • SEPTEMBER 2 0 1 4 # 2 9 0
^ ----------*--------------------------------

DIY RGB Game Desi

An Upgrade for a Classic Platfor
FEATURES

IS

Since the 1960s, engineers and electronics enthusiasts have

been building electronic versions of the Tic-tac-toe game.
This article details a recent iteration of one engineer's
electronic system. It's a microcontroller-based design that
drives matrix LED displays.

By Mitch Matteau (US)

I 've always been fascinated by the sim p licity
of Tic-tac-toe (or "Noughts and Crosses").
About 40 years ago, Popular Science published
the a rticle , "E lectronic Tick-Tack-Toe in a
Cigarette Box," which detailed an interesting
electronic version of the classic game. Since
then, I've designed a few variations of that
electronic system. In this article, I'll present
my m ost recent version. I'll explain how
I brought the game to life w ith a modern
upgrade—a red-green-blue (RGB) 8 x 8 LED
m a trix display.
My original interpretation of the Popular
Science game was based on a 40-pin DIP
Motorola 68HC705C8A m icrocontroller and
bipolar LEDs. The green wires shown in
Photo 1 go to off-board push-button switches.
The controller was atypically mounted on the
solder side of the PCB. And you'll probably
notice th a t the single-sided PCB was drawn
out freehand and m anually etched. Ah, the
good old days! The software counter-move
algorithm used in th a t version was based
on the one described in the original Popular
Science article. That same algorithm was
ported to the newer m icrocontroller fo r the
current im plem entation, which saved a bit of
coding tim e. I'll explain th a t algorithm later on.

Photo 1
This design, b u ilt in the 1980's, usee
a 68HC705C8A m ic ro c o n tro lle r
b ipola r LEDs to d ire c tly in te rp re t the
o rig in a l gam e a lg o rith m .
SYSTEM OVERVIEW
The latest incarnation of the game is
shown in Figure 1 . The heart of the design
is a Freescale Sem iconductor HC908JB16
(U1) m icrocontroller, which I chose fo r a few
reasons. One, I've been coding Freescale
processors in assem bler fo r years, and I'm
com fortable w ith Freescale devices and
softw are tools. Two, this p a rticu la r va ria n t
includes a sim ple USB interface fo r in -circu it
program m ing (ICP). And three, there were
ane
enough p o rt pins available to connect to the
in p u t/o u tp u t peripherals, requiring only a
small num ber of outboard devices.
 c ircu itce lla r.co m 41

FEATURES
Surrounding the m icrocontroller are the Products DS2408 used as the keyboard input. Figure 1

interface components. M icrocontroller U1 port Port D also dire ctly interfaces to SW5, which This is the RGB T ic -ta c -to e gam e's
c irc u itry . A Freescale 68HC908JB16
A dire ctly drives the display rows. U1 p o rt E is used as the center switch of the Tic-tac-toe
(U1) is the h e a rt o f the gam e.
drives U2, U3, and U4, which are 74HC595's game as well as the control mechanism fo r
used as display column drivers. Port E also ICP during reset. U1 Port C is used only fo r a
serves as the USB interface, which is needed debugging serial interface; it isn 't used in the
fo r ICP. U1 p o rt D provides the 1-Wire final product. U1 does not have a p o rt B in the
interface to U5, which is the Maxim Integrated package style th a t I selected.

* P a ra m e te r E q u a te s
ICP_FLAG EQU $F7FE ; ICP f l a g
o

GO
^ *

CÛ

EQU $FA19 ; M o n ito r USB ICP r o u t in e s

_

_I
C
P

* M ain P rog ra m
*
ORG $F800 ; h a rd - c o d e d lo c a tio n fo r th is r o u t in e
I C P _ R e s e t _ I n it :
BCLR 3,DDRD ; s e t PTD,3 as i n p u t ( i . e . , use SW5 f o r th is app)
BRCLR 3,P T D ,U S B _IC P ; e n t e r ICP i f s w it c h i s p re s s e d
jm p RESET ; e ls e jm p t o th e a p p l i c a t i o n p ro g ra m
*
* USB ICP
*
USB_IC P :
sei ; d i s a b le i n t e r r u p t s
mov #% 00000011,C 0N FIG ; e n a b le STOP and d i s a b le COP
mov #% 00000100,UCR3 ; e n a b le USB p u l lu p
jm p Mon_USB_ICP ; c h e c k f o r new f l a s h p ro g ra m

LISTING 1
This is the Power-On ICP check A s im ple check fo r SW5 being depressed (logic zero) is m ade a t pow er-on tim e , and the re s u lt dete rm in e s w h e th e r or n o t to enter ICP m ode,
w h ich is a call d ire c tly in to the m ic ro c o n tro lle r's fa c to ry ROM code
 42 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 C
Figure 2
As you'd expect, the m ain gam e
a lg o rith m is s tra ig h tfo rw a rd . W ait
fo r a m ove fro m the player, check
fo r a cou n te r-m o ve , see if the gam e
outcom e has changed, and then do it
FEATURES
again.
I chose the DS2408 as a keyboard interface
because it offers a ve ry simple processor
connection, only one p o rt pin, and I have a
ve ry extensive softw are lib ra ry th a t I have
developed over the years fo r interfacing to
1-Wire devices. The 74HC595's were ideal
fo r driving each color of the display columns
w ith only a th re e -w ire interface required to
com m unicate w ith all of them . A fo u rth pin
fro m p o rt D is used to reset the 74HC595s and
the DS2408 during power-on.
Nine input switches are available, one
fo r each position of the Tic-tac-toe display.
The DS2408 decodes eight of them , and, as
I mentioned previously, the center switch is
connected dire ctly to a m icrocontroller port
pin. The bootloader also uses the center
switch to determ ine if Normal mode or In ­
Circuit Program m ing mode is required.
The ICP circu it comprises SW5, the USB
connector, J1, capacitor C4, and the tw o
470-kQ resistors, R2 and R3. Except for
a 12-MHz crystal, w hich is required for
proper tim in g of the USB interface, no other
components are required fo r ICP. A Windows
XP program , provided by Freescale, handles
the flash m em ory program m ing. ( If anyone
can provide me w ith a w orking Windows 7
v a ria n t of this softw are, I w ill gladly donate
a w orking Tic-tac-toe game!) Power-on reset
capacitor C4 is an absolute necessity fo r ICP
as it handles the processor's reset circuitry.
When firs t sta rtin g to use this controller, I left
out the reset capacitor, but soon found out
th a t the controller would not always boot into
ICP mode properly w ith o u t it.
Listing 1 shows the s im p lic ity of the ICP
softw are interface. As stated in the Freescale
application note AN2399: "Routines embedded
in the m onitor ROM area ($FA00-$FDFF and
$FE10-$FFCF) are available to s im p lify the
ICP process. A USB com m unications handler
is already in the m onitor ROM."M The code
shown in Listing 1 makes use of those built-in
m o n ito r ROM routines a fte r checking fo r the
request fo r ICP. This check is done at power-
up by looking at switch SW5's state. If SW5 is
depressed during the power-up process, the
ICP m onitor ROM code w ill be entered. If it
is not, norm al program code is entered. By
chip design, if the program flash m em ory is
blank, the ICP m onitor code w ill be entered
im m ediately at power-up, which is handy for
a surface-m ounted device.
The last m ajor com ponent is, of course,
the RGB m a trix display, DS1. I found mine
on the In te rn e t. Others are readily available
fro m a v a rie ty of sources.
I added a piezo beeper SP1 to provide
some feedback on key entries and w ins/
losses. The USB connector J1 is used as the
power interface to the circu it, as well as the
program m ing interface. Since 5-V USB power
adapters are so common and inexpensive
these days, I was able to s im p lify the power
circuit.
 c ircu itce lla r.co m 43

The prototype o riginally included a header Table 1

C o u n te r Take a look a t the o rig in a l Po p u la r
J2 th a t brought out the TXD and RXD signals M ove N o te
M ove S cien ce a lg o rith m . This is a sim ple
from the m icrocontroller. This was tied to a
look-up table w ith one c o n stra in t: the
plug-in TTL-to-USB converter—which allowed Mandatory
1 5 fir s t move m u s t be in position 1.
a serial connection from a PC—and was wired starting move
on the PCB so it could be connected to a 2 3

FEATURES
serial-to-USB "frie n d ." I used this interface
extensively during the softw are debug 3 2
process, but it is not required in the finished 4 7
product. Counter-move to
5 N/A the m andatory
FIRMWARE
starting move
At sta rt-u p , follow ing the ICP check, a
sequence is entered th a t resets the peripheral 6 8
devices, sets up all m icro co n tro lle r registers, 7 4
and then displays a "W elcom e" message that
8 6
scrolls across the LED m a trix display. A simple
flash pattern of Xs and Os is then shown. That 9 8
was o rigin ally put in the code as a lamp test
feature. It could have been deleted, but I left
it in fo r the nice effect.
Figure 2 shows firm w a re 's main loop. The
code is extrem ely linear and sim ple since I 1 2 3
wanted to finish the project fa irly quickly. In
Table 2
the flow diagram , the player is G (green) and
This is the w a y th a t the softw are
the softw are is B (Blue). 4 5 6
in te rp re ts the position o f any move.
The softw are continuously scans fo r a All moves m ade are m apped into
key press. Once any key has been pressed, a th is fo rm a t before checking for
check is made to see if the pattern indicates 7 8 9
counterm oves.

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 44 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
PHOTO 2
a —Take a look a t the final p ro d u c t ir
its case, w h ich is the b o tto m half o f a
standard PacTec case. b—This is the
com pone nt side o f the fin a l product.
FEATURES
a w in by the player. If not, a response is
calculated and, a fte r an intentional 1-s
delay, the counter-m ove is presented. If a
w in, loss, or draw occurs, a corresponding
"W in", "Loser," or "D ra w " message is scrolled
across the display and the program resets all
registers, a fte r which it returns to a known
sta rtin g point.
The counter-m oves are calculated in two
d iffe re n t ways. The firs t is the sim plest. If the
sta rtin g move is a corner square, a table look­
up is perform ed. This table is based on the
a lg o rith m used in the original Popular Science
article. That a lg o rith m requires a corner
sta rtin g move and was devised by the original
authors to p e rm it a w in by the player every
now and then, although not as often as the
player would like! A draw is by fa r the more
likely outcome.
The second method checks fo r counter­
moves to a sta rtin g move in either the center
(logic tree 1) or an edge (logic tree 2). This is
a simple state check of each move based on
the h isto ry of moves up to this point. Counter­
moves are designed to force a draw or loss
whenever possible. There are some moves
th a t cannot be countered easily. Those are left
to you to determ ine.
Each move, either by the player or by the
controller, is recorded in an array. That array
is used by the second method to check for
the next best move. The a rra y is also kept by
the firs t method (table look-up); however, it
isn 't used to calculate a counter move. The
table look-up method is stateless and does
not require the program to understand w hat
moves have already been made, except to
determ ine if a w in, loss, or draw has occurred.
Table 1 shows the counter-m oves fo r the
table look-up method. Note th a t there is no
counter-m ove fo r a center square. The original
authors did this in tentionally since they
required the firs t move to be a predeterm ined
corner, position 1 in Table 1 and Table 2, and
the counter-m ove fo r th a t was the center.
Table 1 is quite ingenious. I commend the
original authors fo r the s im p lic ity caused by
forcing the firs t move. I have only adapted
th a t a lg o rith m to allow fo r any corner to be
equivalent to a move fro m position 1.
THE HARDWARE
I chose to im plem ent this game on a
custom PCB, w hich let me use surface-m ount
com ponents fo r the m ost part. This kept the
game small enough to be hand-held.
The PCB was sized to fit into a standard
PacTec enclosure, which I happened to have
on hand. Only half of the enclosure is used fo r
sim plicity.
The interesting aspect of the PCB design is
th a t the com ponent side was used fo r all the
surface-m ount and th rough-hole components;
however, the solder side was designed to
p e rm it the m ounting of the display and
switches. I did this to keep the visible portion
of the game as clean as possible. This made
fo r an interesting exercise in m irro rin g the
pinouts of the display m a trix while designing
the PCB, but th a t d id n 't take too long.
Photo 2a shows the final product in its
case, which is the bottom half of a standard
PacTec case. In the tim e I had, coming up
w ith a clean way to have the display visible
w hile still allowing the switches to be pressed
prevented the use of a full case. Photo 2b
shows the component side of the final product.
THEORY OF OPERATION
My game's operation is simple. A player
always begins w ith X and is represented
by green LEDs. The Player presses a switch
(any switch) and then chases the Os (blue
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 46 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
Figure 3
There are only thre e possible s ta rtin g
m oves if you e lim in a te s ym m e tric a l
ones: the center, a co rn e r, and an
edge.
FEATURES
PROJECT FILES
c irc u itce lla r.co m /ccm a te ria ls
REFERENCES
[1] D. Lau, "In -C irc u it Program ­
m ing o f FLASH M em ory via the
Universal Serial Bus for the
MC68HC908JB16,” AN2399, Frees­
cale Semiconductor, 2003.
LEDs) around the game. There is nothing to
configure, and no options to pick.
How does this all work? Well, the game
th e o ry is p re tty stra ig h tfo rw a rd . Let's look at
some details.
First, you need to know the total number
of the game board's possible variations.
According to W ikipedia, there are 255,168
total combinations of the game, 51% of
which are wins by sta rtin g player and 31%
of which are wins by the second player.[2] The
rem ainders are draws. However, this includes
all possible states. According to the same
post, if sym m etrical moves are removed
(i.e., moves th a t are the same if the board is
rotated 90°, 180°, or 270°), then this leaves
only 26,830 possible com binations. Whew!
That still seems like a lot. However, these can
[2 ] W ik ip e d ia , "T ic-T a c-T o e ,” h tt p ://e n .w ik ip e -
d ia .o r g /w ik i/T ic - ta c - to e .
RESOURCE
B. B a w e r and W. J. H aw kins, "E le c tro n ic T ic k -
Tack-Toe in a C ig a re tte B ox,” Popular Science,
D e c e m b e r 1970.
SOURCES
HC908JB16 Microco ntroller
F reescale S e m ic o n d u c to r, In c . | w w w .fre e s c a le .
com
DS2408 1-Wire Switch
M a x im In te g ra te d | w w w .m a x im in te g r a te d .c o m
be broken down even fu rth e r if you elim inate
w hat I call "stupid moves." Those would be
moves th a t lead to an easy win by either
player. Non-stupid moves are w hat I deemed
to be moves by both players playing to win.
There are only three possible startin g
moves if you elim inate sym m etrical ones: the
center, a corner, and an edge (see Figure 3).
Since I chose to use the original authors'
a lg o rith m (see Tables 1 and 2) fo r a corner
s ta rtin g move, this left me w ith the design
of an a lg o rith m to counter center and edge
s ta rtin g moves. According to the original
a lg o rith m , only a sta rtin g move fro m a corner
was perm issible, w hich was another reason
to develop algorithm s fo r the other startin g
moves. In Table 1, the only perm issible
s ta rtin g move is fo r position 1. (Refer to Table
2 fo r the num bering of each position in the
Tic-tac-toe m atrix.) In softw are, however, we
can rotate the board so th a t sta rtin g moves
in position 3, 7, and 9 are all equivalent to a
s ta rtin g move of 1.
A fte r spending hours analyzing the many
possible game com binations, I determ ined
th a t numerous com binations could be
elim inated by rem oving "stupid moves"
and by try in g to force the player (X) to
play where the com puter (O) could either
w in or draw. Empirically, this le ft me w ith
a small com bination of moves to inspect
fo r center s ta rts and to inspect fo r edge
s ta rts. In softw are, I determ ined th a t these
com binations could easily be checked via a
sim ple look-up, check, and branch routine.
Counter-moves th a t would tr y and force a
loss or draw at each X player's move were
devised fo r each com bination and hard-coded
in to the routines. Since each successive move
determ ines the type of inspection to make fo r
the next move, a move h isto ry table is used
as p a rt of the look-up, check, and branch
softw are. The hard-coded responses fro m my
study then become the counter-moves.
Moves th a t are not on my list of em pirical
com binations are sim ply ignored and a sort
of random counter-m ove is provided in their
place. This is probably the best way fo r X to
w in since these random counter-m oves don't
account fo r any strategy. Of course, I w on't
reveal those moves.
OTHER OPTIONS
When o rig in a lly designing my electronic
game, I had aspirations to use 1-Wire devices
th ro u g h o u t fo r the interfaces to the display
and keys. However, a fte r building the firs t
prototype, which used all 1-Wire devices, I
p re tty quickly proved th a t the 1-Wire protocol
is ju s t too slow fo r m ultiplexing 64 LEDs. If
I had spent more tim e analyzing the 1-Wire
tim in g , I would have known th a t and saved

m yself a redesign and PCB layout change.
Lesson learned: read the freaking manual
(RTFM). That oversight led to changing the
column drivers from DS2408s to 74HC595s.
The HC595s are driven w ith a 3-m s in te rru p t
to keep the flicker of the display to a m inim um .
1-Wire tim ing is ce rta in ly fa st enough to
detect switch presses, so I le ft a DS2408 in as
the keypad scanner.
What I did not th in k through ahead of tim e
was th a t the LEDs' forw a rd voltage varies
so much between the colors of the chosen
8 x 8 m a trix display (from 1.9 to 3 V). This
difference leads to the dim m ing of green LEDs
in a row th a t also has red LEDs on. Use of
a constant cu rren t supply, such as provided
w ith a MY9221 or MY9268 fro m MY-Semi
m ig ht have been an option; however, the tim e
I had available and the space available on the
PCB did not p e rm it the lu xu ry of such a m ajor
change to the circuit. Thus, I changed the
color scheme fo r the game fro m green and
red to green and blue, because the blue and
green LEDs have sim ila r fo rw a rd voltages.
The red LEDs are still used fo r te x t o utput
since there is only one color used fo r text.
I had o riginally planned on using a
standard USB-B connector fo r this design, but
it was so large (relatively) th a t it prevented
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c ir c u itc e lla r .c o m
@circuitcellar
□ @editor_cc ^ T circuitcellar
c ircu itce lla r.co m 47
a proper fit in my available enclosure. That
resulted in changing the standard USB-B ABOUT THE AUTHOR
connector to a m ini-B type of connector. M it c h M a t t e a u ( m it c h @
The beeper th a t I had on hand was also a midondesign.com) founded
physical problem . The PCB size did not leave Midon Design, a co mpany
me w ith enough space to m ount it on the
t h a t p ro v id e s h o b b y is ts
FEATURES
solder side, and the available vertical space
w it h 1-W ire control solu ­
w asn't enough to m ount it on the component
tio ns. He holds a Bache­
side. So, I squeezed the connection into a
lo r's o f Ap p lie d Sciences
spot on the com ponent side and extended the
f rom O ttawa University in
connection via w ires. Adding a b it of length
Ottawa, Canada. Mitch en­
to the PCB would have left me the space I
joys both th e h a rd w a r e -
needed to add the beeper below or beside the
switches. Of course, this would've resulted in and s o ftw a re -re la te d
an enclosure change, but th a t w ould've been a s p e c ts a s so c ia te d w i t h
easy enough if planned ahead. d e s ig n in g embedded
Lastly, if I'd had m ore tim e, I could've devices.
designed the softw are m ore elegantly—that
is, the look-up, check, and branch routines
could have been contained w ith in a routine
accessing a look-up table or group of tables.
RESULTS
Modernizing my original m icrocontroller
design was a lot of fun and the resulting game
looks p re tty nice. Hopefully, this a rticle and
the accompanying softw are w ill help you
understand a b it about the game th e o ry and
driving m a trix LED d is p la y s .©
F la s h P r é 43Û
flash P ro -C C
F Ia sh P ro 2 0 0 0
C a n g P ro 4 3 0
m n
G a n g P rO rC C
U S B FSash P r o g ra m m e r s f a r T e x a s I n s t r u m e n t s ' M C iJs
M S P 4 3 0 , C h i p c o n C C x k , C ÏO O O D S P s
N r l t a h k - j i i i d llu - ta s tc s l f ir o ji i u iiiiiil t u n I ht- n i : i r k i : ï ,
P e r f i T r f u r p r o d u c t io n u s ^ l 1.
■ca n a s s ig n u n iq u e se ria l n u m b e r
up to eight programmers can be connected to one
PC a n d pnewjram ta rg e t d e v ic e s s im u lta n e o u s ly
J T A .fi i £ Ë W
Of KL
On* Pi- «tld
B pi u ÿ iM iit m t
ElproLronic
wwwelprotroniacom
 48 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 * # 2 9 0
GREEN COMPUTING
Pooling Microarchitectural
Resources
Towards Flexible Heterogeneity
3-D stacking enables novel ways of "resource
COLUMNS
pooling" in a processor owing to the short wiring
distances among the layers in the stack. This
article investigates how pooling microarchitectural
resources intelligently across applications improves
energy efficiency.
By Ayse K. Coskun (US)
M a jo rity of com puting system s today
include m ulticore processors. These
m ulticore systems typ ica lly include
"hom ogeneous" set of cores, meaning that
all the cores w ith in the processor are of
the same kind and have the same size and
types of m icroarchitectural components. In
addition, in such homogeneous system s, the
external resources given to each core, such as
the L2 caches or ne tw o rk interfaces are also
typ ica lly identical.
While such sym m etrical homogeneous
m ulticore design provides ease of circu it
design, placement, and routing, there are
potential lim ita tio n s as well. First, resources
on a m ulticore system are often under-used as
the systems are not necessarily designed fo r
the typical or average use case, b u t instead
they are designed w ith some "he a d ro o m "
considering th a t some applications may need
a larger am ount of resources. This headroom
indicates over-design such as placing a large
am ount of on-chip cache th a t may be under­
utilized fo r a significant portion of the time.
Obviously, over-design increases the area and
power costs.
Over-design is less of an issue when a
m ulticore a rchitecture is highly optim ized for
a specific application, such as in the case of
an embedded processor th a t is responsible of
perform ing a few tasks only. Most systems
today, including many embedded systems,
however, run a v a rie ty of tasks throughout
th e ir lifetim e. In addition, applications often
have d iffe re n t phases (e.g., a single application
may go through a num ber-crunching phase
th a t is heavily using the a rith m e tic units
a followed by a m em ory-intensive phase
including lots of reads and w rites to /fro m
caches and memory).
Overall, different softw are applications, or
different tasks w ithin an application, thrive
(i.e., achieve high performance) under different
architectural configurations. For example, one
application may benefit from a larger L2 cache
while another one may not need much cache
space and instead may operate better w ith a
larger instruction issue queue.
Considering most systems are
homogeneous by design but run a
heterogeneous set of applications, how can
we design efficient architectures th a t can
provide desirable perform ance and power
tradeoffs fo r a v a rie ty of applications?
One approach is to design the processor in
a heterogeneous way, such as by employing
d iffe re n t cores in the same chip (e.g., ARM's big.
LITTLE architecture) or by including GPUs or
accelerators along w ith a set of homogeneous
CPU cores (e.g., AMD's APU systems).
(Note th a t alm ost all processors include
heterogeneity as they include many d iffe re n t
components. Here heterogeneity specifically
refers to including d iffe re n t types of cores in
a m ulticore processor.) Heterogeneous design
has its challenges, too, as it may bring higher
design com plexity and potentially longer
tim e -to -m a rk e t. Nevertheless, I expect to
see a larger set of heterogeneous m ulticore
systems in com m ercial products in the near

fu tu re as such systems have the potential to
achieve better energy efficiency.
Instead of designing the system w ith
a heterogeneous set of cores, this article
discusses a novel design alternative:
flexible heterogeneity. The goal of flexible
heterogeneity is to achieve higher energy
efficiency through low-cost, simple
reconfigurations of the homogeneous system
based on applications' needs. This low-cost
reconfiguration "pools" the perform ance-
critical a rchite ctu ral components among the
cores and allocates more hardw are resources
to cores th a t need them . At the same tim e , it
lim its the resources given to cores th a t are
running less intensive applications. In this
way, a pool of resources can be shared more
efficiently. Also, in this way, it is possible to
reduce the need fo r over-design.
FLEXIBLY HETEROGENEOUS
PROCESSORS
The key idea of flexible heterogeneity
is to determine the application needs while
the system is running and allocating the
architectural resources in a way that matches
this demand. Which resources should we pool
among the cores? In my research lab at Boston
University, my students and I developed a
cache pooling technique fo r tw o reasons.^ One,
caches significantly affect the performance
of many software applications. And two,
applications strongly differ in their cache needs
(or in other words, in their "cache-hungriness").
c ircu itce lla r.co m 49
FIGURE 1
Cache pooling on a 3-D m ultiprocesso r
system . Each core has fo u r dedicatee
cache banks by default. Each bank,
how ever, can be pooled to the core ir
the a d jacent layer if needed. In this
exam ple, A p plication 1's perform ance
benefits s tro n g ly fro m using a larger
L2 cache. Thus, A p plication 1 is given
a la rge r am ount of priva te cache
banks by b o rro w in g cache banks from
the core rig h t underneath.
COLUMNS
Many processor architectures today have
private L1 and L2 caches fo r the cores, and
some also have large shared L3 caches. L1
caches are small-sized and are often highly
utilized as a result. L2 usage among the
applications, however, changes dram atically.
L2 cache is also where over-design occurs
more often to accomm odate fo r the
application diversity. A 1- or 2-MB private
L2 cache per core is fa irly common in high­
perform ance desktop and server processors.
As a result, caches occupy a large portion of
the silicon area.
Note th a t designing a system w ith a shared
L2, where all cores are connected to the same
cache, reduces the cache coherence overhead
and provides a more flexible d istrib u tio n
of cache resources to the cores, compared
to assigning a private cache to each core.
(Private caches require hardw are or softw are
coherence protocols th a t m aintain correct
program operation and data consistency.)
Still, shared cache design at the L2 level is
often not preferred due to several reasons.
First, applications generally perform better
w ith dedicated resources as they do not
in te rfe re w ith each other's cached data in
this way. Second, shared caches are larger
and may have longer access tim es as a result.
Most im p o rta n tly, shared L2 cache approach
is not scalable to su p p o rt a large num ber of
cores because of the high access latency and
routing overhead th a t occur when each core
needs to reach a centralized resource.
FIGURE 2
Job allocation policy to m axim ize
resource pooling efficiency. Jobs (J1-
J4) are ranked based on th e ir cache
needs and IPC, w h ich is an in dicator
of pow er consu m ptio n. Jobs w ith
c o n tra s tin g cache needs are then
placed on adjacent layers. Higher IPC
jo b pairs are placed closer to the heat
sink to ease heat rem oval.
 50 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
Private caches generally provide better
perform ance and easier design, b u t they
re s tric t the cache size given to each core,
as discussed above. Thus, if we can pool the
L2 cache resources dynam ically according to
application resource needs, each core can
then get a private but appropriately-sized
cache.
Cache pooling can be performed at the
granularity of cache banks, where each bank
can be used by its dedicated core or can be
borrowed by another core when needed. As
the number of cores and caches increase, this
COLUMNS
approach is not easily scalable in traditional
design, sim ply because a core would need to
ABOUT THE AUTHOR access cache banks potentially at the opposite
Ayse K. Coskun (acoskun@ side of the chip. Long access distance means
b u .e d u ) is an a s s is t a n t longer w ire length, which indicates larger
professor in the latency. For example, sharing m icroarchitectural
Electrical and C o m p u te r resources across a short distance incur only
Engineering D e p a rtm e n t a few picoseconds of additional delay, while
a t Boston University. She accessing a unit across the chip may cause
hundreds of nanoseconds.[2]
re ce ive d MS a n d PhD
3-D stacking, where sm aller chips are
d e g re e s in C o m p u t e r
stacked v e rtic a lly instead of building a single
Science and Eng ineering
big chip, provides low -latency resource
fr o m th e U n iv e rs ity of
sharing opportunities across the different
C a l i f o r n i a , San D ie g o .
layers in the stack. This is because the
Ayse's research interests
through-silicon vias (TSV) th a t connect two
include t e m p e r a tu r e and
a rchitectural components on adjacent layers
e n e rg y m a n a g e m e n t, are only tens of microns a p a rt (as opposed
3-D s ta c k a rc h ite c tu r e s , to m m -scale w ire -le n g th to connect tw o units
c o m p u te r a rc h ite c tu re , across the chip). In addition to the advantage
and e m b e d d e d systems. of the sh o rt distance, it is possible to place a
She w orked at Sun larger num ber of TSVs th a t can be clocked at a
Microsystems (now high rate, and thus, provide a wide bandwidth
O r a c le ) in San D ie g o , fo r data transfer.
CA, p r i o r to h e r c u r r e n t Figure 1 dem onstrates the cache pooling
position at BU. Ayse idea. In this example 3-D system , there are
s e rv e s as an a s s o c ia t e fo u r cores on each layer and each core has
editor of the I EEE fo u r private cache banks. A cache bank can be
Em bedded S y ste m s configured to be used by its main dedicated
Letters. core, or it can be taken over by the core rig h t
above/under the main core. In this example,
Application 1 thrives when running w ith a
larger L2 cache size, so it is given a total of
six cache banks. Application 2, on the other
REFERENCES
[1 ] J. M eng, T. Z h a n g , and A. K. C oskun, "D y ­
n a m ic C ache P ooling fo r Im p ro v in g E nergy
E ffic ie n c y in 3D S tacked M u ltic o re P roce ssors,”
in P ro c e e d in g s o f th e IF IP /IE E E I n t e r n a tio n ­
al C o nferen ce on V ery Large Scale In te g ra tio n
(VLSI-SoC), 2013.
c irc u itce lla r.co m /ccm a te ria ls
[2 ] H. H o m a yo u n , H., V. K o n to rin is , A.
S haya n, T.-W . L in , and D. M. T u llse n, "D y ­
n a m ic a lly H e te ro g e n e o u s Cores T h ro u g h 3D
R esource P o o lin g ,” in P ro ce e d in g s o f IEEE 18th
In te rn a tio n a l S y m p o s iu m on H igh P e rfo r­
m a n c e C o m p u te r A rc h ite c tu re (HPCA), 2012.
hand, does not need much cache space and
therefore is given only tw o banks. As the
applications running on the system change,
the cache allocation can be reconfigured.
An essential step in resource pooling is to
determ ine the application demand. In cache
pooling, one needs to estim ate the cache-
hungriness of each application. One way
to do this is to firs t determ ine how much
instructions-per-cycle (IPC) im provem ent
any application should get fro m using an
additional cache bank in order to achieve
better energy efficiency (e.g., lower energy
delay product, or EDP). This threshold of
im provem ent can be determ ined by the
designer through a rchitectural perform ance
and power sim ulations using tools such as
gem5 (www.gem 5.org/M ain_Page) a nd McPat
(w w w .hpl.hp.com /research/m cpat/).
A fte r determ ining a threshold, it is possible
to ite ra tive ly converge on the best cache bank
d istrib u tio n among tw o applications running
on cores above/below each other on adjacent
layers as follows. First, run each application
using a small num ber of banks. Then, add
another cache bank to each core, run the
application fo r a sh o rt interval, and see if
IPC im proves beyond the predeterm ined
threshold. If it does, add another cache bank.
If the perform ance im provem ent is less than
the predeterm ined threshold, then use the
last cache bank setting fo r th a t application.
If both applications continue to th rive w ith
a larger num ber of cache banks, then one
approach would be to favor the application
th a t is getting larger perform ance benefits.
Any unused cache banks can be selectively
turned o ff to save energy.
Clearly, one would need to add some
hardware into the tra d itio n a l processor
a rchitecture to be able to pool the cache
banks across the layers. To ease the design
of this reconfigurable system , my students
and I restricted the cache pooling mechanism
such th a t only a pair of cores th a t are rig h t
above/below each other on a 3-D stack can
share resources. The hardware we added
m ainly included registers (status bits) for
keeping tra ck of the cache bank assignm ent,
selection logic (m ultiplexers) fo r determ ining
which layer to read fro m /w rite to, and TSVs
to enable data transfer.[1] Overall, the total
area overhead is on the order of a few
thousand tra n sisto rs and a few hundred TSVs.
This overhead is negligible fo r a m ulticore
processor.
Another source of overhead is the
cache flushing th a t is needed a fte r a cache
reconfiguration to ensure the data in the
caches are relevant. In our experim ents,
we used a 100-ms interval to check for
the need of cache pooling ad ju stm ent and
AN ELEKTOR INTERNATIONAL MEDIA PROMOTION

Get Started with Advanced

Control Robotics
By C. J. Abate (Content Director, EIM)

I met Hanno Sander in 2008 at n e x t level w ith m ic r o c o n tro lle r s and

the Embedded Systems Conference in the k n o w -h o w to im p le m e n t th e m
San Jose, CA. At the tim e , Sander was effe ctive ly.
a t Parallax's booth d e m on stra tin g a
Propeller-based, tw o-w heeled balanc­ THEORY & BEST PRACTICES
ing robot. When I saw his interesting A d v a n ce d C o n tro l R o b o tics s im ­
balance bot design and his engaging p lifie s the th e o r y and best p r a c tic ­
way of explaining design to interested es of advanced ro b o t technologies.
engineers, I knew th a t Sander woulc You're ta u g h t basic em bedded d e ­
be an e xcellent resource fo r fu tu re sign th e o r y and presen te d handy
Circu it Cellar content. I was right. code sam ples, essential sche m atics,
Several m onths a fte r and va luable design tip s
the conference, we s tru c tio n to d ebugging).
ADVANCED CONTROL published an article
he w ro te about the LEARN THEN DESIGN
Dalancing ro b o t p r o j ­ The p rin c ip le s d escribed and t o p ­
STÄS
HANNO SANDER
e ct (Circuit
March 2009). Today,
Cellar ics p resented in A d v a n c e d C o n tro l
R o b o tic s are im m e d ia te ly a p p li­
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"b u ild in g h ig h -q u a l­ Sander covers:
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to th e ir lim its ." 1 Embedded Technology: m ic r o ­
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THE FUTURE IS NOW P ro g ra m m in g Languages: m a ­
When it comes to chine level (Assem bly), low lev­
robotics, the fu tu re el (C/BASIC/Spin), and hum an
is now. With the ev­
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mand fo r robotics sta te m achines, m u ltip ro c e s s o rs ,
a p p lic a t io n s —fr o m and events
home control sys­ Visual D ebugging: LED/speaker/
Title: Advanced Control Robotics
Author: Hanno Sander
tem s to a n im a tro n- gauges, PC-based d e ve lo p m e n t
Publisher: Elektor/Circuit Cellar ic toys to unmanned e n v iro n m e n ts , and te s t in s t r u ­
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Buy: www.elektor.com/advanced exciting tim e to be a O u tp u t: sounds and synthesized
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1OneRobot.org/about

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 52 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

a) b)

Normalized Normalized 08
EDP EDAP '
to 2MB to 2MB
Baseline Baseline 0.6

Non Low Med High All Non Low Med High All
COLUMNS

(a) Normalized EDP (b) Normalized EDAP

FIGURE 3
Energy-delay pro d u ct
ene rgy-delay-are a p ro d u ct
results fo r using 1-MB priva te caches
and fo r using cache resource pooling
(CRP) on a 3-D stacked system w ith
equ ivalent to ta l cache size. X axes
provide the cache-hungriness o f the
app lica tion m ix , increasing fro m
to rig h t. Low er EDP and
m ore desirable.
reconfigure if needed. Flushing the caches
(EDP) and causes a "cold s ta r t" as the application needs
(EDAP)
to bring its relevant data fro m memory.
My students and I measured the cold s ta rt
overhead to be less than 1 ms fo r SPEC CPU
2006 applications using the gem5 sim ulator.
Thus, cache pooling causes at most 1%
left delay when it is run w ith a 100-m s period.
EDAP are This delay is easily compensated w ith the
perform ance im provem ent achieved by
efficiently d istrib u tin g the cache banks. Cache
pooling frequency can be adjusted as needed
to capture application phases at a negligible
overhead fo r other application suites.
INTEGRATING JOB ALLOCATION
& CACHE POOLING
Job allocation im pacts the potential
benefits of cache pooling as it determ ines
on which core each application runs. For
example, if the OS allocates tw o cache-hungry
applications on adjacent cores on top of each
other, cache pooling benefits may be lim ited.
On the other hand, placing applications w ith
contrasting cache needs on top of each other
would increase the pooling efficiency.
In my lab, we designed a job allocation
policy th a t maximizes benefits of cache
pooling. Figure 2 dem onstrates the main
idea of this policy. We firs t estim ate the
cache needs of each application using L2
misses and L2 replacem ent rates over a given
num ber of cycles. We also observe the IPC of
each application as IPC is often an indicator
of the power consum ption. We then pair the
applications w ith contrasting cache demands,
and use the IPC m easurem ents to place
potentially higher power applications closer
to the heat sink.
Placing applications w ith higher power
consum ption closer to the heat sink eases
cooling and reduces the th e rm a l hot spots.
Note th a t IPC alone may not always be
sufficient fo r accurate power estim ation
as the in stru ctio n m ix also determ ines the
power consum ption (e.g., a flo a tin g -p o in t
intensive application may consume higher
power than an integer application even
when they have the same IPC). It is possible
to use a larger set of perform ance counter
m easurem ents to im prove power estim ation
accuracy if needed.
High tem peratures are among the
im p o rta n t challenges of 3-D stacking. I
discussed some of the te m perature modeling
and m anagem ent issues in 3-D systems in
my January 2014 and March 2014 Circuit
Cellar articles. If high-pow er cores are
integrated into a 3-D stack, therm ally-aw are
job allocation may not be sufficient and novel
cooling solutions such as liquid cooling may
need to be considered. In our cache pooling
experim ents, we used 1-GHz m edium -pow er
cores. For these experim ents, the proposed
job allocation method was sufficient to keep
the tem perature below critical levels.
I f we integrate a larger am ount of cores
into the 3-D stack, each layer w ill likely have
m ultiple cores. In this case, one can envision
the 3-D stack as a collection of "colum ns of
cores," where a column is sim ply cores stacked
on top of each other. W ithin each column of
cores, one can apply the job allocation and
cache pooling policies described above. Across
these columns, it is possible to balance the
num ber of cache-hungry jobs using additional
job m igrations to m aximize pooling efficiency.
Figure 3a shows the EDP when using a
1-MB static private cache configuration and
when using cache resource pooling (CRP)
on a four-core 3-D system. The results are
norm alized w ith respect to the EDP results
fo r a system w ith 2-MB private L2 caches.
The x-axis shows the cache-hungriness of
the application m ix running on the system.
For example, medium means some of the
applications are cache-hungry, none refers
to the case where none of the applications
are cache-hungry, and all means all of the
applications are cache-hungry.
Lower EDP is m ore desirable as it indicates
lower energy consum ption and lower delay
 c ircu itce lla r.co m 53

/4s 3-D stacking enables placing on-chip stacked DRAM

(i.e., higher perform ance). When all or m ost of
the applications are cache-hungry and using together with the processor, as shown in Figure 1,
the caches intensively, there is not much
m otivation fo r cache pooling as expected. DRAM banks and the on-chip memory bandwidth
For low and m edium cases, CRP achieves
over 30% reduction in EDP compared to are also candidates for dynamic pooling.
using 2-MB static caches. Real-life w orkloads
often include a m ix of cache-hungry and non­
cache-intensive applications, resem bling the
"lo w " and "m e d iu m " cases in the figure. DRAM together w ith the processor, as shown
When area is also considered as a factor, in Figure 1, DRAM banks and the on-chip
the CRP results are even more impressive. m em ory bandw idth are also candidates for
Figure 3b dem onstrates the energy- dynam ic pooling.

area-delay product (EDAP) results fo r the
same experim ent and indicates over 50%
reduction in EDAP. This means th a t CRP can
sim ultaneously achieve lower energy and
good perform ance at a much lower area
compared to using large static L2 caches.
OTHER POOLING OPPORTUNITIES
Caches are not the only resource on a
m ultiprocessor th a t can be dynam ically
pooled. For example, recent w o rk by Houman
Homayoun et a l.H introduces resource pooling
fo r pe rfo rm an ce-critica l m icroarchitectural
units such as reorder buffer, register file,
load/store queue, and in stru ctio n queue. As
3-D stacking enables placing on-chip stacked
COLUMNS
I believe there are trem endous efficiency
im provem ent opportunities in designing a
fle xib ly heterogeneous com puting fa b ric that
can be configured using simple and low-cost
hardw are and softw are methods. For
example, envision a set of cores, a set of
poolable caches, a group of scratchpad
m em ories, and on-chip DRAM banks, whose
p a rtitio n s and bandw idth can be allocated to
applications based on th e ir demands and
characteristics. In this way, each application
can be provided w ith a customized set of
resources and energy efficiency of the
processor can be substantially improved. I
th in k 3-D stacking technology is a great
candidate to realize this vision. £

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Each month, the editorial staff reviews dozens of article
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circuit cellar
COLUMNS
I n the firs t p a rt of this a rticle series, I
introduced the fixed resistor and then
covered the topics of th ic k and thin film
resistors. Now let's tu rn our a ttention to
variable resistors.
VARIABLE VARIETIES
Variable resistors come in many
d iffe re n t sizes, power ratings, and values:
potentiom eters or rheostats, single or
m u ltitu rn , and so on. They comprise a
resistive elem ent, a sliding contact (wiper)
th a t moves along the resistive element,
making a contact to it. They also include some
fo rm of a mechanism and housing to keep the
parts together, move the w iper, and keep out
the d irt. Refer to Photo 1 fo r a few examples
of variable resistors.
POTS
A potentiom eter, or "p o t," has three
term inals and perhaps some taps along the
resistive element. Potentiom eters are used
to v a ry o u tp u t voltage by the w ip e r position
on the resistive elem ent (see Figure 1).
Potentiom eters should not be loaded—that
is, the load resistance should be at least
10x th a t of the potentiom eter. However,
potentiom eters can be loaded intentionally
to m odify th e ir otherwise linear output. Most
potentiom eters' output is linear w ith respect
to the position of the w ip e r on the resistive
element. But there are potentiom eters—such
as those fo r audio volum e control—w ith,
typically, logarithm ic characteristics and a
tap or taps fo r frequency com pensation at
low audio levels.
In term s of th e ir mechanical arrangem ent,
there are potentiom eters w ith a shaft to be
fitte d w ith a knob fo r frequent adjustm ents,
such as the volume control. Multiple
potentiom eters (i.e., tw o or m ore pots on a
single shaft) are used in stereo equipm ent
or dual-redundant control systems. Some
are rotary. Others, such as those popular in
professional audio equipm ent, have a linear
sliding track. An im p o rta n t characteristic of
m ultiple potentiom eters is the accuracy of
th e ir m utual tracking.
Potentiom eters referred to as trim m e rs,
trim p o ts , or presets m ostly have ju s t a slot
fo r a screw d rive r to adjust th e ir outputs.
They are usually set only once to trim a
param eter, such as an a m p lifie r offset or a
reference voltage. Typical pots are made of
a plastic base covered w ith a resistive track.
The w iper rotates along the track. All rotary,
single tu rn potentiom eters and trim m e rs
have about 270° rotational angle. Depending
on the q u a lity grade, some potentiom eters'
resistive elements are graphite, plastic w ith
embedded carbon particles, or cerm et. W ire-
wound potentiom eters are used when high
quality or power dissipation is desired.
M ultiturn potentiom eters, instead of the
typical 270° travel of sin g le -tu rn pots, require
five to 20 tu rn s fo r the full range. This enables
you to set the desired ou tp u t m ore accurately

and w ith much greater long-term s ta b ility
than single -tu rn devices. Some m u ltitu rn
pots have a linear resistive elem ent while
the w ip er moves across it by a lead screw.
Others, m ainly w ire-w ound pots, have a
helical resistive elem ent and the w iper moves
across the helix.
RHEOSTATS
Rheostats a djust cu rre n t flow ing through
a circu it (see Figure 2). Sim ply put, their
resistance is added to the load, thus
m odifying the current through it and, in
effect, the voltage across the load. Before
power sem iconductors, such as th y ris to rs ,
made th e ir way into power control, high­
power rheostats had been used to dim lights
in theaters or control the speed of electric
m otors.
Rheostats need only tw o term inals,
although potentiom eters w ith three term inals
can be w ired as rheostats too, provided th e ir
power rating is adequate. As you can see in
Figure 2, in the presence of the th ird term inal,
it is a good idea to connect it to the w iper as
shown. W iper contacts can become flakey due
to the wear and tear, vib ra tio n , corrosion, and
so fo rth . Because the rheostats' resistance
when used to trim value of a cu rre n t is often
only a small percentage of the total resistance,
a small overall resistance increase in case of
the w iper contacts failure may be preferred to
complete loss of the current.
This is an im p o rta n t consideration fo r all
trim m e rs , be it potentiom eters or rheostats.
Their ad justm en t range should not be any
greater than needed. For example, an
integrated circu it (IC) analog am plifier, due
to m anufacturing tolerances, may require
some adjustment of its bias current. A 50-kQ
resistance has been calculated to provide
the nominal cu rrent value. You calculate the
needed a dju stm e nt th a t can be achieved w ith
a 1-kQ pot. Don't use a larger one! You'll
also have to analyze the repercussions of
the potentiom eter's w iper failing and thus
the bias then determ ined by an additional 1
kQ. You may find th a t the p ro b a b ility of this
happening is very small or th a t the effect
is not serious. Otherwise, you may take
additional steps to m inim ize the effects of the
trim m e r failing or consider some other way
of trim m in g .
TIPS
Packaging is ve ry im p o rta n t for
potentiom eters of all kinds. It has several
fundam ental functions: it provides reliable
means of varying the resistance, mechanical
sta b ility, m ounting of the potentiom eter
assembly, and protection fro m the elements.
In term s of quality, you usually get w hat you
c ircu itce lla r.co m SS
COLUMNS
PHOTO l
pay for.
Various pote n tio m e te rs and trim m e rs
I tr y to lim it the use of variable resistor
trim m e rs . They are sim ple to im plem ent,
sm all, some types are fa irly inexpensive, but
th e ir re lia b ility is not great compared w ith
other resistive components and methods of
trim m in g . Their setting can change w ith age
due to vib ra tio n or accidental movement.
When I do use them , I m inim ize th e ir
a d ju stm e n t range to the absolute m inim um
needed. Often a series/parallel com bination
of fixed resistors can p e rfo rm the trim w ith
excellent long te rm stability.
Potentiom eters are still used in feedback
control systems fo r position command as well
as feedback. For critical applications, ro ta ry or
linear variable diffe re n tia l tra n sfo rm e rs (RVDT
or LVDT), or some of many digital encoders
are, in my experience, better, m ore reliable
solutions. It depends on the application, its
safety requirem ents, and the cost.
I like to use solid-state potentiom eters.
They have many advantages over th e ir
mechanical brethren, such as sta b ility,
accurate tracking and so fo rth . You can find
them in a lot of audio equipm ent in volume
and tone control circuits. Essentially, they
are a strin g of resistors w ith taps connected
through solid-state switches to the output. A
num ber of m anufacturers make them , such
as In te rs il, Maxim Integrated Products, and
Analog Devices. They have some idiosyncrasies
compared to electrom echanical resistive
products. For instance, they do not provide
FIGURE 1
P o tentio m eter usage
 se C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
COLUMNS
FIGURE 2
Rheostat usage
c irc u itce lla r.co m /ccm a te ria ls
RESOURCES
A nalog D evices, "A D 5227:
6 4 -P o s itio n D ig ita l U p /D o w n
C o n tro l P o te n tio m e te r,” w w w .
a n a lo g .c o m /e n /d ig ita l- to - a n -
a lo g - c o n v e rte rs /d ig ita l-p o te n -
tio m e te r s /a d 5 2 2 7 /p r o d u c ts /
p r o d u c t.h tm l.
ABOUT THEAUTHOR
G e o rg e N o v a c e k is a p r o f e s s io n a l e n g i n e e r
w it h a d egre e in Cyb e rn e tic s and Closed-Loop
C o n tro l. No w r e t i r e d , he w a s m o s t r e c e n t ly
p re s id e n t o f a m u l ti n a t io n a l m a n u f a c t u r e r fo r
e m b e d d e d c o n tro l s y s te m s fo r aero space a p ­
plications. George w r o te 26 feature artic les fo r
Circuit Cellar between 1999 and 2004. Contact
h im a t g n o v a c e k @ n e x ic o m . n e t w ith " C i r c u i t
C ellar"in th e s u b je c t line.
the "in fin ite ly fin e " a djustm ent of pots, but
one can usually w o rk around those. Read their
specifications carefully. One criticism I heard
was th a t the volume or tone a d ju stm e n t was
unacceptably coarse. I don't have "golden
ears," but the alleged shortcom ing seems to
be hardly w orrisom e. The dynam ic range of
human hearing is about 140 dB. Live music
range does not exceed 80dB. The electrically
reproduced music's range is less; but let's
assume it's also 80 dB. Humans can discern
an approxim ately 2-dB change in volume.
Thus, 1,024 steps available in many digital
pots should provide 0.078 dB steps, which
is more than sufficiently fine a d ju stm e n t for
In te r s il, " D ig ita l P o te n tio m e te rs(D C P s),” w w w .
in te r s il.c o m /e n /p r o d u c ts /d a ta - c o n v e r te r s /d ig i-
t a l - p o te n tio m e te rs --d c p s -.h tm l.
M a x im In te g ra te d P ro d u cts, " 1 0 -B it, D ual,
N o n v o la tile , L in e a r-T a p e r D ig ita l P o te n tio m e -
te rs ,” 1 9 -3 5 6 2 , 20 06, h ttp ://d a ta s h e e ts .m a x im in t-
egrated.com /en/ds/MAX5494-MAX5499.pdf.
TT E le c tro n ic s , "U ltra -H ig h V alue P re cision
R e s is to rs ,” w w w .w e lw y n - tt.c o m /p d f/d a ta -
s h e e t/3810.PDF.
V ishay, "M e ta l F ilm R esistors, M ilita r y /E s ta b ­
lish e d R e lia b ility , M IL-P R F-39017 Q u a lifie d ,
Type RLR,” 3 1 0 2 3 , 2 0 1 3 , w w w .v is h a y .c o m /
d o c s /3 1 0 2 3 /e rl.p d f.
even the pickiest music aficionado.
A nother p e culiarity of the digital pots
is th a t they need a DCoperating voltage,
typ ica lly 2.7 to 5.25 V. None of the pot's
term inals can be exposed to a voltage outside
this lim it.
In some m icroelectronic devices (e.g.,
Micrel QwikRadioTM IC receivers), switched
capacitor technology is used to sim ulate
resistors. Also, FETs can act like variable
resistors when th e ir drain to source voltage is
kept w ith in th e ir specified "resistive region."
In other words, the drain cu rre n t modulated
by the gate voltage is reasonably linearly
proportional to the drain voltage. This can be
used, fo r example, to m odulate operational
a m p lifie r gain. Sim ilar nonlinear dependencies
can be found in PN junctions.
THERMISTORS & VARISTORS
When discussing variable resistors we
m ust not fo rg e t th e rm is to rs and varistors.
Therm istors are tem perature-dependant
resistors. Most common th e rm istors, called
NTC, have a negative tem perature coefficient.
Their resistance dim inishes w ith tem perature.
They are m ostly made of sintered metal oxide,
and th e ir common use is fo r tem perature
sensing.
Posistors, or PTCs, have positive
te m perature coefficient. Their resistance
grows w ith tem perature, and they're used, for
example, to stabilize operating characteristics
of circuits or as fuses. They are made of doped
polycrystalline ceram ic containing barium
tita n a te (BaTiO3). There are other types of
te m perature sensors, such as Silistors, made
of silicone. Unlike th e rm is to rs , th e ir resistance
changes linearly w ith tem perature.
In a harsh environm ent, such as a je t
engine, the tem perature is sometim es
measured by resistance tem perature
detectors (RTDs) in addition to therm ocouples.
RTDs are essentially w ire-w ound resistors
made out of platinum , nickel, or copper
w ire, w ith a highly predictable tem perature
characteristic/resistance. You can use them
up to about 1,112°F (600°C).
M etal-oxide va risto rs (MOV) are made
typ ica lly of zinc-oxide or silicon carbide. They
begin to conduct cu rre n t when the clamping
voltage (from volts to kilovolts) of either
p o la rity is exceeded. They are used m ostly
in com m ercial equipm ent fo r tra nsie nt and
overvoltage protection.
NOT SO HUMBLE
So th a t's it fo r variable resistors. Come to
th in k of it, none of the resistors we discussed
were p a rticu la rly "h u m b le ." G
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 58 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

ABOVE THE GROUND PLANE

Improv
MOSFf
COLUMNS

S h o rtly a fte r the March 284 Circuit Cellar

appeared reader Carl Hage sent an
readers
decisions
often com m ent on my design
(and, alas, blunders), they rarely
evaluation of my Hall-effect LED current send half a dozen pages of detailed analysis!
control c irc u itry and firm w a re . Although Hage has both a k ille r LED headlight on his

LED strings - A LED strings - B

Nominal VF = 6 V Nominal VF = 6 V
Max I - 500 mA Max I - 500 mA

FIGURE 1
A dding M axim In te g ra te d MAX4544 analog sw itches to the schem atic fro m m y "A rd u in o PWM vs MOSFET T ransdu ctance " (C ircuit C ellar 284, 2014) a rtic le im proves the MOSFET
gate w a vefo rm s. The analog sw itches connect the MOSFET gates to e ith e r ground or the PWM filte r o u tp u t, so the pulse edges no longer depend on the filte r response. The code
can also change the PWM voltage w ith the gate ground ed, thus allow ing m ore tim e fo r the voltage to stabilize.

// Timer 1: PWM 9 PWM 10 - Hall o ffs e t
TCCR1A = B10000001;
TCCR1B = B00001001;
// Timer 2: PWM3 PWM11 - MOSFET gate dr ive A, B
TCCR2A = B10100011; / / Mode 3 = fa s t PWM with TOP= FF
TCCR2B = B00000001; //
analogWrite(PIN_SET_VGATE_A,0);
analogWrite(PIN_SET_VGATE_B,0);
bicycle and deep knowledge of Atm el's AVR
m icrocontrollers, so his suggestions obviously
came from experience.
In this article, I'll take a second look at a
design I'd considered nearly finished and, by
blending some of Hage's suggestions w ith a
few tweaks of my own, explore how the result
im proves on the original design.
As before, the circu it uses a Hall-effect
sensor to measure the cu rre n t flowing
from the b a tte ry to the LEDs, then controls
th a t current w ith PWM outputs th a t set the
MOSFET gate voltages. A single-supply op-
am p removes the sensor's VCC/2 offset and
am plifies the result fo r the A rduino's analog
inputs. Figure 1 presents the key p a rt of the
revised circuit; you can download the entire
schem atic from Circuit Cellar's FTP site.
FASTER PWM = LOWER RIPPLE
My original design selected the 1:1 clock
prescaler fo r T im e rl and Tim er2, which
produced a 32-ps PWM period. Hage pointed
out th a t the default A rduino PWM configuration
uses the dual-slope Phase-Correct mode that
w orks well fo r m otor drivers, but runs at half
the m axim um possible rate. In contrast, Fast
PWM mode uses a single-slope comparison
th a t instantly doubles the PWM frequency.
I'd used Fast PWM mode in other projects
fo r exactly th a t reason, so his com m ent
produced an im m ediate face palm: w hy d id n 't
I th in k of that?
Listing 1 shows the statem ents th a t set
both tim e rs into Fast PWM Mode w ith 1:1 clock
prescalers. Although Tim er1 can operate w ith
8, 9, 10, or 16 bits of resolution, the Arduino
firm w a re supports only 8 bits and I left it that
way fo r reasons I'll discuss later.
I'd used a frequency-dom ain analysis
to figu re the ripple at the ou tp u t of the
PWM filte rs , w ith a 1-kQ resistor and 1-pF
capacitor producing a 1-ms tim e constant
th a t corresponds to a 160-Hz cutoff. Because
an RC filte r has one pole, the response rolls
off at 6 dB/octave: doubling the frequency
reduces the ripple by 6 dB. Hage suggested
using the tim e-do m ain equivalent: applying
c ircu itce lla r.co m 59
LISTING 1
The A rd u in o 's d efault c o u n te r-tim e r
/ / Mode 5 = fa s t 8- b i t PWM with setup produces re lative ly slow PWM.
T
O
=
P
F
F
These s tatem ents set 1:1 clock division
// . . . WGM, 1:1 clock scale -> 64 kHz
and 8 -b it Fast PWM Mode fo r T im er1
and T im e r2 , and then set th e ir ou tp u t
voltage to zero.
. . . 1:1 clock scale -> 64 kHz
/ / force gate voltage = 0
COLUMNS
1 mA through the resistor w ill change the
ou tp u t by 1 V/ms. Reducing the PWM period
by a fa cto r of tw o reduces the voltage change
by a fa cto r of two: exactly - 6 dB.
No m a tte r how you figure it, doubling the
PWM frequency or halving the period should
reduce the ripple by about a fa cto r of two.
Comparing the 100 mA of ripple in Photo
3 fro m my March a rticle ("Arduino PWM vs
MOSFET Transductance") w ith the 40 mA
of ripple in Photo 1 here shows th a t the
reduction is about a fa cto r of two. A close look
shows th a t slig h tly d iffe re n t PWM values in the
tw o photos affect the exact ripple amplitude.
In all of the oscilloscope photos, the LED
cu rre n t trace comes fro m a Tektronix AM503
Hall-effect c u rre n t probe scaled at 50 mA/div,
w ith a bandwidth fa r exceeding my circu itry:
PHOTO 1
you can depend on those traces!
Less than 20 mV o f ripple in the PWM
The A rduino tim e r configuration allows
filte r voltage (upper tra c e ) produces
only 256 PWM values: 0 through 255,
40 m A o f LED c u rre n t v a ria tio n (lower
corresponding to the range of each tim e r's trace, 50 m A /div). D oubling the PWM
eight bits, w ith about 20 mV separating freq uency to 62.5 kHz reduced the
successive PWM values at the filte r output. c u rre n t ripple by a b o u t a fa cto r of
As I showed in my March article, a 20-mV tw o. The 0-V level fo r the gate voltage
change in gate voltage produces a 50-m A trace is fa r o ff screen, w ith the cursor
change in drain c u rre n t when the MOSFET readou t show ing its 1.2-VDC level.
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 62 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

conducts about 200 mA. Obviously, increasing

the num ber of PWM values would enable finer
control of the LED current.
The T im e rl hardw are can operate w ith
more than eight bits, but each additional
bit reduces the PWM frequency by a factor
of two. Given the same PWM filte r hardware,
each additional b it increases the ripple by a
fa cto r of tw o, giving fin e r control of an output
w ith more variation. Because I doubled the
PWM frequency, another bit of resolution
would produce the same ripple as before.
Hage suggested a solution th a t shows
COLUMNS

his fa m ilia rity w ith w ringing ultim ate

perform ance fro m lim ited m icrocontroller
hardware: use firm w a re to d ith e r the PWM
value while the tim e r runs! For example, an
8 -b it tim e r cannot produce a non-integral
PWM value of 64.25, but running a PWM
value of 64 fo r three periods and 65 fo r one
period yields an average of 64.25 and the
corresponding "fra c tio n a l" voltage from the
filter.
He suggested setting the hardw are tim e r
to count 5 bits, then using firm w a re to dither
the counter value of eight successive periods.
In effect, the firm w a re provides three high­
order bits and the hardw are provides five
low -order "fra c tio n a l" bits, but those high­
PHOTO 2
order bits can change on the fly. Got that?
A M axim In te g ra te d MAX4544 epoxied atop the MOSFET w ith a ir-w ire d connections validated the idea, bu t it However, this requires form idable
c e rta in ly w o n 't survive actual use! The MOSFET on the r ig h t side hasn 't been m odifie d yet. program m ing a b ility and produces extrem ely
fra g ile code. As you saw earlier, the tim ers
run fro m the 1:1 clock prescaler, which
means they would require a ttention every 32
instructions. Normally, you'd use an in te rru p t
handler, but a handler saving and restoring
registers at th a t rate would cripple the CPU's
throu g h p u t. As Hage noted, "You w ouldn't
w ant the Tim er0 in te rru p t messing up the
PWM dithering anyway, so [you] don't need
Tim er0 while in the PWM."
While I agree th a t his method is possible,
it ce rta in ly requires more e ffo rt than seems
w arranted. It's the s o rt of code you w rite
when confronted w ith changing requirem ents
and frozen hardware: you m ust solve the
problem w ith o u t changing the BOM. I'll leave
th a t as an exercise fo r the ve ry motivated
reader!

CRISP GATE VOLTAGE

TRANSITIONS
Photo 2 in my March a rticle showed the
relatively slow tra n sitio n s on each edge of the
LED cu rre n t pulse due to the filtered PWM at
the MOSFET gate. Hage suggested a solution
th a t draws on the power of a m icrocontroller:
PHOTO 3
calculate the tra n sitio n tim e based on applying
The lower sections o f the upper trace show when the firm w a re m easures the LED c u rre n t, w ith the PWM
a constant 0 or 5 V, tu rn o ff the pWM, set
changing by one co u n t im m e d ia te ly a fte rw a rd . The m ain loop's path length lim its the m a x im u m update rate the ou tp u t bit low or high fo r the appropriate
to 1.7 ms, so slewing the LED c u rre n t by 150 m A requires 10 ms. tim e , and then re s ta rt the PWM. The filte r
 c ircu itce lla r.co m 63

i f ( m i l l i s ( ) >= (EventStart + (unsigned long)Events[EventIndex].duration)) {

EventStart = m i l l i s ( ) ; / / record s t a r t time

Events[EventIndex].drive_a = VGateDriveA; / / save drive voltages

Events[EventIndex].drive_b = VGateDriveB;

i f (++EventIndex > MAX_EVENT_INDEX) / / step to next event

EventIndex = 0;

VGateDriveA = Events[EventIndex].drive_a; / / restore previous drives

SetPWMVoltage(PIN_SET_VGATE_A,VGateDriveA);

COLUMNS
VGateDriveB = Events[EventIndex].drive_b;
SetPWMVoltage(PIN_SET_VGATE_B,VGateDriveB);

delay(PWM_Settle);

digitalWrite(PIN_ENABLE_A,Events[EventIndex].en_a); / / enable gates fo r new state

digitalWrite(PIN_ENABLE_B,Events[EventIndex].en_b);

i f (!(Events[EventIndex].en_a Events[EventIndex].en_b))
FindSensorNull(); / / both LEDs now o f f -> null sensor

LISTING 2
This code tim e s each pulse, stores the PWM drive voltages, and fetches the next outputs. When both LEDs w ill be off, it nulls the H all-effect sensor output.

would lim it the slew rate, but the tra n sitio n

tim e would still be much s h o rte r than w aiting
s tr u c t event {
fo r the filtered PWM voltage. boolean en_a; / / true = enable LED A output
A lternatively, rather than reducing the boolean en_b; / / true = enable LED B output
PWM all the way to zero, leave it slig h tly below word duration; / / milliseconds u n til next event
the MOSFET's 0.9-V threshold to reduce the f l o a t current; / / amps - to ta l current in LED A + B
overall tra n sitio n tim e. Hage also suggested f l o a t drive_a; / / vo lts - previous drive fo r LED A
turn in g the output on, m onitoring the LED f l o a t drive b; // LED B
cu rre n t until it approaches the desired value,
};
then enabling the PWM output.
I decided to solve the problem w ith solder,
event Events[] = {
by splicing a single pole, double th ro w (SPDT)
{true, fa lse, 10, 0 200, 1. 0, 0. 0},
analog gate between the PWM filte r and the
MOSFET gate (see Figure 1). The norm ally
{fa ls e , fa lse, 20, 0 000, 0. 0, 0. 0},
closed input connects to 0 V and tu rn s the {true, fa lse, 10, 0 150, 1. 0, 0. 0},
MOSFET com pletely off, w ith the pull-down {fa ls e , fa lse, 20, 0 000, 0. 0, 0. 0},
resistor on the A rduino control signal ensuring {true, fa lse, 10, 0 100, 1. 0, 0. 0},
th a t the pin stays low until the firm w a re gains {fa ls e , fa lse, 20, 0 000, 0. 0, 0. 0},
control a fte r a hardware reset. {true, fa lse, 10, 0 050, 1. 0, 0. 0},
The gate voltage in the upper trace of {fa ls e , fa lse, 20, 0 000, 0. 0, 0. 0},
Photo 1 rises from 0 to about 1.2 V in less {true, fa lse, 10, 0 025, 1. 0, 0. 0},
than 1 |js and the corresponding drain current {fa ls e , fa lse, 370, 0 000, 0. 0, 0. 0}
tra n sitio n in the lower trace requires about
};
1 js . The direct PWM drive solution I'd been
using required nearly 10 ms fo r the same
EVENT_INDEX ( (s iz e o f(E v e n ts )/s iz e o f(s tru c t event)) - 1)
transitions.
_X
A
d
e
n
e
M
fi

Photo 2 shows th a t th e ha rd w a re
d o e s n 't look q u ite as im p re ssive as its LISTING 3
o u tp u t. R ather th a n bu ild an e n tire ly new An a rra y o f s tru c tu re s defines each LED pulse's c u rre n t and d u ra tio n . The pulse gen era tion code saves the
PCB, I s im p ly epoxied a M axim In te g ra te d PWM o u tp u t req u ire d to produce each pulse and restores it when th a t pulse happens again.
 64 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

MAX4544 SOT23-6 package a to p the

MOSFET, c u t th e gate tra c e , and soldered
the a irw ire s . This o b vio usly w o n 't w ith s ta n d
a ctual use, b u t it s u ffic e s fo r th e p ro to ty p e
and shows th a t th e idea w o rk s w ell. The
second MOSFET to the rig h t o f th e red LED
re m a in s u n m o d ifie d .
Although the analog sw itch produces crisp
transitions, it can't im prove the speed of gate
voltage changes. The main loop measures
the LED cu rre n t and adjusts the gate voltage
by one PWM count on each ite ra tio n , which
lim its both the m axim um slew rate and the
COLUMNS

loop's response to overshoot. The lower trace

in Photo 3 shows a single LED pulse, w ith the
cu rre n t sta rtin g at 50 mA and ending at ju s t
under 200 mA; the slew rate and overshoot
are painfully obvious.
However, at the end of each pulse, the
firm w a re has adjusted the cu rre nt close to
PHOTO 4 the desired level, so I modified the code, as
P resetting the PWM o utputs a t the s ta rt o f each pulse produces sharp-edged LED blinks. The o p -a m p o u tp u t shown in Listing 2, to save th a t PWM value
in the top trace scales the Hall-effect c u rre n t sensor to abo ut 1 V/100 m A, w ith the sm all bum ps between and restore it when the pulse occurs again.
pulses show ing the sensor null operation. The lower trace shows the actual LED c u rre n t a t 50 m A /d iv , w ith The firs t i f statem ent detects the end of the
the PWM ripple clearly visible. pulse, saves and restores the PWM values
th a t control the gate voltages, and then
enables the appropriate analog switches. The
d e la y ( ) function allows tim e fo r the PWM
filte rs to settle at th e ir new levels, so th a t the
gates see a step tra n sitio n when the analog
switch selects a d iffe re n t input.

PROJECT FILES
circ u itce lla r.co m /ccm a te ria ls
RESOURCES
E. N isley, "A rd u in o PWM vs
MOSFET T ra n s d u c ta n c e ” Cir­
cuit Cellar 28 4, 2014.
--------- , "Lo w -Lo ss H a ll-E ffe c t
C u rre n t S e n s in g ,” Circuit Cel­
lar 28 0, 2013.
--------- , S o fts o ld e r.c o m , "H a ll-E ffe c t C u rre n t
C o n tro l PCB: F ir s t L ig h t,” h ttp ://s o fts o ld e r .
--------- , S o fts o ld e r.c o m , "H a ll-E ffe c t C u rre n t
C o n tro l PCB: V o lta g e V a ria tio n s ,” h t t p : / / s o f t s -
o ld e r.com .
SOURCES
MAX4544 S O T23-6 Package
M a x im In te g ra te d | w w w .m a x im in te g r a te d .
com
AM 503 AC/DC c u r r e n t p ro b e a m p lifie r
T e k tro n ix , In c . | w w w .te k .c o m
PULSE SHAPING
Producing a single blink requires little
more than tw o tim in g loops th a t produce the
on and off durations, but th a t code doesn't
scale well fo r a complex sequence of blinks
w ith d iffe re n t durations, am plitudes, and
delays. The easiest way to generate a series
of events is to put the com plexity in a table
(or a rra y) and use a simple routine th a t steps
fro m one e n try to the next.
The s t r u c t e v e n t in Listing 3 defines
the values required to produce each pulse,
including its duration and total current, as
well as the delays between successive pulses.
Because the hardw are includes one current
sensor and tw o MOSFET drivers, it can sense
only the total cu rre n t in both LED strings. The
en_a and e n _ b values determ ine which
outputs w ill be active during each pulse. If
both are active, the firm w a re m ust adjust
both gate voltages.
Each e n try of the E v e n t s [ ] a rra y is a
single s t r u c t pulse defining a single pulse
or delay. The firs t i f statem ent in Listing 2
steps the E v e n tI n d e x variable to the next
e n try at the end of each pulse.
The A rduino runtim e copies the values
form ing the E v e n ts [ ] a rra y into RAM
during sta rtu p , so you could change the
pulse durations and currents on the fly.
 c ircu itce lla r.co m 65

U nfortunately, th a t means a random glitch

can trash the array. Good practice suggests ILEDSense = ReadCurrent(); / / Sample LED current
sp littin g it into tw o arrays: one in flash ROM
fo r the fixed constants th a t define the pulses / / Adjust gate drives to maintain LED current setpoint
and another in RAM fo r the variables holding
the dynam ic PWM values.
i f (ILEDSense < (Events[EventIndex].current - IDeadBand/2.0))
Homework: make it so! PWMStep = VStep;
Photo 4 shows the complete solution in
else i f (ILEDSense > (Events[EventIndex].current + IDeadBand/2.0))
action, w ith the Hall-effect sensor ou tp u t in PWMStep = -VStep;
the top trace matching the actual LED current else
(from the Tek probe) in the bottom trace,
PWMStep = 0.0;
a lbeit w ith a lower bandw idth th a t suppresses
the PWM current ripple. The analog switch VGateDriveA += Events[EventIndex].en_a ? PWMStep : 0.0;

COLUMNS
produces crisp edges w ith the preset PWM SetPWMVoltage(PIN_SET_VGATE_A,VGateDriveA);
values requiring little or no a d ju stm e n t at the
s ta rt of each pulse. VGateDriveB += Events[EventIndex].en_b ? PWMStep : 0.0;
The small bump following each pulse in the SetPWMVoltage(PIN_SET_VGATE_B,VGateDriveB);
top trace occurs when the code adjusts the
offset value th a t nulls the Hall-effect sensor delay(PWM_Settle);
output. When both LED outputs are off and no
current flows through the Hall-effect sensor,
the nulling routine ensures the op-am p output LISTING 4
is exactly zero. Even though the sensor output The LED c u rre n t control feedback loop closes th ro u g h the firm w a re 's m a in loop, w h ich adjusts the PWM value
doesn't d rift enough to require nulling a fte r by one PWM coun t when the m easured LED c u rre n t falls outside the deadband around the desired setpoint.
every pulse, there's no harm in doing so.
I f the Hall-effect sensor ou tp u t d rifts
below the offset value, the op-am p output
rem ains at zero, so the code begins the
nulling process by reducing the offset until
the op-am p output goes slig h tly positive and
then increasing the offset until it becomes
zero again. Hage suggested nulling the output
to a slight positive offset to elim inate the
need fo r p re-adjustm ent, then subtracting
th a t ze ro -cu rre n t offset fro m subsequent
m easurements. I th in k either method w ill
produce the same results, so I reused the
existing routine.
Homework: im plem ent Hage's suggestion,
perhaps w ith a deadband around the setpoint.
With all th a t in m ind, the code
in Listing 4 closes the cu rre n t feedback loop.
On each iteration of the main loop, it reads the
LED cu rrent and, if the values fall outside the
deadband, adjusts the gate voltages upward
or downward to compensate. Because V S te p
PHOTO 5
equals the voltage corresponding to a single W ith the deadband set to 25 mA, the c u rre n t control loop hunts back and fo rth on each ite ra tio n , because
PWM count, the gate voltage changes by the a single PWM co u n t changes the c u rre n t by abo ut 50 mA. The to p trace shows the c u rre n t sense a m p lifie r's
sm allest possible amount. o utput. The botto m trace shows the actual LED c u rre n t a t 50 m A /div.
I reduced the deadband's value to 25 mV
in Photo 5, which shows the loop hunting
back and fo rth on each side of the 200-m A CONTACT RELEASE
setpoint. In this situation, none of the possible Hage thinks the A rduino hardware hasn't
gate voltages produce an LED c u rre n t th a t lies come close to its lim its, but he has definitely
inside the deadband, so the cu rre n t alternates pushed it much closer to the edge. In any
between 200 and 250 mA on successive passes event, the results you see here w o rk better
through the main loop. than my original design did, so I'll call it a
I th in k the value of IG a in th a t converts success.
the op-am p output into cu rre n t is a bit too The info rm a tio n on Circuit Cellar's FTP site
low, because the cu rre n t should settle at 200 contains the new firm w a re and schematic; I
mA. Fixing th a t is a simple m a tte r of softw are, haven't revised the PCB layout to accommodate
of course. the new parts. O
 66
COLUMNS C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
ppliance m anufacturers are
Galways looking fo r new ways
to make th e ir products user frie n d ly and keep
By Jeff Bachiochi (US) up w ith the latest technology trends. Lately,
I've noticed more appliance m anufacturers
have adopted infrared (IR ) technology as an
inexpensive way fo r users to interface re ­
motely, w ith o u t having to use th e ir local con­
trols. While this doesn't help if you don't have
the IR rem ote handy or lose it between the
couch cushions, it does tend to make even an
o rd in a ry ceiling fan kind of techie.
Many universal rem ote controls (URCs)
on the m arket offer the a b ility to integrate
m ultiple rem otes into a single device or ju st
allow one to have an extra. This way, you
do n 't have to fig h t over who has control
of the rem ote. The universal remotes can
handle alm ost any fo rm a t a m anufacture
wants to use in its equipm ent. So you need
only choose the secret fo u r-d ig it code fro m a
device/m anufacture list and enter it into the
URC. An internal look-up table then provides
the correct fo rm a t param eters fo r the URC to
be able to emulate specific IR remote. What
does the list look like? For the m ost p a rt, it
isn 't public knowledge; it's kept secret by
the m anufacturer. Usually, the same code
on another URC w ill not produce the same
fo rm a t. There has been no standardization
of these codes or the form ats they represent.
This also means th a t any new fo rm a t th a t is
introduced cannot be handled by an older
URC, since the device w o n 't be in the list. If
only there was a way to describe the fo rm a t in
a more dynam ic way, changes m ight be made
w ith o u t necessarily breaking everything. I
ended last month w ith a sh o rt description of
the infrared protocol (IRP) th a t a ttem pts to
do this. The protocol is well th o u ght out and
both sim ple and complex. A single line of text,
punctuation, and values contain the complete
description of an IR transm ission by breaking
it into three pieces: GeneralSpec, BitSpec,
and IRStream.
The GeneralSpec contains basic info like
m odulation frequency, order of data (MSB/
LSB firs t), and tim e units like microseconds or
cycles. The BitSpec describes the relationship

between a b it = 1 and a bit = 0 in te rm s of
Mark (m odulated) and Space (idle) tim e units.
While m ost fo rm ats use a Mark followed by
a Space of one of tw o possible lengths to
represent a single bit (1/0), some form ats
may use m ultiple bits (e.g., one of four space
durations to represent 2 -bit possibilities
or Manchester encoding, which uses M ark/
Space or Space/Mark to represent bit values).
Lastly, the IRStream describes the data to be
transm itted using the BitSpec form at. This
consists of a list of param eters, special bits,
variables, and constants. Special bits m ight
be used in a header or other identifier, while
variables m ight be key press data and constants
product identifiers. Each value isn't necessarily
8 bits, so it has a bit count associated w ith it
and sometimes a bit starting position.
Initially, manufacturers favored transmission
form ats that offered m inim um IR modulation
times. The main object was to conserve battery
life, so unnecessary bit transmissions would be
wasteful. Today manufacturers are more likely
to send more data per transmission. Not only
is consumption less of an issue, but today's
remotes are more functional than early remotes
and require more data.
LEARN BY DOING
Some URCs use brute force to m im ic
rem otes th a t they can't duplicate. This
requires a vast am ount of m em ory since you
m ust save every tra n sitio n of IR th a t you
see in order to replicate it. While a single
transm ission may not be overburdening by
itself, m ultip ly this by the num ber of keys you
need to m im ic and you w ill quickly run out of
m em ory space.
It w asn't until I was well into this project
th a t I found the discussion of the IRP. I only
needed to figure out a few rem otes th a t I had
hanging around, so I w asn't thinking in such
general term s. However, as I dug through the
IRP spec, it became clear th a t incorporating
this fo rm a t could u ltim ate ly s im p lify the code
and be m ore useful. So, even though I had
started by coding each m anufacturer w ith its
own specialized routines, I rew rote the code
w ith a more generic tw ist.
The m ost d ifficu lt p a rt was in terpreting
each IRP fo rm a t. Each protocol is stored in a
table as a list of characters. My firs t e n try is
fo r the Sharp protocol. Let's look at this IRP.
S h a r p { 3 8 k , 2 6 4 } < 1 ,-
3 |1 ,-7 > (D :5 ,F :8 ,1 :2 ,1 ,-
1 6 5 ,D : 5 , ~ F : 8 , 2 : 2 , 1 ,- 1 6 5 )+
You can easily separate this into five parts:
1. S h a rp
2. { 3 8 k , 2 64}
c ircu itce lla r.co m 67
3. < 1 , - 3 11 , -7>
4. ( D :5 ,F :8 ,1 :2 ,1 ,-
1 6 5 ,D :5 , ~ F :8 , 2 :2 , 1 ,- 1 6 5 )
5. +
Placing the protocol name (1) along w ith
the IRP fo rm a t not only makes it easy to
id e n tify the fo rm a t in the code listing, but
also provides identification fo r any display
message you may be creating. Last m onth, I
talked about the IR transm ission itself, which
is separated into a num ber of modulated
and unmodulated tim e periods. Note th a t the
m odulation is clearly spelled out in the curly
bracket section (2) as indicated by using the
" k " thousand m ultiplier. Unless we find the
strin g MSB in p a rt 2, we can assume th a t the
o rder is LSB firs t. Any value rem aining w ill
define a unit tim e m ultiplier, 264. This defaults
to microseconds w ith o u t any value suffix. The
suffix "p " means the value is a cycle m u ltip lie r
and not a tim e unit (picosecond) as one m ight
suspect. A lack of any un it tim e should default
to a value of 1.
Part 3 indicates tw o bit tim ings (separated
by " |" ) . The firs t bit (zero) equals a Mark tim e
= 1 (tim es the unit tim e m u ltip lie r) x 264, or
264 |js, and a Space tim e = 3 x 264, or 792
|js. The second b it (one) equals a Mark tim e
= 1 x 264, or 264 js , and a Space tim e = 7
x 264, or 1848 js . A positive value is a Mark
or modulated tim e , while a negative value
denotes a Space tim e. The Sharp fo rm a t isthe
sim plest, using pulse distance m odulation, a
constant duration Mark (264 js ) followed by a
variable duration Space 792 or 1848 js .
Now comes the data fo rm a t sequence in
p a rt 4. There are 10 elements to this data:
Variable D consisting of 5 bits
Variable F consisting of 8 bits
Constant 1 consisting of 2 bits
Mark with a length of 1 x 264 or 264 j
Space with a length of 165 x 264 or 43,560 js
Variable D consisting of 5 bits
Complement of Variable F consisting of 8 bits
Constant 2 consisting of 2 bits
Mark with a length of 1 x 264 or 264 js
Space with a length of 165 x 264 or 43,560 js
Each Sharp transm ission is actually tw o
nearly identical transm issions. The variable
F is complemented in the second sequence.
This is Sharp's way of checking th a t the F
(function) data has been correctly received.
The last p a rt (5) indicates w hether the
transm ission is norm ally repeated as long
as the key is depressed. The plus sign (+)
indicates it is repeated one or more tim es.
MODULATION
While using an IR dem odulator fro n t
 68 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 C

In te rte ch n o lo g y TSMP6000 th a t w ill sense

the IR and pass the signal though w ith o u t
dem odulating it. The TSMP600 is an SMT
p a rt th a t can be easily m ounted on an eight-
pin SOIC Schm artBoard fo r easy handling
(see Photo 1). Figure 1 shows the project's
schem atic, which has a ju m p e r th a t enables
you to sw itch between devices.
To begin capturing an IR transm ission,
select F (Frequency) fro m the menu screen (see
Photo 2) using the serial te rm in a l application
RealTerm. A p ro m p t in stru cts you to press
one of the rem ote's buttons (or h it any key to
COLUMNS

cancel the operation). This sam pling routine

PHOTO 1
This is m y prototype w ith (from rig h t to left) an IR receiver d e m odu lator, IR receiver, IR LED tra n s m itte r,
and drive tra n s is to r all m ounted along the fro n t edge o f the PC board.
end (e.g., Vishay In te rte ch n o lo g y TSOP322)
sim p lifie s your life trem endously, you do
not "see" the m odulation, so you can't find
out w hat m odulation frequency your rem ote
uses by its output. To measure the actual
frequency you need a device like a Vishay
w aits fo r the firs t tra n s itio n (a falling edge)
and measures the tim e between falling edges
(whole m odulation periods). We know that
all transm issions begin w ith m odulation that
last fo r a num ber of cycles. Eventually, the
tim e m easurem ent w ill exceed a m inim um
of, say, 33 |js, which is 30 kHz. This sample
can be tossed out and all previous samples
are summed w ith the to ta l being divided by
the num ber of samples to get an average
sample tim e. The m odulation frequency is
the reciprocal of this sample tim e.
I could have used tw o separate devices
fo r th is project. In fa ct, I began w ith an IR
dem odulator and added the TSMP6000 ju s t to
measure the frequency. The p ro je ct now uses
only the latter, as a dem odulated signal can

FIGURE 1
My p roje ct's schem atic includes
a few LEDs th a t display
app lica tion status along w ith
an IR dem o d u la to r receiver, IR
receiver, and IR LED. The USB
connection is used to display
user functions like those shown
in Photo 2.
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 70 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

1 S U 'ô l I V r r ï K l i r - r i J l t - s p t i i i - f - p j o q r - a n i Ï . Ü . D . 7 0 -Id «J was sampled fo r F (Frequency) and S (Sample)

' ÿ » FT B 2 8 Î <“ □ menu items.
[9ft Confiun i c * t i o n
? - T h ii LU l
P - lifA m r r til* .I
£ — Siin p le a k e y press. FORMAT RECOGNITION
R “ Dunp Nam B a t a i n b u f f e r ■ChArk/'S'pAce c y c l e c o u n t }
C - Dunp C h a r t DaI a i n b u f f e t - ( p a i n t s t a p l o t } Last m onth, I w ent through the process of
1 - J - Dunp I d e n t i f i e d D a t a
P P i C h a Ropwte sam pling the IR w ith an IR dem odulator using
if - B u t e * * la te
[ - IB tr * n s « ii* io n 1i. 1 1 * i n b u f f i r edge triggered in te rru p ts to measure the
d tim e periods between falling edge indicating
UÜ________ __________ the s ta rt of m odulation (Mark) and a rising
Disphp Pi*1 j C-spti-ie| Pra | Send I EchoP«l | I2C | I2C-2 | I S C M b c \U bc | Je) a ° nH Freeze | _?j
edge denotes the end of m odulation and the
Slatui
fl^|«ÎQÜ 3 ^1 ^ 3 [îâ^ isd s ta rt of the idle period (Space) using a IR
Îiÿ lm » * Fk^C adiiV »®«2| demodulator. Now I'm using the TSMP6000 so
r KmQiM-|i7 Txt>|3)
I'm not seeing ju s t the presence and absence
j ï i u r î w i
Ï3 CTSI.SJ
COLUMNS

r TiWùt Mjfl Char fü of IR m odulation, but the m odulation itself. I

ocoru
CNsi» r fiTÎÆTÎ D5ht£|
f BIRi&SFir RSUhtt need to do a b it more finagling to tu rn this input
r Fi fiiBl#
If gpcAt: into Mark and Space tim ings. The frequency
ins. routine above is the key to this. That routine
veuun uwj^irr^y «uhdyrtMi te ccrtid .-*< gave us the tim e fo r one m odulation cycle.
This tim e can be used as a w indow of when to
expect either another m odulation cycle or the
PHOTO 2
This screenshot shows the m enu o f fun ctio n s th a t you can select using a serial te rm in a l p ro g ra m like
lack of one. This would indicate a transition
RealTerm via the p roje ct's serial port.
between a Mark (continuous modulation)
and Space (a lack of m odulation). The Mark
and Space tim es can be adjusted slig h tly to
be derived thro u g h code. You can sim p lify account fo r a lack of fo rtu n e telling. The S
the code by using both in p u t devices if you (Sample) d iffers fro m the F (Frequency) in
want. Note th a t m ost IR dem odulators can tw o ways. First, tim es recorded are separated
be purchased w ith th e ir filte rs centered on into Mark tim es and Space tim es. And second,
a specific frequency; however, they can be the tim es are not per m odulation cycle, but
used at other frequencies w ith a decrease in the total consecutive m odulation tim e and the
sensitivity. total lack of m odulation tim e.
The firs t check you can make on each Note th a t IR com m unication uses a return
fo rm a t is the m odulation frequency. This to zero (RTZ) data fo rm a t. Thus, both a Mark
quickly elim inates protocols th a t use other and a Space is required fo r each data bit.
m odulation frequencies. Photo 3 shows The sample buffer holds records of the Mark
display ou tp u t when an Acer ta b le t remote and Space duration tim in g using a 4-byte
sequence fo r each sample. "M ", byteU, byteH,
and byteL are fo r each Mark sample. "S",
v R e a l I p r i i i : b f - n a l I A p t è r e P / a g r a m ZJD.DlTD byteU, byteH, and byteL are fo r each Space
Looking f o r f r e q u e n c y d a t a f m n y a u r I F dev i c e sample.
t c aRwrt>
:.ï?»r4&l feüs fa n To determ ine if an IR rem ote is using
Cl!>nirAt k-nr« F i n i s h e d
S - Sa ng !l e a. lie y p r e s s the Sharp protocol (or any other protocol),
].o i3 ki n g f o r k e y d A tn f r s n g o u r IR d e w i c e c y c l e c o u n t )
if ld ÿ k e y t o a b o r t >a in b u f f e r <p o i n t ï t o p l o t ) each protocol e n try in the IRP table m ust be
1-9 - Dunp Identified Itata
Meiitiflfrd NËC3 PrôCdi&ï compared (one at a tim e) to the Sample buffer
iPPbBufccan into but tor
II i t ^ A i n s n i s a i a n o f dsiCA in b u ffer th a t holds the tim in g inform ation of the
S -l* =8 protocol in question. To do this, an IRP is read
F-S2:8
T-7D:B fro m the table and used to build a num ber of
buffers th a t w ill hold things like m odulation
E h ^ PM I tv h rtj hv | I2C-Z j liCHoc| Mik Vnl C la n il F re e - in l 11
rate, b it sequence, Mark and Space bit tim ing,
St«*
and the data elements.
~B f f l ^ SHilf y ' O ' i w P
SMMmnmbni« ___ resist Every element of a protocol is made up
r 54^01» [ïï TXÛL5? of Marks and Spaces defined in the BitSpec
& Hn tr aw: crspi
r Odd f ïjd- Srt»** Flfr»(eriiod r Tfw«* wfgyrirT^ section. Mark and Space tim es are calculated
f Cw J K tt ll
r Mat r Eh: » Ni»* r BTÎJCIÎ dsaiei fo r each potential bit value. The Sharp protocol
r î i» « r iw ( r p iB /o s n r K 4 » a RrsH
M EW
uses single bits; therefore, we have two
Enef values, b it l and bit0. Previously we calculated
these in the following way: bit0 as Mark=264
|js and Space = 792 |js and b it = 1 as Mark =
PHOTO 3
Selecting F (Frequency) w ill w a tch fo r an IR tra n s m is s io n and m easure the freq uency o f the m odulation.
264 j s and Space = 1848 js . This tells us that
This can be p e rfo rm e d w ith only an IR receiver th a t does n o t dem odulate the received signal. Selecting S
a Mark can be no sh o rte r than 264 j s and no
(Sample) a tte m p ts to recognize an IR tra n sm issio n and proceeds to list the variab le data found w ith in th a t longer th a t 264 j s (w ith an average tim e of
protocol according to the IRP. 264 js , more on this later) and a Space can
 c ircu itce lla r.co m 71

IRPSize equ 0x80

IRP0 org 0x7000

data "Sharp{38k,264}<1,-3|1,-7>(D:5,F:8,1 :2,1,-16 5 ,D:5 ,~F:8,2 :2 ,1,-165)+",0

IRP1 org IRP0+IRPS i ze

data " NEC2{38.4 k,564}<1,-1|1,-3> (16,-8,D :8,S:8,F :8,~F :8,1,-78)+ ",0

IRP2 org IRP1+IRPS i ze

data "Nokia32{36k,msb}<164,-2761164,-4451164,-6141164,-783>(412,-276,D:8,S:8,X:8,F:8,164,^100m)+",0

LISTING 1

COLUMNS
This is a code snippet fo r the IRPs I placed in m y app lica tion. IRP0 is fo r the S harp TV. IRP1 is fo r the Acer tablet. IRP2 is fo r the AT&T cable box.

be no shorter than 792 |js and no longer than bits according to the GeneralSpec section.
1,848 j s (w ith an average of 1,056 js ). I use If we make it through a protocol w ith o u t
a tolerance value along w ith each expected any samples being out of tolerance, we have
Mark or Space tim e to calculate acceptable id entified the protocol. Next, we w ill w ant to
lim its fo r each sample. If a sample falls know w hat data is produced fo r each button
w ith in the calculated acceptable lim its , the press. I t tu rn s out we are e xtre m e ly close to
process proceeds w ith the next sample and this w ith the code we have ju s t used. If we
next elem ent (or p a rt th e re o f). Any out of add one m ore routine to th is process, we are
tolerance fa ilu re is flagged and the process there. We ju s t need to gather the actual data
fo r the present protocol is abandoned. we find in the sample b u ffe r as we are going
The protocol lists each elem ent that through and testing each data b it to see if
makes up its transm ission in the IRStream it's w ith in acceptable tolerance. It tu rn s out
section. Previously we saw th a t the Sharp we can do th is w ith in the tolerance testing
protocol uses tw o variable elements (D and routine fo r variables. Remember when I
F), a constant elem ent, and Mark and Space m entioned the average b it tim e above? A fte r
elements. Mark and Space elements are testing a sample fo r tolerance, a second te st
s tra ig h t fo rw a rd and we can easily determ ine is done on the sample using the average
w hether a sample tim e falls w ith in a Mark
or Space tolerance. But firs t we need to deal
w ith the variable and constants. A variable
0 - Sharp Protocol
elem ent has a b it count associated w ith it. 1 HEC2 P r o t o c o l
2 - Protocol
The firs t elem ent D in the Sharp protocol has 3 - JtCS Protocol
5 bits. This means th a t we w ill need to check HE&Z Protecel
01 - p S M C -r
fo r 5 Mark and Space samples fo r th is variable. - n in u s
The next elem ent, variable F has a bit count “
■■
p
p
lu s
p e v ia u s
of 8. So the next 8 Mark and Space samples - p i
6 - netx!
m ust be checked to cover this element. The ? ~ tele
ft - k l Itr
th ird elem ent is a constant value of 1 w ith a
fl ^ up
b it count of 2. With a variable we do n 't know B - left
if any p a rticu la r b it w ill be a b it l or a bit0 ‘ ” rak
D - rig h t
IE - io w r»
so we m ust te st fo r m axim um and m inim um
tim es. With a constant we know exactly w hat
the bits should be and w here, so we can test
(C *»w |fVt j | CGtaPoi | ift | tacwitt ] M«t L Claarj Fmt)*»| _>J
accordingly. A value of 1, w hich is represented
r SUlK
by tw o bits, would be 01, a bit0 followed by I- pwtrwnwdf _:Om fvwt
a bit1. Next, the protocol has a Mark element r |rwefl ¿Hdi fiMJCI
P :■■: 13»
and a Space elem ent. You may have observed CTSpj
th a t the same elem ents are repeated again By»! j? i j
w ith slight differences in variable F and &
f£ i‘ r Spif c * J DSRJE|
fir * »
the constant. Finally the + indicates that BREAK
f
this whole shebang (transm ission) could be r Hat C hoi

repeated again. In fact, if sample buffer's T th j i v - K X c o u ltK r i t o c n A r u J m ol On ¿mrt:I*',

size is su fficie n t, m ultip le transm issions will
be sampled and can be decoded. One last
PHOTO 4
thing to point out here. The Sharp protocol
Tables fo r each re m o te w ere added to the app lica tion a fte r sam pling all o f the rem o te's buttons. Here's the
defaults to an LSB firs t sequence fo r data bits data listed fo r the Sharp TV based on sam pling those buttons. F inally, you can use P (Pick) and B (B utton )
w ith in each elem ent. You m ust reverse the m enu selections to m ake use o f the d a ta , fir s t to pick a re m o te and then a butto n to em ulate.
 72 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0
ABOUT THEAUTHOR
J e ff B a c h io c h i ( p r o n o u n c e d B A H -ke y-A H -
key) has been writing fo r C ir c u it C e l­
la r s in c e 1 9 8 8 . His b a c k g r o u n d in c lu d e s
p ro d u c t d e s ig n and m a n u f a c t u r i n g . You
ca n r e a c h h i m a t j e f f . b a c h i o c h i @ i m a g i n e
t h a t n o w . c o m o r a t w w w .im a g in e t h a t n o w . c o m .
COLUMNS
tim e. Any sample th a t is less than average is a
bit0. More than average is a b itl. We ju s t need
to store this into the rig h t variable at the right
bit position and continue. Like variables should
have equal data. Complemented variables
should have complemented data. Now, if a
protocol is identified, you already collected
all the variable data th a t corresponds to a
particular key press.
BUTTON DATA
The C (Chart) function lets me make good
use of Michael Vogt's DatPlot. Using DatPlot,
I can visually see w hat an IR device is
sending and deduce which protocol I needed
to support. With the general outline fo r IRP
interpretation complete, adding additional
protocols sometimes requires a m inor tweak
to the identification routines. I can't imagine
tryin g to do this w ith o u t the benefit of having
actual hardware to w o rk with.
Once my S routine was recognizing a
protocol and reporting variable data, I needed
to create a list of all the keys on the remote,
use the S routine on each button to map the
variable data values fo r each. I'll need a list
fo r each remote I w ant to m im ic and add it to
this application to be able to reproduce each
remote's button-related data transm ission. The
IRP describes a remote's protocol but does not
indicate which keys and associated data values
make up a remote (see Listing 1). I suppose
if you don't have a rem ote, you could use trial
PROJECT FILES w w w .d a tp lo t.c o m .
PIC18F2320 M ic ro c o n tro lle r
M ic ro c h ip T e chno lo gy, In c . | w w w .m ic o c h ip .c o m
SFH4547 IR E m itte r
OSRAM O p to S e m ic o n d u c to rs ! w w w .o s ra m -o s .
com
c irc u itce lla r.co m /ccm a te ria ls
TSOP322 x x and TSMP6000TR IR R eceiver
SOURCES modules
DatPlot
V ishay In te rte c h n o lo g y , In c . | w w w .v is h a y .c o m
A e ro P e rf (M ich ael V ogt) |
and e rro r by sending out transmissions w ith
each possible data value and w aiting to see if
it produces a function on the equipm ent. You
may even find some undocumented function
that a rem ote would not norm ally give access
to! For this project, I started w ith a list of
any buttons fo r a rem ote th a t produced an
IR transm ission fo r a specific protocol. For
instance, my URC has a num ber pad and the
buttons produce output fo r the television and
not fo r the cable.
Producing IR requires adding an IR LED to
the hardware. While the Microchip Technology
PIC18F2320 m icrocontroller I am using can
provide 25 mA of current, I added a drive
transistor capable of supplying more current
to the OSRAM Opto Semiconductors SFH4547
IR transm itter. This device can handle 100 mA
and up to 1 A at modulated frequencies. Up
to this point, I haven't specifically mentioned
IR duty cycle, ju s t modulation frequency.
Early rem ote m anufacturers noted they could
improve battery life by shortening the "on"
portion of the modulation duty cycle. Since
current consumption is directly proportional
to the am ount of tim e an IR LED is on,
reducing the duty cycle from a nominal 50%
to 25% doubles battery life (at least that
portion directly attributed to transmissions).
While an IR receiver may still operate under
these conditions, the m axim um transmission
distance will be affected. I am using the
m icrocontroller's PWM function to provide
a modulated output to the IR LED, so I can
easily set the duty to any value of choice. The
PWM function is enabled to provide modulated
output fo r Mark tim ing and disabled providing
no output fo r Space tim ing.
Two additional routines were added to this
application. The firs t, P (Protocol), enables
you to choose from a list of the supported
protocols. Photo 4 shows the serial display for
the menu item P, the list of protocols, followed
by a list of button options using menu item
B. P interprets the IRP, as I discussed earlier,
in the S function used to tr y and match a
protocol against a recorded sample. The
same inform ation is required to reproduce
an IR transm ission (e.g., modulation rate, bit
sequence, bit tim in g , and a list of elements).
This tim e we will not be gathering data values;
we w ill be providing data values. These values
come from the second function, B (Button).
This function brings up a list of buttons
associated w ith the chosen protocol. Listing 2
is a code snippet that defines the Sharp remote
functions. Once a button choice is made, the
data elements associated w ith the chosen
button are loaded into th e ir related variables.
Next, we construct bit tim ings using the sample
buffer in the same fo rm a t as S transmissions,
M, byteU, byteH, byteL and S, byteU, byteH,

byteL. By following the list of elements
prepared by interpreting the IRP, we should
be able to reproduce the original transmission.
Once all the tim ings inform ation is present, a
final routine reads through the buffer enabling
and disabling the PWM function, producing
Mark and Space tim es th a t create an authentic
IR transmission.
I was not surprised to find th a t my
transm issions did not operate any of my
equipm ent. Where do I start? Since the form at
of the sample buffer data is identical fo r the
S and B functions, the C function can be used
to display what's there. If I reproduced data
correctly, the graphs of both should be the
same. Again, I was not surprised when I saw
tw o different graphs. It d id n 't take too much
w ork to figure out w hat was going on.
The hard part is done: identifying the
protocol from a graph. Knowing the protocol
allows you to identify actual data values
from a graph. By comparing the data values
each graph represents, you should be able to
determ ine the error's location. For example,
my error was in the bit sequencing. While I
shifted the data correctly, note that the earlier
discussed Sharp fo rm a t consists of a 5-bit
variable D. I forgot to sh ift 0s fo r the last 3-bit
used bits. My value 00001 looked like 00001000
and not 00000001.
SUCCESS
Until I started this project, I w asn't using
my Acer 7" tablet solely as a storage device for
my music collection because it came w ith an
IR remote and I thought I'd make use of it. I
added the NEC32 fo rm a t it uses to this project.
With Realterm running on the PC, I can instruct
the project to select and play music from the
Acer. All right! Now for the real test, the cable
and TV located in my den.
I often sit in fro n t of the tube and pluck on
a laptop while watching cable programming
on our ancient CRT TV. (I've yet to purchase
an HDTV. If it ain't broke, don't replace it.) My
wife Beverly seems to be getting a little hard
of hearing. She likes flipping the channels and
upping the volume past my com fort level.
So, tonight I connected up this project to my
laptop and kept the circuit out of sight while I
did my normal investigative surfing. Every once
in a while, I issued a few VOL- commands. It
didn't take her long to boost it back up, but
this went on fo r a while before she made a
comment about the cable company. I let these
pass and changed tactics. This tim e I kept
sending commands to change to my favorite
channel, "NASA select." Wowsers! This was my
downfall. I should have selected something like
the shopping channel. She quickly realized that
I was somehow involved w ith this evil trickery.
She's a good sport.
c ircu itce lla r.co m 73
IRPButtonSizeequ 0x10
IRPOButtonsequ D’ 14’
IRP0_Power org 0x7400 ; Sharp
db "D ",0x01," F " , 0x16,0
IRP0_V0LPLUS org IRP0_Power+IRPButtonSize
db "D ",0x01, " F " , 0x14,0
IRP0_V0LMINUSorg IRP0_V0LPLUS+IRPButtonSize
db "D ",0x01, " F " , 0x15,0
IRP0_ENTER org IRP0_V0LMINUS+IRPButtonSize
COLUMNS
db "D ",0x01, " F " , 0xF7,0
IRP0_MUTE org IRP0_ENTER+IRPButtonSize
db "D ",0x01," F " , 0x17,0
IRP0_TV org IRP0_MUTE+IRPButtonSize
db "D ",0x01, "F",0xFC,0
IRP0_INF0 org IRP0_TV+IRPButtonSize
db "D ",0x01, " F " , 0x1B,0
IRP0_D0WN org IRP0_INF0+IRPButtonSize
db "D ",0x01, " F " , 0x58,0
IRP0_UP org IRP0_D0WN+IRPButtonSize
db "D" ,0x01, " F " , 0x57,0
IRP0_LEFT org IRP0_UP+IRPButtonSize
db "D" ,0x01, " F " , 0xF5,0
IRP0_RIGHT org IRP0_LEFT+IRPButtonSize
db "D ",0x01, "F",0xF6,0
IRP0_0K org IRP0_RIGHT+IRPButtonSize
db "D" ,0x01, " F " , 0xF7,0
IRP0_MENUorg IRP0_0K+IRPButtonSize
db "D ",0x01, " F " , 0x20,0
IRP0_TV_VIDEOorg IRP0_MENU+IRPButtonSize
db "D ",0x01, " F " , 0x13,0
LISTING 2
Here is a code snip p e t o f the butto n en trie s fo r the Sharp TV. W hen used w ith the cable box, only volum e
controls are necessary. The TV_Video butto n cycles th ro u g h the a u x ilia ry TV inputs, w hich is useful for
selecting the DVD player.
To reduce the workload on this project, I
added only the protocols fo r which I have
remotes. This means that this project does
not tout com patibility w ith every remote out
there. It is an educational tool developed for
my requirem ents and may require extra w ork
if you want to add additional form ats. There is
certainly plenty of room for that.
This IR project, while not the end of this
story, stands on its own. I am planning to
morph this project into something else. Are you
curious? Stay tuned. O
 74 C I R C U I T CE LLA R • S EP TE MB ER 2 0 1 4 # 2 9 0

CROSSWORD SEPTEMBER 2014

The answers will be available at circuitcellar.com/crossword.

10

11
TESTS & CHALLENGES

12 13

14 15

16

17

ACROSS DOWN
2. T rivalent valence 1. PCB path
3. Kilby's Noble Prize in 2000 3. Quick fix
5. Converts DC to AC 4. Used to m o n ito r ne tw o rk tra ffic
8. BAT file 6. A Gauss is one of these per square centim eter
9. Founded ARRL in 1914 7. "Big Blue"
10. If you are AFK, w hat are you away from? 8. "An Investigation of the Laws of T hought" (1854)
11. Un iversity th a t housed the ENIAC in a 30' x 40' room 13. Move fro m setting A to B
12. 1 cycle per second 15. Screen of death
14. 4 bits 16. A nonet is a group of what?
17. Asi mov was the great what? 17. Exawatt
 circuitce lla r.co m 75

What's your EQ? The answers are posted at w w w .circu itce lla r.co m /
ca te g o ry/te st-yo u r-e q /. You can contact the quizm asters at
eq@ circuitcellar.com .

TEST YOUR EQ
Contributed by David Tweed

PROBLEM 1
What is an R-C snubber, and w hat is a typical application fo r one?

PROBLEM 2
How do you pick the resistor value in an R-C snubber?

PROBLEM 3
How do you pick the capacitor value in an R-C snubber?

PROBLEM 4
What additional concern is there w ith regard to an R-C snubber when sw itching AC power?

TESTS & CHALLENGES

76 C I R C U I T CELL AR • S EP TE MB E R 2 0 1 4 # 2 9 0

CC SHOP

Programming 1 PC PROGRAMMING 4 RFID MIFARE AND

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Many d iffe re n t PC program m ing CONTACTLESS CARDS IN
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c ircu itce lla r.co m 77
CC SHOP
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The Future of 3-D

Printed Electronics
By Dr. Martin Hedges

T hree-dimensional (3-D) printing for prototyping has been around for nearly three decades
since the introduction of the first SL systems. The last few years have seen this technology
receiving considerable attention to the point of hype in the mainstream media. However,
there is a new emerging 3-D printing market that is increasing in importance: 3-D printed
electronics (3-D PE). Whilst traditional 3-D printing builds structural parts layer by layer, 3-D
PE prints liquid inks that have electronic functionality on to existing 3-D components. 3-D PE
is achieved by combining advanced printing technologies, such as Aerosol Jet, with specially
designed five-axis systems and advanced software controls that allow complex print motion
to be achieved. The integrated print systems allow the full range of electronic functionality
to be applied: conductors, semiconductors, resistors, dielectrics, optical, and encapsulation Photo 1
materials. 3-D PE d e m o n s tra to r—T a n k -fillin g sensor produced
These can be printed on to virtually any surface material of almost any shape. Once deposited in the FKIA p ro je c t funded by the Bavarian Research
the inks are post processed: sintered, dried, or cured to achieve their final properties. Multiple Foundation (C ourtesy o f Neotech AMT G mbH)
materials can be printed to build up functionality, or surface mount devices (SMD) can be added
to make the final electro-mechanically integrated system (see Photo 1). In this example, two
capacitive sensor structures have been printed on the ends of an injection-molded PA6 tank. The
TECH THE FUTURE

sensors are connected by a printed circuit (conductive Ag) and SMD components are added to
complete the device. When water is pumped into the tank, the sensors register the water level as
it rises, lighting the LEDs to indicate the fill level. When the tank compartment is full, the circuit
senses the water fill level and reverses the pump direction.
3-D PE has the potential to provide enormous technical and economic benefits in comparison
to conventional electronics based on 2-D printed circuit boards. It allows the combination of
electronic, optic, and mechanical functions on shaped circuit carriers. Therefore, it enables entirely
new product functions and supports the miniaturization and weight-saving potential of electronic
products. By eliminating mechanical components, process chains can be shortened and reliability
Photo 2
is increased. As a digitally driven, additive manufacturing process materials are only applied where
3-D chip packaging (Courtesy o f F raunhofer IKTS)
needed, improving the ecological balance of electronics production. With no fundamental limitation
on substrate material, the user is able to select low-cost, easy-to-recycle and more environmentally
friendly materials. The novel design and functional possibilities offered by 3-D PE and the potential
for rationalization of production steps indicate a potential quantum leap in electronics production.
Advances in this field have been rapid since the first developments that focused on 3-D chip
packaging. In this field, printing is conducted over small changes in z-height to connect SMDs.
Photo 2 shows an example where wire bonds are replaced by printing interconnects, from the PCB,
up the side of a chip, and over onto the top contact pads. Such applications only require relatively
simple print motion. The current "state of the a rt" is to use five axes of coordinated motion to
print high complex shapes. This capability enables the production of truly 3-D PE systems, such
as a 3-D antenna for mobile devices (see Photo 3). This application is well advanced and moving
Photo 3
towards high-volume mass production driven by the benefits of a flexible manufacturing, novel
3-D p rin te d antenna (Courtesy o f Lite-O n Mobile)
design capabilities, and cost reduction compared to the current methods based on wet chemical
plating processes. 3-D PE is also being scaled to print on large components beyond the size range
possible with current manufacturing methods. For example, in the automotive field, 3-D prints of
heater patterns are being developed for molded PC windscreens of up to 2 m x 1 m in size.
Currently, 3-D PE applications are mainly limited to circuits, antennas, strain gauges, or sensors
using conductive metal as the print media with additional electronic functionality being added as
SMDs. However, the technology also has the potential to leverage new material and process
developments from the printed and organic electronics world. In this field, many different material
systems are currently being applied on planar surfaces to create multi-material and multi-layer
devices. Functionality such as resistors, capacitors, sensors, and even transistors are being
incorporated into fully printed 2-D electronic systems. As these print materials and processes
mature, they can be adapted to 3-D applications. It is expected that the coming years will see a
rapid increase in the range of fully printed 3-D electronic devices of novel functionality. ©

Dr. Martin Hedges (mhedges@neotech-amt.com) is the Managing Director o f Neotech A M T GmbH based in
Nuremberg, Germany. His research includes aspects o f additive manufacturing, materials and processes. His
company projects focus on the development o f integrated manufacturing systems for 3-D printed electronics..
 eerin
embedded
electronics

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