M Tech Microelectronics, WILP

REJESH N.A.
Assistant Professor
BITS Pilani Department of Electrical & Electronics Engineering
Bangalore (Off-Campus)
Pilani Campus
 BITS Pilani
Pilani Campus

MELZG 625:
Advanced Analog Mixed Signal Design

Lecture 8
Sample and Hold Circuits

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Sample and Hold Circuits

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Minimize error

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Another approach

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Error due to finite slopes

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Another Modification

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Disadvantage

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Solution

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Improved S/H

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Advantages

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CMOS S/H Circuits

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Another S/H Architecture

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SC Sample and Hold

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A recycling S/H

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Hold Mode

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BITS Pilani, Pilani Campus
Another switched capacitor S/H

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Hold Mode

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Switched Capacitor S/H and LPF

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Translinear Gain cells

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Working

BITS Pilani, Pilani Campus

Working

BITS Pilani, Pilani Campus

Working

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Translinear Multiplier

BITS Pilani, Pilani Campus

Working

BITS Pilani, Pilani Campus

Working

BITS Pilani, Pilani Campus