Lecture 3:

The 80x86 Microprocessor

Dara Rahmati

Microprocessors and Assembly 1

 anvae sakhtar ha vaseye bus mitune vojud dashte bashe
har bus shamele address bus data bus va control bus has

Single-bus Structure
kolan yek bus vase ertebatat dare
peroformance kamtar
tedad pine kamtar vali

Address Bus

IO device
CPU RAM ROM I/O ports
IO device

Data Bus

Control Bus

A bus connects all modules

• pro：simple
• con：poor performance in terms of throughput

Microprocessors and Assembly 2

 CPU-Central Dual-Bus Structure 2 bus darim va cpu dar markaze
memory joda vasle io joda
khubish ine k data transfer sari taro behine tare va jloye hamo nmigirn
badish ine k age io bkhad ba memory dar ertebat gharar bgire in etefagh bayad az dakhele cpu bashe chon khodeshun b ham vasl nistan>>performnce e cpu pain miad

I/O bus
CPU
Memory I/O ports I/O ports I/O ports
bus

Memory
IO device IO device IO device

• A dedicated bus between CPU and memory, and a dedicated bus between CPU
and I/O devices
• pro：efficient in terms of data transfer
• con：information between memory and I/O devices has to go through CPU.
Therefore, poor CPU performance

Microprocessors and Assembly 3

 Memory-Central Dual-Bus Structure
memory markaz bashe
badish ine k hazinash bishtare va memory pichide tare
I/O bus

Memory I/O port I/O port

CPU Memory
bus

• Gain both High CPU IO device IO device

performance and data transfer
throughput

Microprocessors and Assembly 4

agar baraye memory va io az bus e moshtarak estefade konim chtori b memory va io dastresi peyda konim
age khastim ham az memory bkhunim ham az keyboard ye reg ro bkhunim chtori inkaro bokonim

Memory-mapped I/O
ye decoder k msln bge az 0 ta 500 vase MEM age 500 ta 1000 bud vase IO
yani ba hamun mechanismi k ba memory dar ertebatim ba hamun ba io dar ertebatim

Address
Address Memory

CPU Address chosen

decoder
chosen I/O
address

Microprocessors and Assembly 5

 Isolated I/O
instruction ha dg mese ghabli nis va fargh mikone ba ham

ye rah ine k 2 seri bus asln dashte bashim mitune hm moshtarak bashe ama ye pin baraye choose krdn dashte bashim

MA address
Address Memory address Memory
chosen
CPU CPU

IOA address I/O address I/O

chosen

pas hamzaman nmishe ham ba io va memory dar ertebat bud

Dedicated address lines Multiplexing address lines

What is the essential difference between the memory-mapped

and isolated I/O addressing schemes? agar k bus ha joda bashe obviously tu performance

Microprocessors and Assembly 6

 Addressing scheme to accessing
memory and I/O modules
• Memory-mapped I/O
– One single address space for both memory and I/O
– Status and data registers of I/O modules are treated
as memory locations
– Using the same machine instructions to access both

• Isolated I/O
– Two separate address spaces for memory and I/O
modules mamulan ba shomare port kar mikone

– Using different sets of accessing instructions

Microprocessors and Assembly 7
 CPU Performance
• There are two ways to make the CPU process
information faster:
– Increase the working frequency
• Technology dependent, cost, number of trans., Packing
many functionalities in a single chip, packaging ,…
– Change the internal architecture of the CPU to
perform parallel tasks which is known as
pipelining

Microprocessors and Assembly 8

 Internal Structure of 8086
ba estefade az pipeline k 2 stage bishtar nadash
yeseri reg vase address dehi vojud dare
yeseri dg baraye dade ya index haye
dade

address generation anjam mishe ertebat ba memory anjam mishe…

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions already BIU fetches instructions,

fetched by the BIU. reads/writes data from/to memory
and I/O ports.
BIU and EU functions separately.
Microprocessors and Assembly 9
 Pipeline vs. Nonpipeline

• Note: In 8086 it does not imply the amount of

time for fetch and execute are equal!
• In more powerful computers pipelining can have
many stages

Microprocessors and Assembly 10

 Bus interface unit vs. Execution unit
• The BIU accesses memory and peripherals
• At the same time the EU executes instructions
previously fetched baraye zakhireye instruction ha

• The BIU of the 8088/86 has a buffer, or queue

• If any instruction takes too long to execute, the
queue is filled to its maximum capacity and the
buses will sit idle
• The BIU fetches a new instruction whenever the
queue has room for 2 bytes in the 6-byte 8086
queue, and for 1 byte in the 4-byte 8088 queue

Microprocessors and Assembly 11

 Branch Penalty
• In some cases, the microprocessor
must flush out the queue.
• For example, when a jump
instruction is executed
• The BIU starts to fetch new
instructions from the memory
• The queue that was fetched
previously is discarded.
• The EU must wait until the BIU
fetches the new instruction
– Known as branch penalty
Microprocessors and Assembly 12
 Registers
• In the CPU, registers are used to store
information temporarily
• That information could be one or two bytes of
data to be processed or the address of data
reg ha tu 8086 koln ya 8 bitn ya 16 bit

• The registers of the 8088/86 fall into the six

categories, some 8-bit and some 16-bit

Microprocessors and Assembly 13

Six Categories of Registers in 8086/88

The general registers can be accessed as the full l6 bits (such as AX), or as
the high byte only (AH) or low byte only (AL).

Microprocessors and Assembly 14

 Types of Registers
• Different registers in the 8088/86 are used for
different functions
• Some instructions use only specific registers to
perform their tasks.
• The first letter of each general register indicates
its use.
– AX is used for the accumulator,
– BX as a base addressing register, bishtar baraye mohasebate ba aaraye

– CX is used as a counter in loop operations, and mamulan baraye countere loop

– DX is used to point to data in I/0 operations

Microprocessors and Assembly 15
 Assembly Language
majmuei az dastrat k ba mnemonicashun neshun dade mishan

• A CPU can work only with 0 and 1 binary numbers

• It can do so at very high speeds
• But, it is quite tedious and slow for humans to deal
with 0s and 1s in order to program a computer
• A program that consists of 0s and 1s is called machine
code (using machine language constructs)
• Assembly languages were developed, which provide
mnemonics for the machine code instructions mnemonics hamun jamo menhao…

• Mnemonics are easy to remember abbreviations

• They made programming faster and less prone to error

Microprocessors and Assembly 16

 Assembly to Machine Code Conversion
farghe assembler o compiler

• Assembler is a program used for this conversion

• Assembly language is referred to as a low-level language because it deals directly
with the internal structure of the CPU in contrast to high-level languages

• High-level languages (like C) are translated into machine code by a program called a
compiler
e.g. using a C compiler to translate the program into machine language.
• There are many assemblers available for translating 80x86 Assembly language
programs into machine code. One of the most commonly used assemblers, DEBUG
(Appendix A), MASM by Microsoft, others TASM, NASM, FASM, …

Microprocessors and Assembly 17

 Assembly Language Programming
• An Assembly language instruction consists of a
mnemonic (the instruction), optionally followed
by one or two operands (the data items)
• The move and add instructions:
MOV destination,source
ADD destination,source
examples:
MOV DX,CX
ADD DX,CX

Microprocessors and Assembly 18

 Other examples
8-bit operation
• MOV CL,55H ;move 55H into register CL
• MOV DL,CL ;copy the contents of CL into DL (now DL=CL=55H)
• MOV AH,DL ;copy the contents of DL into AH (now AH=DL=55H)
• MOV AL,AH ;copy the contents of AH into AL (now AL=AH=55H)
• MOV BH,CL ;copy the contents of CL into BH (now BH=CL=55H)
• MOV CH,BH ;copy the contents of BH into CH (now CH=BH=55H)
16-bit operation
• MOV CX,468FH ;move 468FH into CX (now CH=46,CL=8F)
• MOV AX,CX ;copy contents of CX to AX (now AX=CX=468FH)
• MOV DX,AX ;copy contents of AX to DX (now DX=AX=468FH)
• MOV BX,DX ;copy contents of DX to BX (now BX=DX=468FH)
• MOV Dl,BX ;now Dl=BX=468FH
• MOV Sl,Dl ;now Sl=Dl=468FH
• MOV DS,SI ;now DS=Sl=468FH
• MOV BP,DI ;now BP=Dl=468FH
Microprocessors and Assembly 19
 Exceptions
• In 8086, data can be moved among all the
registers except the flag register.
MOV FR,AX
• Data can not be moved directly into segment
registers DS,CS,ES,SS
MOV DS,2341 H, MOV CS,3F47H
• Solution:
MOV AX,2345H
MOV DS,AX
age bkhein mostaghiman immidiate berizin ba AX in karo bayad krd

Microprocessors and Assembly 20

 ADD Instruction
• ADD destination,source
adds the source operand to the destination
• Example
MOV AL,25H ;move 25 into AL
MOV BL,34H ;move 34 into BL
ADD AL,BL ;AL= AL+ BL
Result:
AL= 59H (25H + 34H = 59H)
• Another way:
MOV AL,25H
ADD AL,34H
(25H and 34H are called immediate data)

Microprocessors and Assembly 21

 Program Segments
• A typical Assembly language program consists
of at least three segments:
– Code segment: contains the Assembly instructions
– Data segment is used to store information (data)
that needs to be processed
– Stack segment is used to store information
temporarily

Microprocessors and Assembly

 Program Segments
umdn ino taghsim krdn chon tu 8086 1mb khune dare >> 20 bit baraye address darim k hala umde uno 64 kb tai krdn amalan
segment segment krdn k ba 8085 compatible bashan

• A segment is an area of memory that includes up

to 64K bytes and begins on an address divisible
by 16 (ends in 0H) 64 kbyte segment > 16 bit mitune kolesho address dehi kone

Max Segment size 64KB  8085 can address a max of 64K bytes
• This limitation was carried into the design of the 8088/86 to
ensure compatibility with 8085
• 8088/86 can only handle a maximum of 64K bytes of code and
64K bytes of data and 64K bytes of stack at any given time
How to move this window of 64K bytes to cover all 1 megabyte of
memory in 8088/86!?

Microprocessors and Assembly 23

 Types of addresses

• In 8088/86 literature, there are three types of

addresses: 20-bit address that is actually
put on the address pins of the
– the physical address 8086 microprocessor, actual
physical location in RAM or
– the offset address ROM, 00000H-FFFFFH`
b tedade pin ha k chon tash
– the logical address 1mg e bayad 20 bit dashte
bashim >> addresse vagheie

Is a location within a 64K-byte

segment range. Therefore, an
offset address can range from
The logical address 0000H-FFFFH.
consists of a segment tu har segment address ro b nesbate
avale un segment neshun mide k
value and an offset chon harkodum 64kb e ba 16 bit e

address
un addressi k tu barname nevisi estefade mishe >> zoje moratabi az segment address o offset
Microprocessors and Assembly 24
 Code Segment, Logical Address
4bit seg / 16 bit offset ye raheshe ama chon nmikhastan knare ham bashan hatman segment ha vase hamin azin rah estefade nkrdn

• To execute a program, the 8086 fetches the

instructions (opcodes and operands)
from a code segment in memory
• Logical Address of an Instruction:
code segment ham 16 bit k tu jahaye mokhtalef bashe instruction pointer >> 16bit >> kojaye segment

CS:IP >> logical address

hamvare b 16 ghabele taghsime

• The physical address for the location of the instruction

is generated by shifting the CS left one hex digit and
then adding it to the IP (offset address) 25
Microprocessors and Assembly
baraye residn b physical seg code seg ro tahesh 4 ta 0 ezafe mikoni bad ba offset jam mikoni
 Logical Address
• Example:
– Logical Address:
CS:IP 2500:95F3H
– Physical address:
25000H+95F3H=2E5F3H
Q: What happens if the desired instructions are located
beyond these two limits?
A: The answer is that the value of CS must be
changed to access those instructions.

• IP is between 0000H and FFFFH,

– The logical address range in this example is
2500:0000 to 2500:FFFF.
– The Physical address range between
25000H (25000 + 0000) and 34FFFH (25000+ FFFF)
26
Microprocessors and Assembly
 Example
• If CS= 24F6H and IP= 634AH, show:
– (a) The logical address
– (b) The offset address
– (c) The physical address
– (d) The lower range
– (e) The upper range of the code segment
• Solution:
– (a) 24F6:634A
– (b) 634A
– (c) 2B2AA (24F60 + 634A)
– (d) 24F60 (24F60 + 0000)
– (e) 34F5F (24F60 + FFFF)
age ja akharin k inja h e 0 bzari mishe avale address pas vase lower va upper + 0000/FFFF mikonim

Microprocessors and Assembly 27

 Advantages of Segmentation
• Compatibility with 8085
• Provides a powerful memory management mechanism
• Data/Stack/Code related operations may perform in
different segments shayad overlap dashte bashan ama logically az ham joda shodan

• Easily share data between processes/programs

• Extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an
addressing capability of 1 Megabytes. Without
segmentation, it would require 20 bit registers.
• Enhance the memory size of Data/Stack/Code segments
beyond 64 KB by allocating more than one segment

Microprocessors and Assembly 28

 A Program Example
The following Assembly language instructions have been assembled
(translated into machine code) and stored in memory.
Physical Machine
address code contents
Assembly Machine Logical 11420 BO
11421 57
Language Address 11422 B6
MOV AL,57 B057 1132:0100 mamulan az 100 shoru
mishe tu 8086
11423 86
11424 62
MOV DH,86 B686 1132:0102 chon machine code ha 2
bytie dota dota ezafe 11425 72
mishe 11426 89
MOV DL,72 B272 1132:0104 11427 D1
MOV CX,DX 89D1 1132:0106 11428 88
11429 C7
MOV BH,AL 88C7 1132:0108 1142A 63
11426 9F
MOV BL,9F B39F 1132:010A 1142C 64
1142D 20
MOV AH,20 B420 1132:010C 1142E 01
ADD AX,DX 01DO 1132:010E 1142F DO
11430 01
ADD CX,BX 01D9 1132:0110 11431 D9
11432 05
ADD AX,1F35 05351F 1132:0112 11433 35
inja in instruction sizesh ba baghie fargh dare va 3 bytie vase hamin
addresse instruction e badi bayad 115 bashe 11434 1F

Microprocessors and Assembly 29

 A Code Segment Example
Assume that a program is being written to add 5 bytes of data, such as 25H,
12H, 15H, lFH, and2BH

MOV AL,00H ;initialize AL In this program, the data and code are
;add 25H to AL mixed together in the instructions.
ADD AL,25H
ADD AL,12H ;add 12H to AL the idea arose to set aside an area of
ADD AL,15H ;add 15H to AL memory strictly for data
ADD AL,1FH ;add 1FH to AL
This area is called Data Segment
ADD AL,2BH ;add 2BH to AL Like code segment we have:
DS:offset
Example: 5000:1950
Physical: 50000 + 1950 = 51950

mitunim bjaye faghat code segment ye Data Segment dashte bashim k dade ha untu bashe va intori addresse dade ha b dast miad va komak mikone b segmentation k un khavaso
dasht
Microprocessors and Assembly 30
 Rewriting the Program
Using Data Segment
Assume that the offset for the data segment begins at 200H.
The data is placed in memory locations:

DS:0200 = 25
DS:0201 = 12
DS:0202 = 15
DS:0203 = 1F
DS:0204 = 26

the program can be rewritten as follows:

tu krushe mishe addresse 200 e data segmentemun va mohtavaro ba AL jam mikone

MOV AL,0 ;clear AL

ADD AL, [0200] ;add the contents of DS:200 to AL , [] shows the base address
ADD AL, [0201] ;add the contents of DS:200 to AL
ADD AL, [0202] ;add the contents of DS:200 to AL
ADD AL, [0203] ;add the contents of DS:200 to AL
ADD AL, [0204] ;add the contents of DS:200 to AL

Microprocessors and Assembly 31

 hal harseri b jaye estefade az address miaim az moteghayer inkaro mikonim

Improve the program

MOV AL,0 ;initialize AL
MOV BX,0200H ;BX points to the offset addr of first byte
ADD AL,[BX] ;add the first byte to AL
INC BX ;increment BX 1 unit to point to the next byte
ADD AL,[BX] ;add the next byte to AL
INC BX ;increment the pointer
ADD AL,[BX] ;add the next byte to AL
INC BX ;increment the pointer
ADD AL,[BX] ;add the last byte to AL

Why BX? The 8086/88 allows only the use of registers BX, SI,
and DI as offset registers for the data segment.

Note1: BX is used as a pointer

Note2: CS uses only the IP register as an offset
Note3: Repeated pattern
bade cs: hamishe ip ie ama bade ds: mitune bx ya si ya di bashe
Microprocessors and Assembly 32
 Little Endian / Big Endian Convention
MOV AX,35F3H
;load 35F3H into AX
MOV [1500],AX
;copy the contents of AX to offset 1500H
chon 16 bitie bayad tu 1500 o 1501 zakhire kone

the low byte goes to the low memory location and the high
byte goes to the high memory address
DS:1500 = F3 and DS:1501 = 35 >> little endian
This convention is called little endian versus big endian.

Little Endian: All Intel microprocessors and many others like A Gulliver’s Travels story
VAX from DEC (Digital Equipment Corporation), most of about how an egg should be
AVR microcontrollers. opened: from the little end
or the big end
Big Endian: IBM's mainframes, most RISC-based computers,
and Motorola microprocessors. TCP/IP (thus big-endian is
sometimes called network order)

ARM?
Supports both Little and Big endian and it is left to the 33
implementer Microprocessors and Assembly
 end

Microprocessors and Assembly 34