THIN FILM DEPOSITION CH-9

EPITAXY : growth of thin film with the same atomic

oreder as the underlying substrate

• Si growth on Si substrate (Homo epitaxy)

• SiGe growth on Si (Hetoroepitaxy)
• GaAlAs growth on GaAs

NON-EPITAXY (Thin Film Deposition) : Deposition of

the film without any order on a substrate. The film can
be amoruphous or polycrystalline

• Metals, Poly-Si deposition, Dielectric deposition

like SiO2, Si3N4
 EPITAXY
Epitaxy methods can be classified as

• Vapor Phase Epitaxy

• Chemical Vapor Deposition (CVD)
− MOCVD, LPCVD, PECVD, APCVD, LPCVD
• Molecular Beam Epitaxy (MBE)
• Liquid phase Epitaxy
• Solid Phase Epitaxy

Epitaxy can be classified according to the substrate

• Home Epitaxy : substrate and the grown layers are the same :
remember BJT application : Si on Si
• Hetero Epitaxy : different layer is grown on the substrate : lasers,
infrared dedectors, LEDs all have heterostructures grown by epitaxy

2
 Historical Development and Basic Concepts
Two main deposition methods are used today:
1. Chemical Vapor Deposition (CVD) 2. Physical Vapor Deposition (PVD)
- APCVD, LPCVD, PECVD, HDPCVD - evaporation, sputter deposition

Chemical Vapor Deposition (CVD)

Exhaust scrubber
Standup wafers
Furnace - with resistance heaters
Trap
RF induction (heating) coils
Quartz reaction chamber

vent
VaccumPump
SiH4 + O 2 SiO 2 + 2H2
Silicon wafers
Graphite susceptor Gas control
SiCl4 H and
HCl 2 sequencer
SiH4
H2+B2H6
H2+PH3 O2
Ar H2 SiCl4 + 2H2  Si + 4HCl

Source Gases

APCVD - Atmospheric Pressure CVD LPCVD - Low Pressure CVD

3
 EPITAXY
Epitaxy is applied to grow crystalline layers on crystalline substrate.
In epitaxy, the substrate acts as the seed layer.

Epitaxy is applied to grow crystalline layers on crystalline substrate.

In epitaxy, the substrate acts as the seed layer.

4
 EPITAXY – Why ?
Epitaxy was first developed to improve the perfromance of bipolar
junction transistor.

In BJTs low resistance is needed to reduce

the overall RC constant.

At the same time we need high resitance to

have higher breakedow voltages.

This is solved by growing a high resistive

layer on top of low resistive wafer

Source : Hayashi lab

Later epitaxy was used in a variety of applications such as, CMOS

technologies, lasers, dedectors etc.

Typical laser structure has several epitaxial

layers made of mostly GaAs based

Source : Wikipedia
5
 CHEMICAL VAPOR DEPOSITION

Chemical Vapor Deposition (CVD) is performed in a reactor at high

temperatures where several chemical reactipons take place

Exhaust scrubber
Standup wafers
Furnace - with resistance heaters
RF induction (heating) coils Trap
Quartz reaction chamber

vent
VaccumPump
SiH 4 + O 2 SiO 2 + 2H 2
Silicon wafers
Graphite susceptor
SiCl 4 H Gas control
HCl 2 and
sequencer
H 2+B2H 6 SiH 4
H 2+PH 3
Ar H2 SiCl 4 + 2H 2  Si + 4HCl
O2

APCVD - Atmospheric Pressure CVD Source Gases

LPCVD - Low Pressure CVD

Several gas sources are used in CVD :

Silicon Tetrachloride (SİCl4), Dichlorosilane (SiH2Cl2), Trichlorosilane (SiHCl3), Silane (SiH4)

6
 CHEMICAL VAPOR DEPOSITION

Gas stream

1 7
2 6

3 4 5
Wafer
Susceptor

1. Transport of reactants to the deposition region.

2. Transport of reactants from the main gas stream
through the boundary layer to the wafer surface.
3. Adsorption of reactants on the wafer surface.
4. Surface reactions, including: chemical
decomposition or reaction, surface migration to
attachment sites (kinks and ledges); site incorporation;
and other surface reactions (emission and redeposition
for example).
5. Desorption of byproducts.
6. Transport of byproducts through boundary layer.
7. Transport of byproducts away from the deposition
region.

Watch : https://www.youtube.com/watch?v=hkYb35e5JGo
7
 MODELLING

Since CVD processes involve carrier gas flow

over the the issue must be addressed with in
assessing the effectiveness of CVD.

Whenever a fluid flowing over a solid surface, a

“boundary layer” is created:

In the CVD, the boundary layer plays a significant role in the rate of deposition.

The thickness of the boundary layer over the substrate surface at a distance x from the leading
edge can be evaluated by:

Where Re is called Reynold number which characterizes the fluid flow in the reactor

where Dr is the hydraulic diameter of the reaction tube, n is the gas velocity, r is the gas density, m
is the viscosity
8
 MODELLING EPITAXY
Boundary F1 = diffusion flux of reactant species to the wafer
layer
= mass transfer flux

CG
Gas Silicon F1  h G C G  C S  (1)

where hG is the mass transfer coefficient (in cm/sec).

F1 CS F2 = flux of reactant consumed by the surface reaction

= surface reaction flux, steps 3-5

F2  k S C S (2)
F2
where kS is the surface reaction rate (in cm/sec).

In steady state: F = F1 = F2

 k S 1
Equating Equations (1) and (2) leads to C S  C G 1  
 h G 
F k h CG k h CT
The growth rate of the film is now given by v  S G  S G Y
N k S  hG N k S  hG N

where N is the number of atoms per unit volume in the film (5 x 1022 cm-3 for the case of epitaxial Si
deposition) and Y is the mole fraction (partial pressure/total pressure) of the incorporating species.

9
 MODELLING EPITAXY
F k h CG k h CT
v  S G  S G Y
N k S  hG N k S  hG N

1. If kS << hG, then we have the CT

surface reaction controlled case:
v k SY
N

CT
2. If hG << kS, then we have the mass transfer, v hGY
or gas phase diffusion, controlled case: N


• The surface term is Arrhenius with EA depending

 on the particular reaction (1.6 eV for single crystal
silicon deposition).

• hG is ≈ constant (diffusion through boundary layer).

• As an example, Si epitaxial deposition

is shown below (at 1 atm. total pressure).
Note same EA values and hG ≈ constant.
Rate is roughly proportional to
(mol. wt.)-1/2.

10
MODELLING EPITAXY

Key points:
• kS limited deposition is VERY temp sensitive.
• hG limited deposition is VERY geometry (boundary
layer) sensitive.
• Si epi deposition often done at high T to get high
quality single crystal growth. \ hG controlled. \
horizontal reactoR configuration.

• hG corresponds to diffusion through a boundary layer

of thickness  S.


• But typically  S is not constant as the
gas flows along a surface. Special
geometry is required for
uniform deposition.


11
 Low Pressure Chemical Vapor Deposition (LPCVD)
• Atmospheric pressure systems have major drawbacks:
• At high T, a horizontal configuration must be used (few wafers at a time).
• At low T, the deposition rate goes down and throughput is again low.

• The solution is to operate at low

pressure. In the mass transfer limited
regime,

DG 1
hG  But DG  (12)
S Ptotal

• DG will go up 760 times at 1 torr,

while  S increases by about 7 times.
 Thus hG will increase
 by about
100 times.
• Transport of reactants from gas phase
to surface through boundary layer is
 no longer rate limiting.
• Process is more T sensitive, but can
use resistance heated, hot-walled
system for good control of temperature
and can stack wafers.

12
 DOPING

 Add dopant gas to deposition reaction

 PH3, AsH3, B2H6 are added in ppm levels in H2
 Typical reaction : 2AsH3 2As (s) + 3H2

 Outdiffusion from doped substrate

 High deposition temperature drives diffusion out of highly doped
substrates into growing epi films.

 Auto doping
 Deposition temperature evaporates dopants from substrates or
from chamber walls
 Dopants are then incorporated in growing film

 To prevent back side auto doping, the back side can be sealed
using undoped Si, SiO2 or Si3N4
 CVD EQUIPMENTS

•Horizontal reactors have high

capacity and high throughput, but
suffers from the difficulty in
temperature control over the long
region.

•Pancake reacktors have good

temperature uniformity, suffers from
low capacity and mechanical
complexity.

•Barrel reactors good in temperature

uniformity, but not good at high
temperature.

Three common susceptors for chemical vapor deposition: (a) horizontal,

(b) pancake, and (c) barrel susceptors.
 MOLECULAR BEAM EPITAXY

• It is a non-CVD process

• It is a direct evaporation
Anadolu University
technique.

• Used to deposit single crystal

thin films on crystalline subtrate

• Inventors: J.R. Arthur and

Alfred Y. Chuo (Bell Labs, 1960)

• Very/Ultra high vacuum (10-11

Torr)

• Important aspect: slow

deposition rate (1 micron/hour).
Low throughput, not suitable for
large volume production

In Turkey : Two MBE systems at METU

One system at Eskişehir Anadolu University
One at Gazi University
 MOLECULAR BEAM EPITAXY

Knudsen cells

Arrangement of the sources and substrate in a conventional molecular beam epitaxy (MBE) system.
In the UHV environment, deposition and doping are precisely controlled.
Mean free path of the atoms : 5 x 10 6 cm
The initial surface is extremely important fro unifrom deposition. Substrate is cleaned either by
heating at very high temperatures or HF dip prior to loading
Applications : HBJT, MODFET, Lasers, Dedectors, Solar Cells
 LIQUID PHASE EPITAXY

Liquid phase epitaxy (LPE) is a method to grow semiconductor crystal layers

from the melt on solid substrates. This happens at temperatures well below the
melting point of the deposited semiconductor.

Liquid phase

Crystal Substrate

SOLID PHASE EPITAXY

Solid Phase Epitaxy (SPE) is a transition between the amorphous and crystalline phases of a
material. It is usually done by first depositing a film of amorphous material on a crystalline
substrate. The substrate is then heated to crystallize the film. The single crystal substrate
serves as a template for crystal growth

Solid phase (amorphous)

Crystal Substrate
 THIN FILM DEPOSITION
NON-EPITAXY

NON-EPITAXY (Thin Film Deposition) : Deposition of the

film without any order on a substrate. The film can be
amoruphous or polycrystalline

• Poly-Si deposition, Dielectric deposition like SiO2,

Si3N4
• Metalization
THIN FILM DEPOSITION
• Many films, made of many different materials
are deposited during a standard CMOS proces
• Requirements or desirable traits for deposition:
1. Desired composition, low contaminates, good
electrical and mechanical properties.
2. Uniform thickness across wafer, and
wafer-to-wafer.
3. Good step coverage (“conformal coverage”).
4. Good filling of spaces.
5. Planarized films .

Step Coverage Issues

Filling Issues

19
 Polysilicon and Dielectric Film Deposition
Commonly used thin film materials : Poly Si , SiO2, Si3N4 Metals

Application areas : MOSFET (and CMOS) fabrication, TFT transistors,

MEMS, electrooptical devices.

Deposition techniques : Chemical Deposition : CVD, LPCVD, PECVD

Physical Depositions : Thermal Evaporation, Sputtering, E-beam evaporation

Typical reactions for depositing dielectric and polysilicon

20
 Polysilicon
Polysilicon is used as the gate electrode in MOS devices.
It is also used to fabricate resistors.

Polysilicon

• Major advantage of polysilicon : can be exposed to very high temperatures,

which is needed during device processing.
• It can be doped to have low resistance.
• Polysilicon is commonly deposited by LPCVD at low temperatures (600 -650 oC)
• Typical reaction during poly Si deposition :
600 oC
SiH4 Si + 2H2
 Polysilicon
Polysilicon is not an epitaxila process. Any substrtae including SiO2, glass,
Al2O3 can be used as the subtrate

Polycrystal models

Deposition below 600 oC generates amorphous structure. It starts to crystallize

when heated above 600 oC.
Poly Si consists of grains with different orientation.
Grain size depends on temperature of the deposition.
Grain boundaries forms electronic barrier for carrier transport.

22
 Polysilicon growth rate in LPCVD process

Effect of silane concentration on the polysilicon deposition rate.

 Doping Polysilicon
Doping is extremely important because it is mainly used as conductors (MOSFET
gate) and resistors.
Extremely low resistance values should be obtained for MOSFET applications.
Doping poly Si can be done by ion implantation, diffusion and in situ during
deposition :

Doping affetcs the growth rate : adding diborane increases the growth rate. Adding
arsine or phosphine causes a decrease in the growth rate

24
 Fabrication of Polysilicon
• Atmospheric pressure systems have major drawbacks:
• At high T, a horizontal configuration must be used (few wafers at a time).
• At low T, the deposition rate goes down and throughput is again low.
• The solution is to operate at low
pressure. In the mass transfer limited
regime,

But (12)
‘ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇˇˇ ˇ

• DG will go up 760 times at 1 torr,

ks term while increases by about 7 times.
hG term at 1 torr (low P)
Thus hG will increase by about
100 times.
Growth velocity

hG term at 760 torr

(log scale)

• Transport of reactants from gas phase

to surface through boundary layer is
Net growth velocity
no longer rate limiting.
• Process is more T sensitive, but can
Mass transfer Surface reaction use resistance heated, hot-walled
controlled controlled
system for good control of temperature
1/T
and can stack wafers.
25
 Silicon Dioxide (SiO2)
SiO2 is as important as the Si crystals for IC production.
It is used as insulating layer in various devices. These are some of the
applications :

1. Insulating layer in the active area of MOSFET

2. Insulating layer between metal layers
3. Capping layer to prevent out diffusion
4. Surface passivation both in IC devices and solar cells
5. Mask for ion implantation and diffusion.
6. Doping source in the diffusion process
7. MEMS applications (Sacrificial layers)
ION IMPLANTATION
MOSFET CCD

26
 Silicon Dioxide (SiO2) For MEMS

SiO2 is as the sacrificial layer in this

cantilever fabrication process

27
 Fabrication of SiO2

SiO2 is fabricated by

1. Thermal oxidation of Si crystal (Chapter 4)

2. Deposition by APCVD, LPCVD, PECVD

SiO2 deposition
SiO2 can be formed at low temperatures (500 oC) by the following reaction

SiH4 + O2 SiO2 + 2H2

SiO2 is also deposited at 650 oC – 750 oC in LPCVD using Si(OC2H5)4 -
tetraethylorthosilicate abreviated as TEOS

Si(OC2H5)4 SiO2 + by-products

SiO2 is also deposited at high temperatures by CVD with the following reaction

SiCl2H2 + 2N2O SiO2 + 2N2 + HCl

28
 SiO2 Properties

SiO2 deposition

In general, oxides deposited at high temperatures resembles the thermal

oxide. However, high temperature oxides can not be deposited on Al

Low temperature oxides contain H2 in the form of Si-OH, Si-H, or water (H2O)

Oxide from SiO2Cl contains Cl which can react with the substrate.

29
 Step coverage

a) Conformal step coverage : reactants adsorb on

the surface and then rapidly migrate along the
surface before reacting. This is a uniform step
coverage

b) Nonconformal step coverage :when the

reactants adsorb and react without significant
surface migration

Oxide from SiH4 has bad step coverage

Oxide from TEOS has good step coverage
 Silicon Nitride (Si3N4)
Silicon nitride is used as

passivating layer on Si devices because it serves as an extremely good barrier to diffusipn of water
and sodium.

ASilicon
maskNitride
for selective oxidation. Si3N4 is oxidized very slowly while Si substrate oxidizes very rapidly
Oxidation Mask for Recessed Oxidation
It is used as an anti reflection coating in Si solar cells
Final Passivation Layer Over Die Surface

Silane Reaction with Ammonia - 700 - 900 o C at Atmospheric Pressure

3SiH 4 + 4NH 3 ® Si3 N 4 + 12H 2

Dichlorosilane Reaction - LPCVD at 700 - 800 o C

Si3N4 coating
3SiCl2 H 2 + 4NH 3 ® Si3 N 4 + 6HCl + 6H 2

Plasma Reaction of Silane with Nitrogen

2 SiH 4 + N 2 ® 2SiNH + 3H 2

Plasma Reaction of Silane with Ammonia (Argon Plasma)

SiH 4 + NH 3 ® SiNH + 3H 2
 Plasma Enhanced CVD (PECVD)

• Non-thermal energy to enhance processes at lower temperatures.

• Plasma consists of electrons, ionized molecules, neutral molecules, neutral and
ionized fragments of broken-up molecules, excited molecules and free radicals.
• Free radicals are electrically neutral species that have incomplete bonding and
are extremely reactive. (e.g. SiO, SiH3, F)
• The net result from the fragmentation, the free radicals, and the ion bombardment
is that the surface processes and deposition occur at much lower temperatures
than in non-plasma systems.

32
 High Density Plasma (HDP) CVD

• Remote high density plasma with independent RF substrate bias.

• Allows simultaneous deposition and sputtering for better planarization and
void-free films (later).
• Mostly used for SiO2 deposition in backend processes.

33
 Metal Thin Film Deposition
Metallization is needed in different parts of integrated circuits :
Gate metallization
Source and drain metallization
Emitter, base, and collector metallization
Interconnections between devices
Schottky junctions for special puposes (dedectors etc.)
 Metallization – State of the art

Earlier structures were simple

•Today more sophisticated metallization is

required.
•More metal interconnect levels increases
circuit functionality and speed.
• Interconnects are separated into local
interconnects (polysilicon, silicides, TiN) and
intermediate/global interconnects (Cu or Al).
• Starting to dominate total speed of circuit.

(From ITRS)
 Deposition techniques for metallization

✤ Resistance heating evaporation

✤ Electron-beam evaporation
✤ Sputter deposition
✤ Chemical vapor deposition

The metallization process is usually done in vacuum chamber. The

contamination should be avoided. The vacuum level is 1x10-5 - 1 10 -8 Torr
 Physical Vapor Deposition (PVD)

Wafer holder

Wafers

Atomic
flux

Vacuum Source material

Heater (resistance
or E-beam)

Vacuum system Exhaust

• PVD uses mainly physical processes to produce reactant species in the gas
phase and to deposit films.
• In evaporation, source material is heated in high vacuum chamber. (P < 10-5
torr).
• Mostly line-of-sight deposition since pressure is low.
• Deposition rate is determined by emitted flux and by geometry of the target
and wafer holder.
37
 Thermal Evaporation (resistive heating)
A metal flament or boat made of refractory metals (W) is heated by passing a high enough
current through it. The metal which is in thermal contact with the boat is heated and
evaporated in this way. Simple and inexpensive.
 Thermal Evaporation (electron beam heating)
A hot filament provides an electron beam
This beam is accelerated by a voltage of the order of 10 kV.
A magnet is used to curve the path of the electron beam on to the metal target.
Metal is heated and evaporated
Neutral impurities can not reach the sample.
 Uniformity

• The evaporation source can be

considered either a point source
or as a small area surface source
(latter is more applicable to
most evaporation systems).

•  is the solid angle over which

R evap R the source emits (4π if all
FkP  FkP 
evap
cosn  i directions, 2π if only upwards);
r 2 r 2 N is the density of the material
R evap R evap  being deposited.
v cos k v n
cos  i  cos k • The outward flux FkP from a point
2
Nr Nr 2 source, is independent of  i ,
 while the outward flux from a
small area surface source, varies
n
as cos  .i


a. Uniform (isotropic) b. Ideal cosine emission c. Non-ideal, more
emission from a from a small planar anisotropic emission from a
point source surface source. small planar surface source.
(n = 1 in cos n (n > 1 in cosn
distribution) distribution)
 Uniformity

r0

r0 r

Source

The deposition rate is same for all points on the spherical surface
Uniformity and Step Coverage

• Uniform thickness - use spherical wafer

holder.
- Point source: put source at center of sphere.
- Small surface source: put source on inside
surface of sphere (compensates for cosn  i ).

• With evaporation:
• Can evaporate just about any element.

• Difficult to evaporate alloys and
compounds
• Step coverage is poor (line of sight and
Sc≈ 1).
• Rarely used today.

SC = 1 SC < 1
 Sputtering
•Ar ions are accelerated by an electric field towards the target which is eroded by
momentum transfer.

•DC magnetron : only electric field.

•Magnetron sputtering : a magnetic field changes the path of the electrons so that the
plasma efficiency increases, and electron bombardment of substrate is avoided.

•It is a low temperature process.

•Alloys can be sputtered
 DC Sputter Deposition
-V (DC)

Electrode/target
(cathode)
Argon plasma
(glow discharge)
Wafers
Electrode (anode)
Heater

Ground
Sputtering gas inlet Vacuum
( Ar)

• Uses plasma to sputter target, dislodging atoms which then deposit on wafers to
form film.
• Higher pressures than evaporation - 1-100 mtorr.
• Better at depositing alloys and compounds than evaporation.
• The plasma contains ≈ equal numbers of positive argon ions and electrons as
well as neutral argon atoms.

44
 ‘ DC Sputter Deposition
• Most of voltage drop of the system
Wafers

(due to applied DC voltage, Vc)

_ occurs over cathode sheath.
(Vc) Cathode
(target) Anode

• Ar+ ions are accelerated across

Cathode Cathode Argon plasma, or Anode sheath
cathode sheath to the negatively
glow dark space
or sheath
negative glow
charged cathode, striking that
electrode (the “target”) and
+
sputtering off atoms (e.g. Al). These
Voltage

Vp
0 0
Distance travel through plasma and deposit
-
Vc
on wafers sitting on anode.
_
• Rate of sputtering depends on the
Al
Al target

O
e- sputtering yield, Y, defined as the
Dark space

Aro
or sheath
number of atoms or molecules
Ar+ Ar+

Al
O-
ejected from the target per incident
Aro

Ar+ ion.
e-
Negative glow

e-
• Y is a function of the energy and
Al Al
Al
mass of ions, and the target material.
Wafer surface It is also a function of incident angle.
45
 DC Sputter Deposition
a) Source b) Source

Wafer Wafer

• Sputtering targets are generally large and provide a wide range of arrival
angles in contrast to a point source.

cosn 
• Arrival angle distribution generally described by distribution (the normal
component of flux striking the surface determines the deposition or
growth rate). 
• Size and type of source, system geometry and collisions in gas phase
are important in arrival angle distribution.
RF Sputter Deposition
• For DC sputtering, target electrode
is conducting.
• To sputter dielectric materials use
RF power source.

• Due to slower mobility of ions vs. electrons,

the plasma biases positively with respect to
both electrodes. (DC current = zero.)
 continuous sputtering.
• When the electrode areas are not equal,
the field must be higher at the smaller
electrode (higher current density), to
maintain overall current continuity
m
V1 A2 
   (m = 1-2 experimentally) (13)
V2 A1 
• Thus by making the target electrode smaller,
sputtering occurs "only" on the target. Wafer
 electrode can also be connected to chamber
walls, further increasing V2/V1.
47