clock_divider:Clock_Divider_module

Signals Usage Active

clk_clk
reset_reset_n
clk_ov7670_clk
clk_vga_clk

Address_Generator:Block_Address_Generator
Signals Usage Active
CLK25
Enable
vsync
address[16..0]
 ov7670_capture:Block_ov7670_capture
Signals Usage Active
d[7..0]
href
Pclk
vsync
address[16..0]
dout[11..0]
we
 RGB:Block_RGB
Signals Usage Active
Din[11..0]
Nblank
B[7..0]
G[7..0]
N[7..0]

VGA:Block_VGA
Signals Usage Active
CLK25
Hsync
Nblank
Nsync
Vsync
activeAera
Clkout
 frame_buffer:Block_frame_buffer
Signals Usage Active
data[11..0]
raddress[16..0]
rdclcok
wraddress[16..0]
wrclock
wren
q[11..0]
 my_frame_buffer_15to0:Inst_buffer_bottom
Signals Usage Active
data[11..0]
raddress[15..0]
rdclock
waddress[15..0]
wrclock
wren
q[11..0]
 my_frame_buffer_15to0:Inst_buffer_top
Signals Usage Active
data[11..0]
raddress[15..0]
rdclock
waddress[15..0]
wrclock
wren
q[11..0]
 ov7670_controller:Block_ov7670_controller
Signals Usage Active
clk
resend
config_finished
pwdn
reset
sioc
siod
xclk
 i2c_sender:Inst_i2c_sender
Signals Usage Active
id[7..0]
reg[7..0]
vals[7..0]
clk
send
siod
taken
sioc
 ov7670_registers:Inst_ov7670_registers
Signals Usage Active
clk
resend
advance
command[15..0]
finished

x00 x1208 COM7 Reset

x01 x1208 COM7 Reset
x02 x1204 COM7 Size & RGB output
x03 x1100 CLKRC Prescaler - Fin/(1+1)
x04 x0C00 COM3 Lots of stuff, enable scaling, all others off
x05 x3E00 COM14 PCLK scaling off
x06 x8C00 RGB444 Set RGB format
x07 x0400 COM1 no CCIR601
x08 x4010 COM15 Full 0-255 output, RGB 565
x09 x3a04 TSLB Set UV ordering, do not auto-reset window
x0A x1438 COM9 - AGC Celling
x0B x4f40 ; x4fb3 MTX1 - colour conversion matrix
x0C x5034 ; x50b3 MTX2 - colour conversion matrix
x0D x510C ; x5100 MTX3 - colour conversion matrix
x0E x5217 ; x523d MTX4 - colour conversion matrix
x0F x5329 ; x53a7 MTX5 - colour conversion matrix
x10 x5440 ; x54e4 MTX6 - colour conversion matrix
x11 x581e ; x589e MTXS - colour conversion matrix
x12 x3dc0 COM13 - Turn on GAMMA and UV Auto adjust
x13 x1100 CLKRC Prescaler - Fin/(1+1)
x14 x1711 HSTART HREF start (high 8 bits)
x15 x1861 HSTOP HREF stop (high 8 bits)
x16 x32A4 HREF Edge offset and low 3 bits of HSTART and
HSTOP
x17 x1903 VSTART VSYNC start (high 8 bits)
x18 x1A7b VSTOP VSYNC stop (high 8 bits)
x19 x030a VREF VSYNC low two bits
x1A x0e61 COM5(0x0E) 0x61
x1B x0f4b COM6(0x0F) 0x4B
x1C x1602
x1D x1e37 MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x
x1E x2102
x1F x2291
x20 x2907
x21 x330b
x22 x350b
x23 x371d
x24 x3871
x25 x392a
x26 x3c78 COM12 (0x3C) 0x78
x27 x4d40
x28 x4e20
x29 x6900 GFIX (0x69) 0x00
x2A x6b4a
x2B x7410
x2C x8d4f
x2D x8e00
x2E x8f00
x2F x9000
x30 x9100
x31 x9600
x32 x9a00
x33 xb084
x34 xb10c
x35 xb20e
x36 xb382
x37 xb80a
others xffff