26 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO.
1, JANUARY 2020
Design Considerations for Si- and Ge-Stacked
Nanosheet pMOSFETs Based on
Quantum Transport Simulations
Shuo Zhang , Jun Z. Huang , Member, IEEE , Hao Xie , Afshan Khaliq, Dawei Wang ,
Wenchao Chen , Member, IEEE , Kai Miao, Hongsheng Chen , Senior Member, IEEE ,
and Wen-Yan Yin , Fellow, IEEE
Abstract — Design considerations of vertically stacked
horizontal nanosheet (NSH) gate-all-around pMOSFETs are
examined at the sub-5-nm technology node using in-house-
developed non-equilibrium Green’s function (NEGF) quan-
tum ballistic transport simulator. In the individual Si and
Ge NSHs, ON-state current and subthreshold swing are
evaluated and analyzed for different crystal orientations and
various sheet widths. Performance benchmarking of the
stacked FET arrays at the iso-footprint is accomplished to
explore the roles of sheet configurations further with stack
number and sheet spacing changed. It is found that the
benefit of the larger effective channel width provided by
the wider NSH is always compromised by degraded gate
control, especially in the Ge channel. [111] and [100] are
shown to be the best transport orientations for individ-
ual Si and Ge NSHs, respectively. However, [100] channel
vertically confined along [011] shows greater potential for
the applications of wider Si and Ge NSHs in the stacked
FET array. The process-induced NSH width variation is
studied statistically, and it is shown to cause significant
performance fluctuations in the stacked array consisting of
wide Si or narrow Ge NSHs.
Index Terms — Crystal orientation, gate-all-around (GAA),
k · p non-equilibrium Green’s function (NEGF) method,
pMOSFET, process-induced sheet variation, quantum trans-
port, stacked nanosheet (NSH) transistor.
I. I NTRODUCTION
T HE gate-all-around (GAA) MOSFET architecture is
widely regarded as one of the most promising candi-
dates to push the CMOS technology beyond the ending of
Manuscript received August 18, 2019; revised November 13, 2019;
accepted November 15, 2019. Date of publication December 16, 2019;
date of current version December 30, 2019. This work was supported in
part by the National Natural Science Foundation of China (NSFC) under
Grant 61431014 and Grant 61971375 and in part by the Science
Challenge Project under Project TZ2018002. The review of this article
was arranged by Editor J. Mateos. (Corresponding authors: Wen-Yan Yin;
Jun Z. Huang.)
S. Zhang, H. Xie, A. Khaliq, D. Wang, W. Chen, H. Chen, and
W.-Y. Yin are with the Innovative Institute of Electromagnetic Information
and Electronic Integration (EIEI), College of Information and Electronic
Engineering, Zhejiang University, Hangzhou 310027, China (e-mail:
wyyin@zju.edu.cn).
J. Z. Huang is with MaxLinear Inc., Carlsbad, CA 92008 USA (e-mail:
junhuang1021@gmail.com).
K. Miao is with Synopsys Inc., Mountain View, CA 94043 USA.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2019.2954308
0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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Moore’s law [1]–[7]. Recently, the vertically stacked hori-
zontal nanosheet (NSH) GAA structure has been seriously
considered as the FinFET replacement so as to meet the
requirement of the 5-nm technology node and beyond [8]–[10].
As the width of the NSH channel is not limited by fin pitch
and fin quantization, it is reported to offer more freedom
to achieve a sufficient effective channel width (Weff ), which
brings versatile design options for performance and power
management [8], [11].
Many efforts have been made for the exploration of relia-
bility, electrostatics, integration process, and parasitic effects
in the stacked NSH-FETs [11]–[16]. In the numerical stud-
ies, most of them are limited in the semiclassical transport
regime with quantum corrections [13]–[15], and few seriously
consider quantum transport in the ultrascaled NSH channel.
Fully quantum transport simulation can accurately capture the
tunneling and confinement effects and has been shown to be
critical in understanding nanowire transistors [17], [18]. How-
ever, as quantum effects strongly depend on the crystal orien-
tation and cross-sectional geometry, a separate study based on
such quantum simulation should be performed for NSH-FETs
with rectangular cross sections. Moreover, the process-induced
variation of the sheet cross-sectional dimension is significant
but scarcely included in the previous simulation studies. The
impact of such a variation to the threshold voltage (Vth ) and
drive current of the NSH array needs to be quantified.
In this article, self-consistent Poisson non-equilibrium
Green’s function (NEGF) simulator [19] is employed to cap-
ture the hybrid electrostatic and quantum effects in the p-type
NSH-FETs, with the six-band k · p Hamiltonian incorporated
to model the complex valence band structure accurately [20].
In order to improve the simulation efficiency of the 3-D
structures, all ballistic NEGF equations are transformed into
the reduced-order mode space and solved therein [21], [22].
Different cross-sectional dimensions and crystal orientations
are considered for the Si and Ge channels. The performances
of the single NSH as well as the stacked NSH array at the iso-
footprint are evaluated and explained in detail, with practical
design guidelines provided. The process-induced geometry
variation is considered for the stacked NSH-FET array in
a statistical way. In Section II, the device structure, crystal
orientation configuration, and statistical evaluation method of
ZHANG et al.: DESIGN CONSIDERATIONS FOR Si- AND Ge-STACKED NSH pMOSFETs
Fig. 1. Device structures of p-type. (a) Vertically stacked NSH-FETs.
(b) Single NSH-FET. Lg , Ls and Ld represent the lengths of channel
(gate), source, and drain extensions, respectively. The equivalent oxide
thickness is Tox and the doping density of source/drain extension
is Nsd . The channel width and thickness are denoted by Wch and Tch ,
respectively.
Fig. 2. Ball–stick structures of Ge channel oriented to (a) [100], (b) [110],
and (c) [111]. All of them display a cross section of 2 nm × 4 nm. For the
Si channel, the atomic arrangement is the same, and the only difference
is the size scaling resulted from the lattice constant, i.e., aSi = 0.543 nm
and aGe = 0.565 nm.
the stacked NSH array are described. Numerical results for
individual NSHs and their stacked arrays are presented in
Sections III and IV, respectively. The conclusions are drawn
in Section V.
II. D EVICE S TRUCTURE AND M ETHODOLOGY
A. Device Structure
The 3-D schematic of a vertically stacked horizontal
NSH-FET array and its single cell are shown in
Fig. 1(a) and (b), respectively. The simulated region is
horizontally confined along the channel width (y-axis)
direction and vertically confined along the channel thickness
(z-axis) direction, and the hole transport is along the channel
length (x-axis) direction. To represent the device dimensions at
the sub-5-nm node, we choose L g = 10 nm and Tch = 4 nm.
In addition, we set L s = L d = 8 nm, Tox = 1 nm, and Nsd =
1 × 1020 /cm3 . In order to assess the impact of sheet/channel
width, we consider Wch = 4, 8, 12, and 16 nm, corresponding
to the Wch /Tch ratio of 1, 2, 3, and 4, respectively.
B. Crystal Orientations
As shown in Fig. 2, the atomic arrangement is anisotropic
along different confinement orientations, which strongly
affects the valence-band dispersion and the hole-transport
properties. Horizontal and vertical confinement orienta-
tions are geometrically non-equivalent in these rectangular
NSH channels. Therefore, for each transport orientation, two
groups of confinement orientation combinations are evalu-
ated, as listed in Table I. We use [100]/[001] to represent
the configuration, where the transport (x) crystal orientation
is [100], the vertical confinement (z) orientation is [001], and
the horizontal one (y) is [010]. The crystal orientation in the
y-direction is omitted for simplicity, since it can be deduced
from the other two.
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27
TABLE I
C RYSTAL O RIENTATION C ONFIGURATIONS
Fig. 3. 2-D cross-sectional views of the three-stacked NSH-FET arrays
for different device configurations, with the same footprint (LF ) and
sheet-to-sheet spacing (Tsp ). The cross-sectional size of single cell is
(a) 4 nm × 4 nm, (b) 8 nm × 4 nm, and (c) 16 nm × 4 nm, respectively. The
red dashed lines represent the channel cross sections of the FinFETs.
C. Statistical Study of Stacked NSH-FETs
Fig. 3(a)–(c) shows the 2-D cross-sectional views of the
stacked NSH-FETs with different values of Wch , which
describe the cases of 4-nm × 4-nm, 8-nm × 4-nm, and
16-nm × 4-nm channel cross section, respectively. Except for
the Wch , the other dimensions are constant in all the cases,
where LF = 48 nm, Tsp = 6 nm, Tch = 4 nm, and Tox = 1 nm.
The cross-sectional area (LF × H) is also identical across
different Wch cases, where H is the height of the selected
rectangular region. The red dashed lines are the peripheries of
the FinFET channels. For each case, assuming that the channel
cross sections of the individual cells are the same, the Vth of
them is seen as identical and the synchronous gate voltage
is applied on them. The total ON-current (ION ) in the area is
compared premising the same total OFF-current (IOFF ).
In a more realistic case, the cross-sectional size of each
single cell may have some deviations from the standard
because of the fabrication technology. Such slight variation
in the channel size can result in different values of Vth for
each cell in the array, and thus, total ION and IOFF will also
have some variations. The relative error of Wch for each single
NSH cell is defined as R, and it is assumed to obey the
normal distribution R ∼ N (0, σ 2 ), where the expectation
of R for these individual cells is set as zero, and the standard
deviation of R is σ . According to the empirical “3σ ” rule [23],
3σ is set as 12.5% to represent a moderate process precision.
NEGF transport simulations are performed to obtain ION and
IOFF for single FET with different values of R at the standard
Wch = 4, 8, and 16 nm. Then, R-dependent ION and IOFF and
their corresponding probabilities are further used to obtain the
expectations and standard deviations of total ION and IOFF for
the stacked sheet array statistically.
III. S INGLE NSH P ERFORMANCE
A. Switching Performance Metrics
NEGF simulations are accomplished at room temper-
ature (T = 300 K). The specified OFF-current target
28
Fig. 4. ION as a function of Wch for (a) Si and (b) Ge channel
NSH-FETs oriented to [100], [110], and [111] with different cross-
sectional confinement crystal orientations. Insets are the corresponding
width-normalized current ION /Wch versus Wch , in comparison with the
UTB DG-FET results.
(IOFF = 0.01 μA) and the fixed supply voltage (VDD = 0.5 V)
are used to evaluate the ION , and thus, the gate work function
is adjusted to shift the ID –VG curve, achieving ID = 0.01 μA
at VG = 0 and VD = 0.5 V.
Fig. 4(a) and (b) present the ION extracted at VG =
VD = VDD from the I –V curves for the Si and Ge NSHs,
respectively. In Fig. 4(a), as Wch increases from 4 to 16 nm,
ION is increased almost linearly, and this improvement by Wch
can be as high as nearly 90% for [100] channel. It is also seen
that for the Si NSH-FET, the [111]-oriented channel always
performs better than the [110] and [100] cases regardless
of Wch , where the [100] transport orientation leads to the low-
est drive current. However, the situation is very different in the
Ge sheet, where [100] becomes the best transport orientation,
as indicated in Fig. 4(b). The value of ION rebounds between
Wch = 8 and 12 nm for the [100]/[011] configuration and
between Wch = 12 and 16 nm in the [100]/[001] case, while
for the other configurations of the Ge channel, ION decreases
with Wch monotonically. Note that ION can be improved
by over 70%, with the orientation configuration optimized
as [100]/[011] at Wch = 16 nm.
In both Si and Ge cases, the two confinement orientation
configurations for the [111]-oriented channel show very close
performances across different values of Wch . However, as
Wch increases, the ION difference between the two orientation
configurations for the [110] channel becomes smaller, and for
the [100] channel, it becomes larger. In general, [100]/[011],
[110]/[001], and [111]/[1̄10] perform better than [100]/[001],
[110]/[1̄11], and [111]/[167̄], respectively, and the Si NSH
has an overall higher ION than that of its Ge counterpart, except
that Ge outperforms Si for the [100] transport orientation case
at Wch = 4 and 8 nm.
The insets in Fig. 4(a) and (b) show the corresponding ION
normalized by Wch (ION /Wch ), premising a common IOFF =
0.01 μA/μm, in comparison with that of the ultrathin-body
(UTB) double-gate MOSFETs (DG-FETs) at the same L ch
and Tch . As the Wch is normally very large and homogeneous
in the UTB DG-FET, the hole transport is treated as peri-
odic in this direction for simplification. Its NEGF simulation
is performed in the 2-D real space (xz plane), where the
transverse wave vector k y is parameterized properly. For both
Si and Ge NSH-FETs, it is shown that their ION /Wch decreases
with Wch , approaching the value of the UTB case, and this
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 1, JANUARY 2020
Fig. 5. SS as a function of Wch for (a) Si and (b) Ge NSH-FETs oriented
to [100], [110], and [111] with different cross-sectional confinement
crystal orientations.
Fig. 6. (a) Current spectrum (blue) and its corresponding potential profile
(black) at OFF-state, where the peak of the potential barrier is shown by
the green dashed line, and EFs /EFd is the Fermi level of source/drain,
respectively. (b) SDT ratios at OFF-state for the Si and Ge FETs with
[100]/[011] and [110]/[1̄11] orientation configurations at Wch = 4, 8,
and 12 nm.
observation effectively validates the simulation approach, and
reveals weaker lateral gate control in the sheet width direction
at large Wch . In addition, the ION /Wch of the Si channel
is overwhelmingly larger than that of its Ge counterpart.
The ION /Wch difference is not very large across different
orientations in the Si NSH, while the [100] channels result
in the highest ION /Wch in the Ge case.
The subthreshold swing (SS) is also calculated at the
OFF -state, and its variations with Wch for the Si and Ge cases
are displayed in Fig. 5(a) and (b), respectively. In general,
SS is degraded by Wch , and the SS of the Si device is obviously
better. It is also found that in the Si NSH, SS shows a very
slight difference across all crystal orientation configurations,
while in the Ge device, the SS for the [100]-oriented channel
is obviously lower than the other orientation configurations.
B. Source-to-Drain Tunneling (SDT)
Fig. 6(a) shows the IOFF spectrum together with its potential
distribution along the transport direction for the [110]/[1̄11] Si
sheet with Wch = 4 nm. The potential profile is obtained
by averaging the cross-sectional potentials at each x point,
and the IOFF spectrum can be roughly divided into two parts
from the barrier top. The part below can be attributed to
the thermionic portion, while the part above is contributed
by the quantum SDT. As a constant leakage current is assumed
at the OFF-state, larger SDT leakage current means less portion
of thermionic current corresponding to a larger potential
barrier height. The SDT ratio, defined as the portion of the
ZHANG et al.: DESIGN CONSIDERATIONS FOR Si- AND Ge-STACKED NSH pMOSFETs
Fig. 7. (a) ION as a function of (VON − Vth ) for typical [100]-, [110]-, and
[111]-oriented channels in both Si and Ge FETs. The Wch is increased
from 4 to 16 nm along the direction of the arrow. (b) ON-state valence
band edge profiles for the Si and Ge NSH-FETs with [100]/[011] and
[110]/[1̄11] channels at Wch = 8 nm.
tunneling current above the barrier peak, is calculated to char-
acterize the SDT strength. Fig. 6(b) displays the SDT ratios
for both Si and Ge FETs with [100]/[011] and [110]/[1̄11]
orientation configurations at Wch = 4, 8, and 12 nm. It is seen
that as Wch increases, SDT becomes stronger, except that the
drastic increase in the effective mass (m eff ) reduces the SDT
strength slightly at Wch = 8 nm for the Ge channel. This
overall aggravating SDT is caused by the weakening of the
gate electrostatic control as a result of wider Wch . In addition,
due to the difference in m eff , Ge NSH suffers from more severe
SDT than that of the Si case, and [100] channel contributes
to a weaker SDT in comparison with the [110] case.
SDT is known to greatly degrade SS, and thus, Vth is
also increased at the fixed IOFF -target, leading to reduced
ON -state gate overdrive (VON − Vth ). Fig. 7(a) is plotted to
reveal the relation between ION and (VON −Vth ) for three typical
crystal orientation configurations in both Si and Ge NSHs,
where the Vth is set as the gate bias corresponding to a current
magnitude that is ten times of IOFF (Ith = 0.1 μA). It is found
that the larger Wch generally can have two competing effects:
one is the increase of Weff and the other is the degradation
of lateral gate control in the sheet-width direction. For the
Si NSHs with a much weaker SDT and sufficient (VON − Vth ),
the increase in Wch can bring larger Weff, showing a positive
effect on ION , as the barrier is low and the thermionic current
is dominant. However, Ge channels suffer from a much
stronger SDT, so the negative effect of a larger Wch wins in
the competition, resulting in even thinner barrier width, more
tunneling current, and less (VON −Vth ). Thus, such a reduction
in the electrostatic control caused by the increase in Wch leads
to the situation that ION is almost determined by SS, and
the larger the Wch , the more the SS and ION are degraded.
In Fig. 7(a), the [100]-oriented Ge channel gives relatively
larger m eff and it is some kind of intermediate case with a
moderate SDT and (VON −Vth ), where the turning point clearly
shows the competition between the larger Weff and the worse
gate control. This competition is also why the improvement of
ION is not proportional to Wch for the Si channel in Fig. 4(a),
where the gate control degradation causes ION /Wch to decrease
with Wch .
Fig. 7(b) shows the valence band-edge profiles at the
ON -state, for the Si and Ge NSH-FETs with [100]/[011]
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29
Fig. 8. (a) ION as a function of Wch with Nsd = 0.5 × 1020 , 0.8 ×1020 ,
and 1.0 ×1020 cm−3 , for [100]/[011] (solid line) and [110]/[1̄11] (dashed
line) Ge channel NSH-FETs. (b) Full ID − VG curve with work function
adjusted at Wch = 4, 8, 12, and 16 nm, for the Ge NSH-FETs with the
[110]/[001] channel.
and [110]/[1̄11] channels, respectively. Corresponding to the
SDT ratio shown in Fig. 6(b), it shows that stronger SDT
leads to a higher potential barrier at the ON-state as a result
of the reduced gate overdrive, and thus, thermionic current
is suppressed by the high barrier. Sufficient (VON − Vth ) can
result in dominant thermionic current with a low enough
barrier; thus, ION is mainly determined by the ballistic velocity.
In such a case, crystal orientation with lighter m eff and higher
velocity contributes to higher drive current, and this is why
[111]- and [110]-oriented Si channels show better performance
in Fig. 4(a). However, as (VON − Vth ) is reduced to a very
low value region, where SDT is dominant due to extremely
light m eff , ION will be nearly proportional to (VON − Vth ),
as can be seen in Fig. 7(a) as well. Therefore, for Ge sheet
except for the case of [100] channel, as VG is increased to VON ,
the tunneling leakage current is reduced dramatically, while
the thermionic current is also suppressed by the high barrier
at the ON-state. This explains the generally lower ION of the
Ge channel in comparison with its Si counterpart in Fig. 4.
Note that since we hope Ge NSH to give a higher drive
current or an ON/ OFF ratio, Nsd can be optimized to realize
its potential advantages by modulating the electrostatics and
suppressing SDT, as seen in Fig. 8(a), where ION is greatly
improved at lower Nsd . Meanwhile, Fig. 8(b) shows that
further increase in VDD can result in larger (VON − Vth ) and
lower barrier height for the domination of thermionic current
at ON-state, where the positive effect of larger Weff can be
used for the Ge channel.
IV. P ERFORMANCE OF S TACKED NSH-FET S
A. Total Drive Current
Three options of stacked NSH-FETs at the same LF and
cross-sectional area, as shown in Fig. 3(a)–(c), are evaluated
and compared. In the ideal case with no variation in Wch ,
the NSH cells in the cross section are treated as the same with
each other. Assuming that a fixed total IOFF = 0.06 μA passes
through the considered area in Fig. 3, individual cells with the
same Wch in each case are supposed to equally contribute to
this IOFF magnitude; hence, the adjustment of work function is
treated as identical for them, and the total ION is simply the ION
of single cell times the number of cells in the cross-sectional
area.
30
Fig. 9. Total ION versus Wch , passing through the same cross-sectional
area for both (a) Si and (b) Ge channels, where the device configurations
are given in Fig. 3. The results of the NSH-FETs are compared with those
of the FinFETs when Wch = 4 and 8 nm, for the optimal crystal orientation
configurations of the Si and Ge channels, respectively.
The total ION for all the considered configurations is shown
in Fig. 9(a) and (b) for Si and Ge devices, respectively. It is
found that, when comparing the total ION , the performance
ranking of different crystal orientation configurations is con-
sistent with that of the single NSH case. However, as the
footprint is fixed, larger Wch of the single cell corresponds
to less number of cells; thus, the total ION in the same
area demonstrates an overall decrease with the Wch . This is
different from the ION performance for the single sheet case
(see Fig. 4), where the effect of cell number is not included.
In particular, the [100]-oriented Si channel is an exception,
where its total ION grows with Wch increased from 8 to 16 nm,
showing great potential for wider NSH applications, no matter
the vertical confinement orientation is [001] or [011]. This
is because their heavier m eff can result in weaker SDT, and
thus, each single NSH takes the upmost advantage of larger
Weff with drive current improved most. Note that small Wch is
critical to the Ge channel to maintain good performance, while
it does not matter that much for Si.
The result of NSH-FET is also compared with that of
FinFET at Wch = 4 and 8 nm for both Si and Ge channels,
according to the configurations shown in Fig. 3(a) and (b).
The optimal crystal orientations for the NSH-FETs are also
considered in the FinFET case. As a result, NSH-FETs show
obviously better performance than the FinFET, especially for
widened channels. Compared with the [111]/[1̄10] Si case,
stacked NSH-FETs made of the [100]/[011] Ge chan-
nel exhibit more significant advantage over their FinFET
counterparts.
B. Effect of Process-Induced Wch Variation
Considering the variation of Wch in the real case, the statis-
tical method aforementioned is used for the stacked NSH-FET
arrays at iso-footprint in Fig. 3. The optimal crystal orientation
configurations for the Si and Ge devices are evaluated, i.e.,
[111]/[1̄10] and [100]/[011], respectively. The expectations
of ION and IOFF with their standard deviations are compared
with the corresponding current values in the ideal case at
different values of Wch . ION /ION is the change in current
with Wch variation included relative to the ION in the ideal
case, while IOFF /IOFF represents the relative IOFF change.
Fig. 10(a) and (b) displays the results of the single cell in the
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 1, JANUARY 2020
Fig. 10. (a) ΔION /ION and (b) ΔIOFF /IOFF as functions of Wch for the
single cell in the arrays with the optimal crystal orientations of the Si and
Ge channels at the same footprint. (c) and (d) Corresponding results
of the total ION and IOFF passing through the same area for the NSH
arrays. All results are shown in the form of error bar, with Wch variations
considered.
iso-footprint NSH-FET array, and Fig. 10(c) and (d) displays
the corresponding total ION and IOFF passing through the same
area.
In general, the expectations of ION and IOFF at different val-
ues of Wch show very little deviation (no more than 5%) from
the ideal case, and this tiny difference decreases with Wch .
It can be seen that for both expectation and fluctuation,
Si device is less affected by the Wch variation compared
with its Ge counterpart. Its ION fluctuates more drastically
at larger Wch , whereas for the Ge case, the fluctuation is
more significant at a smaller Wch . This can be interpreted by
Fig. 7(a), as the (VON −Vth ) of the single Ge NSH is smaller
than that of the Si case, the fluctuation of ION in the Si
NSH is more related to the variation of Weff , while in the
Ge case, it is more sensitive to that of gate control. Because
larger Weff at wider Wch and better gate control at narrower
Wch will result in larger variations of themselves, such behav-
iors are responsible for the ION fluctuations of the Si and
Ge NSH-FETs, respectively.
On the other hand, IOFF shows much more fluctuation caused
by the Wch variation in comparison with ION , and this is due to
the exponential I –V characteristics in the subthreshold region.
For both Si and Ge channels, Fig. 10(b) and (d) indicates that,
the larger the Wch , the lower the variation of IOFF is. Because
a fixed work function adjustment is applied on each NSH cell,
the variation of subthreshold current is mainly determined
by the SS and the shift of Vth . For the same Wch , SDT is
more severe in the Ge case, leading to a larger Vth shift,
so IOFF fluctuates more drastically in comparison with its
Si counterpart. For the same material, SS is better at
smaller Wch , thus resulting in larger fluctuation in IOFF . The
larger NSH density at a narrower Wch further intensifies the
corresponding fluctuation in the total IOFF .
ZHANG et al.: DESIGN CONSIDERATIONS FOR Si- AND Ge-STACKED NSH pMOSFETs
Fig. 11. 2-D cross-sectional views of the stacked NSH-FET arrays
for different sheet-to-sheet spacings and stack configurations at Wch =
4 nm. (a) Three vertical stacks, Tsp = 6 nm. (b) Three vertical stacks,
Tsp = 10 nm. (c) Two vertical stacks, Tsp = 6 nm. Fin height, fin pitch,
vertical pitch, H, and LF are also changed according to the number of
vertical stacks, vertical and horizontal Tsp , to guarantee the same values
across different Wch cases. Solid line is the boundary of the iso-footprint
area, and dashed line means the boundary is beyond the region.
Fig. 12. Ratios of ION _Fin/ION _NSH as the functions of vertical pitch for
different numbers of vertical NSH-FET stacks. ION _Fin is the total ION of
FinFETs, while ION _NSH is that of stacked NSH-FETs. Their horizontal
geometric parameters are the same, as shown in Fig. 3. (a) [110]/[1̄11]
Si channel withWch = 4 and 8 nm. (b) [100]/[011] Ge channel Wch = 4
and 8 nm.
C. Effect of Sheet-to-Sheet Spacing
As shown in Fig. 11, different values of vertical and
horizontal Tsp as well as the stack numbers will accordingly
change both vertical and horizontal fin pitches, fin height,
identical footprint, and cross-sectional area assumed for all
the three Wch cases, so they are examined for a more compre-
hensive consideration.
The vertical Tsp is varied from 2 to 20 nm with the
corresponding vertical pitch varied from 8 to 26 nm in the 2-,
3- and 4-stack NSH-FETs, and their total ION is compared with
that of the FinFET with Wch = 4 and 8 nm at the same fin pitch
and footprint. Fig. 12 shows the effects of stack number and
vertical pitch for the optimal crystal orientation configurations
of the Si and Ge channels. As the total IOFF at the fixed
LF keeps identical for both FinFET and NSH-FET cases, it is
found from the ION _Fin/ION _NSH ratio that, at the same fin
pitch and Wch , smaller vertical Tsp and stack number help
stacked NSH-FETs outperform the FinFET in terms of the
intrinsic current, because the Weff of the FinFET is reduced.
As Wch increases, it is more difficult for the FinFET to achieve
the same drive current as that of the NSH-FET case due
to worse gate control. Therefore, in Fig. 12(a) and (b), the
total ION of the stacked NSH-FETs is overwhelmingly larger
than that of the FinFET at Wch = 8 nm.
The horizontal Tsp is further set as 10, 14, and 18 nm for
the performance evaluation of the stacked NSH-FET array at
Wch = 4, 8, and 16 nm, and thus, the LF is also changed
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31
Fig. 13. Ratio of ION at Wch = 16 nm to that at Wch = 4 nm, as a function
of horizontal Tsp , for (a) Si and (b) Ge channels with different crystal
orientation configurations. Vertical dimensions keep identical across all
the cases.
to 560, 480, and 504 nm, respectively. For each Tsp and its
corresponding LF, the total IOFF is still identical for different
Wch cases. Fig. 13 shows the ratio of total ION at Wch = 16 nm
to that at Wch = 4 nm, and its variation with horizontal Tsp ,
for both Si and Ge channels with different orientation configu-
rations. This ratio indicates the relative change in the total ION
and its extent when the Wch increases from 4 to 16 nm. The
increase in horizontal Tsp is shown to benefit the performance
of the NSH-FET array with larger Wch , and the total ION of the
stacked NSH-FET array at Wch = 16 nm can surpass that at
Wch = 4 nm, with an appropriate horizontal Tsp reached. This
is because larger horizontal Tsp can mitigate the disadvantage
of the sheet density of a wider Wch in the iso-footprint cross
section. Fig. 13 also indicates that the impact of increase in
Wch strongly depends on the crystal orientation configuration.
For both Si and Ge channels, [110]/[001] leads to the device
performance most degraded by larger Wch , while the total ION
for [100]/[011] is least decreased or even improved due to its
weaker SDT. In general, the performance degradation of the
Ge stacked NSH-FET array caused by the increase in Wch is
more severe than that in the Si case.
V. C ONCLUSION
In summary, an in-house developed NEGF quantum trans-
port simulator is employed to investigate accurately the hybrid
effects of different device configurations on the performance of
individual as well as vertically stacked p-type Si and Ge NSH-
FETs at the sub-5-nm technology node. The wider channel
of NSH not only brings larger Weff but also weakens the
lateral gate control in the sheet width direction, which has
a significant negative impact on the Ge sheet with light-m eff .
Thus, for an individual NSH, Si NSH accounts for an overall
better performance than its Ge counterpart and takes greater
advantage of a larger Weff . [111]/[1̄10] and [100]/[011] are
shown to be the optimal crystal orientation configurations for
individual Si and Ge NSHs, respectively. In the iso-footprint
comparison of the stacked NSH-FET arrays, the performance
of the Ge channel is more sensitive to Wch than that of the
Si case. In particular, [100]/[011] orientation configuration is
the most promising option for the applications of both Si- and
Ge-stacked NSH-FETs with a larger Wch . The process-induced
Wch variation is shown to cause larger current fluctuation at
the OFF-state, while the ION fluctuates more drastically in the
horizontally wider Si and narrower Ge channels. In addition,
32
a larger horizontal Tsp is beneficial to the NSH-FET array
with a wider Wch , while fewer stacks and lower vertical Tsp
help NSH-FETs maintain superiority over the FinFET at
reduced Wch .
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