Lab report 10 - The Inductive DC-DC Converter

1st Luiz Augusto Frazatto Fernandes 2nd Yasmim de Souza

Department of Electrical and Electronic Engineering Department of Electrical and Electronic Engineering
Federal University of Santa Catarina Federal University of Santa Catarina
luiz.a.frazatto.fernandes@gmail.com yasmimdesouza30@gmail.com

Abstract—This report aims to analyze and build an inductive sL

DC-DC converter.
Index Terms—DC-DC converter, diode, capacitors. IL
IR

+ Vg 1/sC R
− V

I. B OOST ( STEP - UP ) CONVERTER

(b) Equivalent circuit when switch is in position 2.

The boost converter is a switched circuit which involves Fig. 2: Boost switching regulators equivalent circuits.
reactances, as well as resistances, in order to obtain a bigger
voltage output with the cost of providing lesser currents. The From the circuit 2a, it is possible to obtain:
described circuit can be seen below:
VG
VG = IL · sL =⇒ sIL = (1)
L
sL IR IR VOU T
2 VC = =⇒ sVC = =− (2)
sC C RC
1
Whilst, from 2b:
+ Vg 1/sC R
− V
VG − VOU T
sIL = (3)
L
VOU T
sVC = (4)
Fig. 1: Switching boost regulator. RC

Besides that, some more important conditions and charac-

teristics are considered:
From the circuit analysis, in the frequency domain, it is 1. The switch has a duty cycle of 50%.
possible to analyse the above circuit in two stages: switch in 2. The current through inductors does not oscillate abruptly.
the first and second position. 3. The voltage across capacitors does not oscillate abruptly.
4. The average current which flows through the source is
represented by IG .
sL 5. The switch oscillation frequency is 500kHz. Its period is,
then, 2µs.
IL 6. R = 1.5kΩ; L = 2mH; C = 33nF; VG = 5V.
IR
Therefore, the waveforms of both currents which flow
+ Vg 1/sC R through the inductor and the load can be graphically described
− V
as follows:
IR Whilst in steady-state, the current oscillates between two
values, called IM IN and IM AX . Given the inclination of
each line was calculated from the schematics, the proportion
(a) Equivalent circuit when switch is in position 1. between VG and VOU T can be calculated:
 VG T
IM IN + · = IM AX (5)
L 2 Imax

VG − VOU T T Iout

IM AX + · = IM IN (6) Imin
L 2

Current output from source (A)

(7)

Thus, by summing the two equations above:

VOU T = 2 · VG (8)

0 T/2 T 3T/2 2T 5T/2 3T 7T/2 4T

Time (s)

Therefore

Fig. 3: Current flowing through source in relation to time.

VG · T
IM IN = IG + (9)
4·L
VG · T
IM AX = IG − (10)
4·L

The average DC current which flows through the load is, Vout/R

on the other hand, easily described by the conservation of

Current through load resistance (A)

energy. Since the same energy which is generated from the

voltage source is consumed by the resistor, it is possible to
write: 0

PG = POU T (11)
-Vout/R
VG · IG = VOU T · IOU T (12)
VG IG
IOU T = IG · = (13) 0 T/2 T 3T/2 2T 5T/2 3T 7T/2 4T
VOU T 2 Time(s)

Then, from all conditions and circuit characteristics con- Fig. 4: Current flowing through load in relation to time.
sidered, and from the equations obtained above, it is possible
to calculate the current which flow through the inductor (and
II. E XPERIMENTAL R ESULTS
source) and load:
The experiments are concerning the inductive DC-DC con-
verter.
While experimentation, the following characteristics were
VOU T = 2 · VG = 10V (14) measured:
VOU T
IR = IOU T = ± = ±6.67mA (15) • V+5 = 5.02 V
R • V+5 = 5.02 V
IOU T,RM S = 6.67mA (16) ∼
• V min = 0.0 mV
IOU T,RM S ∼
IG = = 3.33mA (17) • V max = 10.9 mV
2
• C33 = 32.40 nF
IM AX = 4.58mA (18)
• L2m = 2 ∗ 1mH
IM IN = 2.08mA (19) • R750 = 737Ω (1,5k//1.5k)
• R1.5k = 424Ω
• R1k//750 = 97.7kΩ
We set up the circuit in figure 5.

Fig. 5: Schematic of the step-up converter.

Fig. 7: Waveforms of both the output and NMOS voltages;
CH1=CK and CH2=pin6.

TABLE I: DC-DC converter measurements. III. C ONCLUSIONS

The values obtained were close to the theoretical values.
Duty Cycle Load (Ω) V0 (V) Comparing the output voltage of the circuit with the duty
51.9 1.5k 9.45
39.8 1.5k 8.55
cycle, we realize that, as we increase the duty cycle, the output
59.9 1.5k 9.76 voltage increases. In addition, when the frequency changes
52.5 750 8.77 from 500 kHz to 250 kHz, with the same duty cycle, the
39.7 750 8.08 output voltage decreases considerably.
59.4 750 9.15
50.0 750//1k 8.43
41.0 750//1k 7.71
59.7 750//1k 9.01
52.4** 750//1k 7.69

**The last measurement was made with a frequency equal

to 250 kHz.
The waveforms of ”V0 ” and ”CK” are shown in the figure
6.

Fig. 6: DC-DC converter measurements; CH1=CK and

CH2=V0 .

We measure voltage drop on the NMOS transistor shown in

figure 5. We get the value of 4.64 V. The waveforms of both
output and NMOS voltages are shown in the figure 7.