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NBWAA
2
Low Cost Los Angeles 10L 2

LA-5821P REV 1.0 Schematics


3

Intel Penryn/ Cantiga/ ICH9M 3

2008-08-10 Rev. 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 1 of 41
A B C D E
A B C D E

Compal Confidential
Model Name : NBWAA Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control EMC1402-1 SLG8SP556VTR
File Name : LA-5821P page 5
uPGA-478 Package page 5 page 17
1
(Socket P) page 5,6,7
1

FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

CRT Memory BUS(DDRII)


page 18 200pin DDRII-SO-DIMM X2
Intel Cantiga Dual Channel BANK 0, 1, 2, 3 page 15,16
LCD Conn. GM45/GL40
page 18 1.8V DDRII 533/667/800

HDMI Conn. Level Shifter uFCBGA-1329


page 19 page 19
page 8,9,10,11,12,13,14

2
DMI x 4 C-Link 2
PCIeMini Card
USB USB/B USB conn
WLAN 5V 480MHz USB port 0,1 USB port 3
USB port 7 PCIe 1x [2,4,5] USB page 24 page 24
page 25
1.5V 2.5GHz(250MB/s)
5V 480MHz
PCIe port 4 Int. Camera
page 25 Intel ICH9-M USB port 11
page 18,25

BGA-676
RJ45 PCIe 1x SATA port 1 SATA HDD
page 26 RTL8103EL 10/100M 1.5V 2.5GHz(250MB/s) page 19,20,21,22 5V 1.5GHz(150MB/s) page 24
PCIe port 3 page 26
SATA port 4 SATA ODD
5V 1.5GHz(150MB/s) page 24
USB
RTS5159-VDD 3IN1 5V 480MHz
3 3
USB port 10 page 29

3.3V 33 MHz
LPC BUS
HD Audio 3.3V 24.576MHz/48Mhz

MDC 1.5 Conn HDA Codec


ALC272
Debug Port ENE KB926 D3 page 25 page 27
NBWAA Sub-boards page 31 page 30
RTC CKT.
page 21
USB/B AMP.
page 24
Touch Pad SPI ROM Int. TPA6017
DC/DC Interface CKT. Int.KBD MIC CONN MIC CONN HP CONN
page 31 page 31 page 31 page 28 page 28 page 28 page 28
page 33 Power/B
page 32
4 SPK CONN 4
page 28
Power Circuit DC/DC CS/B
page 31
page 34~40
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 2 of 41
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5 4 3 2 1

DESIGN CURRENT 0.1A +3VL


B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
SBPWR_EN#
N-CHANNEL DESIGN CURRENT 2mA +5V_SB
D 2N7002DW D

SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
TPS51125RGER DESIGN CURRENT 0.5A
DIODE FUSE
+HDMI_5V_OUT
PMEG2010AEH 1.1A_6V

Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW

WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413

SBPWR_EN#
C N-CHANNEL DESIGN CURRENT 225mA +3V_SB C
SI3456

SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 UMA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413

VR_ON
DESIGN CURRENT 47A +CPU_CORE
ISL6262ACRZ-T

SYSON
Ipeak=8A, Imax=5.6A, Iocp min=19.8 DESIGN CURRENT 10A +1.8V
TPS51117RGYR
SUSP
B B
DESIGN CURRENT 1.5A +0.9VS
APL5331KAC

SUSP#

Ipeak=5A, Imax=3.5A, Iocp min=16.5 DESIGN CURRENT 4A +1.5VS


TPS51124RGER Ipeak=10A, Imax=7A, Iocp min=16.5 DESIGN CURRENT 10.2A +1.05VS

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 3 of 41
5 4 3 2 1
A B C D E

Voltage Rails SIGNAL


STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Power Plane Description S1 S3 S5 G3 Full ON HIGH HIGH HIGH HIGH

VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
1 1
B+ AC or battery power rail for power circuit. ON ON ON ON
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+3VALW 3.3V always on power rail ON ON ON OFF
+3VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF
Function North Bridge RJ11 CAMERA MIC HDMI
+5VL 5V always on power rail ON ON ON ON
2
+5V_SB 5V power rail for SB ON ON OFF OFF description GM GL Y 2

+5VS 5V switched power rail ON OFF OFF OFF


explain GM45 GL40 MODEM CAMERA MIC HDMI Non-HDMI
+VSB VSB always on power rail ON ON ON OFF
GM45R3@ GL40R3@
+RTCVCC RTC power ON ON ON ON BTO GM45R1@ GL40R1@ MDC@ CAM@ MIC@ IHDMI@ NIHDMI@
+CPU_CORE Core voltage for VGA chip ON ON OFF OFF
+VGA_PCIE_1.1VS 1.1V switched power rail for VGA PCIE ON ON OFF OFF
+1.8VS 1.8V power rail for VRAM ON ON OFF OFF

External PCI Devices

EC SM Bus1 address EC SM Bus2 address


3 3
Power Device Address Power Device Address
+3VL EC KB926 D3 +3VS EC KB926 D3
+3VL Smart Battery 0001 011X b CPU THM Sen
+3VS SMSC SMC1402 0100 110x b
+3VL FUN/B (CAP Sensor)

ICH9M SM Bus address


Power Device Address
+3V_SB ICH9M

Clock Generator 1101 001Xb


4 +3VS (SLG8SP556V) 4

+3VS DDR DIMM0 1001 000Xb


+3VS DDR DIMM1 1001 010Xb
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 4 of 41
A B C D E
5 4 3 2 1

@
8 H_A#[3..16] +3VS
JCPUA
H_A#3 J4 H1
A[3]# ADS# H_ADS# 8

ADDR GROUP_0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 8
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 8
H_A#6 K5 1

0.1U_0402_16V4Z
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 8
H_A#8 N2 F21 C1
A[8]# DRDY# H_DRDY# 8
H_A#9 J1 E1 U1
A[9]# DBSY# H_DBSY# 8 2
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 8
H_A#12 P2 1 8
A[12]# VDD SMCLK EC_SMB_CK2 30

CONTROL
D H_A#13 L2 D20 H_IERR# R1 1 2 56_0402_5% +1.05VS D
H_A#14 A[13]# IERR# H_INIT# H_THERMDA
P4 A[14]# INIT# B3 H_INIT# 21 2 DP SMDATA 7 EC_SMB_DA2 30
H_A#15 P1 C2
H_A#16 A[15]# H_THERMDC
R1 A[16]# LOCK# H4 H_LOCK# 8 1 2 3 DN ALERT# 6 1 2 +3VS
M1 2200P_0402_50V7K R2 10K_0402_5%
8 H_ADSTB#0 ADSTB[0]#
C1 H_RESET# CPU_THERM# 4 5 @ Reserve for source control
RESET# H_RESET# 8 THERM# GND
8 H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 8
H2 F4 if use XDP,these resistor are 51ohm +1.05VS R3
8 H_REQ#1 REQ[1]# RS[1]# H_RS#1 8
8 H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 8 +3VS 1 2
J3 G2 XDP_TDO 1 2 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
8 H_REQ#3 REQ[3]# TRDY# H_TRDY# 8
8 H_REQ#4 L1 REQ[4]#
R14 54.9_0402_1% Address:0100_1100 EMC1402-1
G6 XDP_TMS 1 2 Address:0100_1101 EMC1402-2
8 H_A#[17..35] HIT# H_HIT# 8
H_A#17 Y2 E4 R4 54.9_0402_1%
A[17]# HITM# H_HITM# 8
H_A#18 U5 XDP_TDI 1 2
H_A#19 A[18]# R5 54.9_0402_1%
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]# XDP_TCK
U4 AD1 1 2
H_A#22
H_A#23
Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4
XDP_TRST#
R6 54.9_0402_1%
+5VS
FAN Control Circuit
U1 AC2 1 2

XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# R7 54.9_0402_1%
R4 A[24]# PREQ# AC1
H_A#25 T5 A[25]# TCK AC5 XDP_TCK 1A
H_A#26 T3 AA6 XDP_TDI
H_A#27 A[26]# TDI XDP_TDO
W2 A[27]# TDO AB3 PAD T13

1
H_A#28 W5 AB5 XDP_TMS +1.05VS 1 2
H_A#29 A[28]# TMS XDP_TRST# R8 @ 56_0402_5%
Y4 A[29]# TRST# AB6 1SS355_SOD323-2
H_A#30 U2 C20 XDP_DBRESET# 1 2 2
A[30]# DBR# XDP_DBRESET# 22
H_A#31 V4 R9 56_0402_5% @ D1
A[31]#

2
JFAN

B
H_A#32 W3 C3

2
H_A#33 A[32]# 10U_0805_10V4Z +FAN1
AA4 A[33]# THERMAL 1
1 1

E
C H_A#34 AB2 H_PROCHOT# 3 1 2 C
A[34]# OCP# 22 2

1
C
H_A#35 AA3 D21 H_PROCHOT# Q6 2 3
A[35]# PROCHOT# H_THERMDA @ MMBT3904_SOT23 U2 3
8 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC PROCHOT# PU: 68Ohm near CPU and MVP6. 1 8 D2 C4 4
H_A20M# THERMDC EN GND @ @ 1000P_0402_25V8J GND
21 H_A20M# A6 A20M# 56Ohm near CPU if no used. 2 VIN GND 7 5 GND
1
ICH

H_FERR# A5 C7 +FAN1 3 6
21 H_FERR# H_THERMTRIP# 9,21

2
H_IGNNE# FERR# THERMTRIP# VOUT GND
21 H_IGNNE# C4 IGNNE# 30 EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
1 BAS16_SOT23-3
21 H_STPCLK#
H_STPCLK# D5 STPCLK#
10mil APL5607KI-TRG_SO8 @
H_INTR C6 H CLK C5
21 H_INTR LINT0
H_NMI B4 A22 H_THERMDA, H_THERMDC routing together, 10U_0805_10V4Z R10 10K_0402_5%
21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 17 2
H_SMI# A3 A21 2 1 +3VS
21 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17 Trace width / Spacing = 10 / 10 mil
M4 RSVD[01] FAN_SPEED1 30
N5 RSVD[02] 2
T2 RSVD[03]
V3 C6
RSVD[04]
B2 0.01U_0402_16V7K
RESERVED

RSVD[05] 1 @
D2 RSVD[06]
D22 RSVD[07]
Reserve for D3 RSVD[08]
F6
debug RSVD[09]
close to South
Bridge
Penryn

H_FERR# 2 1
B C596 180P_0402_50V8J B

H_SMI# 2 1
C597 180P_0402_50V8J
H_INIT# 2 1
C598 180P_0402_50V8J
H_NMI 2 1
C599 180P_0402_50V8J
H_A20M# 2 1
C600 180P_0402_50V8J
H_INTR 2 1
C601 180P_0402_50V8J
H_IGNNE# 2 1
C602 180P_0402_50V8J
H_STPCLK# 2 1
C603 180P_0402_50V8J

Reserve for
debug
close to CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/THM/FAN
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 5 of 41
5 4 3 2 1
5 4 3 2 1

@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
8 H_D#[0..15] @ A16 R5
H_D#[32..47] 8 VSS[005] VSS[086]
JCPUB A19 R22
H_D#0 H_D#32 VSS[006] VSS[087]
E22 D[0]# D[32]# Y22 A23 VSS[007] VSS[088] R25
H_D#1 F24 AB24 H_D#33 AF2 T1
H_D#2 D[1]# D[33]# H_D#34 VSS[008] VSS[089]
E26 D[2]# D[34]# V24 B6 VSS[009] VSS[090] T4

DATA GRP 0
D H_D#3 G22 V26 H_D#35 B8 T23 D
D[3]# D[35]# VSS[010] VSS[091]

DATA GRP 2
H_D#4 F23 V23 H_D#36 B11 T26
H_D#5 D[4]# D[36]# H_D#37 VSS[011] VSS[092]
G25 D[5]# D[37]# T22 B13 VSS[012] VSS[093] U3
H_D#6 E25 U25 H_D#38 B16 U6
H_D#7 D[6]# D[38]# H_D#39 VSS[013] VSS[094]
E23 D[7]# D[39]# U23 B19 VSS[014] VSS[095] U21
H_D#8 K24 Y25 H_D#40 B21 U24
H_D#9 D[8]# D[40]# H_D#41 VSS[015] VSS[096]
G24 D[9]# D[41]# W22 B24 VSS[016] VSS[097] V2
H_D#10 J24 Y23 H_D#42 C5 V5
H_D#11 D[10]# D[42]# H_D#43 VSS[017] VSS[098]
J23 D[11]# D[43]# W24 C8 VSS[018] VSS[099] V22
H_D#12 H22 W25 H_D#44 C11 V25
H_D#13 D[12]# D[44]# H_D#45 VSS[019] VSS[100]
F26 D[13]# D[45]# AA23 C14 VSS[020] VSS[101] W1
H_D#14 K22 AA24 H_D#46 C16 W4
H_D#15 D[14]# D[46]# H_D#47 VSS[021] VSS[102]
H23 D[15]# D[47]# AB25 C19 VSS[022] VSS[103] W23
8 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 8 C2 VSS[023] VSS[104] W26
8 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 8 C22 VSS[024] VSS[105] Y3
8 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 8 C25 VSS[025] VSS[106] Y6
8 H_D#[16..31] H_D#[48..63] 8 D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
H_D#16 N22 AE24 H_D#48 D8 AA2
H_D#17 D[16]# D[48]# H_D#49 VSS[028] VSS[109]
K25 D[17]# D[49]# AD24 D11 VSS[029] VSS[110] AA5
H_D#18 P26 AA21 H_D#50 D13 AA8
D[18]# D[50]# VSS[030] VSS[111]
H_D#19 R23 D[19]# D[51]# AB22 H_D#51 Resistor placed within D16 VSS[031] VSS[112] AA11
H_D#20 L23 AB21 H_D#52 D19 AA14
D[20]# D[52]# 0.5" of CPU pin.Trace VSS[032] VSS[113]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D23 AA16
D[21]# D[53]# VSS[033] VSS[114]

DATA GRP 3
H_D#22 L22 D[22]# D[54]# AD20 H_D#54 should be at least 25 D26 VSS[034] VSS[115] AA19
H_D#23 M23 AE22 H_D#55 E3 AA22
H_D#24 D[23]# D[55]# H_D#56
mils away from any other VSS[035] VSS[116]
P25 D[24]# D[56]# AF23 E6 VSS[036] VSS[117] AA25
H_D#25 P23 D[25]# D[57]# AC25 H_D#57 toggling signal. E8 VSS[037] VSS[118] AB1
H_D#26 P22 AE21 H_D#58 COMP[0,2] trace width is E11 AB4
C H_D#27 D[26]# D[58]# H_D#59 VSS[038] VSS[119] C
T24 AD21 E14 AB8
+1.05VS Close to H_D#28 R24
D[27]# D[59]#
AC22 H_D#60 18 mils. COMP[1,3] trace E16
VSS[039] VSS[120]
AB11
D[28]# D[60]# VSS[040] VSS[121]
CPU pin H_D#29 L25 D[29]# D[61]# AD23 H_D#61 width is 4 mils. E19 VSS[041] VSS[122] AB13
H_D#30 T25 AF22 H_D#62 E21 AB16
AD26 D[30]# D[62]# VSS[042] VSS[123]
1

H_D#31 N25 AC23 H_D#63 E24 AB19


within D[31]# D[63]# VSS[043] VSS[124]
8 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 8 F5 VSS[044] VSS[125] AB23
R11 500mils. 8 H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 8
COMP0 1 2 F8 VSS[045] VSS[126] AB26
1K_0402_1% N24 AC20 R12 27.4_0402_1% F11 AC3
8 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 8 VSS[046] VSS[127]
COMP1 1 2 F13 AC6
2

+CPU_GTLREF +CPU_GTLREF COMP0 R13 54.9_0402_1% VSS[047] VSS[128]


AD26 GTLREF COMP[0] R26 F16 VSS[048] VSS[129] AC8
C23 MISC U26 COMP1 COMP2 1 2 F19 AC11
TEST1 COMP[1] VSS[049] VSS[130]
1

D25 AA1 COMP2 R15 27.4_0402_1% F2 AC14


TEST2 COMP[2] COMP3 COMP3 VSS[050] VSS[131]
C24 TEST3 COMP[3] Y1 1 2 F22 VSS[051] VSS[132] AC16
R17 AF26 R18 54.9_0402_1% F25 AC19
2K_0402_1% TEST4 H_DPRSTP# VSS[052] VSS[133]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# 9,21,40 G4 VSS[053] VSS[134] AC21
A26 B5 H_DPSLP# G1 AC24
H_DPSLP# 21
2

TEST6 DPSLP# VSS[054] VSS[135]


C3 TEST7 DPWR# D24 H_DPW R# 8 G23 VSS[055] VSS[136] AD2
B22 D6 H_PW RGOOD G26 AD5
9,17 CPU_BSEL0 BSEL[0] PWRGOOD H_PW RGOOD 21 VSS[056] VSS[137]
B23 D7 H_CPUSLP# H3 AD8
9,17 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 8 VSS[057] VSS[138]
9,17 CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 40 H6 VSS[058] VSS[139] AD11
layout note: Please use "Daisy Chain" H21 VSS[059] VSS[140] AD13
Penryn H24 AD16
to layout and the signal (H_DPRSTP#) J2
VSS[060] VSS[141]
AD19
VSS[061] VSS[142]
is routed from ICH9 to power IC, J5 VSS[062] VSS[143] AD22
then to NB and CPU J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 K26 VSS[068] VSS[149] AE14
Reserve for L3 VSS[069] VSS[150] AE16
H_CPUSLP# 2 1 L6 AE19
C650 180P_0402_50V8J debug L21
VSS[070] VSS[151]
AE23
VSS[071] VSS[152]
166 0 1 1 H_PW RGOOD 2 1 close to CPU L24 VSS[072] VSS[153] AE26
C651 180P_0402_50V8J M2 A2
H_DPRSTP# VSS[073] VSS[154]
2 1 M5 VSS[074] VSS[155] AF6
C652 180P_0402_50V8J M22 AF8
VSS[075] VSS[156]
200 0 1 0 H_DPSLP# 2 1 M25 VSS[076] VSS[157] AF11
C653 180P_0402_50V8J N1 AF13
VSS[077] VSS[158]
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
266 0 0 0 N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25

Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/GND
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 6 of 41
5 4 3 2 1
5 4 3 2 1

+CPU_CORE
Near CPU CORE regulator
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M +CPU_CORE
1 1 1 1

ESR <= 1.5m ohm C7


+
C8
+
C9
+
C10
+
1
C11
1
C12
1
C13
1
C14
1
C15
1
C16
1
C17
1
C18
Capacitor > 1980uF @
2 2 2 2
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 2 2 2 2 2 2 2 2

Change to SGA00002680
D D
+CPU_CORE +CPU_CORE +CPU_CORE
@
JCPUC
A7 VCC[001] VCC[068] AB20 1 1 1 1 1 1 1 1
A9 AB7 C19 C20 C21 C22 C23 C24 C25 C26
VCC[002] VCC[069] Place these capacitors on L8
A10 VCC[003] VCC[070] AC7
A12 AC9 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[004] VCC[071] 2 2 2 2 2 2 2 2
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 VCC[007] VCC[074] AC15
A18 VCC[008] VCC[075] AC17
+CPU_CORE
A20 VCC[009] VCC[076] AC18
B7 VCC[010] VCC[077] AD7
B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10 1 1 1 1 1 1 1 1
B12 AD12 C27 C28 C29 C30 C31 C32 C33 C34
VCC[013] VCC[080] Place these capacitors on L8
B14 VCC[014] VCC[081] AD14
B15 AD15 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[015] VCC[082] 2 2 2 2 2 2 2 2
B17 VCC[016] VCC[083] AD17
B18 VCC[017] VCC[084] AD18
B20 VCC[018] VCC[085] AE9
C9 VCC[019] VCC[086] AE10
+CPU_CORE
C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17 1 1 1 1 1 1 1 1
C17 AE18 C35 C36 C37 C38 C39 C40 C41 C42
VCC[024] VCC[091] Place these capacitors on L8
C18 VCC[025] VCC[092] AE20
C D9 AF9 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
VCC[026] VCC[093] 2 2 2 2 2 2 2 2
D10 VCC[027] VCC[094] AF10
D12 VCC[028] VCC[095] AF12
D14 VCC[029] VCC[096] AF14
D15 VCC[030] VCC[097] AF15
D17
D18
VCC[031] VCC[098] AF17
AF18
Mid Frequence Decoupling
VCC[032] VCC[099] +1.05VS
E7 VCC[033] VCC[100] AF20
E9 VCC[034]
E10 VCC[035] VCCP[01] G21
E12 V6 1 1 Place these inside socket cavity on L8
VCC[036] VCCP[02] +1.05VS (North side Secondary)
E13 VCC[037] VCCP[03] J6
E15 K6 + +
VCC[038] VCCP[04]
E17 VCC[039] VCCP[05] M6
E18 J21 @ C43 C912 1 1 1 1 1 1
VCC[040] VCCP[06] 2 2 C44 C45 C46 C47 C48 C49
E20 VCC[041] VCCP[07] K21
F7 M21 330U_D2_2VY_R7M 330U_6.3V_M_R15
VCC[042] VCCP[08] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
F9 VCC[043] VCCP[09] N21
2 2 2 2 2 2
F10 VCC[044] VCCP[10] N6
F12 VCC[045] VCCP[11] R21
F14 VCC[046] VCCP[12] R6 reserve for test
F15 VCC[047] VCCP[13] T21
F17 VCC[048] VCCP[14] T6
F18 VCC[049] VCCP[15] V21
F20 VCC[050] VCCP[16] W21
AA7 VCC[051] Near pin B26
AA9 VCC[052] VCCA[01] B26 +1.5VS
AA10 VCC[053] VCCA[02] C26 1 1
AA12 C51
B VCC[054] C50 B
AA13 VCC[055] VID[0] AD6 CPU_VID0 40
AA15 AF5 CPU_VID1 40 0.01U_0402_16V7K 10U_0805_6.3V6M
VCC[056] VID[1] 2 2
AA17 VCC[057] VID[2] AE5 CPU_VID2 40
AA18 VCC[058] VID[3] AF4 CPU_VID3 40
AA20 VCC[059] VID[4] AE3 CPU_VID4 40
AB9 VCC[060] VID[5] AF3 CPU_VID5 40
AC10 VCC[061] VID[6] AE2 CPU_VID6 40
AB10 VCC[062]
AB12 VCC[063]
AB14 AF7 VCCSENSE VCCSENSE 40
VCC[064] VCCSENSE
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 40
VCC[067] VSSSENSE
Penryn
.

+CPU_CORE

VCCSENSE 100_0402_1% 2 1 R19

VSSSENSE 100_0402_1% 2 1 R20

A Close to CPU pin A

within 500mils.

Length match within 25 mils.


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
The trace width/space/other is Penryn(3/3)-PWR/Bypass
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
14/7/25. Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 7 of 41
5 4 3 2 1
5 4 3 2 1

H_A#[3..35] 5
6 H_D#[0..63] U3A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
D H_D#7 F6 R16 H_A#11 D
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# 5
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 5
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 5
C H_D#36 Y12 A9 C
H_D#_36 H_BNR# H_BNR# 5

HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 5
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# 5
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 5
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 5
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 17
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 17
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPW R# 6
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# 5
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# 5
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# 5
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 5
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 5
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8 H_D#_51
Layout Note: H_D#52 AA3 H_D#_52
H_D#53 AD3 J8
H_RCOMP / +H_VREF / H_SWNG H_D#54 AD7
H_D#_53 H_DINV#_0
L3
H_DINV#0 6
H_D#_54 H_DINV#_1 H_DINV#1 6
trace width and spacing is 10/20 H_D#55 AE14 H_D#_55 H_DINV#_2 Y13 H_DINV#2 6
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 6
within 100 mils from NB H_D#57 AC1 H_D#_57
H_D#58 AE3 L10
H_D#_58 H_DSTBN#_0 H_DSTBN#0 6
H_D#59 AC3 M7
+1.05VS +1.05VS H_D#_59 H_DSTBN#_1 H_DSTBN#1 6
H_D#60 AE11 AA5
H_D#_60 H_DSTBN#_2 H_DSTBN#2 6
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 6
H_D#62 AG2 H_D#_62
1

H_D#63 AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#0 6
R22 M8
B H_DSTBP#_1 H_DSTBP#1 6 B
R21 221_0402_1% AA6
H_DSTBP#_2 H_DSTBP#2 6
1K_0402_1% H_SW NG C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 6
H_SWING=0.3125*VCCP H_RCOMP E3
1 2

+H_VREF H_RCOMP H_SW NG H_RCOMP


H_REQ#_0 B15 H_REQ#0 5
H_REQ#_1 K13 H_REQ#1 5
1

1 1 H_REQ#_2 F13 H_REQ#2 5


R23 C52 R24 B13
H_REQ#_3 H_REQ#3 5
2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% R25 C53 C12 B14
5 H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 5
@ 100_0402_1% 0.1U_0402_16V4Z E11
6 H_CPUSLP#
2

2 2 H_CPUSLP#
B6 H_RS#0 5
2

H_RS#_0
H_RS#_1 F12 H_RS#1 5
Near B3 pin +H_VREF A11 H_AVREF H_RS#_2 C8 H_RS#2 5
B11 H_DVREF
CANTIGA ES_FCBGA1329
GM45R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 8 of 41
5 4 3 2 1
5 4 3 2 1

Strap Pin Table +1.8V


U3B
011 = FSB667
CFG[2:0] 010 = FSB800 M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 15

1
000 = FSB1067 N36
RSVD2 SA_CK_1
AT21 DDRA_CLK1 15
R33 AV24 R26
RSVD3 SB_CK_0 DDRB_CLK0 16
0 = DMI x 2 T33 AU20 1K_0402_1%
RSVD4 SB_CK_1 DDRB_CLK1 16

COMPENSATION
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH9 RSVD5
AH10 AR24 DDRA_CLK0# 15

2
RSVD6 SA_CK#_0 +SM_RCOMP_VOH
0 = iTPM Host Interface is enabled can support disble by SW. AH12
RSVD7 SA_CK#_1
AR21 DDRA_CLK1# 15
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled *(Default) AH13
K12
RSVD8 SB_CK#_0 AU24
AV20
DDRB_CLK0# 16
RSVD9 SB_CK#_1 DDRB_CLK1# 16 1 1

1
0 = Intel Management Engine Crypto Transport Layer Security AL34 2.2U_0603_6.3V6K
RSVD10 C54 C55
AK34 BC28 DDRA_CKE0 15
(TLS) cipher suite with no confidentiality AN35
RSVD11 SA_CKE_0
AY28 DDRA_CKE1 15
0.01U_0402_16V7K R27
D RSVD12 SA_CKE_1 2 2 D
CFG7 Internal pull-up AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 16 SM_DRAMRST# would be 3.01K_0402_1%
1 = Intel Management Engine Crypto TLS cipher suite with T24 BB36 DDRB_CKE1 16 needed for DDR3 only

2
RSVD14 SB_CKE_1
confidentiality *(Default) BA17 DDRA_SCS0# 15
SA_CS#_0 +SM_RCOMP_VOL
AY16 DDRA_SCS1# 15
SA_CS#_1
0 = Lane Reversal Enable B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 16 For Cantiga 80 Ohm

1
CFG9 Internal pull-up 1 = Normal Operation *(Default) B2
RSVD16 SB_CS#_1
AR13 DDRB_SCS1# 16 1 1

DDR CLK/ CONTROL/


M1 2.2U_0603_6.3V6K
RSVD17

RSVD
0 = PCIe Loopback Enable BD17 C56 C57 R28
SA_ODT_0 DDRA_ODT0 15
CFG10 Internal pull-up 1 = Disable*(Default) SA_ODT_1
AY17 DDRA_ODT1 15
0.01U_0402_16V7K 1K_0402_1%
2 2
AY21 BF15 DDRB_ODT0 16

2
RSVD20 SB_ODT_O +1.8V +1.8V
01 = All Z Mode Enabled SB_ODT_1
AY13 DDRB_ODT1 16
CFG[13:12] 00 = Reserved
SMRCOMP
10 = XOR Mode Enabled BG22 R29 1 2 80.6_0402_1%
SM_RCOMP

2
Internal pull-up 11 = Normal Operation*(Default) BG23 BH21 SMRCOMP# R30 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R31
BF23
RSVD23 +SM_RCOMP_VOH
0 = Dynamic ODT Disabled BH18 RSVD24 SM_RCOMP_VOH BF28 1K_0402_1%
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) BF18 BH28 +SM_RCOMP_VOL
RSVD25 SM_RCOMP_VOL
20mil

1
0 = Normal Operation AV42 +SM_VREF
SM_VREF SM_PWROK
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable *(Default) SM_PWROK
AR36 R32 1 2 0_0402_5%

2
BF17 SM_REXT R33 1 2 499_0402_1% 1
SM_REXT R34
CFG20
Internal pull-down
0 = Only PCIE or [SDVO/DP/HDMI] is operational. * (Default) SM_DRAMRST# BC36
C58 1K_0402_1%
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. 0.1U_0402_16V4Z
CLK_DREF_96M 2 @
B38 CLK_DREF_96M 17

1
DPLL_REF_CLK CLK_DREF_96M#
A38 CLK_DREF_96M# 17
DPLL_REF_CLK# CLK_DREF_SSC
E41 CLK_DREF_SSC 17
DPLL_REF_SSCLK CLK_DREF_SSC#
DPLL_REF_SSCLK# F41 CLK_DREF_SSC# 17

CLK
F43 CLK_MCH_3GPLL 17
PEG_CLK
E43 CLK_MCH_3GPLL# 17
C PEG_CLK# C

DMI_RXN_0 AE41 DMI_ITX_MRX_N0 20


DMI_RXN_1 AE37 DMI_ITX_MRX_N1 20
AE47 DMI_ITX_MRX_N2 20
DMI_RXN_2 +1.05VS
DMI_RXN_3 AH39 DMI_ITX_MRX_N3 20

DMI_RXP_0 AE40 DMI_ITX_MRX_P0 20


6,17 CPU_BSEL0
R35 2 1 1K_0402_5% MCH_CLKSEL0 T25 AE38 DMI_ITX_MRX_P1 20
CFG_0 DMI_RXP_1

1
R36 2 1 1K_0402_5% MCH_CLKSEL1 R25 AE48 +3VS
6,17 CPU_BSEL1 CFG_1 DMI_RXP_2 DMI_ITX_MRX_P2 20
6,17 CPU_BSEL2
R37 2 1 1K_0402_5% MCH_CLKSEL2 P25 AH40 DMI_ITX_MRX_P3 20
R38
CFG_2 DMI_RXP_3 Lane reversal 1K_0402_5%
T14 PAD P20 CFG_3
T15 PAD MCH_CFG_5 P24 AE35 DMI_MTX_IRX_N0 20
CFG_4 DMI_TXN_0

1
R39 2@ 2.21K_0402_1%

DMI
1 C25 AE43 DMI_MTX_IRX_N1 20

2
R40 MCH_CFG_6 CFG_5 DMI_TXN_1
1 2@ 2.21K_0402_1% N24 AE46 DMI_MTX_IRX_N2 20
R41 R42
R43 MCH_CFG_7 CFG_6 DMI_TXN_2
1 2@ 2.21K_0402_1% M24 AH42 DMI_MTX_IRX_N3 20
54.9_0402_1% 1K_0402_5%
CFG_7 DMI_TXN_3

2
CFG

B
E21
R44 MCH_CFG_9 CFG_8
1 2@ 2.21K_0402_1% C23 AD35 DMI_MTX_IRX_P0 20

2
CFG_9 DMI_TXP_0

E
R45 1 2@ 2.21K_0402_1% MCH_CFG_10 C24 AE44 MCH_TSATN# 3 1
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 20 MCH_TSATN_EC# 30

C
N21 AF46 Q7
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 20
R46 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 MMBT3904_SOT23-3
MCH_CFG_13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 20
R47 1 2@ 2.21K_0402_1% T21
CFG_13
R20
CFG_14
M20
+3VS R48 MCH_CFG_16 CFG_15
1 2@ 2.21K_0402_1% L21
CFG_16
H21 CFG_17
P29

GRAPHICS VID
T16 PAD MCH_CFG_19 CFG_18
R49 1 2 4.02K_0402_1% R28
R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28
CFG_19
CFG_20 GFX_VID_0
B33 Strap Pin Table
B32
GFX_VID_1
B GFX_VID_2
G33 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default) B
PM_SYNC#_R GFX_VID_3 F33 (Internal pull-down) 1 = SDVO interface Port B enabled
22 PM_SYNC# R51 1 2 0_0402_5% R29 E33
PM_SYNC# GFX_VID_4
+3VS 1 2 PM_EXTTS#_R 6,21,40 H_DPRSTP# B7 DDPC_CTRLDATA *(Default)
0 = Digital display (iHDMI/DP) interface disabled
R52 10K_0402_5% PM_DPRSTP#
N33 PM_EXT_TS#_0 (Internal pull-down) 1 = Digital display (iHDMI/DP) interface Port C enabled
PM

15,16 PM_EXTTS# R53 1 2 0_0402_5% PM_EXTTS#_R P32


GMCH_PWROK PM_EXT_TS#_1
AT40 C34
PWROK GFX_VR_EN
20,25,26,30,31 PLT_RST# R54 1 2 100_0402_5% MCH_RSTIN# AT11
R55 NB_THERMTRIP# RSTIN# +1.05VS
5,21 H_THERMTRIP# 1 2 0_0402_5% T20
R56 0_0402_5% DPRSLPVR THERMTRIP#
22,40 PM_DPRSLPVR 1 2 R32
DPRSLPVR

2
BG48 AH37 R57
NC_1 CL_CLK CL_CLK0 22
Use VGATE for GMCH_PWROK BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 22
ME

BD48 AN36 ICH_PWROK Width:Spacing


GMCH_PWROK NC_3 CL_PWROK
22,30,40 VGATE 1 2 BC48 AJ35 CL_RST#0 22 12mil:12mil CL_VREF

1
R58 @ 0_0402_5% NC_4 CL_RST# +CL_VREF
BH47 AH34 should be
NC_5 CL_VREF
22,30 ICH_PWROK 1 2 BG47
NC_6
+CL_VREF=0.355V 0.35 V

2
R59 0_0402_5% BE47 1
NC_7 C59 R60
BH46 N28
NC_8 DDPC_CTRLCLK
NC

BF46 M28 0.1U_0402_16V4Z 499_0402_1%


NC_9 DDPC_CTRLDATA SDVO_SCLK
BG45 G36 SDVO_SCLK 19
NC_10 SDVO_CTRLCLK SDVO_SDATA 2
BH44 E36 SDVO_SDATA 19

1
NC_11 SDVO_CTRLDATA +3VS
BH43 K36 CLKREQ_3GPLL# 17
NC_12 CLKREQ#
MISC

BH6 NC_13 ICH_SYNC# H36 MCH_ICH_SYNC# 22


BH5 SDVO_SCLK 2 1 2.2K_0402_5%
NC_14 R61
BG4
NC_15 MCH_TSATN# SDVO_SDATA 2
BH3 NC_16 TSATN# B12 1 2.2K_0402_5%
BF3 R62 IHDMI@
NC_17
BH2
NC_18
BG2
NC_19
the strap pin will impact no IHDMI SKU if mount
BE2 B28 AZ_BITCLK_MCH 21
NC_20 HDA_BCLK
BG1 NC_21 HDA_RST# B30 AZ_RST_MCH# 21
A AZ_SDIN2_MCH_R A
BF1 B29 1 2 AZ_SDIN2_MCH 21
NC_22 HDA_SDI R63 33_0402_5%
BD1 NC_23 HDA_SDO C29 AZ_SDOUT_MCH 21
BC1 A28 IHDMI@
HDA

NC_24 HDA_SYNC AZ_SYNC_MCH 21


F1
NC_25
A47 NC_26
CANTIGA ES_FCBGA1329
GM45R3@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(2/7)-GTL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 9 of 41
5 4 3 2 1
5 4 3 2 1

D D
15 DDR_A_D[0..63] 16 DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AJ38 BD21 DDR_B_D0 AK47 BC16
SA_DQ_0 SA_BS_0 DDR_A_BS0 15 SB_DQ_0 SB_BS_0 DDR_B_BS0 16
DDR_A_D1 AJ41 BG18 DDR_B_D1 AH46 BB17
SA_DQ_1 SA_BS_1 DDR_A_BS1 15 SB_DQ_1 SB_BS_1 DDR_B_BS1 16
DDR_A_D2 AN38 AT25 DDR_B_D2 AP47 BB33
SA_DQ_2 SA_BS_2 DDR_A_BS2 15 SB_DQ_2 SB_BS_2 DDR_B_BS2 16
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 15 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_B_D5 AJ48 AU17
SA_DQ_5 SA_CAS# DDR_A_CAS# 15 SB_DQ_5 SB_RAS# DDR_B_RAS# 16
DDR_A_D6 AM44 AY20 DDR_B_D6 AM48 BG16
SA_DQ_6 SA_WE# DDR_A_W E# 15 SB_DQ_6 SB_CAS# DDR_B_CAS# 16
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_W E# 16
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 DDR_A_DM[0..7] 15 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
SA_DQ_14 SA_DM_1 SB_DQ_14 DDR_B_DM[0..7] 16
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6

B
SA_DQ_21 SB_DQ_21 SB_DM_6

A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] 15 SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] 16
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0

MEMORY
C DDR_A_D26 AV37 BC37 DDR_A_DQS3 DDR_B_D26 BH35 AV48 DDR_B_DQS1 C
MEMORY
DDR_A_D27 SA_DQ_26 SA_DQS_3 DDR_A_DQS4 DDR_B_D27 SB_DQ_26 SB_DQS_1 DDR_B_DQS2
AT36 SA_DQ_27 SA_DQS_4 AW12 BG35 SB_DQ_27 SB_DQS_2 BG41
DDR_A_D28 AY38 BC8 DDR_A_DQS5 DDR_B_D28 BH40 BG37 DDR_B_DQS3
DDR_A_D29 SA_DQ_28 SA_DQS_5 DDR_A_DQS6 DDR_B_D29 SB_DQ_28 SB_DQS_3 DDR_B_DQS4
BB38 SA_DQ_29 SA_DQS_6 AU8 BG39 SB_DQ_29 SB_DQS_4 BH9
DDR_A_D30 AV36 AM7 DDR_A_DQS7 DDR_B_D30 BG34 BB2 DDR_B_DQS5
DDR_A_D31 SA_DQ_30 SA_DQS_7 DDR_B_D31 SB_DQ_30 SB_DQS_5 DDR_B_DQS6
AW36 SA_DQ_31 BH34 SB_DQ_31 SB_DQS_6 AU1
DDR_A_D32 BD13 DDR_B_D32 BH14 AN6 DDR_B_DQS7
SA_DQ_32 DDR_A_DQS#[0..7] 15 SB_DQ_32 SB_DQS_7
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 DDR_A_DQS#1 DDR_B_D34 BH11 SB_DQ_34 DDR_B_DQS#[0..7] 16
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0

SYSTEM
DDR_A_D36 BD37 DDR_A_DQS#3 DDR_B_D36 AV47 DDR_B_DQS#1
SYSTEM

AU13 SA_DQ_36 SA_DQS#_3 BH12 SB_DQ_36 SB_DQS#_1


DDR_A_D37 AV13 AY12 DDR_A_DQS#4 DDR_B_D37 BF11 BH41 DDR_B_DQS#2
DDR_A_D38 SA_DQ_37 SA_DQS#_4 SB_DQ_37 SB_DQS#_2
BD12 SA_DQ_38 SA_DQS#_5 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 SB_DQ_38 SB_DQS#_3 BH37 DDR_B_DQS#3
DDR_A_D39 BC12 AU9 DDR_A_DQS#6 DDR_B_D39 BG7 BG9 DDR_B_DQS#4
DDR_A_D40 SA_DQ_39 SA_DQS#_6 SB_DQ_39 SB_DQS#_4
BB9 SA_DQ_40 SA_DQS#_7 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 SB_DQ_40 SB_DQS#_5 BC2 DDR_B_DQS#5
DDR_A_D41 BA9 DDR_B_D41 BC6 AT2 DDR_B_DQS#6
DDR_A_D42 SA_DQ_41 DDR_B_D42 SB_DQ_41 SB_DQS#_6
AU10 SA_DQ_42 DDR_A_MA[0..14] 15 AY3 SB_DQ_42 SB_DQS#_7 AN5 DDR_B_DQS#7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] 16
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1


DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
DDR_A_D48 AV5 BG25 DDR_A_MA4 DDR_B_D48 AV2 AU25 DDR_B_MA3
DDR_A_D49 SA_DQ_48 SA_MA_4 DDR_A_MA5 DDR_B_D49 SB_DQ_48 SB_MA_3 DDR_B_MA4
AV7 SA_DQ_49 SA_MA_5 BA24 AU3 SB_DQ_49 SB_MA_4 AW25
DDR_A_D50 AT9 BD24 DDR_A_MA6 DDR_B_D50 AR3 BB28 DDR_B_MA5
DDR_A_D51 SA_DQ_50 SA_MA_6 DDR_A_MA7 DDR_B_D51 SB_DQ_50 SB_MA_5 DDR_B_MA6
AN8 SA_DQ_51 SA_MA_7 BG27 AN2 SB_DQ_51 SB_MA_6 AU28
DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D52 AY2 AW28 DDR_B_MA7
DDR_A_D53 SA_DQ_52 SA_MA_8 DDR_A_MA9 DDR_B_D53 SB_DQ_52 SB_MA_7 DDR_B_MA8
AU6 SA_DQ_53 SA_MA_9 AW24 AV1 SB_DQ_53 SB_MA_8 AT33
DDR_A_D54 AT5 BC21 DDR_A_MA10 DDR_B_D54 AP3 BD33 DDR_B_MA9
B DDR_A_D55 SA_DQ_54 SA_MA_10 DDR_A_MA11 DDR_B_D55 SB_DQ_54 SB_MA_9 DDR_B_MA10 B
AN10 SA_DQ_55 SA_MA_11 BG26 AR1 SB_DQ_55 SB_MA_10 BB16
DDR_A_D56 AM11 BH26 DDR_A_MA12 DDR_B_D56 AL1 AW33 DDR_B_MA11
DDR_A_D57 SA_DQ_56 SA_MA_12 DDR_A_MA13 DDR_B_D57 SB_DQ_56 SB_MA_11 DDR_B_MA12
AM5 SA_DQ_57 SA_MA_13 BH17 AL2 SB_DQ_57 SB_MA_12 AY33
DDR_A_D58 AJ9 AY25 DDR_A_MA14 DDR_B_D58 AJ1 BH15 DDR_B_MA13
DDR_A_D59 SA_DQ_58 SA_MA_14 DDR_B_D59 SB_DQ_58 SB_MA_13 DDR_B_MA14
AJ8 SA_DQ_59 AH1 SB_DQ_59 SB_MA_14 AU33
DDR_A_D60 AN12 DDR_B_D60 AM2
DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
GM45R3@ GM45R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(3/7)-GTL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 10 of 41
5 4 3 2 1
5 4 3 2 1

+3VS U3C
within 500 mils
1 2 LCTLA_CLK 18 NB_INVT_PW M L32
R64 10K_0402_5% L_BKLT_CTRL PEG_COMP 1
30 UMA_ENBKL G32 L_BKLT_EN PEG_COMPI T37 2 +1.05VS
1 2 LCTLB_DATA LCTLA_CLK M32 T36 R65 49.9_0402_1%
R66 10K_0402_5% LCTLB_DATA L_CTRL_CLK PEG_COMPO
UMA_LCD_EDID_CLK
M33
UMA_LCD_EDID_CLK K33 L_CTRL_DATA 10mils
1 2 18 UMA_LCD_EDID_CLK L_DDC_CLK
R67 2.2K_0402_5% 18 UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44
UMA_LCD_EDID_DATA UMA_ENVDD L_DDC_DATA PEG_RX#_0
1 2 18 UMA_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
R68 2.2K_0402_5% L44
R69 1 PEG_RX#_2
2 LVDS_IBG C44 LVDS_IBG PEG_RX#_3 L40
D 2.37K_0402_1% Spacing=20mil B43 N41 D
LVDS_VBG PEG_RX#_4
E37 LVDS_VREFH PEG_RX#_5 P48
L_DDC_DATA E38 LVDS_VREFL PEG_RX#_6 N44
PEG_RX#_7 T43
0 = LFP Disable *(Default) 18 UMA_LCD_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
1 = LFP Card Present; PCIE disable 18 UMA_LCD_TXCLK+ C40 LVDSA_CLK PEG_RX#_9 Y43
B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 LVDSB_CLK PEG_RX#_11 Y36

LVDS
PEG_RX#_12 AA43
18 UMA_LCD_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
18 UMA_LCD_TXOUT1- E46 LVDSA_DATA#_1 PEG_RX#_14 AC47
18 UMA_LCD_TXOUT2- G40 LVDSA_DATA#_2 PEG_RX#_15 AD39
A40 LVDSA_DATA#_3
PEG_RX_0 H43
18 UMA_LCD_TXOUT0+ H48 LVDSA_DATA_0 PEG_RX_1 J44
18 UMA_LCD_TXOUT1+ D45 LVDSA_DATA_1 PEG_RX_2 L43

GRAPHICS
F40 L41 PCIE_GTX_C_MRX_P3 1 2
18 UMA_LCD_TXOUT2+ LVDSA_DATA_2 PEG_RX_3 PCIE_GTX_C_MRX_HDMI_P3 19
B40 N40 R505 IHDMI@ 0_0402_5%
LVDSA_DATA_3 PEG_RX_4
PEG_RX_5 P47
A41 LVDSB_DATA#_0 PEG_RX_6 N43
H38 LVDSB_DATA#_1 PEG_RX_7 T42
G37 LVDSB_DATA#_2 PEG_RX_8 U42
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
B42 LVDSB_DATA_0 PEG_RX_11 Y37
G38 LVDSB_DATA_1 PEG_RX_12 AA42
F37 LVDSB_DATA_2 PEG_RX_13 AD36
K37 LVDSB_DATA_3 PEG_RX_14 AC48

PCI-EXPRESS
PEG_RX_15 AD40
C C
J41 PCIE_MTX_GRX_N0 C60 1 2 IHDMI@ 0.1U_0402_16V7K
PEG_TX#_0 PCIE_MTX_C_GRX_HDMI_N0 19
1 2 TV_COMPS PEG_TX#_1 M46 PCIE_MTX_GRX_N1 C61 1 2 IHDMI@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_HDMI_N1 19
R70 75_0402_1% TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C62 1 2 IHDMI@ 0.1U_0402_16V7K
TVA_DAC PEG_TX#_2 PCIE_MTX_C_GRX_HDMI_N2 19
1 2 TV_LUMA TV_LUMA H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C63 1 2 IHDMI@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_HDMI_N3 19
R71 75_0402_1% TV_CRMA K25 M42
TVC_DAC PEG_TX#_4
1 2 TV_CRMA PEG_TX#_5 R48

TV
R72 75_0402_1% H24 N38
TV_RTN PEG_TX#_6
PEG_TX#_7 T40
PEG_TX#_8 U37
PEG_TX#_9 U40
C31 TV_DCONSEL_0 PEG_TX#_10 Y40
E32 TV_DCONSEL_1 PEG_TX#_11 AA46
PEG_TX#_12 AA37
PEG_TX#_13 AA40
1 2 UMA_CRT_B AD43
R73 150_0402_1% PEG_TX#_14
PEG_TX#_15 AC46
1 2 UMA_CRT_G
R74 150_0402_1% UMA_CRT_B E28 J42 PCIE_MTX_GRX_P0 C64 1 2 IHDMI@ 0.1U_0402_16V7K
18 UMA_CRT_B CRT_BLUE PEG_TX_0 PCIE_MTX_C_GRX_HDMI_P0 19
1 2 UMA_CRT_R L46 PCIE_MTX_GRX_P1 C65 1 2 IHDMI@ 0.1U_0402_16V7K
PEG_TX_1 PCIE_MTX_C_GRX_HDMI_P1 19
R75 150_0402_1% UMA_CRT_G G28 M48 PCIE_MTX_GRX_P2 C66 1 2 IHDMI@ 0.1U_0402_16V7K
18 UMA_CRT_G CRT_GREEN PEG_TX_2 PCIE_MTX_C_GRX_HDMI_P2 19
M39 PCIE_MTX_GRX_P3 C67 1 2 IHDMI@ 0.1U_0402_16V7K
PEG_TX_3 PCIE_MTX_C_GRX_HDMI_P3 19

VGA
UMA_CRT_R J28 M43
18 UMA_CRT_R CRT_RED PEG_TX_4
PEG_TX_5 R47
+3VS G29 N37
CRT_IRTN PEG_TX_6
PEG_TX_7 T39
1 2 UMA_CRT_CLK UMA_CRT_CLK H32 U36
18 UMA_CRT_CLK CRT_DDC_CLK PEG_TX_8
R76 4.7K_0402_5% UMA_CRT_DATA J32 U39
18 UMA_CRT_DATA CRT_DDC_DATA PEG_TX_9
1 2 UMA_CRT_DATA UMA_CRT_HSYNC J29 Y39
B 18 UMA_CRT_HSYNC CRT_HSYNC PEG_TX_10 B
R77 4.7K_0402_5% 2 1UMA_CRT_IREF E29 Y46
R78 1.02K_0402_1% CRT_TVO_IREF PEG_TX_11
PEG_TX_12 AA36
PEG_TX_13 AA39
UMA_CRT_VSYNC L29 AD42
18 UMA_CRT_VSYNC CRT_VSYNC PEG_TX_14
PEG_TX_15 AD46

CANTIGA ES_FCBGA1329
GM45R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(4/7)-GTL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 11 of 41
5 4 3 2 1
5 4 3 2 1

U3F
DDR2,667MHz,2600mA +1.05VS Extnal Graphic: 1210.34mA
DDR2,800MHz,3000mA Int. Graphic integrated Graphic: 1930.4mA
W28 Intel Management Engine Link:508.12mA
+1.8V VCC_AXG_NTCF_1
AP33 VCC_SM_1 VCC_AXG_NCTF_2 V28
DDR PWR AN33
VCC_SM_2 VCC_AXG_NCTF_3
W26
10U_0805_10V4Z BH32 V26
VCC_SM_3 VCC_AXG_NCTF_4
BG32 W25
VCC_SM_4 VCC_AXG_NCTF_5
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
1 1 BD32 W24
VCC_SM_6 VCC_AXG_NCTF_7
1 1 1 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
D + + BB32 W23 +1.05VS NB Core,Intel Management Engine Link U3G D
VCC_SM_8 VCC_AXG_NCTF_9

VCC
C78 C68 C69 C70 C71 BA32 V23
220U_D2_4VM_R15 VCC_SM_9 VCC_AXG_NCTF_10 220U_6.3V_M 0.22U_0402_10V4Z 0.1U_0402_16V4Z
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AG34 VCC_1
220U_6.3V_M 2 @ 2 2 2 2 AW32 AL21 1 1 AC34
VCC_SM_11 VCC_AXG_NCTF_12 VCC_2
AV32 AK21 1 1 1 1 AB34
VCC_SM_12 VCC_AXG_NCTF_13 + + VCC_3
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AA34 VCC_4
10U_0805_10V4Z 0.1U_0402_16V4Z AT32 V21 C72 C73 C74 C75 C76 C77 Y34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_5
AR32 U21 V34

VCC CORE
VCC_SM_15 VCC_AXG_NCTF_16 2 2 2 2 2 2 VCC_6
AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20 U34 VCC_7
AN32 AK20 220U_6.3V_M 10U_0805_10V4Z 0.22U_0402_10V4Z AM33
VCC_SM_17 VCC_AXG_NCTF_18 VCC_8
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 Intel: VCC -- 220U*2, ESR 12mOhm AK33 VCC_9
BG31 U20 AJ33
VCC_SM_19 VCC_AXG_NCTF_20 VCC_10
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AG33 VCC_11
BG30 AL19 AF33
VCC_SM_21 VCC_AXG_NCTF_22 VCC_12
BH29 AK19
VCC_SM_22 VCC_AXG_NCTF_23
BG29 AJ19
VCC_SM_23 VCC_AXG_NCTF_24
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
BD29 AG19 AE33
VCC_SM_25 VCC_AXG_NCTF_26 VCC_13
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 AC33 VCC_14
BB29 AE19 AA33
VCC_SM_27 VCC_AXG_NCTF_28 VCC_15
BA29 AB19 Y33
VCC_SM_28 VCC_AXG_NCTF_29 VCC_16
AY29 AA19 W33
VCC_SM_29 VCC_AXG_NCTF_30 VCC_17
AW29 Y19 V33

GFX NCTF

POWER
VCC_SM_30 VCC_AXG_NCTF_31 VCC_18
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 U33 VCC_19
AU29 V19 AH28
VCC_SM_32 VCC_AXG_NCTF_33 VCC_20
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AF28 VCC_21
AR29 AM17 AC28
VCC_SM_34 VCC_AXG_NCTF_35 VCC_22
AP29 AK17 AA28
VCC_SM_35 VCC_AXG_NCTF_36 VCC_23
VCC_AXG_NCTF_37 AH17 AJ26 VCC_24
VCC_AXG_NCTF_38 AG17 AG26 VCC_25
AF17 AE26
VCC_AXG_NCTF_39 VCC_26
BA36 AE17 AC26
C VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_27 +1.05VS C
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AH25 VCC_28

VCC
Could be NC for DDR2 Board. BD16
VCC_SM_38/NC VCC_AXG_NCTF_42
AB17 AG25
VCC_29
BB21 Y17 AF25
VCC_SM_39/NC VCC_AXG_NCTF_43 VCC_30
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AG24 VCC_31 VCC_NCTF_1 AM32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AJ23 VCC_32 VCC_NCTF_2 AL32
AT13 AM16 AH23 AK32
VCC_SM_42/NC VCC_AXG_NCTF_46 VCC_33 VCC_NCTF_3
VCC_AXG_NCTF_47 AL16 AF23 VCC_34 VCC_NCTF_4 AJ32
AK16 T32 AH32
VCC_AXG_NCTF_48 VCC_35 VCC_NCTF_5

POWER
VCC_AXG_NCTF_49 AJ16 VCC_NCTF_6 AG32
AH16 AE32
VCC_AXG_NCTF_50 VCC_NCTF_7
8700mA VCC_AXG_NCTF_51 AG16 VCC_NCTF_8 AC32
AF16 AA32
VCC_AXG_NCTF_52 VCC_NCTF_9
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_10 Y32
AE25 AC16 W32
VCC_AXG_2 VCC_AXG_NCTF_54 VCC_NCTF_11
For layout placement un-mound C123 and mound C84 AB25
VCC_AXG_3 VCC_AXG_NCTF_55
AB16
VCC_NCTF_12
U32
AA25 AA16 AM30
VCC_AXG_4 VCC_AXG_NCTF_56 VCC_NCTF_13
Int. Graphic AE24
VCC_AXG_5 VCC_AXG_NCTF_57
Y16
VCC_NCTF_14
AL30
AC24 W16 AK30
+1.05VS VCC_AXG_6 VCC_AXG_NCTF_58 VCC_NCTF_15
AA24 V16 AH30
VCC_AXG_7 VCC_AXG_NCTF_59 VCC_NCTF_16
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_17 AG30
220U_D2_4VM_R15 10U_0805_10V4Z 0.47U_0603_10V7K 0.1U_0402_16V4Z AE23 AF30
VCC_AXG_9 VCC_NCTF_18
1 1 AC23 AE30
VCC_AXG_10 VCC_NCTF_19
1 1 1 1 1 1 AB23 AC30

NCTF
+ + VCC_AXG_11 VCC_NCTF_20
AA23 AB30
C83 C84 C85 C86 C87 C88 C89 C90 VCC_AXG_12 VCC_NCTF_21
AJ21 AA30
@ VCC_AXG_13 VCC_NCTF_22
AG21 Y30
2 2 2 2 2 2 2 2 VCC_AXG_14 VCC_NCTF_23
AE21 VCC_AXG_15 VCC_NCTF_24 W30
220U_D2_4VM_R15 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AC21 V30
VCC_AXG_16 VCC_NCTF_25
AA21 U30
VCC_AXG_17 VCC_NCTF_26

VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm Y21
VCC_AXG_18 VCC_NCTF_27
AL29
VCC

AH20 AK29
For layout issue to separate 220u*2 to +1.05VS VCC_AXG_19 VCC_NCTF_28
AF20 AJ29
B VCC_AXG_20 VCC_NCTF_29 B
AE20 VCC_AXG_21 VCC_NCTF_30 AH29
AC20 VCC_AXG_22 VCC_NCTF_31 AG29
AB20 AE29
VCC_AXG_23 VCC_NCTF_32
AA20 AC29
GFX

VCC_AXG_24 VCC_NCTF_33
T17 AA29
VCC_AXG_25 VCC_NCTF_34
T16 Y29
VCC_AXG_26 VCC_NCTF_35
AM15 W29
VCC_AXG_27 VCC_NCTF_36
AL15 V29
VCC_AXG_28 VCC_NCTF_37
AE15 AL28
VCC_AXG_29 VCC_NCTF_38
AJ15 VCC_AXG_30 VCC_NCTF_39 AK28
AH15 VCC_AXG_31 VCC_NCTF_40 AL26
AG15 AK26
VCC_AXG_32 VCC_NCTF_41
AF15 VCC_AXG_33 VCC_NCTF_42 AK25
AB15 AK24
VCC_AXG_34 VCC_NCTF_43
AA15 VCC_AXG_35 VCC_NCTF_44 AK23
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF

VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
AM40 VCCSM_LF3
VCC_SM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
AY5 VCCSM_LF5 CANTIGA ES_FCBGA1329
VCC_SM_LF5
PAD T3 AJ14 AM10 VCCSM_LF6 GM45R3@
VCC_AXG_SENSE VCC_SM_LF6
PAD T4 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
1 1 C93 1 1 C95 1 1 C96 1
0.22U_0603_10V7K 0.47U_0603_10V7K 1U_0402_6.3V4Z

C91 C92 C94 C97


0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.22U_0603_10V7K 2 2 1U_0402_6.3V4Z 2
A A
CANTIGA ES_FCBGA1329
GM45R3@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(5/7)-GTL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 12 of 41
5 4 3 2 1
5 4 3 2 1

+3VS_TVCRT_DACBG +3VS_TVCRT_DAC +3VS_TVCRT_DACBG


CRT TV +3VS_TVCRT_DACBG
+3VS
2 R80 1 0.01U_0402_25V4Z 0.01U_0402_25V4Z R79
0_0603_5% 1 1 1 1 2 1
Pin A25 BLM18PG181SN1D_0603 1 U3H
C99 C100 C101 C102 FSB=1067Mhz,852mA +1.05VS

2 2
Pin B27 2 2
GNDtoB25 C98 AGTL+
10U_0805_10V4Z
2
73mA VTT_1
U13
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_TVCRT_DAC B27 T13 1
VCCA_CRT_DAC_1 VTT_2
A26 U12 1 1 1 1
VCCA_CRT_DAC_2 VTT_3 + C103
VTT_4 T12
+1.05VS +1.05VS_DPLLA +1.05VS +1.05VS_DPLLB U11 C104 C105 C106 C107 220U_D2_4VM_R15
VTT_5
R81 R82 5mA VTT_6 T11 0.47U_0603_10V7K
2 2
2.2U_0603_6.3V6K 4.7U_0805_10V4Z
2 2
4.7U_0805_10V4Z
2

CRT
D 10U_0805_10V4Z 10U_0805_10V4Z D
2 1 2 1 +3VS_TVCRT_DACBG A25 VCCA_DAC_BG VTT_7 U10
10U_FLC-453232-100K_0.25A_10%
1 10U_FLC-453232-100K_0.25A_10%
1 T10 Intel: VTT 270U*1 ESR 12mOhm
VTT_8
1 1 1 1 B25 VSSA_DAC_BG VTT_9 U9
C108 + C109 + T9
220U_B2_2.5VM C110 C111 220U_B2_2.5VM C112 C113 VTT_10
U8
@ VTT_11
2 2 2
Pin F47 @
2 2 2
Pin L48 VTT_12 T8

VTT
VCCA_DPLLA64.8mA
+1.05VS_DPLLA F47 U7
0.1U_0402_16V4Z 0.1U_0402_16V4Z VTT_13
VTT_14 T7
+1.05VS_DPLLB L48 VCCA_DPLLB64.8mA VTT_15 U6
T6
VTT_16

PLL
+1.05VS +1.05VS_AHPLL +1.05VS +1.05VS_MPLL +1.05VS_AHPLL AD1 VCCA_HPLL 24mA VTT_17 U5
T5
+1.8V_TXLVDS VTT_18
VCCA_MPLL 139.2mA
R83 R84 +1.05VS_MPLL AE1 V3
VTT_19
2 1 2 1 LVDS VTT_20
U3
KC FBM-L11-160808-121LMT
1 0603 1 MBK2012121YZF_0805 1 1 13.2mA VTT_21
V2

A PEG A LVDS
1 2 C117 +1.8V_TXLVDS J48 U2
C115 C116 C114 R85 0.5_0805_1% C118 VCCA_LVDS VTT_22
VTT_23 T2
4.7U_0805_10V4Z 10U_0805_10V4Z Pin AE12 1000P_0402_50V7K J47 V1
2 0.1U_0402_16V4Z
2 2 VSSA_LVDS VTT_24
Pin J48 VTT_25 U1
+1.05VS
Pin AD1 0.1U_0402_16V4Z GND to J47 414uA +1.05VS_AXF
+1.5VS_PEG_BG AD48
VCCA_PEG_BG NB I/O R86
1 2
2 1 0_0603_5%
+1.5VS_PEG_BG +1.05VS_PEGPLL
50mA C119
PCIe&DMI +1.05VS_PEGPLL AA48
VCCA_PEG_PLL
C120
1U_0402_6.3V4Z 10U_0805_10V4Z
1 2 1 2 @
+1.5VS 1
R87 0_0603_5% 1 667MTs,480mA
C121 Pin B22
C122 0.1U_0402_16V4Z
800MTs,720mA
0.1U_0402_16V4Z 2
PCIe&DMI AR20
VCCA_SM_1
POWER
2
C
Pin AD48 Pin AA48 DDR2 +1.05VS_A_SM
AP20
VCCA_SM_2 +1.8V_SM_CK C
+1.05VS AN20 DDR2 +1.8V
R88 VCCA_SM_3
AR17
VCCA_SM_4 Host Interface I/O and HSIO R89

A SM
1 2 4.7U_0805_10V4Z AP17
VCCA_SM_5 321.35mA 1 2
1 0_0805_5% 1 1 1 AN17 VCCA_SM_6 VCC_AXF_1 B22 +1.05VS_AXF 1 1 0_0805_5%

AXF
AT16 VCCA_SM_7 VCC_AXF_2 B21
C123 + C124 C125 C126 AR16 A21 C127 R90 C128
220U_D2_4VM_R15 VCCA_SM_8 VCC_AXF_3 0.1U_0402_16V4Z 1_0805_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
2 2 2 2 2 @
@
2
DDR2,667MHz,119.85mA C129
10U_0805_10V4Z 1U_0402_6.3V4Z Pin BF21
DDR2,800MHz,124mA
Pin AR20 1 2
VCC_SM_CK_1 BF21 +1.8V_SM_CK

SM CK
667MTs,24mA VCC_SM_CK_2
BH20 10U_0805_10V4Z
800MTs,26mA VCC_SM_CK_3 BG20
DDR2 BF20 +1.8V_TXLVDS +1.8V
+1.05VS +1.05VS_A_SM_CK VCC_SM_CK_4
AP28
VCCA_SM_CK_1 LVDS R91
R92 AN28 1 2
0.1U_0402_16V4Z VCCA_SM_CK_2
1 2 AP25
VCCA_SM_CK_3 1 1 0_0603_5%
0_0603_5% 1 1 1 AN25
VCCA_SM_CK_4 118.8mA
AN24 K47 +1.8V_TXLVDS C130 C131
VCCA_SM_CK_5 VCC_TX_LVDS

A CK
C132 C133 C134 AM28 1000P_0402_50V7K 10U_0805_10V4Z
VCCA_SM_CK_NCTF_1 2 2
@

10U_0805_10V4Z AM26
2 2 2 VCCA_SM_CK_NCTF_2
2.2U_0603_6.3V4Z AM25
VCCA_SM_CK_NCTF_3 105.3mA Pin K47
AL25 C35 +3VS
+3VS_TVCRT_DAC +1.5VS +1.5VS_HDA VCCA_SM_CK_NCTF_4 VCC_HV_1
TV Pin AP28 AM24
VCCA_SM_CK_NCTF_5 VCC_HV_2
B35

HV
R94 HDMI's HDA AL24 A35
0.01U_0402_25V4Z VCCA_SM_CK_NCTF_6 VCC_HV_3 D3
1 2 AM23
0_0402_5% 1 VCCA_SM_CK_NCTF_7
1 1 AL23 VCCA_SM_CK_NCTF_8 +3VS 2 R93 1 1 2 +1.05VS
IHDMI@ 1782mA 1 10_0603_5%
C135 C136 C138 V48 +1.05VS C137 CH751H-40PT_SOD323-2
0.1U_0402_16V4Z VCC_PEG_1
2 2
Pin B24 0.1U_0402_16V4Z Pin A32 VCC_PEG_2
U48 0.1U_0402_16V4Z
IHDMI@ 2

PEG
VCC_PEG_3
V47
2
Pin C35
B
79mA VCC_PEG_4
U47
B
B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
+3VS_TVCRT_DAC A24 VCCA_TV_DAC_2

TV
+1.5VS +1.5VS_TVDAC +1.5VS +1.5VS_QDAC
50mA 456mA
R95 TV R96 TV +1.5VS_HDA A32 AH48 +1.05VS
VCC_HDA VCC_DMI_1 +1.05VS

HDA
2 1 0.1U_0402_16V4Z 2 1 0.01U_0402_25V4Z AF48 PCIe&DMI
VCC_DMI_2

DMI
0_0603_5% 1 1 1 0_0603_5% 1 1 AH47
VCC_DMI_3 10U_0805_10V4Z
AG47
VCC_DMI_4
C139 C140 C141 C142 C143 35mA 1 1
@ 10U_0805_10V4Z Pin M25 0.1U_0402_16V4Z Pin L282 +1.5VS_TVDAC M25
2 2 2 2 VCCD_TVDAC

D TV/CRT
C144 C145
VCCD_QDAC500uA
0.01U_0402_25V4Z +1.5VS_QDAC L28
2
10U_0805_10V4Z 2
157.2mA Pin V48
+1.05VS_DHPLL AF1
VCCD_HPLL VTTLF1
+1.05VS +1.05VS_DHPLL
50mA VTTLF1
A8
AA47 L1 VTTLF2
+1.05VS_PEGPLL VCCD_PEG_PLL VTTLF2
VTTLF
R98 AB2 VTTLF3 PCIe&DMI
VTTLF3 +1.05VS
1 2 60.31mA 1 1 1
0_0402_5% 2 M38
VCCD_LVDS_1
LVDS

+1.8V_LVDS L37 C147 C148 C149 1


C150 VCCD_LVDS_2 0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K C151
Pin AF1 2 2 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CANTIGA ES_FCBGA1329 2
Pin AH48
GM45R3@

+1.05VS PCIe&DMI +1.05VS_PEGPLL


A L1 +1.8V_LVDS A
2 1 0.1U_0402_16V4Z R99 LVDS
BLM18PG121SN1D_0603 1 +1.8V 2 1
0_0603_5% 1
R100 C152
1_0805_1% C153
2 1U_0402_6.3V4Z
2 1 C154 2
10U_0805_10V4Z Pin AA47 Pin M38
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (6/7)-VCC

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 13 of 41
5 4 3 2 1
5 4 3 2 1

U3I U3J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8


AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 B36 AH21 AU7
VSS_7 VSS_106 VSS_205 VSS_303
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 AA35 AB21 AJ7
VSS_9 VSS_108 VSS_207 VSS_305
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 U35 M21 AA7
VSS_11 VSS_110 VSS_209 VSS_307
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 AF34 AW20 AV6
VSS_16 VSS_115 VSS_214 VSS_312
BA46 AE34 AT20 AT6
VSS_17 VSS_116 VSS_215 VSS_313
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 B34 AG20 M6
VSS_19 VSS_118 VSS_217 VSS_315
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 BC33 K20 AH5
VSS_22 VSS_121 VSS_220 VSS_318
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 AV33 C20 Y5
VSS_24 VSS_123 VSS_222 VSS_320
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 AL33 BG19 J5
VSS_26 VSS_125 VSS_224 VSS_322
BF44 AH33 A18 H5
VSS_27 VSS_126 VSS_225 VSS_323
AH44 AB33 BG17 F5
VSS_28 VSS_127 VSS_226 VSS_324
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 L33 AW17
VSS_30 VSS_129 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 N32 R17 AV3
VSS_32 VSS_131 VSS_230 VSS_328
T44 K32 M17 AL3
VSS_33 VSS_132 VSS_231 VSS_329
M44 F32 H17 R3
VSS_34 VSS_133 VSS_232 VSS_330
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 AN29 BA16 BA2
VSS_37 VSS_136 VSS_235 VSS_333
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 N29 AU16 AU2
VSS_39 VSS_138 VSS_237 VSS_335
J43 K29 AN16 AR2
VSS_40 VSS_139 VSS_238 VSS_336
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 BG28 E16 AF2
C VSS_44 VSS_143 VSS_242 VSS_340 C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 BA28 AC15 AD2
VSS_46 VSS_145 VSS_244 VSS_342
AE42 AV28 W15 AC2
VSS_47 VSS_146 VSS_245 VSS_343
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
VSS_50 VSS_149 VSS_248 VSS_346
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
VSS_52 VSS_151 VSS_250 VSS_348
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 Y28 BA13 H1
VSS_54 VSS_153 VSS_252 VSS_350
AA41 VSS_55 VSS_154 P28
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 F28 AJ13 U25
VSS_58 VSS_157 VSS_256 VSS_353
M41 C28 AE13 U29
VSS_59 VSS_158 VSS_257 VSS_354
G41 BF26 N13
VSS_60 VSS_159 VSS_258
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
VSS_62 VSS_161 VSS_260 VSS_NCTF_2
BB40 AB26 E13 V32
VSS_63 VSS_162 VSS_261 VSS_NCTF_3
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 C26 AV12 AM29
VSS_65 VSS_164 VSS_263 VSS_NCTF_5
H40 B26 AT12 AF29
VSS_66 VSS_165 VSS_264 VSS_NCTF_6
E40 BH25 AM12 AB29
VSS_67 VSS_166 VSS_265 VSS_NCTF_7
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 BB25 J12 U23
VSS_69 VSS_168 VSS_267 VSS_NCTF_9
AJ39 AV25 A12 AL20
VSS_70 VSS_169 VSS_268 VSS_NCTF_10
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 AJ25 BB11 AC19
VSS_72 VSS_171 VSS_270 VSS_NCTF_12
L39 AC25 AY11 AL17
VSS_73 VSS_172 VSS_271 VSS_NCTF_13
B39 Y25 AN11 AJ17
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 N25 AH11 AA17
VSS_75 VSS_174 VSS_273 VSS_NCTF_15
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 AD12 BG10 A48
VSS_81 VSS_180 VSS_279 VSS_SCB_3
Y38 AY24 AV10 C1

VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4
U38 AT24 AT10 A3
VSS_83 VSS_182 VSS_281 VSS_SCB_5
T38 AJ24 AJ10
VSS_84 VSS_183 VSS_282
J38 AH24 AE10
VSS_85 VSS_184 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46

NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 A23 B47
VSS_99 VSS_198 NC_37
VSS_199 AJ6 NC_38 A46
F48
CANTIGA ES_FCBGA1329 NC_39
E48
GM45R3@ NC_40
NC_41 C48
B48
NC_42

CANTIGA ES_FCBGA1329
GM45R3@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 14 of 41
5 4 3 2 1
5 4 3 2 1

JDDRL @
+DIMM_VREF 1 VREF VSS 2 DDR_A_DQS#[0..7] 10
1 1 3 4 DDR_A_D5
DDR_A_D4 VSS DQ4 DDR_A_D0
5 DQ0 DQ5 6 DDR_A_D[0..63] 10
C155 C156 DDR_A_D1 7 8
2.2U_0603_6.3V6K 0.1U_0402_16V4Z DQ1 VSS DDR_A_DM0
9 VSS DM0 10 DDR_A_DM[0..7] 10
2 2 DDR_A_DQS#0 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_DQS[0..7] 10
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18 DDR_A_MA[0..14] 10
DDR_A_D3 19 20 DDR_A_D13
+1.8V DQ3 DQ12 DDR_A_D12
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D14 DQ8 VSS DDR_A_DM1
D 25 DQ9 DM1 26 Layout Note: D
1

27 28 +1.8V
R101 DDR_A_DQS#1 VSS VSS Place near JP3
29 DQS1# CK0 30 DDRA_CLK0 9
DDR_A_DQS1 31 32
DQS1 CK0# DDRA_CLK0# 9
1K_0402_1% 20mils 33 34
VSS VSS

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D9 35 36 DDR_A_D11 1
2

DDR_A_D15 DQ10 DQ14 DDR_A_D10


+DIMM_VREF 37 DQ11 DQ15 38 1 1 1 1 1 1 1 1 1

C158

C159

C160

C161

C162

C163

C164

C165

C166
39 40 + C157
VSS VSS
1

220U_Y_4VM
R102 @
2 2 2 2 2 2 2 2 2 2
41 VSS VSS 42
1K_0402_1% DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21 4.4
45 46
2

DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS# 9,16
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28 Layout Note: Place one cap close to every 2 pullup
DDR_A_D24 DQ24 DQ28 DDR_A_D25 +0.9VS
63 DQ25 DQ29 64
65 66 resistors terminated to +0.9VS
DDR_A_DM3 VSS VSS DDR_A_DQS#3
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76 1 1 1 1 1 1 1 1 1 1 1 1 1
77 VSS VSS 78
C DDRA_CKE0 79 80 DDRA_CKE1 C
9 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 9
+1.8V 81 VDD VDD 82 +1.8V 2 2 2 2 2 2 2 2 2 2 2 2 2
83 NC NC/A15 84

C167

C168

C169

C170

C171

C172

C173

C174

C175

C176

C177

C178

C179
DDR_A_BS2 85 86 DDR_A_MA14
10 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 Layout Note:
A10/AP BA1 DDR_A_BS1 10
DDR_A_BS0 107 108 DDR_A_RAS#
10 DDR_A_BS0
DDR_A_W E# BA0 RAS# DDRA_SCS0#
DDR_A_RAS# 10 Place these resistor
10 DDR_A_W E# 109 WE# S0# 110 DDRA_SCS0# 9
111 112 closely JP3,all
DDR_A_CAS# VDD VDD DDRA_ODT0
10 DDR_A_CAS# 113 CAS# ODT0 114 DDRA_ODT0 9 trace length Max=1.5"
DDRA_SCS1# 115 116 DDR_A_MA13
9 DDRA_SCS1# NC/S1# NC/A13 +0.9VS
117 VDD VDD 118
9 DDRA_ODT1 DDRA_ODT1 119 120
NC/ODT1 NC RP1 RP2
121 VSS VSS 122
DDR_A_D37 123 124 DDR_A_D39 DDR_A_MA8 8 1 8 1 DDR_A_MA13
DDR_A_D36 DQ32 DQ36 DDR_A_D38 DDR_A_BS2 DDRA_ODT0
125 DQ33 DQ37 126 7 2 7 2
127 128 DDR_A_MA12 6 3 6 3 DDR_A_RAS#
DDR_A_DQS#4 VSS VSS DDR_A_DM4 DDR_A_MA1 DDRA_SCS0#
129 DQS4# DM4 130 5 4 5 4
DDR_A_DQS4 131 132
DQS4 VSS DDR_A_D34 56_0804_8P4R_5% 56_0804_8P4R_5%
133 VSS DQ38 134
DDR_A_D35 135 136 DDR_A_D33
B DDR_A_D32 DQ34 DQ39 RP3 RP4 B
137 DQ35 VSS 138
139 140 DDR_A_D45 DDR_A_MA14 8 1 8 1 DDR_A_MA5
DDR_A_D40 VSS DQ44 DDR_A_D43 DDR_A_MA11 DDR_A_MA3
141 DQ40 DQ45 142 7 2 7 2
DDR_A_D44 143 144 DDR_A_MA6 6 3 6 3 DDR_A_MA9
DQ41 VSS DDR_A_DQS#5 DDR_A_MA7 DDR_A_MA10
145 VSS DQS5# 146 5 4 5 4
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42 RP5 RP12
153 DQ43 DQ47 154
155 156 DDRA_ODT1 8 1 1 8 DDR_A_MA4
DDR_A_D49 VSS VSS DDR_A_D52 DDR_A_CAS# DDR_A_MA2
157 DQ48 DQ52 158 7 2 2 7
DDR_A_D48 159 160 DDR_A_D53 DDR_A_W E# 6 3 3 6 DDR_A_BS1
DQ49 DQ53 DDR_A_BS0 DDR_A_MA0
161 VSS VSS 162 5 4 4 5
163 NC,TEST CK1 164 DDRA_CLK1 9
165 166 56_0804_8P4R_5% 56_0804_8P4R_5%
VSS CK1# DDRA_CLK1# 9
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 172 DDRA_SCS1#R480 1 2 56_0402_5%
DDR_A_D54 VSS VSS DDR_A_D51 DDRA_CKE0 R481 1 56_0402_5%
173 DQ50 DQ54 174 2
DDR_A_D50 175 176 DDR_A_D55 DDRA_CKE1 R482 1 2 56_0402_5%
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D59 189 190
SUPPORT_PAD
SUPPORT_PAD

DDR_A_D58 DQ58 VSS DDR_A_D62


191 DQ59 DQ62 192
A 193 194 DDR_A_D63 A
VSS DQ63
16,17,22,25 PM_SMBDATA 195 SDA VSS 196
16,17,22,25 PM_SMBCLK 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200

1
C180 FOX_AS0A426-M2RN-7F
SO-DIMM A Compal Electronics, Inc.
0.1U_0402_16V4Z

Security Classification Compal Secret Data


203
204

2009/07/28 2010/07/28 Title


REVERSE 2 Issued Date Deciphered Date
DDRII-SODIMM0
Top side THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 15 of 41
5 4 3 2 1
A B C D E

JDDRH @
DDR_B_DQS#[0..7] 10
+DIMM_VREF 1 VREF VSS 2
1 1 3 4 DDR_B_D5 DDR_B_D[0..63] 10
DDR_B_D0 VSS DQ4 DDR_B_D4
5 DQ0 DQ5 6
C181 C182 DDR_B_D1 7 8
DQ1 VSS DDR_B_DM[0..7] 10
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 9 10 DDR_B_DM0
@ 2 2 DDR_B_DQS#0 VSS DM0
11 DQS0# VSS 12 DDR_B_DQS[0..7] 10
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16 DDR_B_MA[0..14] 10
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
21 22 DDR_B_D13 Layout Note:
DDR_B_D8 VSS DQ13 +1.8V
23 DQ8 VSS 24
1 DDR_B_D9 25 26 DDR_B_DM1 Place near JP4 1
DQ9 DM1
27 VSS VSS 28
DDR_B_DQS#1 29 30
DQS1# CK0 DDRB_CLK0 9

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_DQS1 31 32
DQS1 CK0# DDRB_CLK0# 9
33 VSS VSS 34 1 1 1 1 1 1 1 1 1

C183

C184

C185

C186

C187

C188

C189

C190

C191
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
39 VSS VSS 40
2 2 2 2 2 2 2 2 2

41 VSS VSS 42
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS# 9,15
DDR_B_DQS2 51 52 DDR_B_DM2
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
+0.9VS Layout Note: Place one cap close to every 2 pullup
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26 Resistors terminated to +0.9VS
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
77 VSS VSS 78
2 DDRB_CKE0 DDRB_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
9 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 9

C192

C193

C194

C195

C196

C197

C198

C199

C200

C201

C202

C203

C204
+1.8V 81 VDD VDD 82 +1.8V
83 NC NC/A15 84
DDR_B_BS2 85 86 DDR_B_MA14
10 DDR_B_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100 Layout Note:
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0 Place these resistor
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 closely JP4,all
A10/AP BA1 DDR_B_BS1 10
DDR_B_BS0 107 108 DDR_B_RAS# trace length Max=1.5"
10 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 10
DDR_B_W E# 109 110 DDRB_SCS0#
10 DDR_B_W E# WE# S0# DDRB_SCS0# 9
111 VDD VDD 112
DDR_B_CAS# 113 114 DDRB_ODT0
10 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 9 +0.9VS
DDRB_SCS1# 115 116 DDR_B_MA13
9 DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 RP8 RP9
9 DDRB_ODT1 NC/ODT1 NC
121 122 DDR_B_CAS# 8 1 8 1 DDR_B_MA7
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_W E# DDR_B_MA6
123 DQ32 DQ36 124 7 2 7 2
DDR_B_D33 125 126 DDR_B_D37 DDR_B_MA10 6 3 6 3 DDR_B_MA14
DQ33 DQ37 DDR_B_BS0 DDR_B_MA11
127 VSS VSS 128 5 4 5 4
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4 56_0804_8P4R_5% 56_0804_8P4R_5%
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38 RP10 RP11
135 DQ34 DQ39 136
3 DDR_B_D35 DDR_B_RAS# DDR_B_MA8 3
137 DQ35 VSS 138 8 1 8 1
139 140 DDR_B_D44 DDRB_SCS0# 7 2 7 2 DDR_B_MA5
DDR_B_D40 VSS DQ44 DDR_B_D45 DDRB_ODT0 DDR_B_MA1
141 DQ40 DQ45 142 6 3 6 3
DDR_B_D41 143 144 DDR_B_MA13 5 4 5 4 DDR_B_MA3
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46 RP6 RP13
DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_MA12 DDR_B_BS1
153 DQ43 DQ47 154 8 1 8 1
155 156 DDR_B_BS2 7 2 7 2 DDR_B_MA0
DDR_B_D48 VSS VSS DDR_B_D52 DDRB_CKE0 DDR_B_MA4
157 DQ48 DQ52 158 6 3 6 3
DDR_B_D49 159 160 DDR_B_D53 DDR_B_MA9 5 4 5 4 DDR_B_MA2
DQ49 DQ53
161 VSS VSS 162
163 164 56_0804_8P4R_5% 56_0804_8P4R_5%
NC,TEST CK1 DDRB_CLK1 9
165 VSS CK1# 166 DDRB_CLK1# 9
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6 DDRB_ODT1 R4831 56_0402_5%
169 DQS6 DM6 170 2
171 172 DDRB_SCS1# R4841 2 56_0402_5%
DDR_B_D51 VSS VSS DDR_B_D54 DDRB_CKE1 R4851 56_0402_5%
173 DQ50 DQ54 174 2
DDR_B_D50 175 176 DDR_B_D55
DQ51 DQ55
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D59 189 190
SUPPORT_PAD
SUPPORT_PAD

DDR_B_D58 DQ58 VSS DDR_B_D62


191 DQ59 DQ62 192
4 193 194 DDR_B_D63 4
VSS DQ63
15,17,22,25 PM_SMBDATA 195 SDA VSS 196
15,17,22,25 PM_SMBCLK 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200 +3VS

1
FOX_AS0A426-MARG-7F
Security Classification Compal Secret Data Compal Electronics, Inc.
201
202

C205
SO-DIMM B 2
0.1U_0402_16V4Z
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

STANDARD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
Size Document Number Rev
Bottom side

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 16 of 41
A B C D E
A B C D E F G H

+1.05VS_CK505 +3VS_CK505

FSC FSB FSA CPU SRC PCI REF DOT_96 USB R108 80mA R107 250mA
+1.05VS 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 0_0805_5% 1
C213
1
C214
1
C215
1
C216
1
C217
1
C218
1
C219
0_0805_5% 1
C206
1
C207
1
C208
1
C209
1
C210
1
C211
1
C212

0 0 0 266 100 33.3 14.318 96.0 48.0 2 2 2 2 2 2 2 2 2 2 2 2 2 2


0.1U_0402_16V4Z

10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


0 0 1 133 100 33.3 14.318 96.0 48.0
+3VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 U4
1
SDA 9 PM_SMBDATA 15,16,22,25 1
55 VDD_SRC
0 1 1 166 100 33.3 14.318 96.0 48.0 SCL 10 PM_SMBCLK 15,16,22,25
6 VDD_REF
1 0 0 333 100 33.3 14.318 96.0 48.0 12 VDD_PCI CPU_0 71 CLK_CPU_BCLK 5
CPU
72 VDD_CPU CPU_0# 70 CLK_CPU_BCLK# 5
1 0 1 100 100 33.3 14.318 96.0 48.0
19 VDD_48 CPU_1 68 CLK_MCH_BCLK 8
+1.05VS_CK505 NB
1 1 0 400 100 33.3 14.318 96.0 48.0 27 VDD_PLL3 CPU_1# 67 CLK_MCH_BCLK# 8

1 1 1 Reserved 66 VDD_CPU_IO SRC_0/DOT_96 24 CLK_DREF_96M 9


NB (96MHz)
31 VDD_PLL3_IO SRC_0#/DOT_96# 25 CLK_DREF_96M# 9
62 VDD_SRC_IO
LCDCLK/27M 28 CLK_DREF_SSC 9
+/-30ppm 52 VDD_SRC_IO NB_SSC (100MHz)
CLK_XTAL_OUT Routing the 29
LCDCLK#/27M_SS CLK_DREF_SSC# 9
Y1 place 22ohm for damping resistor 23 VDD_IO
trace at when loading is two devices
2 1 CLK_XTAL_IN 38 32
least 10mil VDD_SRC_IO SRC_2 CLK_PCIE_ICH 20
2 2 ICH-DMI
14.31818MHZ_16P 2 R917 1 22_0402_5% 33
29 CLK_48M_CR SRC_2# CLK_PCIE_ICH# 20
C220 C221
18P_0402_50V8J 18P_0402_50V8J 1 R117 2 22_0402_5% CLK_FSA 20
2 1 1 22 CLK_48M_ICH USB_0/FS_A 2
SRC_3 35 CLK_PCIE_SATA 21
FSB CPU_BSEL1 2 FS_B/TEST_MODE SATA
SRC_3# 36 CLK_PCIE_SATA# 21
CLK_FSC 7 REF_0/FS_C/TEST_
22 CLK_14M_ICH R111 1 2 33_0402_5% CLK_14ICH 8 39
REF_1 SRC_4 CLK_W LAN 25
WLAN
SRC_4# 40 CLK_W LAN# 25
2 1 CLK_FSA 1
6,9 CPU_BSEL0 22 CK_PW RGD CKPWRGD/PD#
R116 2.2K_0402_5%
11 NC SRC_6 57
CPU_BSEL1
6,9 CPU_BSEL1
SRC_6# 56

2 1 CLK_FSC 53
6,9 CPU_BSEL2 22 H_STP_CPU# CPU_STOP#
R109 10K_0402_5% 61
SRC_7 CLK_MCH_3GPLL 9
22 H_STP_PCI# 54 PCI_STOP# NB-PEG/DMI
SRC_7# 60 CLK_MCH_3GPLL# 9
CLK_XTAL_IN 5 XTAL_IN
SRC_8/CPU_ITP 64 CLK_LAN 26
CLK_XTAL_OUT 4 LOM
XTAL_OUT
SRC_8#/CPU_ITP# 63 CLK_LAN# 26

13 PCI_1 SRC_9 44

R115 1 2 33_0402_5% CLK_DDR 14 45


31 CLK_PCI_DDR PCI_2 SRC_9#
3 3
15 PCI_3
SRC_10 50
R113 1 2 33_0402_5% CLK_EC 16
30 CLK_PCI_EC PCI_4/SEL_LCDCL
SRC_10# 51
20 CLK_PCI_ICH R112 1 2 33_0402_5% CLK_ICH 17 PCIF_5/ITP_EN

SRC_11 48

18 VSS_PCI SRC_11# 47
+3VS
3 VSS_REF
CLKREQ_SATA# CLKREQ_SATA#
0 = SRC8/SRC8# (100MHz) 22 VSS_48 CLKREQ_3# 37 CLKREQ_SATA# 22 2
R125
1
10K_0402_5%
CLK_ICH CLKREQ_W LAN# CLKREQ_W LAN#
1 = ITP/ITP# (266MHz) 26 VSS_IO CLKREQ_4# 41 CLKREQ_W LAN# 25 2
R124
1
10K_0402_5%
CLKREQ_NEW # CLKREQ_NEW #
0 = Enable DOT96 & SRC1(UMA) 69 VSS_CPU CLKREQ_6# 58 2
R119
1
10K_0402_5%
CLK_EC CLKREQ_3GPLL# CLKREQ_3GPLL#
1 = Enable SRC0 & 27MHz(DIS) 30 VSS_PLL3 CLKREQ_7# 65 CLKREQ_3GPLL# 9 2
R118
1
10K_0402_5%
34 43 CLKREQ_9 CLKREQ_9 2 1
VSS_SRC CLKREQ_9# R123 10K_0402_5%
59 49 CLKREQ_10 CLKREQ_10 2 1
+3VS VSS_SRC SLKREQ_10# R126 10K_0402_5%
42 46 CLKREQ_11 CLKREQ_11 2 1
VSS_SRC CLKREQ_11# R120 10K_0402_5%
1

73 THERMAL_PAD USB_1/CLKREQ_A# 21
R121
4
@ 10K_0402_5% 4
SLG8SP556VTR_QFN72_10X10
2

CLK_ICH CLK_EC
1

R127 R128
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
Clock Generator
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 17 of 41
A B C D E F G H
5 4 3 2 1

CAM@
LCD/PANEL BD. Conn. 1
R182
2
0_0402_5% +5V_LVDS_CAM

CAM@ 0.1U_0402_16V4Z
L26 @
2 2 1 USB20_P11_R
LVDS & CAMERA +5VS 2 R821 1
0_0603_5%
1 2
C765 CAM@
+LCD_VDD +3VS 20 USB20_P11 1
W=20mils
3 4 USB20_N11_R JLVDS
20 USB20_N11 3 4
2 1 +5V_LVDS_CAM
W CM-2012-900T_0805 2 1
11 UMA_LCD_TXOUT0+ 4 4 3 3 UMA_LCD_TXCLK+ 11
1

1
11 UMA_LCD_TXOUT0- 6 6 5 5 UMA_LCD_TXCLK- 11
R621 R622 +3VS CAM@
D 8 8 7 7 D
150_0603_5% 100K_0402_5% W=60mils 1 2 11 UMA_LCD_TXOUT1+ 10 10 9 9 2 DAC_BRIG 30 1.5A
R181 0_0402_5% 12 11 2 INVT_PW M_R 2 L16 1 +LCD_VDD
11 UMA_LCD_TXOUT1- 12 11
14 13 C922 0_0805_5%
6 2

2
14 13 C923
2 11 UMA_LCD_TXOUT2+ 16 16 15 15 220P_0402_50V7K 1 1
C911 1
11 UMA_LCD_TXOUT2- 18 18 17 17 220P_0402_50V7K
0.1U_0402_16V7K reserve for test, close to JLVDS 1
for EMI's request C674 C675
20 20 19 19

3
S
Q17A Inrush current = 0A 22 21 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1 G 22 21 UMA_LCD_EDID_CLK 11 2 2
2N7002DW -T/R7_SOT363-6 2 1 2 2 Q18 1 @ 2 +5V_LVDS_CAM 24 23
11 NB_INVT_PW M 24 23 UMA_LCD_EDID_DATA 11
R623 47K_0402_5% 2 AO3413_SOT23 R929 0_0402_5% 26 25
26 25
3

D 1 2 INVT_PW M_R USB20_P11_R 28 27 +LCDVDD_R


30 INVT_PW M
1

1
C671 +LCD_VDD R930 33_0402_5% USB20_N11_R 28 27
30 30 29 29
0.01U_0402_25V7K 32 31 +3VS
1 32 31
11 UMA_ENVDD 5 W=60mils Close to JLVDS, to prevent EC pin from damage 34 34 33 33 +LCD_INV
Q17B 36 35
2N7002DW -T/R7_SOT363-6 36 35
1 1 38 37
4

38 37
1

30 BKOFF# 1 R937 2 33_0402_5% BKOFF#_R 40 40 39 39 Rated Current MAX:3000mA


C672 C673 42 41 L17 2 1 B+ 1
GND GND

2
R626 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 FBMA-L11-201209-221LMA30T_0805
100K_0402_5% @ 2 2 R903 ACES_88242-4001 C676
1 1
10K_0402_5% C924 @ 0.1U_0402_16V4Z
2

2
25 USB20_N11_R_R 1 @ 2 USB20_N11_R 220P_0402_50V7K C677 C678
R927 0_0402_5% 1 68P_0402_50V8J 0.1U_0402_25V4Z

1
2 2
25 USB20_P11_R_R 1 @ 2 USB20_P11_R
R928 0_0402_5% for EMI's request
reserve for test, close to JLVDS

C C

CRT CONNECTOR +5VS

1
D55 D56 D57 D58 +CRT_VCC_R +CRT_VCC
2 F3 30mil
1 1 2
3 RB491D_SOT23-3 1.1A_6V_MINISMDC110F-2 1
+3VS If=1A
DAN217_SC59 DAN217_SC59 DAN217_SC59 C679

3
@ @ @ @ 0.1U_0402_16V4Z
2

JCRT
L18 6 6
11 UMA_CRT_R 1 2 11 11
NBQ100505T-800Y_0402 CRT_R_L 1 1
7 7
L19 CRT_DDC_DAT 12
CRT_G_L 12
11 UMA_CRT_G 1 2 2 2
NBQ100505T-800Y_0402 8
HSYNC 8
13 13
L20 CRT_B_L 3 3
11 UMA_CRT_B 1 2 +CRT_VCC 9 9
NBQ100505T-800Y_0402 VSYNC 14 16
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
14 G
4 4 G 17
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1 10 10
1

CRT_DDC_CLK 15
R670 R671 R672 C680 C681 C682 C683 C684 C685 15
5 5
B 2 2 2 2 2 2 ALLTO_C10532-11505-L_15P-T B
@
2

+3VS
+CRT_VCC

1 2 2 1

1
C686 0.1U_0402_16V4Z R673 10K_0402_5%
5
1

R916 R674 +CRT_VCC


0_0402_5% 0_0402_5%
OE#
P

2 4 D_CRT_HSYNC 1 2
11 UMA_CRT_HSYNC A Y L21 10_0402_5%

2
G

2
U38
SN74AHCT1G125GW _SOT353-5 D_CRT_VSYNC 1 2 R677 R678
3

L22 10_0402_5% 4.7K_0402_5% 4.7K_0402_5%

2
Q19A
10P_0402_50V8J

10P_0402_50V8J
+CRT_VCC
1 1

1
11 UMA_CRT_DATA 1 2 CRT_DATA 1 6 CRT_DDC_DAT
C687 C688 R679 0_0402_5%
5
1

5
@ @ Q19B 2N7002DW -T/R7_SOT363-6
2 2
OE#
P

11 UMA_CRT_VSYNC 2 A Y 4 11 UMA_CRT_CLK 1 2 CRT_CLK 4 3 CRT_DDC_CLK


R682 0_0402_5% 1 1
G

U39 1 1 2N7002DW -T/R7_SOT363-6


SN74AHCT1G125GW _SOT353-5 C689 C690
3

C850 C849 470P_0402_50V8J 470P_0402_50V8J


33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAM & CRT
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBWAA LA5821P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 06, 2009 Sheet 18 of 41
5 4 3 2 1
5 4 3 2 1

+3VS

1 1 1 1 1 1 1 1
C242 C243 C244 C245 C246 C247 C248 C249
IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 +3VS
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
R141
D 20K_0402_5% U7 D
IHDMI@
IHDMI@

2
PMEG2010AEH_SOD123 F2 IHDMI@ PCIE_GTX_C_MRX_HDMI_P3 +3VS 25 OE 2 R144 1
OE* 10K_0402_5% +HDMI_5V_OUT
+5VS 2 1 2 1 +HDMI_5V_OUT

1
D53 1.1A_6V_MINISMDC110F-2 1 2
C250 R145 VCC3V HDMI_SCLK
11 VCC3V SCL_SINK 28 1 R142 2
IHDMI@ IHDMI@ 7.5K_0402_1% 15 IHDMI@ 2.2K_0402_5%
0.1U_0402_16V4Z IHDMI@ VCC3V HDMI_SDATA
21 VCC3V SDA_SINK 29 1 R143 2
2 IHDMI@ 2.2K_0402_5%
26

2
VCC3V
33 VCC3V
40 30 HDMI_HPD_R
VCC3V HPD_SINK
46 VCC3V
DDC_EN 32 2 1 +3VS
IHDMI@ R147 4.7K_0402_5%

VGA_DVI_TXC- 1 2 R164 HDMI_R_CK- +3VS R148 1 2 @ 0_0402_5% 3 CG0 EQ0 34 R149 2 1 0_0402_5% @
@ 0_0402_5% R150 FUNCTION1 CG1 EQ1 FUNCTION3
1 2 @ 0_0402_5% 4 FUCNTION2 FUNCTION4 35 R151 2 1 0_0402_5% @ +3VS
R152 1 @ 2 0_0402_5%
4 3 R154 1 IHDMI@ 2 0_0402_5%
4 3

2
2 R156 1 6 ANALOG1(REXT)
IHDMI@ 3.3K_0402_1% IHDMI@ R153 R155
1 0_0402_5%
1 2 2 11 PCIE_GTX_C_MRX_HDMI_P3 7 HPD_SOURCE @
0_0402_5%
L9 OCE2012120YZF_0805 IHDMI@
9 SDVO_SDATA 8

1
VGA_DVI_TXC+ SDA_SOURCE
1 2 R166 HDMI_R_CK+
@ 0_0402_5% 9
9 SDVO_SCLK SCL_SOURCE
VGA_DVI_TXD0- 1 2 R167 HDMI_R_D0-
C @ 0_0402_5% +3VS 1 @ 2 10 CG2 C
R689 0_0402_5% ANALOG2
4 4 3 3
VGA_DVI_TXC+ 13 48
IHDMI@ OUT_D4+ IN_D4+ PCIE_MTX_C_GRX_HDMI_P3 11
VGA_DVI_TXC- 14 47
OUT_D4- IN_D4- PCIE_MTX_C_GRX_HDMI_N3 11
1 1 2 2
VGA_DVI_TXD2+ 16 45
L10 OUT_D3+ IN_D3+ PCIE_MTX_C_GRX_HDMI_P0 11
OCE2012120YZF_0805 VGA_DVI_TXD2- 17 44
OUT_D3- IN_D3- PCIE_MTX_C_GRX_HDMI_N0 11
VGA_DVI_TXD0+ 1 2 R172 HDMI_R_D0+
@ 0_0402_5% VGA_DVI_TXD1+ 19 42
OUT_D2+ IN_D2+ PCIE_MTX_C_GRX_HDMI_P1 11
VGA_DVI_TXD1- 20 41
OUT_D2- IN_D2- PCIE_MTX_C_GRX_HDMI_N1 11
VGA_DVI_TXD1- 1 2 R173 HDMI_R_D1-
@ 0_0402_5% VGA_DVI_TXD0+ 22 39
OUT_D1+ IN_D1+ PCIE_MTX_C_GRX_HDMI_P2 11
VGA_DVI_TXD0- 23 38
OUT_D1- IN_D1- PCIE_MTX_C_GRX_HDMI_N2 11
4 4 3 3
IHDMI@
1 1 2 2 1 GND
5 GND
L11OCE2012120YZF_0805 12
VGA_DVI_TXD1+ GND
1 2 R176 HDMI_R_D1+ 18 GND
@ 0_0402_5% 24 GND
27 GND THERMAL_PAD 49
VGA_DVI_TXD2- 1 2 R177 HDMI_R_D2- 31
@ 0_0402_5% GND
36 GND
37 GND
4 4 3 3 43 GND
IHDMI@
B ASM1442T HDMI SHIFTER_QFN48_7X7 B
1 1 2 2
IHDMI@
L12 OCE2012120YZF_0805
VGA_DVI_TXD2+ 1 2 R178
@ 0_0402_5%
HDMI_R_D2+
HDMI Connector
JHDMI
HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16 +HDMI_5V_OUT
HDMI_SCLK SDA HDMI_HPD
15 SCL 2 1
14 IHDMI@ C659 0.1U_0402_16V4Z
Reserved
13 CEC 2 2 1
Vendor suggest un-mound for these. HDMI_R_CK- 12 CK- GND 20 C658 IHDMI@ R572 100K_0402_5%
11 21 IHDMI@
CK_shield GND

1
VGA_DVI_TXC- R159 1 @ 2 1 2 VGA_DVI_TXC+ HDMI_R_CK+ 10 22 0.1U_0402_16V4Z U37
68_0402_5% C251 0.5P_0402_50V8B HDMI_R_D0- CK+ GND 1
9 23

OE#
P
@ D0- GND HDMI_HPD_R
8 D0_shield 2 A Y 4 1 2 +3VS
HDMI_R_D0+ 7 IHDMI@ R570 10K_0402_5%
D0+

G
VGA_DVI_TXD2- R160 1 @ 2 1 2 VGA_DVI_TXD2+ HDMI_R_D1- 6 74AHCT1G125GW _SOT353-5 1 2 +HDMI_5V_OUT
68_0402_5% C252 0.5P_0402_50V8B D1- IHDMI@ @ R935 10K_0402_5%
5

3
D1_shield
@ HDMI_R_D1+ 4 D1+
reserve for test
HDMI_R_D2- 3
VGA_DVI_TXD1- R161 1 @ D2-
2 1 2 VGA_DVI_TXD1+ 2 D2_shield
68_0402_5% C253 0.5P_0402_50V8B HDMI_R_D2+ 1
@ D2+
@ TYCO_1939864-1_19P
A
VGA_DVI_TXD0- R162 1 @ 2 1 2 VGA_DVI_TXD0+ A
68_0402_5% C254 0.5P_0402_50V8B
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 19 of 41
5 4 3 2 1
5 4 3 2 1

+3VS

U9B
D11 F1 PCI_REQ#0 RP15
AD0 REQ0# PCI_REQ#0
C8 AD1 GNT0# G4 PCI_GNT#0 22 1 8
PCI_REQ#1 PCI_REQ#1
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_REQ#2
2
3
7
6
AD3 GNT1#/GPIO51 PCI_REQ#2 PCI_REQ#3
E9 AD4 REQ2#/GPIO52 F13 4 5
C9 AD5 GNT2#/GPIO53 F12
E10 E6 PCI_REQ#3 8.2K_0804_8P4R_5%
AD6 REQ3#/GPIO54 RP16
B7 AD7 GNT3#/GPIO55 F6 STRAP_A16 22
C7 PCI_IRDY# 1 8
AD8 PCI_DEVSEL#
D C5 AD9 C/BE0# D8 2 7 D
G11 B4 PCI_PERR# 3 6
AD10 C/BE1# PCI_PLOCK#
F8 AD11 C/BE2# D6 4 5
F11 AD12 C/BE3# A5
E7 8.2K_0804_8P4R_5%
AD13 PCI_IRDY# RP17
A3 AD14 IRDY# D3
D2 E3 PCI_SERR# 1 8 PLT_RST# 2 1
AD15 PAR PCI_STOP# 100K_0402_5% R910
F10 AD16 PCIRST# R1 2 7
D5 C6 PCI_DEVSEL# PCI_TRDY# 3 6
AD17 DEVSEL# PCI_PERR# PCI_FRAME#
D10 AD18 PERR# E4 4 5
B3 C2 PCI_PLOCK#
AD19 PLOCK# PCI_SERR# 8.2K_0804_8P4R_5%
F7 AD20 SERR# J4
C3 A4 PCI_STOP#
AD21 STOP# PCI_TRDY#
F3 AD22 TRDY# F5
F4 D7 PCI_FRAME#
AD23 FRAME#
C1 AD24
G7 AD25 PLTRST# C14 PLT_RST# 9,25,26,30,31 C257
H7 D4 CLK_PCI_ICH R179
AD26 PCICLK CLK_PCI_ICH 17
D1 R2 CLK_PCI_ICH 2 1 1 2
AD27 PME# @ 10_0402_5%
G5 AD28
H6 @ 10P_0402_50V8J
AD29
G1 AD30
H3 AD31
+3VS +3VS
RP18 RP19
1 8 PCI_PIRQA# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_PIRQE# 1 8
PCI_PIRQB# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# PCI_PIRQF#
2 7 E1 PIRQB# PIRQF#/GPIO3 K6 2 7
3 6 PCI_PIRQC# PCI_PIRQC# J6 F2 PCI_PIRQG# PCI_PIRQG# 3 6
C PCI_PIRQD# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH# PCI_PIRQH# C
4 5 C4 PIRQD# PIRQH#/GPIO5 G2 4 5

8.2K_0804_8P4R_5% ICH9-M ES_FCBGA676 8.2K_0804_8P4R_5%


ICH9R3@

U9D
N29 PERN1 DMI0RXN V27 DMI_MTX_IRX_N3 9
N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P3 9
P27 PETN1 DMI0TXN U29 DMI_ITX_MRX_N3 9
P26 U28

Direct Media Interface


PETP1 DMI0TXP DMI_ITX_MRX_P3 9
L29 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N2 9
L28 PERP2 DMI1RXP Y26 DMI_MTX_IRX_P2 9
M27 PETN2 DMI1TXN W29 DMI_ITX_MRX_N2 9
M26 PETP2 DMI1TXP W28 DMI_ITX_MRX_P2 9
Lane reversal

PCI - Express
26 PCIE_IRX_C_LANTX_N3 J29 PERN3 DMI2RXN AB27 DMI_MTX_IRX_N1 9
LAN 26 PCIE_IRX_C_LANTX_P3
C262 2
J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P1 9
26 PCIE_ITX_C_LANRX_N3 1 0.1U_0402_16V7K PCIE_ITX_LANRX_N3 K27 PETN3 DMI2TXN AA29 DMI_ITX_MRX_N1 9
26 PCIE_ITX_C_LANRX_P3 C263 2 1 0.1U_0402_16V7K PCIE_ITX_LANRX_P3 K26 AA28
PETP3 DMI2TXP DMI_ITX_MRX_P1 9

25 PCIE_IRX_C_W LANTX_N4 G29 PERN4 DMI3RXN AD27 DMI_MTX_IRX_N0 9


25 PCIE_IRX_C_W LANTX_P4 G28 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P0 9
WLAN 25 PCIE_ITX_C_W LANRX_N4 C264 2 1 0.1U_0402_16V7K PCIE_ITX_W LANRX_N4 H27 AC29
PETN4 DMI3TXN DMI_ITX_MRX_N0 9
25 PCIE_ITX_C_W LANRX_P4 C265 2 1 0.1U_0402_16V7K PCIE_ITX_W LANRX_P4 H26 AC28
PETP4 DMI3TXP DMI_ITX_MRX_P0 9
E29 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 17
E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 17
F27 PETN5
B B
F26 PETP5 DMI_ZCOMP AF29
DMI_IRCOMP
Within 500 mils
DMI_IRCOMP AF28 1 2 +1.5VS
C29 R180 24.9_0402_1%
PERN6/GLAN_RXN
C28 PERP6/GLAN_RXP USBP0N AC5 USB20_N0 24
D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 24 USB/B-Right
D26 PETP6/GLAN_TXP USBP1N AD3 USB20_N1 24
USBP1P AD2 USB20_P1 24 USB/B-Right
D23 SPI_CLK USBP2N AC1
+3V_SB D24 AC2
RP21 SPI_CS0# USBP2P
22 SPI_CS#1 F23 SPI_CS1#GPIO58/CLGPIO6 USBP3N AA5 USB20_N3 24
5 4 USB_OC#4 AA4 USB/Conn-Left
USBP3P USB20_P3 24
USB_OC#6
6
7
3
2 USB_OC#11
22 ICH_SPI_MOSI D25
E23
SPI_MOSI SPI USBP4N AB2
AB3
SPI_MISO USBP4P
8 1 USB_OC#10 USBP5N AA1
10K_0804_8P4R_5% USB_OC#0 N4 AA2
24,30 USB_OC#0 OC0#/GPIO59 USBP5P
N5 OC1#/GPIO40 USBP6N W5
RP22 USB_OC#2
5 4 USB_OC#5 USB_OC#3_D
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3
OC3#/GPIO42 USBP7N USB20_N7 25
6 3 USB_OC#0 USB_OC#4 M1 Y2 WiMax(WLAN)
OC4#/GPIO43 USBP7P USB20_P7 25
7 2 USB_OC#8 USB_OC#5 N2 W1
USB_OC#2 USB_OC#6 OC5#/GPIO29 USBP8N
8 1 M4 OC6#/GPIO30 USBP8P W2
10K_0804_8P4R_5% EXP_CPPE# M3 V2
USB_OC#8 OC7#/GPIO31 USBP9N
N3 OC8#/GPIO44 USBP9P V3
1 2 USB_OC#9 USB_OC#9 N1 U5
OC9#/GPIO45 USBP10N USB20_N10 29
R183 10K_0402_5% USB_OC#10 P5 U4 Card reader(3 IN 1)
OC10#/GPIO46 USBP10P USB20_P10 29
1 2 USB_OC#3_D USB_OC#11 P3 OC11#/GPIO47 USBP11N U1 USB20_N11 18
R184 10K_0402_5% U2 Int. Camera
USBP11P USB20_P11 18
1 2 EXP_CPPE# Within 500 mils USBBIAS AG2 USBRBIAS
A
R911 10K_0402_5% 1 2 AG1 A
R186 USBRBIAS#
22.6_0402_1% ICH9-M ES_FCBGA676
ICH9R3@

1 R134 USB_OC#3_D
24,30 USB_OC#3
0_0402_5%
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 20 of 41
5 4 3 2 1
5 4 3 2 1

D D
+RTCBATT C270
12P_0402_50V8J
1

2 1

D10 32.768KHZ_12.5P_MC-306 X1

10M_0402_5%
1
BAS40-04_SOT23-3 3 NC 4
OUT

R189
+RTCVCC
2 1
3

NC IN
+CHGRTC
1 C272 U9A

2
12P_0402_50V8J ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_AD0 30,31
C271 2 1 ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_AD1 30,31
0.1U_0402_16V4Z L6
2 FWH2/LAD2 LPC_AD2 30,31
ICH_RTCRST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 30,31
ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST#
CMOS Setting, near DDR Door J1
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 30,31

RTC

LPC
+RTCVCC R190 1 2 ICH_RTCRST# 1 2 B22 J3
22 ICH_INTVRMEN INTVRMEN LDRQ0#
20K_0402_5% SHORT PADS A22 J1
22 LAN100_SLP LAN100_SLP LDRQ1#/GPIO23
C273 1 2 GATEA20 1 2 +3VS
1U_0402_6.3V6K E25 N7 GATEA20 R191 @ 10K_0402_5%
GLAN_CLK A20GATE GATEA20 30
AJ27 H_DPRSTP# 2 1 +1.05VS
A20M# H_A20M# 5
C13 R192 @ 56_0402_5%
LAN_RSTSYNC H_FERR#
ITPM Setting, near DDR Door J2 DPRSTP# AJ25 H_DPRSTP# 6,9,40 2
R193
1
56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 6
R194 1 2ICH_SRTCRST# 1 2 G13
20K_0402_5% SHORT PADS LAN_RXD1 FERR# R195 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5%H_FERR# H_FERR# 5

LAN / GLAN
C274 1 2
C 1U_0402_6.3V6K D13 AD22 C
LAN_TXD_0 CPUPWRGD H_PW RGOOD 6
D12 LAN_TXD_1
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 5
R196 1 2 SM_INTRUDER# KB_RST# R197 2 @ 1 10K_0402_5% +3VS
1M_0402_5% B10 AE22
GPIO56 INIT# H_INIT# 5
AG25

CPU
INTR H_INTR 5
+1.5VS 1 R198 2 GLAN_COMP B28 GLAN_COMPI RCIN# L3 KB_RST#
KB_RST# 30 2 1 +1.05VS
27 AZ_BITCLK_HD R200 1 2 33_0402_5% 24.9_0402_1% B27 +1.05VS 1 2 R199
R202 1 GLAN_COMPO
25 AZ_BITCLK_MD 2 33_0402_5%MDC@ NMI AF23 H_NMI 5
R201 330_0402_5%

2
B
9 AZ_BITCLK_MCH R203 1 2 33_0402_5%IHDMI@ AZ_BITCLK AF6 AF24 56_0402_5% @
HDA_BIT_CLK SMI# H_SMI# 5
AZ_SYNC AH4 HDA_SYNC

C
AH27 H_THERMTRIP# 3 1 2SC2411K_SOT23
STPCLK# H_STPCLK# 5
27 AZ_SYNC_HD R205 1 2 33_0402_5% AZ_RST# AE7 Q10 @
R206 1 HDA_RST#
25 AZ_SYNC_MD 2 33_0402_5%MDC@ THRMTRIP# AG26 THRMTRIP_ICH# 1 2 H_THERMTRIP#
H_THERMTRIP# 5,9
9 AZ_SYNC_MCH R207 1 2 33_0402_5%IHDMI@ AZ_SYNC 27 AZ_SDIN0_HD AF4 R208 54.9_0402_1%
HDA_SDIN0 TP12
25 AZ_SDIN1_MD AG4 HDA_SDIN1 TP12 AG27 PAD T5

1
9 AZ_SDIN2_MCH AH3 HDA_SDIN2
R209 1 2 33_0402_5% AE5 D50

IHDA
27 AZ_RST_HD# HDA_SDIN3
25 AZ_RST_MD# R210 1 2 33_0402_5%MDC@ AH11 DAN202UT106_SC70-3
SATA4RXN SATA_IRX_C_DTX_N4 24
9 AZ_RST_MCH# R211 1 2 33_0402_5%IHDMI@ AZ_RST# AZ_SDOUT AG5 AJ11 @
22 AZ_SDOUT HDA_SDOUT SATA4RXP SATA_IRX_C_DTX_P4 24
SATA4TXN AG12 SATA_ITX_DRX_N4 24 SATA ODD
AG7 AF12 SATA_ITX_DRX_P4 24

3
R212 1 HDA_DOCK_EN#/GPIO33 SATA4TXP
27 AZ_SDOUT_HD 2 33_0402_5% AE8 HDA_DOCK_RST#/GPIO34
25 AZ_SDOUT_MD R213 1 2 33_0402_5%MDC@
9 AZ_SDOUT_MCH R214 1 2 33_0402_5%IHDMI@ AZ_SDOUT SATA_LED# AG8 ENTRIP1 35,37
32 SATA_LED# SATALED#
SATA5RXN AH9
AJ16 SATA0RXN SATA5RXP AJ9
AH16 SATA0RXP SATA5TXN AE10 ENTRIP2 35,37
AF17 SATA0TXN SATA5TXP AF10
B B
AG17 SATA0TXP
+3VS 1 2 SATA_LED# AH18
SATA_CLKN CLK_PCIE_SATA# 17

SATA
R215 10K_0402_5% 24 SATA_IRX_C_DTX_N1 AH13 AJ18
SATA1RXN SATA_CLKP CLK_PCIE_SATA 17
24 SATA_IRX_C_DTX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
1ST HDD AG14 AH7 SATARBIAS
24 SATA_ITX_DRX_N1 SATA1TXN SATARBIAS
24 SATA_ITX_DRX_P1 AF14 SATA1TXP

2
R216
10mils width
ICH9-M ES_FCBGA676 24.9_0402_1% less than
ICH9R3@
500mils

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 21 of 41
5 4 3 2 1
5 4 3 2 1

+3VS 0_0402_5% 1 2 R219 CLK_14M_ICH 1 2 1 2


R221 1 2 4.7K_0402_5% +3V_SB R228 C276
4.7K_0402_5% 2 1 R223 R224 1 2 4.7K_0402_5% @ 10_0402_5% @ 4.7P_0402_50V8C

2
4.7K_0402_5% 2 1 CLK_48M_ICH 1 2 1 2
R226 R229 C277
1 6 ICH_SMBDATA @ 10_0402_5% @ 4.7P_0402_50V8C
15,16,17,25 PM_SMBDATA

5
U9C
Q4A ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23 SPK_SEL 27
2N7002DW -T/R7_SOT363-64 ICH_SMBCLK ICH_SMBDATA BIOS need to S4_STATE#
15,16,17,25 PM_SMBCLK 3
LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19 AF19
AE21
1
R235
2
@ 10K_0402_5%
+3V_SB

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 set GPIO
D 2N7002DW -T/R7_SOT363-6 ME_EC_CLK1 C17 AD20 ICH_LOW _BAT# 2 1 D
Q4B ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 R237 8.2K_0402_5%
B18 SMLINK1
+3V_SB R230 1 2 10K_0402_5% LINKALERT# H1 CLK_14M_ICH
CLK14 CLK_14M_ICH 17
R232 10K_0402_5% ME_EC_CLK1 ICH_RI# AF3 CLK_48M_ICH
R233
1
1
2
2 10K_0402_5% ME_EC_DATA1
F19 RI# clocks CLK48 CLK_48M_ICH 17
R234 1 2 10K_0402_5% ICH_RI# R4 P1
R236 10K_0402_5% XDP_DBRESET# XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
1 2 5 XDP_DBRESET# G19 SYS_RESET#
SLP_S3# C16 PM_SLP_S3# 30
+3V_SB R238 1 2 10K_0402_5% EC_LID_OUT# M6 E16
9 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 30
G17 @ 0_0402_5%
SLP_S5# PM_SLP_S5# 30

SYS / GPIO
+3VS R240 1 2 8.2K_0402_5% PM_CLKRUN# 30 EC_LID_OUT# EC_LID_OUT# A17 R239 2 1 R902 1K_0402_5% +3V_SB
SMBALERT#/GPIO11 S4_STATE#
S4_STATE#/GPIO26 C10
A14 SB_RSMRST# 1 Q11 3

C
17 H_STP_PCI# STP_PCI# EC_RSMRST# 30
R242 1 2 1K_0402_5% SB_W AKE# E19 G20 ICH_PW ROK 1 2

E
+3V_SB 17 H_STP_CPU# STP_CPU# PWROK ICH_PW ROK 9,30
R241 MMBT3906_SOT23-3
R244 1 2 10K_0402_5% SERIRQ PM_CLKRUN# L4 M2 10K_0402_5%

B
+3VS PM_DPRSLPVR 9,40

2
Power MGT
R245 1 CLKRUN# DPRSLPVR/GPIO16
2 @ 8.2K_0402_5% EC_THERM# 1 2 +3V_SB
THRM# not 30 SB_W AKE# SB_W AKE# E20 WAKE# BATLOW# B13 ICH_LOW _BAT# R243

1
+3VS R246 1 2 10K_0402_5% OCP# used, 8.2K to 30,31 SERIRQ SERIRQ M5 4.7K_0402_5%
EC_THERM# SERIRQ D11B D11A
10K PU to 30 EC_THERM# AJ23 THRM# PWRBTN# R3 PBTN_OUT# 30
+3VS 1 2 ICH_ACIN BAV99DW -7_SOT363 BAV99DW -7_SOT363
R248 330K_0402_5% +3VS. VGATE D21 D20 1 2
9,30,40 VGATE VRMPWRGD LAN_RST#
1 2 R247 0_0402_5%
30,32,34 ACIN D12 CH751H-40PT_SOD323-2 TP11 SB_RSMRST#
T6 PAD A20 D22

6
TP11 RSMRST#
2 1
+3V_SB R250 1
R251 1
2 8.2K_0402_5%
10K_0402_5%
EC_SMI#
EC_SCI#
5 OCP#
OCP#
ICH_ACIN
AG19 GPIO1 CK_PWRGD R5 CK_PW RGD 17
R249
2.2K_0402_5%
RSMRST# circuit
2 AH21 GPIO6
AG21 R6 ICH_PW ROK
GPIO7 CLPWROK
+3VS 1 R807 2 100K_0402_5% 2HDD_DET# 30 EC_SMI# EC_SMI# A21 GPIO8
C EC_SCI# C12 B16 +3VS C
30 EC_SCI# GPIO12 SLP_M#
VGA_HDMI_HPD 1 2 VGA_HDMI_HPD C21
R918 100K_0402_5% GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 9

1
K1 B19

GPIO
GPIO18 CL_CLK1

Controller Link
+3VS R253 1 2 8.2K_0402_5% BT_DET# 2HDD_DET# AF8 R252
BT_DET# GPIO20 3.24K_0402_1%
AJ22 SCLOCK/GPIO22 CL_DATA0 F22 CL_DATA0 9
A9 GPIO27 CL_DATA1 C19
+3V_SB R255 2 1 @ 10K_0402_5% GPIO57 D19

2
R257 2 100K_0402_5% GPIO28
1 17 CLKREQ_SATA# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 +CL_VREF0_ICH
AE19 SLOAD/GPIO38 CL_VREF1 A19 Width:Spacing

1
CIR_EN# AG22 12mil:12mil 2
R809 2 100K_0402_5% CIR_EN# SDATAOUT0/GPIO39 R254
+3VS 1 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 9
AH24 D18 453_0402_1% C278
GPIO57 GPIO49 CL_RST1# 0.1U_0402_16V4Z
A8 GPIO57/CLGPIO5 1
A16

2
SB_SPKR MEM_LED/GPIO24 SUS_PW R_ACK 1
27 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 +3V_SB
iTPM Physical Presence AJ24 C11 R256 10K_0402_5%

MISC
9 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
TP8 TP3 WOL_EN/GPIO9
Assert = iTPM Physical Presence Enable T7 PAD AH20 TP8
CLGPIO5 TP9 AJ20 SUS_PWR_ACK Mobile Platform used only
De-assert = iTPM disable T8 PAD
TP10 TP9
Mobil Platform T9 PAD AJ21 TP10
**Only used in iAMT w/ME Firmware
GPIO57 Desktop Platform used only ICH9-M ES_FCBGA676 GPIO10 Desktop Platform used only
ICH9R3@

B
ICH9M Strap Pin Internal TPM Strap(Internal pull-down) Internal VR Enable Strap B
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) Flash Descriptor Security Override Strap
+3VS 1 2 ICH_SPI_MOSI 20 SPI_MOSI Low= Disable
R258 @ 1K_0402_5% Low= Descriptor Security override
High= iTPM enable by MCH strap*
Low = Internal VR Disabled GPIO33 High= Default* (Internal pull-up)
ICH_INTVRMEN High = Internal VR Enabled(Default)
No Reboot Strap (Internal pull-up)
+RTCVCC 1 2 ICH_INTVRMEN 21
+3VS 1 2 SB_SPKR SB_SPKR Low= *Default R259 330K_0402_5%
R261 @ 1K_0402_5% 1 2 ICH8M LAN100 SLP Strap
High= "No Reboot" R260 @ 0_0402_5%
LAN100_SLP 21
DMI Termination Voltage
(Internal VR for VccLAN1.05 and VccCL1.05) GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
Boot BIOS Strap (Internal pull-up) Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2 PCI_GNT#0 20
R263 @ 1K_0402_5%
0 0 RESERVED
1
R265
2
@ 1K_0402_5%
SPI_CS#1 20 0 1 SPI
1 0 PCI XOR Chain Entrance Strap
1 1 LPC* (Default) ICH_TP3 HDA_SDOUT Description
(Internal pull-up) (Internal pull-down)
0 0 RSVD
A16 Swap Override Strap +3VS
R266 @ 1K_0402_5%
AZ_SDOUT 21 0 1 Enter XOR Chain
A 1 2 STRAP_A16 20 A
R267 @ 1K_0402_5% Low= A16 swap override Enable 1 0 Normal Operation (Default)
PCI_GNT#3 ICH_TP3
High= Default* (Internal pull-up) R268 @ 1K_0402_5% 1 1 Set PCIE port config bit 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 22 of 41
5 4 3 2 1
5 4 3 2 1

U9F
+RTCVCC A23
VCCRTC
6uA at G3 state VCC1_05[01]
A15 +1.05VS U9E
1 1 1 B15 1 1 AA26 H5
VCC1_05[02] VSS[001] VSS[107]
+ICH_V5REF A6
V5REF 2mA VCC1_05[03]
C15 AA27
VSS[002] VSS[108]
J23
C279 C280 C281 D15 C282 C283 AA3 J26
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_05[04] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[003] VSS[109]
E15 AA6 J27
2 2 2 VCC1_05[05] 2 2 VSS[004] VSS[110]
+ICH_V5REF_SUS AE1
V5REF_SUS
2mA VCC1_05[06]
F15 AB1
VSS[005] VSS[111]
AC22
L11 AA23 K28
VCC1_05[07] VSS[006] VSS[112]
AA24
VCC1_5_B[01] 646mA 1634mA VCC1_05[08]
L12 AB28
VSS[007] VSS[113]
K29
AA25 L14 AB29 L13
PJ37 D13 VCC1_5_B[02] VCC1_05[09] VSS[008] VSS[114]
AB24 L16 AB4 L15
CH751H-40PT_SOD323-2 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
2 1 AB25 L17 AB5 L2
2 1 VCC1_5_B[04] VCC1_05[11] VSS[010] VSS[116]
+3VS 2 1 AC24 L18 AC17 L26
JUMP_43X39 @ VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS VSS[011] VSS[117]
AC25 M11 AC26 L27
+ICH_V5REF VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
+5VS 2 1 AD24 M18 AC27 L5
2N7002DW-T/R7_SOT363-6 R269 1 VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K L13 1 VSS[013] VSS[119]

CORE
D AD25 P11 2 AC3 L7 D
100_0402_5% VCC1_5_B[08] VCC1_05[15] MBK1608121YZF_0603 VSS[014] VSS[120]
+5V_SB 1 6 +5VALW AE25 P18 1 AD1 M12
Q16A C284 VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26 T11 AD10 M13
1U_0402_6.3V4Z VCC1_5_B[10] VCC1_05[17] C285 C286 VSS[016] VSS[122]
30,33 SBPWR_EN# AE27 T18 AD12 M14
Q16B 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[017] VSS[123]
AE28 U11 AD13 M15
2

VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]


5

AE29 U18 2 AD14 M16


2N7002DW-T/R7_SOT363-6 VCC1_5_B[13] VCC1_05[20] VSS[019] VSS[125]
F25 V11 AD17 M17
VCC1_5_B[14] VCC1_05[21] VSS[020] VSS[126]
4 3 1 R593 2 +VSB G25 V12 AD18 M23
47K_0402_5% D14 VCC1_5_B[15] VCC1_05[22] +1.05VS VSS[021] VSS[127]
H24 V14 AD21 M28
VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]
1 R594 2 CH751H-40PT_SOD323-2 H25 V16 AD28 M29
330K_0402_5% VCC1_5_B[17] VCC1_05[24] VSS[023] VSS[129]
+3V_SB 2 1 J24 V17 AD29 N11
VCC1_5_B[18] VCC1_05[25] VSS[024] VSS[130]

VCCA3GP
@ J25 V18 1 AD4 N12
+ICH_V5REF_SUS VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
1 2 +5V_SB 2 1 K24 AD5 N13
C913 R270 VCC1_5_B[20] C287 VSS[026] VSS[132]
2 K25 AD6 N14
0.1U_0402_25V6 100_0402_5% VCC1_5_B[21] 4.7U_0805_10V4Z VSS[027] VSS[133]
L23 AD7 N15
C289 VCC1_5_B[22] 2 VSS[028] VSS[134]
L24
VCC1_5_B[23] 23mA VCCDMIPLL R29 AD9
VSS[029] VSS[135]
N16
1U_0402_6.3V4Z L25 AE12 N17
SBPWR_EN# 1 VCC1_5_B[24] VSS[030] VSS[136]
1 R919 2 +5VALW M24 W23 AE13 N18
VCC1_5_B[25] VCC_DMI[1] +1.05VS VSS[031] VSS[137]
47K_0402_5% M25
VCC1_5_B[26] 48mA VCC_DMI[2]
Y23 AE14
VSS[032] VSS[138]
N26
N23 AE16 N27
VCC1_5_B[27] VSS[033] VSS[139]
N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25
VCC1_5_B[29]
2mA V_CPU_IO[2]
AC23 1 1 1 AE2
VSS[035] VSS[141]
P13
P24 AE20 P14
+1.5VS_PCIE_ICH VCC1_5_B[30] C290 C291 C292 VSS[036] VSS[142]
P25 AG29 AE24 P15
VCC1_5_B[31]
R24
VCC1_5_B[32] 308mAVCC3_3[01]
VCC3_3[02]
AJ6 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z AE3
VSS[037]
VSS[038]
VSS[143]
VSS[144]
P16
+1.5VS L14 2 1 10U_0805_10V4Z 2.2U_0603_6.3V6K R25 AC10 AE4 P17
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[33] VCC3_3[07] VSS[039] VSS[145]
1 R26 AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
1 1 1 R27 AD19 AE9 P23
+ VCC1_5_B[35] VCC3_3[03] +3VS VSS[041] VSS[147]

VCCP_CORE
T24 AF20 AF13 P28
C293 C294 C295 C296 VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27 AG24 AF16 P29
220U_6.3V_M_R15 VCC1_5_B[37] VCC3_3[05] VSS[043] VSS[149]
T28
VCC1_5_B[38] VCC3_3[06]
AC20 close to AG29 close to AG24 AF18
VSS[044] VSS[150]
P4
2 2 10U_0805_10V4Z
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
T29 AF22 P7
VCC1_5_B[39] VSS[045] VSS[151]
U24 1 1 1 1 1 1 1 AH26 R11
C VCC1_5_B[40] C297 VSS[046] VSS[152] C
U25 B9 AF26 R12
VCC1_5_B[41] VCC3_3[08] C298 C299 C300 C301 C302 C303 VSS[047] VSS[153]
V24 F9 AF27 R13
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[048] VSS[154]
V25 G3 AF5 R14
+1.5VS +1.5VS_SATAPLL_ICH VCC1_5_B[43] VCC3_3[10] 2 2 2 2 2 2 2 VSS[049] VSS[155]
U23 G6 AF7 R15
VCC1_5_B[44] VCC3_3[11] VSS[050] VSS[156]

PCI
W24 J2 AF9 R16
L15 1 VCC1_5_B[45] VCC3_3[12] VSS[051] VSS[157]
2 W25
VCC1_5_B[46] VCC3_3[13]
J7 close to AD19 close to B9, G6, K7 close to AJ6 AG13
VSS[052] VSS[158]
R17
MBK1608121YZF_0603 1 1 K23 K7 AG16 R18
VCC1_5_B[47] VCC3_3[14] +ICH_HDA VSS[053] VSS[159]
Y24 AG18 R28
C304 C305 VCC1_5_B[48] NIHDMI@ VSS[054] VSS[160]
Y25 AG20 T12
VCC1_5_B[49] VSS[055] VSS[161]
10U_0805_10V4Z
2
1U_0402_6.3V4Z
2
11mA VCCHDA
AJ4 R271 0_0603_5% +3VS AG23
VSS[056] VSS[162]
T13
1 +1.5VS AG3 T14
VSS[057] VSS[163]
47mA 11mA VCCSUSHDA
AJ3 R272 0_0603_5% AG6
VSS[058] VSS[164]
T15
AJ19 C306 IHDMI@ AG9 T16
VCCSATAPLL 0.1U_0402_16V4Z VSS[059] VSS[165]
AH12 T17
2 VSS[060] VSS[166]
1342mA VCCSUS1_05[1]
AC8 TP_VCCSUS1_05_ICH_1 @ PAD T10 AH14
VSS[061] VSS[167]
T23
+1.5VS AC16 F17 TP_VCCSUS1_05_ICH_2 @ PAD T11 AH17 B26
VCC1_5_A[01] VCCSUS1_05[2] VSS[062] VSS[168]
1 1 AD15 AH19 U12
VCC1_5_A[02] +ICH_SUSHDA VSS[063] VSS[169]
AD16 AH2 U13
C307 C308 VCC1_5_A[03] NIHDMI@ VSS[064] VSS[170]
AE15 AD8 AH22 U14
VCC1_5_A[04] VCCSUS1_5[1] VSS[065] VSS[171]
ARX
1U_0402_6.3V4Z 1U_0402_6.3V4Z AF15 R273 0_0603_5% +3V_SB AH25 U15
2 2 VCC1_5_A[05] VSS[066] VSS[172]
AG15 F18 +VCCSUS1_5_ICH_INT 1 +VCCSUS1_5_ICH_INT AH28 U16
VCC1_5_A[06] VCCSUS1_5[2] R274 0_0603_5% VSS[067] VSS[173]
close to AE15 close to AF11 AH15
VCC1_5_A[07] 1 AH5
VSS[068] VSS[174]
U17
AJ15
VCC1_5_A[08] 212mA C310 C309 IHDMI@ AH8
VSS[069] VSS[175]
AD23
A18 0.1U_0402_16V4Z AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 2 VSS[070] VSS[176]
AC11 D16 AJ14 U27
VCC1_5_A[09] VCCSUS3_3[02] VSS[071] VSS[177]
VCCPSUS
2
Symbol S0 S3 S4/S5 AD11
VCC1_5_A[10] VCCSUS3_3[03]
D17 AJ17
VSS[072] VSS[178]
U3
AE11 E22 AJ8 V1
VCC1_5_A[11] VCCSUS3_3[04] VSS[073] VSS[179]
AF11 B11 V13
VCC1_5_A[12] VSS[074] VSS[180]
ATX

VCCLAN1_05 VCC_1_05 VCCLAN3_3 VCCLAN3_3 AG10


VCC1_5_A[13]
B14
VSS[075] VSS[181]
V15
AG11 B17 V23
VCC1_5_A[14] VSS[076] VSS[182]
AH10 B2 V28
VCC1_5_A[15] VSS[077] VSS[183]
VCCCL1_5 VCC_1_5_A VCCCL3_3 VCCCL3_3 close to AC9 AJ10
VCC1_5_A[16] VCCSUS3_3[05]
AF1 +3V_SB B20
VSS[078] VSS[184]
V29
B B23 V4 B
VSS[079] VSS[185]
+1.5VS AC9 1 1 1 B5 V5
VCC1_5_A[17] VSS[080] VSS[186]
VCCCL1_05 VCC_1_05 VCCCL3_3 VCCCL3_3 B8
VSS[081] VSS[187]
W26
1 1 AC18 C311 C312 C313 C26 W27
C314 C315 VCC1_5_A[18] 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19 C27 W3
VCC1_5_A[19] 2 2 VSS[083] VSS[189]
VCCSUS1_5 VCC_1_5_A VCCSUS3_3 VCCSUS3_3 VCCSUS3_3[06]
T1 close to T1 close to AF1 2 E11
VSS[084] VSS[190]
Y1
0.1U_0402_16V4Z AC21 T2 E14 Y28
2 2 VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
T3 E18 Y29
0.1U_0402_16V4Z VCCSUS3_3[08] VSS[086] VSS[192]
VCCSUS1_05 VCC_1_05 VCCSUS3_3 VCCSUS3_3 G10
VCC1_5_A[21] VCCSUS3_3[09]
T4 E2
VSS[087] VSS[193]
Y4
G9 T5 E21 Y5
VCC1_5_A[22] VCCSUS3_3[10] VSS[088] VSS[194]
Internal voltage regulators power these wells inside the ICH9 VCCSUS3_3[11]
T6 E24
VSS[089] VSS[195]
AG28
close to AC14 AC12 U6 E5 AH6
VCCPUSB

and current for this rail is accounted for in the sourcing voltage VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]
AC13 U7 E8 AF2
rail current requirements. AC14
VCC1_5_A[24] VCCSUS3_3[13]
V6 F16
VSS[091] VSS[197]
B25
VCC1_5_A[25] VCCSUS3_3[14] VSS[092] VSS[198]
close to AC7 close to AJ5 VCCSUS3_3[15]
V7 F28
VSS[093]
VCCUSBPLL 11mA
+1.5VS AJ5 W6 F29
VCCSUS3_3[16] VSS[094]
1 1 W7 G12
VCCSUS3_3[17] VSS[095]
USB CORE

AA7 Y6 G14 A1
C316 C317 VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
AB6 Y7 G18 A2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[27] VCCSUS3_3[19] VSS[097] VSS_NCTF[02]
AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 G24 A29
VCC1_5_A[29] VSS[099] VSS_NCTF[04]
AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 AH29
VCCLAN1_05_INT_ICH VSS[101] VSS_NCTF[06]
A10 G8 AJ1
VCCLAN1_05[1] VCCCL1_05_INT_ICH VSS[102] VSS_NCTF[07]
1 A11 G22 H2 AJ2
VCCLAN1_05[2] VCCCL1_05 VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
G23 1 H23 AJ28
C318 VCCCL1_5 VSS[104] VSS_NCTF[09]
+3VS A12 1 1 H28 AJ29
VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
0.1U_0402_16V4Z
2 1
+1.5VS
B12
VCCLAN3_3[2] 78mA C319 H29
VSS[106] VSS_NCTF[11]
B1
A24 +3VS C320 C321 0.1U_0402_16V4Z B29
C322 VCCCL3_3[1] 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 VSS_NCTF[12]
VCCCL3_3[2]
B24
2 2
close to G22
GLAN POWER

2
0.1U_0402_16V4Z A27
VCCGLANPLL 23mA
1 close to G23 ICH9-M ES_FCBGA676
D28 ICH9R3@
A VCCGLAN1_5[1] A
C323 D29
VCCGLAN1_5[2] 80mA
0.1U_0402_16V4Z E26
2 VCCGLAN1_5[3]
E27
+1.5VS VCCGLAN1_5[4]
A26
VCCGLAN3_3 1mA
1 ICH9-M ES_FCBGA676
ICH9R3@
C324
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 23 of 41
5 4 3 2 1
5 4 3 2 1

SATA HDD Conn. SATA ODD Conn

+5VS +5VS
Place closely JHDD0 SATA CONN.
1.2A 1.1A

1 1 1 1
C697 C698 C699 C700 1 1 1 1 1
D 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C721 C722 C723 D
@ C724 C725
2 2 2 2 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2

Place component's closely JODD

JHDD0

GND 1
2 SATA_ITX_C_DRX_P1 C713 1 2 0.01U_0402_25V7K
A+ SATA_ITX_DRX_P1 21
3 SATA_ITX_C_DRX_N1 C715 1 2 0.01U_0402_25V7K
A- SATA_ITX_DRX_N1 21
GND 4
5 SATA_IRX_DTX_N1 C717 1 2 0.01U_0402_25V7K
B- SATA_IRX_C_DTX_N1 21
6 SATA_IRX_DTX_P1 C719 1 2 0.01U_0402_25V7K
B+ SATA_IRX_C_DTX_P1 21
GND 7
JODD

V33 8 +3VS GND 1


9 2 SATA_ITX_C_DRX_P4 C729 1 2 0.01U_0402_25V7K
V33 A+ SATA_ITX_DRX_P4 21
10 3 SATA_ITX_C_DRX_N4 C730 1 2 0.01U_0402_25V7K
V33 A- SATA_ITX_DRX_N4 21
GND 11 GND 4
12 5 SATA_IRX_DTX_N4 C731 1 2 0.01U_0402_25V7K
GND B- SATA_IRX_C_DTX_N4 21
C 13 6 SATA_IRX_DTX_P4 C732 1 2 0.01U_0402_25V7K C
GND B+ SATA_IRX_C_DTX_P4 21
V5 14 +5VS GND 7
V5 15
V5 16
GND 17 DP 8
Reserved 18 +5V 9 +5VS
GND 19 +5V 10
V12 20 MD 11
24 GND V12 21 15 GND GND 12
23 GND V12 22 14 GND GND 13

OCTEK_SAT-22SO1G_RV SANTA_206401-1_RV
@ @

USB Board Conn USB Left Conn


B W=60mils W=60mils B
+5VALW 1.4A
U42
+USB_VCCA +5VALW
U40
1.4A +USB_VCCB

1 GND OUT 8 1 GND OUT 8


2 IN OUT 7 2 IN OUT 7
3 IN OUT 6 3 IN OUT 6
+USB_VCCB W=60mils
30 USB_EN# 4 EN# FLG 5 USB_OC#0 20,30 30 USB_CHG_EN# 4 EN# FLG 5 USB_OC#3 20,30
1 1
G528_SO8 G528_SO8 0.1U_0402_16V4Z
C752 C743 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 @ 2 @ C79 + C727 C728
2 2
D61 220U_6.3V_M 2
2 1000P_0402_50V7K
1
3
+USB_VCCA PJDLC05_SOT23-3 JUSB
1 VCC GND 5
W=60mils JUSBB 20 USB20_N3 2 6
D- GND
1 1 20 USB20_P3 3 D+ GND 7
2 2 4 GND GND 8
3 3
4 P-TW O_CU304G-A0G1G-P
4 @
5 5
6 6
A 20 USB20_N0 7 7 A
20 USB20_P0 8 8
9 9
20 USB20_N1 10 10
20 USB20_P1 11 11
12 12
13
14
GND Security Classification Compal Secret Data
GND
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
E&T_6905-E12N-00R
@
SATA-HDD/ODD& USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Thursday, August 06, 2009 Sheet 24 of 41
5 4 3 2 1
5 4 3 2 1

PCIe Mini Card-WLAN PJ19


+3V_W LAN
+3V_W LAN 2 2 1 1 +3VS
@ JUMP_43X79 0.1U_0402_16V4Z
1 1 1
+3V_W LAN
+1.5VS CM17 CM18 CM19
D D
JW LAN 2 2 2
1 2 0.01U_0402_25V4Z 4.7U_0805_10V4Z
1 2
3 3 4 4
5 5 6 6
17 CLKREQ_W LAN# 7 7 8 8
9 9 10 10
11 12 +1.5VS
17 CLK_W LAN# 11 12
17 CLK_W LAN 13 13 14 14
15 16 0.1U_0402_16V4Z
15 16
17 17 18 18 1 1 1
19 19 20 20 XMIT_OFF# 30
21 22 CM20 CM21 CM22
21 22 PLT_RST# 9,20,26,30,31
20 PCIE_IRX_C_W LANTX_N4 23 23 24 24
2 2 2
20 PCIE_IRX_C_W LANTX_P4 25 25 26 26
27 28 0.01U_0402_25V4Z 4.7U_0805_10V4Z
27 28
29 29 30 30 PM_SMBCLK 15,16,17,22
20 PCIE_ITX_C_W LANRX_N4 31 31 32 32 PM_SMBDATA 15,16,17,22
20 PCIE_ITX_C_W LANRX_P4 33 33 34 34
35 35 36 36 USB20_N7 20
37 37 38 38 USB20_P7 20
+3V_W LAN 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
R920 1 2 0_0402_5% E51_TXD_R 49 50
30 E51_TXD 49 50
R921 1 2 0_0402_5% E51_RXD_R 51 52
30 E51_RXD 51 52
C 53 54 C
GND1 GND2
Debug card using
2 R959 ACES_88911-5204
100K_0402_5% @
1

Int. Camera MDC 1.5 Conn.


+MDC

B B
1 1 1
+5V_CAM C762 C763 C764
1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
R104 1 2 MDC@ 2 MDC@ 2 MDC@
+5VS 2
0_0603_5% @
W=20mils
0.1U_0402_16V4Z
1 2
C766 @ JMDC 1 2 +3V_SB
R731 NIHDMI@ 0_0603_5%
1 2 +MDC 1 2 +VCCSUS1_5_ICH_INT
GND1 RES0 R733 IHDMI@ 0_0603_5%
21 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
JCAM 5 6 +3V_SB
GND2 3.3V
1 1 21 AZ_SYNC_MD 7 IAC_SYNC GND3 8
2 AZ_SDIN1_MD_R 9 10
2 USB20_N11_R_R 18 IAC_SDATA_IN GND4
3 3 USB20_P11_R_R 18 21 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 21
4 4

2
5 5
6 R736

GND
GND
GND
GND
GND
GND
GND1 10_0402_5%
GND2 7
@
ACES_88266-05001 2 1 AZ_SDIN1_MD_R ACES_88018-124G

13
14
15
16
17
18

1
@ 21 AZ_SDIN1_MD R737 33_0402_5% MDC@ @ 1
C768
Connector for MDC Rev1.5 10P_0402_50V8J
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/MDC/CAMERA
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBWAA LA5821P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 25 of 41
5 4 3 2 1
A B C D E

Close to Pin10,13,30,36,45 +LAN_VDD12

2 2 2 2 2
CL15 CL2 CL3 CL4 CL5
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1
Place Close to Chip UL2

20 PCIE_IRX_C_LANTX_P3 CL9 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_P320 HSOP LED3/EEDO 33 LAN_DO PAD T12


34 LAN_DI 1 2
LED2/EEDI/AUX +3V_LAN
20 PCIE_IRX_C_LANTX_N3 CL8 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_N321 HSON LED1/EESK 35 LAN_SK_LAN_LINK# RL1 3.6K_0402_5%
32 LAN_CS 2 1
EECS
20 PCIE_ITX_C_LANRX_P3 15
HSIP
RL2 1K_0402_5% Close to Pin1,37,29
38 LAN_ACTIVITY#
LED0 +3V_LAN
20 PCIE_ITX_C_LANRX_N3 16
HSIN LAN_MDI0+
+3V_LAN
RTL8103EL-GR MDIP0 2
17 3 LAN_MDI0-
17 CLK_LAN REFCLK_P MDIN0 LAN_MDI1+
17 CLK_LAN# 18 5
LAN_WAKE# REFCLK_M MDIP1 LAN_MDI1-
1 2 6 2 2 2
RL4 @ 100K_0402_5% MDIN1 CL10 CL11 CL12
25 CLKREQB NC 8
9
NC
9,20,25,30,31 PLT_RST# 27 PERSTB NC 11 Close to Pin48 1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
12
NC
+3VS RL3 1 2 2.49K_0402_1% 46 4
RSET NC
LAN_WAKE# 26 48 VCTRL12 VCTRL12 0.1U_0402_16V4Z
30 LAN_WAKE# LANWAKEB VCTRL12A
1

ISOLATEB 28
RL5 ISOLATEB
VDDTX 19 +EVDD12 1 2
1K_0402_1% LAN_X1 41 30
CKXTAL1 DVDD12 +LAN_VDD12
LAN_X2 42 36 CL6 CL7 Close to Pin19
CKXTAL2 DVDD12
13
2

ISOLATEB DVDD12 2 1 +EVDD12


1 2 WOL_EN# 30,33 DVDD12 10
R926@ 0_0402_5% @ 10U_0805_10V4Z
39
2 NC 2
RL6 Reserved for test 23
NC NC
44
15K_0402_5% 24 45 +LAN_VDD12 2 2
NC VCTRL12D CL13 CL14
7 29 RL901 20_0402_5%
GND VDD33 RL911
14 37 20_0402_5% +3V_LAN 1U_0402_6.3V4Z 1U_0402_6.3V4Z
GND VDD33 1 1
31 GND
47 1 RL921 20_0402_5%
GND AVDD33
NC 40
22
GNDTX NC
43 for EMI's request
YL1
LAN_X1 2 1 LAN_X2 RTL8103EL-GR_LQFP48_7X7

25MHz_20pF_6X25000017
1 1
CL17 CL18

27P_0402_50V8J 27P_0402_50V8J
2 2

For EMI request


CL19 68P_0402_50V8J
LAN Conn.
2 1
JLAN
LAN_ACTIVITY# 2 1 12
3 RL7 150_0402_1% Yellow LED- 3

+3V_LAN 2 1 11 Yellow LED+


RL11 150_0402_1%
8 PR4-
7
PR4+
RJ45_MIDI1- 6
PR2-
5 PR3-
UL3
4
LAN_MDI0+ RJ45_MIDI0+ PR3+
1 TD+ TX+ 16
LAN_MDI0- 2 15 RJ45_MIDI0- RJ45_MIDI1+ 3
TD- TX- RL8 PR2+
2 1 3 CT CT 14
CL20 0.01U_0402_16V7K 4 13 CL26 1 2 1000P_0402_50V8-J 1 2 75_0402_1% RJ45_MIDI0- 2
NC NC RJ45_GND PR1-
5 12 1 2 1 2 14
NC NC CL27 1000P_0402_50V8-J 75_0402_1% RJ45_MIDI0+ SHLD2
2 1 6 11 1
CL21 0.01U_0402_16V7K LAN_MDI1+ CT CT RJ45_MIDI1+ RL9 PR1+
7 10 13
LAN_MDI1- RD+ RX+ RJ45_MIDI1- LAN_SK_LAN_LINK# SHLD1
8 9 2 1 10
RD- RX- RL10 150_0402_1% Green LED-
2 1 9 Green LED+
Place these components LF-H1201P-2 CL22 68P_0402_50V8J
colsed to UL3 TYCO_2068888-1_12P-T
For EMI request @
2 1
+3V_LAN RL12 150_0402_1%

RJ45_GND 1 2 1000P_1808_3KV7K LANGND


CL23 1 1
CL24 CL25
4 4
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8103EL 10/100 LAN

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NBWAA LA5821P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 06, 2009 Sheet 26 of 41
A B C D E
5 4 3 2 1

+3VS_DVDD RA1
Codec 10U_0805_10V4Z
30mil 2 1 +3VS
1 1 0_0603_1%
CA1 CA2

1
+AVDD RA2
2 2
RA3
40mil 0.1U_0402_16V4Z
0_0603_5%
1 2
+1.5VS_DVDIO NIHDMI@ +VDDA 1 2 +5VS
+VDDA 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z

2
0_0603_1% LA1 +1.5VS PJ33 @
CA3
1
CA4
1
CA5
1
CA6
1
10U_0805_10V4Z
20mil
1 2 JUMP_43X79
1 1 FBMA-L11-160808-800LMT_0603
IHDMI@
2 2 2 2 CA7 CA8
D D
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
0.1U_0402_16V4Z

25

38

9
U49

AVDD1

AVDD2

DVDD_IO
DVDD
14 LINE2-L LOUT1_L 35 AMP_SPK_L 28
C920 @ 33_0402_5%
15 36 2 1 2 1 AZ_BITCLK_HD
LINE2-R LOUT1_R AMP_SPK_R 28
R931
16 39 22P_0402_50V8J @
28 MIC2_L MIC2_L LOUT2_L CA90 @
Int. Mic 17 41 2 1 AZ_RST_HD#
28 MIC2_R MIC2_R LOUT2_R
23 LINE1_L SPDIFO1 48 22P_0402_50V8J for EMI's request
24 LINE1_R SPDIFO2 45

28 MIC1_C_L 21 MIC1_L HPOUT_L 33 1 RA5 2 HP_L 28


63.4_0402_1%
Ext. Mic 28 MIC1_C_R 22 MIC1_R HPOUT_R 32 1 RA6 2 HP_R 28
63.4_0402_1%

1 2 MONO_IN 12 37
CA14 100P_0402_50V8J BEEP_IN MONO_OUT
Beep sound
C 6 46 C
21 AZ_BITCLK_HD BITCLK DMIC_CLK1/2
5 44
21 AZ_SDOUT_HD SDATA_OUT DMIC_CLK3/4 EC Beep RA8
21 AZ_SDIN0_HD 2 1 AZ_SDIN0_HD_R 8 SDATA_IN LINE2_VREFO 20 30 EC_BEEP# 1 2
33_0402_5% RA7 47K_0402_5%
21 AZ_RST_HD# 11 RESET# LINE1_VREFO 18

10 28 10mil
21 AZ_SYNC_HD SYNC MIC1_VREFO
10mil
+MIC1_VREFO
PCI Beep RA9
CA15
19 +MIC2_VREFO 1 2 1 2 MONO_IN
MIC2_VREFO 22 SB_SPKR
22 SPK_SEL 2 GPIO0/DMIC_DATA1/2 47K_0402_5%
31 1 2 0.1U_0402_16V4Z
CPVEE CA16 2.2U_0603_6.3V6K
3 GPIO1/DMIC_DATA3/4
27 AC_VREF CA18 CA19
SENSE_A VREF
13

10U_0805_10V4Z

0.1U_0402_16V4Z
SENSE A AC_JDREF
JDREF 40 1 RA10 2 1 1
SENSE_B 34 20K_0402_1%
SENSE B

1
CBN 30 1 2 1
2 1 EAPD# 47 CA17 2.2U_0603_6.3V6K
28 MUTE# EAPD 2 2
RA31 0_0402_5% 29 RA11 CA20
CBP 10K_0402_5%
43 NC 0.1U_0402_16V4Z
IF test OK, link direct 2

2
4 DVSS AVSS1 26
7 DVSS AVSS2 42
1 2
RA90 0_0603_5%
ALC272-GR_LQFP48_7X7 1 2
B DGND need to re-link
<BOM Structure> ALC272 AGND RA12 0_0603_5%
B
1 2
RA13 0_0603_5%
1 2
GPIO0-->SPK_SEL HIGH:HARMAN RA14 0_0603_5%
LOW:NO-BRAND 1 2
RA15 0_0603_5%

Sense Pin Impedance Codec Signals Function place close to chip


39.2K PORT-A (PIN 39, 41)
28 MIC_SENSE 1 RA18 2 SENSE_A
20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A
10K PORT-C (PIN 23, 24) FM tuner
5.1K PORT-D (PIN 35, 36) SPK out SENSE_B
28 NBA_PLUG 1 2
RA16 5.1K_0402_5%
39.2K PORT-E (PIN 14, 15)
A 1 RA17 2 A
20K_0402_1%
20K PORT-F (PIN 16, 17) MIC@
Int. MIC
SENSE B
10K PORT-H (PIN 37)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-I (PIN 32, 33) Headphone out Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
HD CODEC ALC272
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 27 of 41
5 4 3 2 1
Ext. Mic
CH751H-40PT_SOD323-2
TPA6017 Medium Range Amplifier CA21
RA21 2 RA20 1
1K_0402_5% 4.7K_0402_5%
1
DA1
2 +MIC1_VREFO
4.7U_0805_10V4Z 2 1 2 1 MIC1_L
27 MIC1_C_L
+5VS 4.7U_0805_10V4Z 2 1 2 1 MIC1_R
27 MIC1_C_R
0.1U_0402_16V4Z 1K_0402_5%
CA22 RA22 2 RA23 1 1 2 +MIC1_VREFO
4.7K_0402_5% DA2
1 1 1 CH751H-40PT_SOD323-2

CA23
10U_0805_10V4Z
CA24 CA25 Int. Mic
2 2 2
2 MIC@ 1 +MIC2_VREFO
4.7K_0402_5% RA24
0.1U_0402_16V4Z 10 dB MIC@ RA25 MIC@
CA26 1K_0402_5% MIC@ SBY100505T-121Y_0402 JMIC
1U_0402_6.3V4Z 2 1 2 1 INT_MIC_L LA111 2 INT_MIC 1
+5VS 27 MIC2_L 1 NC1 3
1 2 2 2 NC2 4

1
1U_0402_6.3V4Z CA27

16
15
27 MIC2_R 2 1 2 1

6
UA3 RA28 RA27 1K_0402_5% 220P_0402_50V7K ACES_85204-0200N
100K_0402_5% 100K_0402_5% CA28 RA26 MIC@
Rin =70Kohm @

PVDD1
PVDD2
VDD
MIC@

3
@ MIC@

PSOT24C_SOT23
2

2
7 RIN+ GAIN0 2
CA29 0.033U_0402_25V7K MIC@
3

1
GAIN1 DA3

1
27 AMP_SPK_R LINE_C_OUTR 17
CA30 0.033U_0402_25V7K RIN- SPKR+ RA30 RA29
ROUT+ 18
100K_0402_5% 100K_0402_5%
@
14 SPKR- Left Connector DA4 PJDLC05_SOT23-3

2
ROUT-
9 LIN+ 2
CA31 0.033U_0402_25V7K 1
4 SPKL+ 3
LOUT+ @ JSPKL
27 AMP_SPK_L LINE_C_OUTL 5 SPKL+ LA3 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1 3
LIN- 1 NC1
CA32 0.033U_0402_25V7K
LOUT- 8 SPKL- GAIN0 GAIN1 Av(db)Rin(ohm) SPKL- LA4 1 2 FBMA-L11-160808-800LMT_0603 SPK_L2 2 2 NC2 4

0 0 6 90K ACES_85204-0200N
setting 68Hz @

F=1/2πRC --> -3db 12 Keep 10 mil width


0 1 10 70K Right Connector DA5 PJDLC05_SOT23-3
NC
1 0 15.6 45K 3
C=0.033U,R=70K,F=68Hz BYPASS 10 AMP_BYPASS 1
27 MUTE# 19 SHUTDOWN 1 1 21.6 25K 2
2 @ JSPKR
SPKR+ LA5 1 2 FBMA-L11-160808-800LMT_0603 SPK_R1 1 3
1 NC1
GND5
GND1
GND2
GND3
GND4

CA33 SPKR- LA6 1 2 FBMA-L11-160808-800LMT_0603 SPK_R2 2 4


2 NC2
0.47U_0603_10V7K
1 ACES_85204-0200N
TPA6017A2_TSSOP20 @
21
20
13
11
1

HeadPhone/LINE Out JACK


JLINE
5

27 NBA_PLUG 4

LA7 1 2 HP_R_L 3
27 HP_R
KC FBM-L11-160808-121LMT 0603 6
LA8 1 2 HP_L_L 2
27 HP_L
KC FBM-L11-160808-121LMT 0603 1
+3VS FOX_JA6333L-B3T0-7F

+3VS
Volume Control 1
3 @
1

2
RA32
100K_0402_5% DA6
1

CA35 0.1U_0402_16V4Z PJDLC05_SOT23-3


RA33 RA34 +3VS 1 2
2
5

SW 2 10K_0402_5% 10K_0402_5% +3VS


1
DIP

Ext.MIC/LINE IN JACK
2

CA36 JEXMIC
NC
P

2 1 2 2 4 0.1U_0402_16V4Z AGND 5
A RA35 10K_0402_5% A Y 2
G

74LVC1G14GW _SOT353-5 UA5 4


27 MIC_SENSE
1 UA4 1 14
3

COM CD1# VCC MIC1_R LA9 1


2 D1 CD2# 13 2 MIC1_L_R 3
3 12 KC FBM-L11-160808-121LMT 0603 6
CP1 D2 MIC1_L LA101
B 3 1 2 4 SD1# CP2 11 2 MIC1_L_L 2
RA36 10K_0402_5% 5 10 KC FBM-L11-160808-121LMT 0603 1
Q1 SD2#
1 1 6 Q1# Q2 09 1 DA7
DIP

7 08 CA39 FOX_JA6333L-B3T0-7F
CA37 CA38 GND Q2# @
3 1 1
SW _XRE094_3P 0.01U_0402_16V7K 0.01U_0402_16V7K 74LCX74MTC_TSSOP14 1
4

2 2 2 CA40 CA41
2
120P_0402_50V8K 120P_0402_50V8K
@2 2 @
0.1U_0402_16V4Z PJDLC05_SOT23-3
ENCODER_DIR 30
ENCODER_PULSE 30

Security Classification Compal Secret Data


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
AUDIO AMP/MIC/SPK/VR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
NBWAA LA5821P M/B

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 06, 2009 Sheet 28 of 41
5 4 3 2 1

+3VS_CR

RC2 0_0603_5%
+3VS 1 2

1
CC1
0.1U_0402_16V4Z
D 2 RC7 0_0402_5% D
2 1

CC6 0.1U_0402_16V4Z
1 2

UC2
+3VS_CR
CC4 0.1U_0402_16V4Z 1 AV_PLL
2 1 3
NC
2

7 NC
RC8 +VCC_3IN1 9
100K_0402_5% CARD_3V3
11
D3V3
+3VS_CR 33 10
D3V3 VREG
22 1
1

MS_D4 CC7
30
RC10 0_0402_5% NC 1U_0402_6.3V4Z
1 +3VS_CR 8 3V3_IN
RST# 2 1 RST#_R CC5 RST#_R 44
1U_0402_6.3V4Z MODE SEL RST# 2
45
MODE_SEL
1 47 43
CC8 2 XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42
1U_0402_6.3V4Z 41
XD_ALE_SP17 SD_DATA2
20 USB20_N10 4 40
2 DM SD_DAT2/XD_RE#_SP16 SD_DATA3
20 USB20_P10 5 DP SD_DAT3/XD_WE#_SP15 39
CR_LED# 14 38
GPIO0 XD_RDY_SP14 RC11 1 SDCLK
37 2 22_0402_5%
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12 35
34 SD_MS_CLK RC12 1 2 22_0402_5% MSCLK
+3VS SD_CLK/XD_D1/MS_CLK_SP11 MS_DATA3_SD_DATA6
31
MODE SEL SD_DAT6/XD_D7/MS_D3_SP10 MSCD#
29
C MS_INS#_SP9 MS_DATA2_SD_DATA7 C
SD_DAT7/XD_D2/MS_D2_SP8 28
1

27 SD_MS_DATA0
RC13 SD_DAT0/XD_D6/MS_D0_SP7 MS_DATA1
26
120_0402_5% SD_DAT1/XD_D3/MS_D1_SP6 MSBS
XD_D5_SP5 25
1

1 23 SD_DATA1
CC13 RC16 XD_D4/SD_DAT1_SP4 SDCD#
21
2 2

SD_CD#_SP3 SDWP#
0.1U_0402_16V4Z 0_0402_5% Vf=2.0V(typ),2.4V(max) SD_WP_SP2 20
@ 19
2 DC1 XD_CD#_SP1
18
2

HT-110UYG-CT_YEL/GRN EEDI
2 13 XTAL_CTR
RREF XTAL_CTR
24
MS_D5
12
1

DGND
32 15

CR_LED# 6
DGND EEDO
EECS
16
17
3 in 1 Card Reader
AGND EESK SDCMD
46 36
AGND SD_CMD
2

2
RTS5159-GR_LQFP48_7X7
RC14 RC15
6.19K_0402_1% 0_0402_5% confirm all pin define with connector spec.
1

JREAD
SDWP# 1
SD_DATA1 SD-WP
2
SD_MS_DATA0 SD-DAT1
3
SD-DAT0
4
SD-GND
5
B MSBS MS-GND B
6 MS-BS
SDCLK 7
MS_DATA1 SD-CLK
8
SD_MS_DATA0 MS-DAT1
9 MS-DAT0
+VCC_3IN1 10
MS_DATA2_SD_DATA7 SD-VCC
48Mhz 11
12
MS-DAT2
1 1 SD-GND
CC10 CC11 MSCD# 13
1U_0402_6.3V4Z 0.1U_0402_16V4Z MS_DATA3_SD_DATA6 MS-INS
14
XTLI SDCMD MS-DAT3
17 CLK_48M_CR 1 2 15 SD-CMD
RC19 0_0402_5% 2 2 MSCLK 16 MS-SCLK
1

17
R925 SD_DATA3 MS-VCC
18 SD-DAT3
33_0402_5% 19
SD_DATA2 MS-GND
20 SD-DAT2 GND1 22
@ R C USB AUTO DE-LINK MS FORMATTER Description SDCD# 21 23
2

SD-CD GND2
1 TAITW_R009-125-LR_RV
0 NC YES Recommended @
C919
@ 22P_0402_50V8J
2
NC 47P YES YES
NC NC Compatible with RTS5158E
for EMI's request
+3VS_CR 1 2 XTAL_CTR
RC20 0_0402_5% NC 680P YES LED ON 10_0402_5% 10P_0402_50V8J
MSCLK 1 2
+1.5VS
1 10K 180P LED ON @ RC17 @ CC14
C921
A 0.1U_0402_16V4Z 10_0402_5% 10P_0402_50V8J A

2
@ 10K 680P YES SDCLK 1 2

Close to C919 @ RC18 @ CC15

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5159 Card Reader

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NBWAA LA5821P M/B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 29 of 41
5 4 3 2 1
5 4 3 2 1

+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 C771 1 1 2 2 C769
C770 1 2
C772 C773 C774 C775
1000P_0402_50V7K1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1

111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z

22
33
96

67
9
for EMI request U43

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
CLK_PCI_EC

1
D D
R738 1 21
21 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PW M 18
@ 10_0402_5% 2 23
21 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# 27
22,31 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
21,31 LPC_FRAME# 4 27 ACOFF 36
2

LFRAME# ACOFF/FANPWM2/GPIO13
1 21,31 LPC_AD3 5 LAD3
21,31 LPC_AD2 7 LAD2 PWM Output
C778 8 63 BATT_TEMPA
21,31 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 35
@ 22P_0402_50V8J BATT_TEMPA
2 21,31 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 36 1
C776
2
100P_0402_50V8J
ADP_I/AD2/GPIO3A 65 ADP_I 36
CLK_PCI_EC 12 AD Input 66 ACIN_D 1 2
17 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 36
13 75 C779 100P_0402_50V8J
9,20,25,26,31 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76
+3VL R739 ECRST# SELIO2#/AD5/GPIO43
22 EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% 38
32 W L_BT_LED# CLKRUN#/GPIO1D
2 1 ECRST# 68
DAC_BRIG/DA0/GPIO3C DAC_BRIG 18
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 5
2 1 DA Output IREF/DA2/GPIO3E 71 IREF 36
C780 0.1U_0402_16V4Z KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 36
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A USB_CHG_EN# 24
KSI4 59 84 +5VS
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 24
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C ENCODER_DIR 28
KSI6 61 PS2 Interface 86 TP_CLK 1 2
KSI6/GPIO36 PSDAT2/GPIO4D ENCODER_PULSE 28
1 2 KSO1 KSI7 62 87 TP_CLK 4.7K_0402_5% R740
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 32
R906 47K_0402_5% KSO0 39 88 TP_DATA TP_DATA 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 32
1 2 KSO2 KSO1 40 4.7K_0402_5% R741
R907 47K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
C KSO3 42 97 VGATE +3VALW C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 9,22,40
to avoid EC entry ENE test mode KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 W OL_EN# 26,33
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 SBPW R_EN# 23,33
LID_SW #
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 31 2 1
KSO7 46 SPI Device Interface 47K_0402_5% R766
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 31
KSO10 49 120
31 KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 31
KSO11 50 SPI Flash ROM 126 SPI_CLK SPI_CLK L9121 20_0402_5%
KSO[0..15] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK_L 31
KSO12 51 128 1
31 KSO[0..15] KSO12/GPIO2C SPICS# SPI_CS# 31
KSO13 52 C925
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
RP23 KSO15 54 73
KSO15/GPIO2F CIR_RX/GPIO40 2 10P_0402_50V8J
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
+3VL 1 8 EC_SMB_CK1 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 36
2 7 EC_SMB_DA1
BATT_CHGI_LED#/GPIO52 90 BATT_FULL_LED# 32 reserve for EMI, close to EC
+3VS 3 6 EC_SMB_CK2 91
CAPS_LED#/GPIO53 CAPS_LED# 31
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92
35 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW _LED# 32
EC_SMB_DA1 78 93
35 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_ON_LED# 32 +3VALW
2.2K_8P4R_5% EC_SMB_CK2 79 SM Bus 95
5 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 39
EC_SMB_DA2 80 121
5 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 40
127 ACIN_D 1 2
AC_IN/GPIO59
+3VL 2 1 CEC_INT# 100K_0402_5% R742
R751 100K_0402_5% D64
6 100 ACIN_D 2 1
22 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 22 ACIN 22,32,34
22 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# 22
15 102 CH751H-40PT_SOD323-2
22 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 32
CEC_INT# 16 103 EC_SW I#
LID_SW#/GPIO0A EC_SWI#/GPXO06 PM_PW ROK
31 ESB_CK 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104
B B
31 ESB_DA 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 18
9 MCH_TSATN_EC# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 XMIT_OFF# 25
22 PM_SLP_S4# 25 EC_THERM#/GPIO11 GPXO10 107 CURS_LED# 31
28 108 UMA_ENBKL 1 2
5 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
29 R747 100K_0402_5%
31 CAP_RST# FANFB2/GPIO15
25 E51_TXD 30 EC_TX/GPIO16
25 E51_RXD 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 CAP_INT# 31
+3VL Reserved for ENE CS/B 32 112
32 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 UMA_ENBKL 11
32 PW R_SUSP_LED# 34 PWR_LED#/GPIO19 GPXID3 114 USB_OC#3 20,24
2 1 CAP_INT# 36 GPI 115
31 NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# 22
R932 @ 4.7K_0402_5% 116 ICH_PW ROK 1 2
GPXID5 SUSP# 33,38
2 1 ESB_DA 117 R904 10K_0402_5%
GPXID6 PBTN_OUT# 22
R933 @ 4.7K_0402_5% 118 USB_OC#0_R PM_PW ROK 1 2
ESB_CK CRY1 GPXID7 R231 10K_0402_5%
2 1 122 XCLK1
R934 @ 4.7K_0402_5% CRY2 123 124 +EC_V18R +3VS
XCLK0 V18R
AGND

1 2
GND
GND
GND
GND
GND

C782 C900 0.1U_0402_16V4Z

5
4.7U_0805_10V4Z
KB926QFD3_LQFP128_14X14 VGATE 2

P
11
24
35
94
113

69

R749 B
Y 4 ICH_PW ROK 9,22
CRY1 1 2CRY2 PM_PW ROK 1 A

G
@ 20M_0603_5% U5

3
NC7SZ08P5X_NL_SC70-5

1 2 EC_SW I#
22 SB_W AKE#
R912@ 0_0402_5% 1 1 1 2
1 2 C784 C785 R905@ 0_0402_5%
A LAN_W AKE# 26 A
1

R913 0_0402_5%
USB_OC#0_R 1 2 Y5 To reduce CMOS dischage fail rate
15P_0402_50V8J

15P_0402_50V8J
IN

OUT

R914@ 0_0402_5% 2 2
1 2 USB_OC#0 20,24
R915 0_0402_5%
NC

NC

The circuit is reserve for new design for pre-MP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
2

ENE-KB926 RevD3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
32.768KHZ_12.5P_1TJS125BJ4A421P Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 30 of 41
5 4 3 2 1
SPI Flash (16Mb*1) Lid SW LPC Debug Port
Please place the PAD under DDR DIMM.

H1
+3VL +3VS

6 5
1 20mils
C786 U46 +3VALW
8 VCC VSS 4 22,30 SERIRQ 1 2 7 4 PLT_RST# 9,20,25,26,30
0.1U_0402_16V4Z U48 R761 0_0402_5%
2 APX9132ATI-TRL_SOT23-3
3 W
21,30 LPC_AD3 8 3 LPC_AD2 21,30
7 2 3

GND
HOLD VDD VOUT LID_SW # 30

30 SPI_CS# 1 S 21,30 LPC_AD1 9 2 LPC_AD0 21,30


1 1

1
30 SPI_CLK_L 6 C C822 C823 10 1
21,30 LPC_FRAME# CLK_PCI_DDR 17
5 2 0.1U_0402_16V4Z 10P_0402_50V8J
30 EC_SO_SPI_SI D Q EC_SI_SPI_SO 30 2 2

2
16MBIT MX25L1605AM2C-12G SO8
@ DEBUG_PAD R764
22_0402_5%

1
2
C820
22P_0402_50V8J
1

KEYBOARD please close to JKB


Left switch Right Switch
SW 3
CONN. KSO2 1 2
SW 4 C789 100P_0402_50V8J
SMT1-05_4P SMT1-05_4P KSO1 1 2
1 3 1 3 C790 100P_0402_50V8J
KSI[0..7] KSO0 1 2
KSI[0..7] 30
2 4 2 4 C791 100P_0402_50V8J
32 TP_SW L 32 TP_SW R KSO[0..15]
1 KSO4 1 2
KSO[0..15] 30
1 C792 100P_0402_50V8J
6
5

6
5
C793 KSO3 1 2
180P_0402_50V8J C794 C795 100P_0402_50V8J
3

2
2 180P_0402_50V8J JKB KSO5 1 2
D65 2 D66 C796 100P_0402_50V8J
34 1 2 +3VS
PJDLC05_SOT23-3 PJDLC05_SOT23-3 R755 300_0402_5% KSO14 1 2
33 C797 100P_0402_50V8J
32 KSO6
31 1 2
C798 100P_0402_50V8J
30 KSO7
29 1 2 +3VS 1 2
need to relink the footprint 28
KSO2 R756 300_0402_5% C799 100P_0402_50V8J
KSO1 KSO13 1 2
1

1
27 KSO0 C800 100P_0402_50V8J
26 KSO4 KSO8
25 1 2
@ @ KSO3 C801 100P_0402_50V8J
24 KSO5 KSO9
23 1 2
KSO14 C802 100P_0402_50V8J
22 KSO6 KSO10
21 1 2
KSO7 C803 100P_0402_50V8J
20 KSO13 KSO11
19 1 2
KSO8 C804 100P_0402_50V8J
CS/B Connector 18
17
16
KSO9
KSO10
KSO12 1
C805
2
100P_0402_50V8J
KSO11 KSO15 1 2
15 KSO12 C807 100P_0402_50V8J
14 KSO15 KSI7
13 1 2
KSI7 C808 100P_0402_50V8J
12 KSI2 KSI2
11 1 2
KSI3 C810 100P_0402_50V8J
10 KSI4 KSI3
9 1 2
20 mil width JCS KSI0 C811 100P_0402_50V8J
R103 2 @ 8
+3VL 1 0_0603_5% +3VL_CS 1 1
ESB_DA_L 1 2 1 2 7
KSI5 KSI4 1 2
R518 1 @ 2 0_0402_5% 2 C914 100P_0402_50V8J KSI6 C812 100P_0402_50V8J
30 CAP_INT# 2 6
R922 1 @ 2 0_0402_5% 3 R923 @ KSI1 KSI0 1 2
30 CAP_RST# 3 5
4 @ 100_0402_5% 2 1 +3VS C813 100P_0402_50V8J
L910 1 @ 4 4
30 ESB_CK 2 FBMA-11-100505-301T_0402 ESB_CK_L 5 5 3
CAPS_LED# R762 300_0402_5%
CAPS_LED# 30
KSI5 1 2
L911 1 @ 2 FBMA-11-100505-301T_0402 ESB_DA_L 6 ESB_CK_L 1 2 1 2 CURS_LED# C814 100P_0402_50V8J
30 ESB_DA 6 2 CURS_LED# 30
1 1 1 7 C915 100P_0402_50V8J NUM_LED# KSI6 1 2
GND 1 NUM_LED# 30
C854

C853

C852

2 8 R924 @ C815 100P_0402_50V8J


GND @ 100_0402_5% ACES_88170-3400 KSI1
1 1 2
3 ACES_85201-06051 @ C816 100P_0402_50V8J
@2 @2 @2
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

@ CAPS_LED# 1 2
D82 C817 100P_0402_50V8J
PJDLC05_SOT23-3 CURS_LED# 1 2
@ C818 100P_0402_50V8J
NUM_LED# 1 2
C819 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
SPI ROM/TP/KB/Debug/CS Board
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
NBWAA LA5821P M/B

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 31 of 41
5 4 3 2 1

Power Button Touch Pad Connector ISPD ZZZ PJP1

+3VL
PCB DC-IN

2
R765 PCB ZKU LA-5821P REV1 PJP1
D 45@ D
SW 5 100K_0402_5% JTOUCH
1 3 51_ON# 34 2 R106 1 +5VS_TOUCH 1

1
ON/OFFBTN# +5VS 0_0603_5% 1 U3 U3
ON/OFFBTN# 30 30 TP_CLK 2 2
TOP side 2 4 2 30 TP_DATA 3 3
31 TP_SW L 4 4

6
@ SMT1-05-A_4P C821 5 NB_GL40_R3 NB_GL40_R1
6
5

Q28A 1U_0402_6.3V4Z 31 TP_SW R 5


6 6
2N7002DW -T/R7_SOT363-6 1
7 GND
30 EC_ON 2 another at page32 2 8 GND
CANTIGA GL40 CANTIGA GL40
SW 6 1 GL40R3@ GL40R1@

2
1 3 3 ACES_85201-06051

1
R767 @
BTM side 2 4 10K_0402_5% D80 U3 U9
PJDLC05_SOT23-3
@ SMT1-05-A_4P @
6
5

1
NB_GM45_R1 SB_R1
debug phase using
CANTIGA GM45 ICH9-M ES
GM45R1@ ICH9R1@

ACIN 22,30,34
DC-IN LED PWR/B
2

Vf=2.8V(typ),3.15V(max)
C D67 Q30A C

+3VALW 1 2 2 1 6 1 JPOW ER
R768 120_0402_5% 1
HT-110UYG-CT_YEL/GRN 2N7002DW -T/R7_SOT363-6
5
1
2
GND 3
2
3 ON/OFFBTN#
Screw Hole
6 GND 4 4

ACES_85201-04051
@
H2 H3 H4 H6 H7 H8 H9 H10
BATT CHARGE/FULL LED
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
@ @ @ @ @ @ @ @

Vf=1.9V(typ),2.4V(max) for amber


Vf=2.0V(typ),2.4V(max) for green H12 H13 H14 H15 H11
If=30mA(max)
D70 H_3P0 H_3P0 H_3P0 H_3P0 H_5P0

1
2 @ @ @ @ @
BATT_CHG_LOW _LED# 30

+3VALW 1 2 1
R773 120_0402_5%
3 H16 H36 H38
BATT_FULL_LED# 30

HT-210UD/UYG_AMB/GRN H_3P0N H_5P0X3P0N H_11P0X4P0N


POWER/SUSPEND LED

1
@ @ @
B B

MINI CARD H32 H34 CPU H20 H22 H19 H21

D68
WLAN LED Vf=1.9V(typ),2.4V(max) H_3P8 H_3P8 H_3P7 H_3P8 H_3P8X4P8 H_3P8X4P8

1
D74 2 @ @ @ @ @ @
PW R_SUSP_LED# 30
+3VS 1 2 2 1 W L_BT_LED# 30
R777 120_0402_5% +3VALW 1 2 1
HT-110UD_1204_AMBER R770 120_0402_5%
3 PW R_ON_LED# 30 MDC H27 H33

HT-210UD/UYG_AMB/GRN H_1P2 H_1P2

1
@ @

SATA_LED# 21

PCB Fedical Mark PAD


2

HDD LED
+3VS 2 R779 1 6 1
10K_0402_5% FD1 FD2 FD3 FD4
5

Q31A
A
D76 2N7002DW -T/R7_SOT363-6 @ @ @ @ A
+3VS 1 2 2 1 3 4

1
R780 120_0402_5%
HT-110UYG-CT_YEL/GRN Q31B 2N7002DW -T/R7_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
Comm. SW/ Sub Conn./LEDS/ISPD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 32 of 41
5 4 3 2 1
A B C D E

+3VALW TO +3VS +5VALW TO +5VS


+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
4.7U_0805_10V4Z
Inrush current = 0A Inrush current = 0A
1 1 1 1
Q32 C824 C825 4.7U_0805_10V4Z Q33 C826 C827

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1

2
7 D S 2 7 D S 2
2 2 R781 2 2 R782
6 D S 3 6 D S 3
1 5 D G 4 5 D G 4 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z
SI4800BDY_SO8 1 R784 2 +VSB SI4800BDY_SO8 1 R785 2 +VSB

3 1

3 1
1 1 47K_0402_5% 1 1 47K_0402_5%

0.01U_0402_25V7K
4.7U_0805_10V4Z

0.022U_0402_25V7K

4.7U_0805_10V4Z
1

6
C831
C830 R787 Q35A C832 C833 R788 Q36A
330K_0402_5% Q35B 200K_0402_5% Q36B
2 2 SUSP 2 2 @ SUSP 5
2 5 2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6

2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6

4
+3VALW TO +3V_LAN +3VALW TO +3V_SB
+3VALW +3VALW +3V_SB
2 +3VALW PJ36 2
2 2 1 1
2

Vgs=-4.5V,Id=3A,Rds<97mohm
R793 Q44 @ JUMP_43X79
100K_0402_5% 2 Vgs=10V,Id=6A,Rds=35mohm Inrush current = 0A

D
C910 Q41 6

S
0.1U_0402_16V7K AO3413_SOT23 2 1 5 4 1U_0402_6.3V4Z
1

S 2 PJ35 C842 2 1 1

2
1 G
10U_0805_10V4Z C843
26,30 W OL_EN# 1 2 2 JUMP_43X79 1
R795 47K_0402_5% 2 4.7U_0805_10V4Z C844 R803

G
@ +3V_LAN 2
1

C837 D 470_0805_5%
1

3
0.01U_0402_25V7K SI3456BDV-T1-E3_TSOP6 2 2
1

Inrush current = 0A +VSB 2 1

6 1
1 R804 20K_0402_5%

1
1
1 1 R805 C845 Q46A
Q46B 200K_0402_5% 0.1U_0402_25V6
C840 C841 1U_0402_6.3V4Z SBPW R_EN# 5 2 SBPW R_EN#
2 SBPW R_EN# 23,30
4.7U_0805_10V4Z

2
@ 2 2 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6

1
3 3

+1.5VS +0.9VS +5VALW

2
R801 R802 R796
470_0805_5% 470_0805_5% 100K_0402_5%
1

1
SUSP
39 SUSP

3
Q30B
2N7002DW -T/R7_SOT363-6 Q28B
D
1

2N7002DW -T/R7_SOT363-6
Q21 2 SUSP 5 SUSP
30,38 SUSP# 5 another at page31
2N7002_SOT23-3 G another at page31

2
S
3

4
R799
10K_0402_5%

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 33 of 41
A B C D E
A B C D

PR1
VIN 1M_0402_1%
PL1 1 2
PF1 SMB3025500YA_2P VIN
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2 VS

1
PJP1
1 10A_125V_451010MRL PR3
+ 84.5K_0402_1%

1
1 1

2 PR5
+

8
PC1 PC2 PC3 PC4 PR4 PU1A 22K_0402_1%

2
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 0_0402_5% PR2
+ 3 1 2

P
2

2
-
1 2 1 2 1 0
22,30,32 ACIN

20K_0402_1%
- 4 - 2

1
10K_0402_1%

PR6
@ SINGA_2DW -0005-B03 LM358DT_SO8 PC6

0.1U_0603_25V7K
4
PR7 PD2 1000P_0402_50V7K

2
PC5
10K_0402_1% GLZ4.3B_LL34-2

2
2

2
VIN 1 2
RTCVREF
PR8

2
10K_0402_1%

PD3
RLS4148_LL34-2

1
BATT+ 2 1

1
PD4 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3 Vin Detector
PR11

2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS High 18.384 17.901 17.430 2

Low 17.728 17.257 16.976


1

1
PC8
PR12 PC7 0.1U_0603_25V7K
100K_0402_1% 0.22U_1206_25V7K
RTC Battery
2

2
2

2
32 51_ON# 1 2
PR13
22K_0402_1%
- PBJ1 +
2 1 +RTCBATT +RTCBATT
RTCVREF
1

PR14
200_0603_5% @ MAXEL_ML1220T10
PR15 PR16 PU2 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN
SP093MX0000
1

GND
PC9 PC10
10U_0805_10V4Z 1
2

1U_0805_25V4Z

3 3

PJ3
PJ1 PJ2
+3VALW P 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V VL 2 2 1 1 +5VL
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2)
OCP(min)=7.7A 2 2 1 1
@ JUMP_43X118
PJ7
PJ5 (12A,480mils ,Via NO.= 24)
+5VALW P 2 2 1 1 +5VALW OCP(min)=10.16A +VSBP 2 2 1 1 +VSB
PJ6
@ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) +3VLP 2 2 1 1 +3VL
OCP(min)=7.9A (120mA,40mils ,Via NO.= 1)
@ JUMP_43X39
PJ8 (100mA,40mils ,Via NO.= 2)
2 2 1 1

@ JUMP_43X118 PJ10 PJ11


+0.9VSP 2 1 +0.9VS +1.5VSP 2 1 +1.5VS
PJ9 2 1 2 1

+1.05VSP 2 1 +1.05VS @ JUMP_43X79 @ JUMP_43X79


2 1
(2A,80mils ,Via NO.= 4) (2.0A,80mils ,Via NO.=4)
@ JUMP_43X118 OCP(min)=7.98A
(10A,400mils ,Via NO.=20)
OCP(min)=12.52A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
DCIN & DETECTOR

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KTKAA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 34 of 41
A B C D
A B C D

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C
1 1
VMB VL
PF2 PL2 VL ENTRIP1 21,37
PJP2 15A_65V_451015MRL SMB3025500YA_2P VL
1 BATT_S1 1 2 1 2
1 BATT+
2 2

2
3 3 1 2 1 2 +3VLP
4 PR17 PR18 PR19
4

1
1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
6 EC_SMDA PC11 PC12 PH1 PC13 2 PQ2
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 0.1U_0603_25V7K PR21 G SSM3K7002FU_SC70-3
7

1
7 100K_0402_1%_NCP15W F104F03RC 47K_0402_1%
8 S

3
8

1
9 1 2

2
9 PR20 PR22
12 GNDGND 10

8
13 11 1K_0402_1% 13.7K_0402_1% PU3A
GNDGND
1 2 3

P
@ OCTEK_BTJ-09HD1G +
1 2 1

2
O
2

TM_REF1 2 ENTRIP2 21,37


-

G
PR23 PR24 PD5
100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2

4
0.22U_0805_16V7K
1

1
D

15.4K_0402_1%
1

1
PC14
PR25 2 PQ3

PR26
6.49K_0402_1% SSM3K7002FU_SC70-3

1000P_0402_50V7K
G
2 1 +3VLP 2 1 VL S

3
1

PC15
PR27

2
100K_0402_1%

2
1

1
PR28
2
1K_0402_1% 2

PR29
100K_0402_1%
2

2
BATT_TEMPA 30

EC_SMB_DA1 30

EC_SMB_CK1 30
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 53 degree C

VL VL

PQ4

2
TP0610K-T1-E3_SOT23-3

1
PR30
PH2 47K_0402_1%
B+ 3 1 +VSBP PR31
100K_0402_1%_NCP15W F104F03RC 47K_0402_1%

1
3 3
100K_0402_1%

0.1U_0603_25V7K

1 2
0.22U_1206_25V7K

2
1

1
PR32

PC16

PC17

PR33

8
13.7K_0402_1% PU3B
1 2 5

P
2

+
7 2 1
2

TM_REF1 O
6 -

G
1
VL PR34 PD6

1
22K_0402_1% @ @ LM393DG_SO8 RLS4148_LL34-2

4
1 2 PC18 PR35
2

0.22U_0805_16V7K 16.9K_0402_1%

2
PR36

2
100K_0402_1%

PR37
1

0_0402_5% D
1 2 2 PQ5
37 POK
G SSM3K7002FU_SC70-3
0.1U_0402_16V7K

S
3
1

PC19
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
BATTERY CONN / OTP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KTKAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 35 of 41
A B C D
A B C D

PQ8
PR38 B+ FDS4435BZ_SO8
VIN PQ6 PQ7 0.015_1206_1% 1
FDS4435BZ_SO8 AO4407A_SO8 S D 8
2 S D 7
8 D S 1 1 8 1 4 3 S D 6
7 D S 2 2 7 4 G D 5

2
6 S 3 3 6 2 3

0.01U_0402_25V7K
PR39 D
5 D G 4 5

1
3.3_1210_5% PJ14

100K_0402_1%
4.7_1206_5%

1
2 1 CHG_B+

4
2 1

PR158

PC20

PR40
1000P_0402_50V7K 0.022U_0402_25V7K
2 1
@ JUMP_43X118 @ PQ9

100K_0402_1%

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
0.01U_0603_50V7K

1
1
FDS4435BZ_SO8

2
2

2
PC22

PR42
PR41

CHGEN#
1 D 8

2
S

PC23

PC24

PC25
3.3_1210_5% 2
1
S D 7 1

PC21
PC26 PC28 3 D 6

1
S

5
6
7
8
0.1U_0402_16V7K PU5 0.22U_1206_25V7K 4 D 5

1 1

2
G
1 2 1 CHGEN PVCC 28 1 2
PC29

1
2.2U_0805_25V6K PR44 /BATDRV
2 PC27 PC30 2.2_0603_1% PQ10
@0.1U_0603_25V7K

1K_0402_1%
0.1U_0603_25V7K 27 1 2 4 AO4466_SO8

2
BTST

1
2

PC138

PR159
PR43
340K_0402_1% 2 26
ACN HIDRV
3

3
2
1
ACP PR45

2
4 25 PL3 0.02_1206_1%
ACDET ACDRV PH PD7 10UH_SIL1045RA-100PF_4.5A_30%
5 ACDET
2 1 1 2 1 2 1 4

10U_1206_25V6M
RLS4148_LL34-2 PC31 BATT+

10U_1206_25V6M
REGN
2 3
2

1
PR46 0.1U_0603_25V7K

4.7_1206_5%
5
6
7
8

1
PR160

PC32

PC33
PR47 137K_0402_1%
54.9K_0402_1% 1 2 ACSET 6
VREF

2
ACSET

AO4466_SO8
24 PC36

2
REGN

1
@ 0.1U_0402_16V7K
1

2
1

1
PR48 PC35 1 2

PQ11
PC34 120K_0402_1% 1U_0603_10V6K 4
@ 0.01U_0402_25V7K

2
2

1
2

1
PC38 PC39

680P_0603_50V8J
1 2 7 ACOP
0.1U_0603_25V7K @0.1U_0603_25V7K

@ PC139
PR49 PC37 23

3
2
1

2
340K_0402_1% 0.47U_0603_16V7K LODRV

2
1

PGND 22
2
OVPSET 8 2

OVPSET

9 AGND LEARN 21 ACOFF 30


2

PR50
54.9K_0402_1%
VREF 20 CELLS
CELLS
1

10 VREF
PQ12
3

1
SI2301BDS-T1-E3_SOT23-3 PC40
1U_0603_10V6K
PR51 19

2
100K_0402_1% SRP
RTCVREF
1 2 2 11 VDAC SRN 18

BAT 17
1

VREF

1
PC41 VADJ 12
VREF 0.1U_0603_25V7K PR52 VADJ PC42
2

1
1

ACSET 100K_0402_1% 0.1U_0603_25V7K

2
PR53 29
1

200K_0402_1% ACGOOD# TP
13 ACGOOD
1

VIN
1

D
PR55
2

PR54 2 PQ13 16 2 1 IREF 30


100K_0402_1% G SSM3K7002FU_SC70-3 /BATDRV SRSET
14 BATDRV 49.9K_0402_1%

1
S
2

3
1

1
D
PR57
ACOFF 1 2 2 PQ14 15 1 2 100K_0402_1% PC44 PR156
G SSM3K7002FU_SC70-3 IADAPT @0.01U_0402_25V7K 309K_0402_1%

2
1

3 3

PC43 S BQ24751ARHDR_QFN28_5X5 PR56


3

2
0.1U_0402_16V7K PR58 10_0603_5% PR155

2
340K_0402_1% REGN 10K_0402_1%

1
1 2 ADP_V 30
PC45
2

100P_0402_50V8J

2
1

1
PR59 ADP_I 30 IREF Current PR157
PC137
@ 0_0402_5% 47K_0402_1%
PR60 .1U_0402_16V7K

2
65W,Iadapter=3.42A,PR38=0.015ohm,PR46=137K,PR48=120K,CP=3.146A 210K_0402_1% 2.968V 3A
2

2
30 CHGVADJ 1 2 VADJ CHGVADJ Pre Cell
1

1.484V 1.5A
PR61 3.28V 4.35V
499K_0402_1%
VMB
VREF
0V 4V
2

要要要EC DA pin
499K_0402_1% 340K_0402_1%
1

VS

2
PR62

CHGVADJ
@ PR63
0.01U_0402_25V7K

100K_0402_1%
2

1
1

PC46

CHGEN#
PR64
2

1
D
@ 30 FSTCHG 2 PQ15
G SSM3K7002FU_SC70-3
2
8

4
PR65 PU1B S 4

3
10K_0402_1%
+ 5
P

30 BATT_OVP 1 2 7 0
- 6
G

@
105K_0402_1%
1

LM358DT_SO8
0.01U_0402_25V7K
4

1
PR66

PC47

@ @ Security Classification Compal Secret Data Compal Electronics, Inc.


2

Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title


2

CHARGER

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KTKAA 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 36 of 41
A B C D
5 4 3 2 1

2VREF_51125

1U_0603_10V6K
D D

1
PC48

2
PR67 PR68
13K_0402_1% 30K_0402_1%
1 2 1 2

PR69 PR70
B++
20K_0402_1% 19.6K_0402_1%
B++
1 2 1 2

PJ15
B+ 2 2 1 1 +3VLP

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR71 PR72
2200P_0402_50V7K

150K_0402_1% 150K_0402_1%
10U_1206_25V6M

10U_1206_25V6M
1

1
PC49

1 2 1 2

2200P_0402_50V7K
0.1U_0402_16V7K

1
PC50

PC52
PC51
4.7U_0805_10V6K
2

2
6

5
6
7
8
PU6

PC134
8
7
6
5

1
PC53
C C

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
PQ16 25 PQ17
P PAD

1
AO4466_SO8

2
AO4466_SO8
7 24 POK 35 4

2
VO2 VO1
4
8 23 PR74 PC55
PR73 VREG3 PGOOD 2.2_0603_1% 0.1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_1% VBST2 VBST1
1
2
3

PL4 PC54 UG_3V 10 21 UG_5V PL5 +5VALWP


4.7U_LF919AS-4R7M-P3_5.2A_20% 0.1U_0402_16V7K DRVH2 DRVH1 4.7U_LF919AS-4R7M-P3_5.2A_20%
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
1

8
7
6
5

5
6
7
8

1
LG_3V LG_5V
4.7_1206_5%

12 19

4.7_1206_5%
DRVL2 DRVL1
PR75

PR76
SKIPSEL
PQ18 PQ19
220U_6.3V_M

220U_6.3V_M
VREG5
0.1U_0402_16V7K

0.1U_0402_16V7K
VCLK
1 AO4712_SO8 AO4712_SO8 1

GND
EN0

VIN
2

2
1

1
+ +
PC56

PC57
PC130

PC129
4 4
PR77 TPS51125RGER_QFN24_4X4

13

14

15

16

17

18
1

1
499K_0402_1%
680P_0603_50V8J

680P_0603_50V8J
2

2
2 2
PC58

PC59
1 2
B+
Ipeak = 5A
2

1
2
3

3
2
1

2
1
100K_0402_5%
PR78
Imax = 3.5A 1 2
VL

1
PR79

PC60
4.7U_0805_10V6K
2
B @ 0_0402_5% B
F = 305kHz

0.1U_0402_16V7K
2
ENTRIP1 21,35 ENTRIP2 21,35 Ipeak = 5A
Total Capacitor = 220 uF B++

PC135
1
Imax = 3.5A
ESR = 15m Ohm

0.1U_0603_25V7K

2
2
PC61
D D F = 245kHz
1

2VREF_51125
PQ20 2 2 PQ21
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3 Total Capacitor = 220 uF
S S
3

ESR = 15m Ohm

2 1
VL
PR80
100K_0402_1%
D
1

VS 1 2 2 PQ22
G SSM3K7002FU_SC70-3
PR81 S
49.9K_0402_1%

0.01U_0402_16V7K

3
1

100K_0402_1%
1
PR82

@ PC62

A A
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
+5V/+3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 37 of 41
5 4 3 2 1
A B C D

1 1

PR83 PR84 PR85 PR86


75K_0402_1% 75K_0402_1% 75K_0402_1% 29.4K_0402_1%

+1.5VSP 1 2 1 2 2 1 2 1 +1.05VSP

51124_B+

2
PR87 51124_B+
0_0402_5%

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
PJ16
1 1 2 2 B+
1

1
PC63

PC64

1
1
@ JUMP_43X118

PC65
2

4.7U_1206_25V6K

4.7U_1206_25V6K

2200P_0402_50V7K
8
7
6
5

5
6
7
8

1
PC66

PC67
PU7

1
VO2

VFB2

TONSEL

GND

VFB1

VO1

PC68
PQ23 25 PQ24

2
AO4466_SO8 P PAD AO4466_SO8

2
4 7 PGOOD2 PGOOD1 24 4
PC70
PC69 PR88 8 23 PR89
EN2 EN1 0.1U_0402_16V7K
0.1U_0402_16V7K 2.2_0603_1% 2.2_0603_1%
2
2 1 2 1 BST_1.5V 9 22 BST_1.05V 2 1 1 2 2
1
2
3

3
2
1
VBST2 VBST1
PL6 UG_1.5V 10 21 UG_1.05V PL7
+1.5VSP 1.8UH_SIL104R-1R8PF_9.5A_30% DR VH2 DR VH1 1.8UH_SIL104R-1R8PF_9.5A_30%
+1.5VSP 1 2 LX_1.5V 11 20 LX_1.05V 1 2 +1.05VSP
LL2 LL1 +1.05VSP
LG_1.5V 12 19 LG_1.05V
DR VL2 DR VL1
1

8
7
6
5
220U_6.3V_M

4.7_1206_5%

5
6
7
8

1
PR90

PQ25

4.7_1206_5%
0.1U_0402_16V7K

0.1U_0402_16V7K
PGND2

PGND1
1

V5FILT
TRIP2

TRIP1

PR91
AO4712_SO8
4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
V5IN
1

D
D
D
D
1

+
PC73

PQ26
1

1
+ PC74
PC131

PC71

PC132
2

PC72
4 TPS51124RGER_QFN24_4x4 FDS6670AS_NL_SO8 220U_6.3V_M
2

13

14

15

16

17

18

2
2
4 G
2

2
1

2
680P_0603_50V8J
PC75

1
S
S
S

680P_0603_50V8J
2

1
2
3

PC76
PR93

3
2
1
13.7K_0402_1% PR92

2
1 2 14.7K_0402_1%
Ipeak = 5A

2
Ipeak = 10A
Imax = 3.5A PR94 PR96
0_0402_5% 0_0402_5% Imax = 7A
F = 300kHz SUSP# 2 1 1 2 +5VALW 1 2
SUSP# 30,33
PR95 F = 240kHz
Total Capacitor = 220 uF 3.3_0402_5%
1

PC80
1

1
3
@ 0.1U_0402_16V7K PC77 PC78 PC79 Total Capacitor = 1430 uF 3

ESR = 15m Ohm 1U_0603_10V6K 4.7U_0805_10V6K @ 0.1U_0402_16V7K


2

2
ESR = 1.67m Ohm

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
1.05V / 1.5V

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 38 of 41
A B C D
5 4 3 2 1

D
PL12 D
HCB2012KF-121T50_0805
51117_B+ 1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC81

PC82
5
6
7
8

2
AO4466_SO8
PQ27
PR97
255K_0402_1% 4
1 2
PR98 PR99
0_0402_5% 2.2_0603_1%
1 2 BST_1.8V 1 2
30 SYSON

3
2
1
1

PL8

15

14
PC84

1
PC83 PU8 1.8UH_SIL104R-1R8PF_9.5A_30%
@0.1U_0402_16V7K BST_1.8V-1 1 2 1 2

EN_PSV

TP

VBST
+1.8VP
2

2 13 DH_1.8V 0.1U_0603_25V7K Ipeak = 8A


TON DRVH

4.7_1206_5%
PR100 LX_1.8V

0.1U_0402_16V7K
3 VOUT LL 12

5
6
7
8

PR102
100_0603_1% 1 Imax = 5.6A

PQ28
+5VALW

AO4712_SO8
+5VALW 1 2 4 V5FILT TRIP 11 1 2

1
+ PC85

PC133
PR101

2
5 10 15.4K_0402_1% 220U_D2_4VM F = 312kHz
C VFB V5DRV C

2
1

1
DL_1.8V 2

680P_0603_50V8J
6 PGOOD DRVL 9 4

PGND

PC87
PC86 Total Capacitor = 440 uF
GND
4.7U_0603_10V6K PC88
2

2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC89 ESR = 7.5m Ohm
7

3
2
1
4.7U_0805_10V6K

2
PR103
28.7K_0402_1%
1 2
1

PR104
20.5K_0402_1%
2

+1.8V
1

PJ18
1

@ JUMP_43X79
2

B PU9 B
2

1 VIN VCNTL 6 +3VALW


2 GND NC 5
1

1
PC90
1

4.7U_0805_6.3V6K 3 7 PC91
PR105 VREF NC 1U_0603_6.3V6M
2

2
1K_0402_1% 4 8
VOUT NC
9
2

TP
APL5331KAC-TRL_SO8
1

PR106 +0.9VSP
1

0_0402_5% D PR107
1K_0402_1% PC92
10U_0805_6.3V6M

33 SUSP 1 2 2
1

G 0.1U_0402_16V7K
2
1

PC94

S PQ29
0.1U_0402_16V7K
3

PC93 SSM3K7002FU_SC70-3
2

@ 0.1U_0402_16V7K
2

PC136
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V / 0.9V

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 06, 2009 Sheet 39 of 41

5 4 3 2 1
5 4 3 2 1

+5VS

2
7

7
CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR108
+CPU_B+ PL9

30
1_0603_5%

VR_ON
HCB4532KF-800T90_1812
1 2 B+

1
D D

10U_1206_25V6M

10U_1206_25V6M
1 1

220U_25V_M

220U_25V_M

3300P_0402_50V7K
680P_0603_50V8J
1

1
+ +

PC97

PC95

PC102

PC103
PR110 0_0402_5%

0.022U_0402_16V7K
1

1
PC101

PC98

PC99
9,22 PM_DPRSLPVR 1 2 PC100

2.2U_0603_6.3V6K
PC96
0.01U_0402_25V7K

2
PR109 0_0402_5% 2 2

2
PR113

PR114

PR120

PR115

PR116

PR117

PR118
PR112
6,9,21 H_DPRSTP# 1 2 @

PQ30
PR111 0_0402_5%

SI7686DP-T1-E3_SO8
CLK_ENABLE# 1 2

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PR119 0_0402_5%
+3VS 1 2 4
+3VS PL10

1U_0603_6.3V6M

2
2
2.2_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%

1.91K_0402_1%

1
PC104
PR122 PC105

3
2
1
1

BOOT_CPU1 1 2 1 2 1 4 +CPU_CORE
2

PR121

PR123

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
2

1
@ PQ31 PQ32

3.65K_0805_1%
2 3

1
10K_0402_1%
499_0402_1% PR124

49

48

47

46

45

44

43

42

41

40

39

38

37

PR125

PR127
4.7_1206_5% PR128
2

1_0402_5%

GND

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1

1 2
1 36

2
9,22,30 VGATE PGOOD BOOT1 PC106 PR129 @ 0_0603_5%
4 4
6 H_PSI# 2 35 UGATE_CPU1 680P_0603_50V8J VSUM 1 2
PSI# UGATE1 PC107

2
PGD_IN 1 2 3 34 PHASE_CPU1 1 2
PMON PHASE1
VCC_PRM

3
2
1

3
2
1
1 2PR130 @ 0_0402_5% 4 33 ISEN1
C PR126 147K_0402_1% RBIAS PGND1 0.22U_0603_10V7K C
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
PR131 @ 4.22K_0402_1% PH3 VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M
5

1
1 2 1 2 6 NTC PVCC 31

PC108

PC109
PQ33
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 SI7686DP-T1-E3_SO8

2
SOFT LGATE2
1 2
@ 0.015U_0402_16V7K PC110 8 29
0.022U_0603_25V7K PC111 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PL11
PR132 13K_0402_1% 10 27 UGATE_CPU2 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR133
1 2

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5

1
DROOP

1000P_0402_50V7K PC113 12 25 2.2_0603_1% PC112 @ PQ34 PQ35 2 3


FB2 NC

5
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR135 6.81K_0402_1% 0.22U_0603_10V7K PR134


GND

VDD
RTN

DFB

VIN

4.7_1206_5%
VO

1 2

3.65K_0805_1%
1 2 PU10
13

14

15

16

17

18

19

20

21

22

23

24

1 2

1
PR136

10K_0402_1%

1
PR138
PC114 1000P_0402_50V7K 4 4
ISEN1 PC115 PR142
ISEN2 680P_0603_50V8J 1_0402_5%

2
2

PR139 97.6K_0402_1% PC116 470P_0402_50V7K 1 2 +5VS

2
1

1 2 2 1 PR140

3
2
1

3
2
1

2
1

@ 0_0402_5% PR137 1_0603_5% PR143 @ 0_0603_5%


PR141 PC118 VSUM 1 2
1 2 1U_0402_6.3V6K
1

1K_0402_5% PC120
2

PC117 220P_0402_50V7K 1 2
B PR145 B
255_0402_1% PC119 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 +CPU_B+ 0.22U_0603_10V7K
VCC_PRM
1

PR144 1 2 PC121 ISEN2


0.1U_0603_25V7K
PR146 1K_0402_1%
2

PC122 0.018U_0603_50V7J
7 VCCSENSE 1 2 1 2
VSUM
1

PR147 0_0402_5%
1

PC123 PC124
2.61K_0402_1%

0.018U_0603_50V7J
PR149

+CPU_CORE 1 2 0.018U_0603_50V7J
2

PR148 20_0402_5% 1 2
7 VSSSENSE PR150 0_0402_5%
2
1

11K_0402_1%

PC125 180P_0402_50V8J
PR152

PR151 1 2
2

20_0402_5% 1 2 1 2 PH4
10KB_0603_5%_ERTJ1VR103J
2

PR153 1K_0402_1% PR154 3.9K_0402_1%


PC126 0.1U_0402_16V7K
1

VCC_PRM 1 2

PC128 0.22U_0402_6.3V6K
PC127 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
+CPU_CORE

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 10, 2009 Sheet 40 of 41
5 4 3 2 1
5 4 3 2 1

PIR (Product Improve Record)


NBWAA LA-5821P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 1.0

NO DATE PAGE MODIFICATION LIST PURPOSE


---------------------------------------------------------------------------------------------------------------------------------------------------
1. 08/06 18 Add R936 on BKOFF#; R937 on INVT_PWM To prevent EC pin damage
2. 08/06 26 Add RL90, RL91, RL91 on +3V_LAN For EMI's request
3. 08/06 18 Add C922, C923, C924 220pF on DAC_BRIG, INVT_PWM_R, BKOFF#_R For EMI's request
D 4. 08/06 31 Delete R752, C787 on SPI_CLK; Add L912, C925 on SPI_CLK_L For EMI's request D

5. 08/06 28 Add LA11 on INT_MIC_L For EMI's request


6. 08/06 28 Mount D61, DA3, DA6, DA7 For ESD's request
7. 08/06 32 Un-mount SW5, SW6 Power button, no need after pre-MP

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/07/28 Deciphered Date 2010/07/28 Title
ISPD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBWAA LA5821P M/B
Date: Monday, August 10, 2009 Sheet 41 of 41
5 4 3 2 1

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