Name:SHUBHAM CHUTKE

ROLLNO.:
03
CLASS:
CMPN2
BATCH:C-
3
SUBJECT:
MICROPROCESSOR

Exper
iment10
Ai
m:Tost
udysuperSPARCar
chi
tect
ure.

Obj
ect
ive:
Student
scanl
ear
nabout
basi
car
chi
tect
ureof
SPARCar
chi
tect
ure.

Theor
y:

TheSuper SPARCmi cropr ocessor

,whi chi sahi ghl
yintegrated
superscal
ar SPARCmi croprocessorfullycompat i
blewitht heSPARC
versi
on8ar chit
ecture.Abl ockdiagram oft hedev i
ceisshown.The
processorcontainsani ntegerunit
,doubl epr ecisi
onfloatingpointunit
,
ful
lyconsistentinst
ructionanddat acaches, aSPARCr eferenceMMU
(Memor yManagementUni t
),andadual modebusi nt
erfacesuppor ti
ng
eit
hertheSPARCst andar dMBUS, orani nterfaceopti
mi zedf or
connecti
ont oacompani onsecondl evel cachecont r
ollerchip.More
detai
lonthesef unctionswi l
lbeprovidedi nthef ol
lowingsubsections.

Super
SPARCBl
ockDi
agr
am

1.
1Sy
stemI
nter
connect

Super SPARChasbeendesi gnedtobeeasilyi

ntegr
atedintosystemsat
av ari
etyofcostandperfor
mancel ev
els.I
nparti
cul
ar,t
hedual bus
i
nterfaceallowsfor
systemstobedesi gnedei
therwit
horwi thoutan
externalcache.
Processormodules,ar
econstr
uctedoft
heSuper
SPARCpr ocessor,
andopt
io
nally
an
exter
nalcachebuil
tfr
om sy
nchr
onousst
ati
cRAM andt
heSuper
SPARC
cachecontr
oll
erchi
p.

Inbot hconf i
gurati
ons, thedev icesmai ntai
nfullcacheconsi stency,
allowingmul t
iprocessi
ngsy stemst obeconst ructedwi thoutany
additional component sorsuppor t.Thesemodul econf igurati
onsar e
i
llustratedi nFigure4.I nt heext ernal cacheconfi
gur at
ion, t
hemodul e
cont ainsal ocal cl
ockosci ll
ator .Thecachecont roll
erchi pincl
udesa
clocksy nchronizer,al
lowi ngt hepr ocessormodul etorunatacl ockrat
e
i
ndependentf rom thesy st em bus.Thi sall
ows
forfl
ex iblesystemupgradesasf aster processor
modul esbecomeav ail
abl e.

Pr
ocessor
Modul
eConf
igur
ati
ons

Whenr
unni
ngi
ndi
rectMbusmode,
whi
chi
sanopenl
yav
ail
abl
e64-
bi
tmul
ti
plexed,
cacheconsi
stentbusspeci
fi
cat
ion,
thepr
ocessor
r
unssy
nchr
onousl
ywi
tht
hesy
stembusf
orsi
mpl
i
cit
y.Sel
ect
ionof
thepr
ope
r
busmodef
ort
heCPUi
saccompl
i
shedbyasi
gnal
pinont
heCPU.An
i
dent
ical
CPUchi
pcanbeusedf
orbot
hconf
igur
ati
ons.
1.
2Int
eger
Uni
tCapabi
li
ti
es

The i
ntegeruni
tdy
nami
cal
l
y sel
ect
sa“
group”ofup t
othr
ee
i
nst
ruct
ionst
oissuei
neachcy
cle.Thi
sisaccompl
i
shedbygr
oupi
ng
l
ogi
c, whi
ch
scanst
henext
avai
l
abl
einst
ruct
ions,
andsel
ect
fromzer
otot
hreef
orexec
ut
ion.

Oncet
hissel
ect
ionhasbeenmade,
theunsel
ect
edi
nst
ruct
ionsf
rom
ei
thert
hesequent
ial
ort
argeti
nst
ruct
ionqueuear
ereci
rcul
atedback
i
ntot
hesequent
ial
i
nst
ruct
ionqueue.Thi
sisi
l
lust
rat
edi
nFi
gur
e
5.
Ther
ear
eat
otal
23r
ulest
hat
thei
ntegeruni
thar
dwar
e
checkst
odet
ermi
nei
nst
ruct
iongr
oupi
ng.
Theser
ules,
andt
hehar
dwar
ethat
they
suppor
thav
ebeendesi
gnedt
oexecu
t
eexi
sti
ngSPARCcodeef
fect
ivel
y.

I
nst
ruct
ionQueue/
Groupi
ng
Theexecut
ionuni
tor
gani
zat
ional
l
owsf
ormost
combi
nat
ionsof
indep
endent
,aswel
lasdependenti
ntegeroper
ati
onst
obecompl
etedi
n
asi
ngl
ecy
cle.Theabi
l
ityt
o execut
edependenti
ntegeroper
ati
ons
r
educes t
hebur
denont
he compi
l
er
t
oschedul
eint
eger
dependenci
es,
andwor
kswel
l
wit
h exi
sti
ng bi
nar
y
codes t
hathav
e been schedul
ed f
orsi
ngl
einst
ruct
ion per
cycl
e
machi
nes.Onl
yasi
ngl
eshi
ft
eri
spr
ovi
ded,whi
chi
spar
tofoneof
t
he“
fi
rstst
age”ALU’
s.Machi
nes.Onl
yasi
ngl
eshi
ft
eri
spr
ovi
ded,
whi
chi
spar
tof
oneof
the“
fi
rst
stage”ALU’
s.
 I
nteger
Uni
tOr
gani
zat
ion

Memor
yref
erence addr
ess cal
cul
ati
ons ar
e per
for
med usi
ng a
dedi
cat
ed set
of
regi
ster
fi
lepor
ts,
andadedi
cat
edv
irt
ual
addr
essadder
.Thi
svi
rt
ual
addr
e
ssi
sthenusedbyt
hecacheandMMUt
oaccessl
oad/
stor
edat
a.As
l
ongast
hememor
yref
erence“
hit
s”i
ntheon-
chi
pdat
acache,
allf
orms
ofl
oad and st
orei
nst
ruct
ionscompl
etei
nasi
ngl
ecy
cle.
Thi
sincl
udes64-
bi
tl
oad-
doubl
einst
ruct
ionsaswel
lasal
lsi
gnedandunsi
gnedpar
ti
al
wor
d l
oads. Ther
e i
s no“
load-
use”
int
erl
ockpenal
tyi
nthepr
ocessor
.By
comput
ingmemor
yref
erence
addr
essesear
lyi
nthe pi
pel
i
ne,t
he need f
ora l
oad-
use i
nter
lock
i
sel
i
minat
ed.

Thef
etchst
agei
susedt
oreadi
nst
ruct
ionsf
rom t
hei
nst
ruct
ioncache,
t
hreephases of decode ar
e used as f
oll
ows:Dec0 det
ermi
nes
i
nst
ruct
iongr
oupi
ng,
Dec1checksi
nter
groupi
nst
ruct
iondependenci
es,
al
l
ocat
es ALU and r
egi
ster
fi
le por
ts,and r
eads addr
ess r
egi
ster
oper
ands f
rom t
he r
egi
sterf
il
e.Ex0 i
sthe“
fi
rst
”st
age ofi
nteger
execut
ion,whi
chaccount
sfort
hef
ir
stl
evelofALU’
s.
TheEx1st
agei
s
f
or “
cascaded” ALU oper
ati
ons i
n t
he second l
evel
ALU.
Cacheaccessesar
e per
for
meddur
ing bot
hEx0
andEx1st
ages.
TheWBst
age

updat
est
hei
nteger
regi
ster
fi
lewi
tht
hepr
oper
resul
ts.

Basi
cInt
eger
Pipel
ine

Br
anches ar
eresol
ved “
lat
e”i
nthe pi
pel
i
ne.When a br
anch i
s
encount
ered
by
thedecodel
ogi
c,
afet
cht
othebr
ancht
arget
addr
essi
sissuedt
othei
nst
ru
ct
ioncache.
Thei
nst
ruct
ioncachehasal
ready
progr
essedonei
nst
ruct
iongr
oupf
art
her
alongt
hesequent
ial
i
nst
ruct
ionpat
h,andt
hesequent
ial
i
nst
ruct
ion queue wi
l
l cont
ain any pr
evi
ousl
y uni
ssued
i
nst
ruct
ionsaswel
l
asnewi
nst
ruct
ionsar
ri
vi
ngf
romt
hisl
ast
sequent
ial
fet
c
h.
Thei
nst
ruct
ionsr
etr
iev
edbyt
het
argetf
etchwi
l
lbepl
acedi
nthe
t
argetqueue.
Inst
ruct
ionssequent
ial
l
yfol
l
owi
ngt
hebr
anchi
nst
ruct
ion
wi
l
lcont
inue t
opr
oceed t
hrough t
he pi
pel
i
ne unt
ilt
he br
anch i
s
r
esol
ved.Thesei
nst
ruct
ionsar
eissuedspecul
ati
vel
y,
andwi
l
lbeannul
l
ed
i
fthebr
anchi
staken.
1.3FloatingPoi ntUni
tCapabi liti
es
TheSuper SPARCFPUi scapabl eofexecut ingt hecompl et
esetsi ngle
anddoublepr ecisionfl
oatingpoint operati
onsdef i
nedby theSPARCv 8instru
cti
onset.Singleanddoubl eprecisionaddsandmul tipl
iestakeexactl
ythesa
menumberofcy cl
estocompl etebecauseoft hefactt hattheFPUhas
beenoptimi zedf ordoubl epr ecisionoper ations.Compl exoper ati
ons,
suchasdi v i
deandsquar eroottakeasmal l
numberof additi
onalcy
cles.
Oneuni quef eat ureofthef loating-pointunitist hatdependentf loati
ng-
point
instructionsmaybei ssuedi nthesamei nstructi
ongr oupast he
dependent fl
oat i
ng-pointoperation. As an exampl e, t he following
i
nstructi
onscani ssueinasinglecl ockcycl
e:
 LDD [
%i0+%i
1],
%f2
FMULD %f
2,%f
4,%f
6

Outcome:TheScal abl
ePr ocessorARChit
ecture(SPARC)all
owsf
or
highper
formanceprocessorandsy st
em i
mpl ementati
onsata
vari
etyofpr
ice/
performancet echnol
ogypoints.Thuswehave
successful
lyst
udiedSPARCar chit
ect
ure.