Lesson Summery Week 7 – VHDL Files

Use of Integers

Example 7.1 Write a VHDL file for all odd numbers from 0 to7 inclusive, use
integer as your type.

The Boolean equation is: y= Á B́ C+ Á BC + A B́ C+ ABC or

y ( A , B , C ) =Σm ( 1 , 3 ,5 , 7 )

That is, the function y has three variables (A, B, C) or inputs. The Sum Of Product
minterms are 1, 3, 5 and 7.

entity comblogic_int is
port( a :in integer range 0 to 7;
y :out bit);
end comblogic_int;

architecture int of comblogic_int is

begin
with a select
y <= '1' when 1,
'1' when 3,
'1' when 5,
'1' when 7,
'0' when others;
end int;

Notes:
1. No quotes are used with integers.
2. Integer can be mixed with other types, in this example – bit.
3. Integer must include range.

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Decoder

A decoder is a device which has a coded input (A0, A1) and a unique output (Q0,
Q1, Q2, Q3). The diagram shows a 2 to 4 decoder, that is, it has two inputs and (22
= 4) four outputs. This decoder also has an enable active low input.

4555
1/2
A1 Q3
A0 Q2
Q1
E Q0

Truth table
E A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

Assuming that the enable is low, when the code is 00 the output Y0 is high and all
other outputs are low. This is so because the device has active high outputs.

VHDL Files

--VHDL Concurrent file for a 2 to 4 decoder

entity decoder_2to4cc is
port(a, b :in bit;
y0, y1, y2, y3 :out bit);
end decoder_2to4cc;

architecture arc of decoder_2to4cc is

begin
y0 <= (not a) and (not b); --b is the LSB
y1 <= (not a) and ( b);
y2 <= ( a) and (not b);
y3 <= ( a) and ( b);
end arc;

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--Write a Selected Signal VHDL file for a 2 to 4 decoder with
--active high outputs.

entity decoder_2to4 is
port(a :in bit_vector(1 downto 0);
y :out bit_vector(3 downto 0));
end decoder_2to4;

architecture adec of decoder_2to4 is

begin
with a select
y <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"0000" when others;
end adec;

Simulation file for the 2 to 4 decoder

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 Topic Summary
item topic page
35 VHDL Files – using integers 70
36 Decoder file - Concurrent 71
37 Decoder file – Selected Signal 72
Simulation file for the 2 to 4 Decoder 72

Questions 73 - 74

Questions

1. Write a concurrent VHDL file for a 3 to 8 decoder with active high enable. Use
std_logic as your type.

2. Write a selected signal VHDL files for a 3 to 8 decoder with active low enable. Use
bit as your type.

3. For each of the following, find the minimum sum of product expressions.

a) y ( A , B , C ) =Σm ( 1 , 2, 3 , 6 , 7 )\
b) f ( A , B ,C , D )=Σm ( 0 ,2 , 5 ,7 ,8 , 10 , 12, 13 )

4. For each of the following, find the minimum product of sum expressions.

c) y ( A , B , C ) =ΠM ( 0 , 4 , 5 )
d) f ( A , B ,C , D )=ΠM ( 1 ,3 , 4 ,6 ,9 , 11, 14 , 15 )

5. For the function y, simplify the following in sum of product form.

a.
Ć D́ Ć D CD C D́
Á B́
Á B 1 1 1 1
AB 1
A B́ 1 1

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b.
Ć D́ Ć D CD C D́
Á B́ 1
Á B 1 1
AB 1 1 1
A B́ 1

c.
Ć D́ Ć D CD C D́
Á B́ x x
Á B 1 x
AB 1 1
A B́ x x 1 1

6. For the following K-map with function f, find the minimum product of sum expression.

Ć D́ Ć D CD C D́
Á B́ x 1
Á B 1 1 x
AB x x
A B́ 1 x

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