Injection Locking

EECS 242 Lecture 26

Prof. Ali M. Niknejad
 Outline

• Injection Locking
- Adler’s Equation (locking range)
- Extension to large signals
• Examples:
- GSM CMOS PA
- Low Power Transmitter
- Dual Mode Oscillators
- Clock distribution
• Quadrature Locked Oscillators
• Injection locked dividers

Ali M. Niknejad University of California, Berkeley Slide: 2

 Injection Locking

http://www.youtube.com/watch?v=IBgq-_NJCl0

• Injection locking is also known as frequency entrainment or

synchronization
• Many natural examples including
- pendulum
over time
clocks on the same wall observed to synchronize

- fireflies put on a good light show

• Injection locking can be deliberate or unwanted
Ali M. Niknejad University of California, Berkeley Slide: 3
 Injection Locking Video Demonstration

http://www.youtube.com/watch?v=W1TMZASCR-I

• Several metronomes (similar to pendulums) are initially excited

in random phases. The oscillation frequencies are presumably
very close but vary slightly due to manufacturing imperfections
• When placed on a rigid surface, the metronomes oscillate
independently.
• When placed on flexible table with “springs” (coke cans), they
couple to one another and injection lock.

Ali M. Niknejad University of California, Berkeley Slide: 4

 A Study of Injection Locking and Pulling
Unwanted Injection Pulling/Locking
in Oscillators
Behzad Razavi, Fellow, IEEE

• One of the difficulties in designing a

Abstract—Injection locking characteristics of oscillators are de-

fully integrated transceiver is

rived and a graphical analysis is presented that describes injection
pulling in time and frequency domains. An identity obtained from
exactly due to pulling / pushing
phase and envelope equations is used to express the requisite os-
cillator nonlinearity and interpret phase noise reduction. The be-

• enough,
havior of phase-locked oscillators under injection pulling is also
If the injection signal is strong
formulated.

it
Index will lock
Terms—Adler’s the
equation,source.
injection locking, injection
pulling, oscillator nonlinearity, oscillator pulling, quadrature
Otherwise
oscillators.it will “pull” the source

and produce unwanted modulation

• In the I
NJECTION of a periodic signal into an oscillator leads
first example,
to interesting locking orthe pullingtransmitter
phenomena. Studied by
Adler [1], Kurokawa [2], and others [3]–[5], these effects have
is locked
found to a XTAL
increasingly whereas
greater importance for theythe
manifest them-
receiverselvesisin locked
many of today’sto the
transceivers data clock.
and frequency synthesis

Unwantedtechniques.
coupling
This paper describes new(package,
insights into injection locking and
substrate,
pulling Vdd/Gnd) can
and formulates the behavior cause
of phase-locked oscillators

pulling.illustrates pulling in both time and frequency domains while

under injection. A graphical interpretation of Adler’s equation

• A PA isanexpresses
aidentity derived from the phase and envelope equations
classic source
the required
in a direct-conversion
range.
of trouble
oscillator nonlinearity
transmitter
across the lock

Section II of the paper places this work in context and Fig. 1.

Source: [Razavi]
Oscillator pulling in (a) broadband transceiver and (b) RF transceiver.

Section III deals with injection locking. Sections IV and V

respectively consider injection pulling and the required oscil- Injection locking becomes useful in a number of applica-
lator nonlinearity. Section VI quantifies the effect of pulling tions, including frequency division [8], [9], quadrature genera-
on phase-locked loops (PLLs) and Section VII summarizes the tion [10], [11], and oscillators with finer phase separations [12].
experimental results. Injection pulling, on the other hand, typically proves undesir-
able. For example, in the broadband transceiver of Fig. 1(a),
Ali M. Niknejad University of California, Berkeley the transmit voltage-controlled oscillator, , is lockedSlide:
to 5
I. GENERAL CONSIDERATIONS
 */0&1)2(/$3(142/5 Injection Locking is Non-Linear
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• For weak injection, you get a response at both side-bands

• As the injection is increased, it begins to “pull” the oscillator
• Eventually, for large enough injection, the oscillation locks to the
injection signal
Ali M. Niknejad University of California, Berkeley Slide: 6
 Injection Locking in LC Tanks
1416 IE

• Consider (a) a free-running

oscillator consisting of an ideal
positive feedback amplifier and
an LC tank.
• Now suppose (b) we insert a
phase shift in the loop. We
know this will cause the
oscillation frequency to (c)
shift since the loop gain has to
have exactly 2π phase shift
(or multiples)
Gm ZT (ω0 ) = gm R = 1

Gm ejφ0 ZT (ω1 ) = 1 Fig

Gm ejφ0 |ZT (ω1 )|e−jφ0 = 1

Fig. 2. (a) Conceptual oscillator. (b)Source:
Frequency[Razavi]
shift due to additional phase wh
shift. (c) Open-loop characteristics. (d) Frequency shift by injection.
∠ZT (ω1 ) = −φ0
shift), and the ideal inverting buffer follows the tank to create a
total phase shift of 360 around the feedback loop. What hap- if
Ali M. Niknejad pens if Berkeley
University of California, an additional phase shift is inserted in the loop, e.g.,Slide:
as 7
 Injection Locking in LC Tanks [cont]
• Achange
phase shift in the tank will cause the oscillation frequency to
in order to compensate for the phase shift through the
tank impedance.
• The oscillation frequency is no longer at the resonant
frequency of the tank. Note that the oscillation amplitude
must also change since the loop gain is now different (tank
impedance is lower)
• Maximum phase shift that the tank can provide is ± 90°
• In a high Q tank, the frequency shift is relatively small since
1.5

ω0 dφ
Q= 0.5

2 dω
0

ω0 ∆φ
∆ω ≈ -0.5

2 Q
-1

-1.5
8 8 8 9 9 9 9 9
9.25 · 10 9.5 · 10 9.75 · 10 1 · 10 1.025 · 10 1.05 · 10 1.075 · 10 1.1 · 10

Ali M. Niknejad University of California, Berkeley Slide: 8

 Phase Shift for Injected Signal

• It’s interesting to observe that if a signal is

injected into the circuit, then the tank current is
a sum of the injected and transistor current.
• Assume the oscillator “locks” onto the injected
current and oscillates at the same frequency.
• Since the locking signal is not in general at the
resonant center frequency, the tank introduces
Fig

a phase shift Source: [Razavi]

Fig. 2. (a) Conceptual oscillator. (b) Frequency shift due to additional phase

•
wh
In order for the oscillator loop gain to be equal
shift. (c) Open-loop characteristics. (d) Frequency shift by injection.

to unity with zero phase shift, the sum of the

current of the transistor and the
shift), andinjected
the ideal inverting buffer follows the tank to create a
total phase shift of 360 around the feedback loop. What hap-
currents must have the proper phase shift to
pens if an additional phase shift is inserted in the loop, e.g., as
if
compensate for the tank phasedepicted shift.
in Fig. 2(b)? The circuit can no longer oscillate at
• We see that the oscillator current,
current, and injected currentby all. Thus,
have
tank
because the total phase shift at this frequency deviates from 360
as different
illustrated in Fig. 2(c), the oscillation frequency De
must change to a new value such that the tank contributes
phases enough phase shift to cancel the effect of . Note that, if the
be
en
buffer and contribute no phase shift, then the drain current m
of must remain in phase with under all condi- re
tions.
Ali M. Niknejad University of California, Berkeley Slide: 9tan
Now suppose we attempt to produce by adding a sinu-
 Injection Locked Oscillator Phasors
0 Itank

Vtank = Itank ZT (!1 )
Iosc
Itank Itank = Iosc + Iinj

j 0
Iosc e Iinj


6 Iosc = 6 Vtank = 6 Itank + 0 Iinj

• Note that the frequency of the injection signal determines the

extra phase shift Φ of the tank. This is fixed by the frequency
0
offset.
• The current from the transistor is fed by the tank voltage, which by
definition the tank current times the tank impedance, which
introduces Φ0 between the tank current/voltage.
• The angle between the injected current and the oscillator current
θ must be such that their sum aligns with the tank current.
Ali M. Niknejad University of California, Berkeley Slide: 10
 Injection Geometry
A B
B
sin φ0 = 
Itank
B Itank
cos(π/2 − θ) = sin(θ) =
Iinj
Iosc
Iinj
sin φ0 = sin(θ)
Itank
0
Iinj sin(θ) Iinj sin(θ)
sin φ0 = = !
|Iosc e + Iinj |
jθ
2 + I 2 + 2 cos θI
Iosc inj osc Iinj

Iinj

• The geometry of the problem implies the following constraints

on the injected current amplitude relative to the oscillation
amplitude.
• The maximum value of the rhs occurs at:
!
2 − I2
Iosc
−Iinj inj Iinj
cos θ = sin θ = sin φ0,max =
Iosc Iosc Iosc
Ali M. Niknejad University of California, Berkeley Slide: 11
 Locking Range
• At the edge of the lock range, the injected
current is orthogonal to the tank current.
• The phase angle between the injected current
and the oscillator is 90° + Φ 0,max Itank
• The lock range can be computed by noting that
the tank phase shift is given by
2Q
tan φ0 = (ω0 − ωinj ) Iosc
ω0

2Q Iinj Iinj
tan φ0 = (ω0 − ωinj ) = =!
ω0 Itank 2 − I2
Iosc 0
inj

ω0 Iinj 1
(ω0 − ωinj ) = !
2Q Iosc 2
Iinj
1− 2
Iosc


Maximum Locking Range Iinj

Ali M. Niknejad University of California, Berkeley Slide: 12
 Weak Injection Locking Range
• Adler first derived these results in a celebrate paper [Adler]
under the conditions of a weak injection signal.
• The results for a large injection signal were first derived by
[Paciorek] and then re-derived (as shown here) by [Razavi]
• Under weak injection: I ! I inj osc

Iinj
sin φ0 ≈ sin(θ)
Iosc
Iinj 2Q
sin φ0 = sin(θ) ≈ tan φ0 = (ω0 − ωinj )
Itank ω0

2Q Itank
sin(θ) = (ω0 − ωinj )
ω0 Iinj
• At the edge of the locking range, the angle reaches 90°, and the
injected signal is occurring at the peaks of the output, which
cannot produce locking (think back to the Hajimiri phase noise
model)
ω0 Iinj
(ω0 − ωinj ) =
2Q Itank
Ali M. Niknejad University of California, Berkeley Slide: 13
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
Injection Pulling Dynamics
, and

(15)
Source: [Razavi]
ains phase modula- Fig. 6. LC oscillator under injection.
•
phase shift can Suppose
be now that the oscillator is under injection
oscillator signal feeding the tank can be written as
so that
antaneous input fre- Equating this result to , we obtain
VX = Vinj,p cos ωinj t + Vosc,p cos(ωinj t + θ)

VX = (Vinj,p + Vosc,p cos θ) cos ωinj t − Vosc,p sin θ sin ωinj t (23)
(16)

• This We
slowly-varying ),
canalso
benote
written
from as athat
(19) cosine with a phase shift
ection phenomena. V = Vinj,p + Vosc,p cos θ cos(ω t + ψ) Vosc,p sin θ
X inj tan ψ =
cos ψ Vinj,p + Vosc,p cos θ
• Which allows us to write! the output as
m shown in Fig. 6, " ! (24) #$#
Vinj,p + Vosc,p cos θ −1 2Q dψ
e input. The output
Vout = cos ωinj t + ψ + tan ω0 − ωinj −
having a carrier fre- cos ψ ω0 dt
words, the output is (25)
sibly time-varying)
Ali M. Niknejad University of California, Berkeley Slide: 14
 Injection Pulling Dynamics [cont]
• We have assumed that the phase shift through the tank is given
by the simple expression derived earlier where the
instantaneous frequency is dψ
ω+
dt
! "
2Q dψ
tan α ≈ ω0 − ω −
ω0 dt

• Ifto:the injection signal is weak, then the previous result simplifies

! " ! #$#
2Q dψ
Vout = Vosc,p cos ωinj t + ψ + tan −1
ω0 − ωinj −
ω0 dt

• Which must equal to the output voltage, or the phase shifts

must equal
! " #$
2Q dψ
ψ + tan −1
ω0 − ωinj − =θ
ω0 dt

Ali M. Niknejad University of California, Berkeley Slide: 15

 Pulling [cont]

• These equations can be manipulated into a form of Adler’s equation:

dθ ω0 Vinj,p
= ω0 − ωinj − sin θ
dt 2Q Vosc,p

dθ ω0 Vinj,p
= ω0 − ωinj − ωL sin θ ωL !
dt 2Q Vosc,p

• This equation describes the dynamics of the phase change of the

oscillator under injecting pulling. If we set the derivative to zero,
we obtain the injection locking conditions (same as before).
• Notice that maximum value of the rhs is quite small, which means
that the rate of change of phase is
• This equation can be used to study the behavior of locking signals
outside the lock range. Note that this equation agrees with our
graphical analysis:
dθ
=0
dt

Ali M. Niknejad University of California, Berkeley Slide: 16

 Pull-In Process
! " #$
1 ωL cos θ0
θ(t) = 2 tan
−1
− cot θ0 tanh (t − t0 )
sin θ0 2

ω0 − ω1
θ0 = sin −1
ωL

• θand0 isthe
the steady-state phase shift between the injected signal
active device signal and t is an integration constant that
0
depends on the initial phase shift.
• From this equation the lock-in time can be computed (it’s
approximately an exponential process):
! "θ #$
2 −1 1 − sin θ0 tan
L

tL = tanh 2
+ t0
ωL cos θ0 cos θ0

Ali M. Niknejad University of California, Berkeley Slide: 17

 Phase Noise in Injection Locked Systems
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004

input frequency deviates

uction becomes less pro-
either edge of the lock
g the impedance seen by

o rely on the phase noise

g. Since the lock range is
atural frequency of oscil-
ocess variations and poor
he edge of the lock range, Fig. 14. Reduction of phaseSource:
noise due [Razavi]
to injection locking.

•
slightly. For example, if
Under
% and the natural fre- a lock, the phase of the oscillator follows the phase of
% with process and thetem-injection signal. If a “clean” signal is used to lock a VCO,
thenat the phase noise would improve up to the locking range.
njection locking occurs

•
37) and the above obser-
At the edge of the lock, the injected signal cannot correct for
e noise falls from infinity
the phase noise since it injects energy at a 90° phase offset,
degradation in the phase
. where the signal has a peak amplitude

LOCKED OSCILLATORS
with pulling in nominally Fig. 15. PLL under injection pulling.
Ali M. Niknejad University of California, Berkeley Slide: 18
 Fig. 8. Microstrip balun.

964
Example: GSM Class E PA IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO

Fig. 10. Output power and PAE versus frequency for and V.

Fig. 9. Output power, efficiency, and PAE versus supply voltage.

Fig. 5. Illustration of the mode-locking concept.

10 and 5 mil, respectively. A single-ended signal at port 1

can be converted to differential signals at ports 2 and 3 or B. Mode-Locking Technique
Fig. 11. Amplified GMSK modulated signal ( ) and the GSM
vice versa. The edge-coupled microstrip lines and the discrete
tuning capacitors are shown in the enlarged portion of Fig. 8.
Modemask.
spectral emission Source: [Tsai]condition in which an
locking refers to the
self-oscillating circuit is coupled and forced to
of the same
PAE infrequency
this regionasis an dueinput
to thesignal,
progressively morein a
resulting
VI. MEASUREMENT RESULTS prominent input power
reduction in theterminput in driving
the PAE requirement.
definition. At This
2-V is
Fig. A.
4. Power-Amplifier
Schematic of thePrototype
complete power amplifier. supply, the PAE was measured to be 48%.
each stage of the amplifier by a pair of cross-coupl
•
Fig. 10 shows the output power and PAE at two different
Large single-ended
A 10-dBm output stage input device
was converted is hard to drive
to supply voltages(large
devices, as shown
across capacitance).
the in Fig.
range of 5. The twowhere
frequencies input thevolta

•
differential signals, using a commercial balun (Murata amplifier of isphase,
mode as are the
locked two output
successfully. Thisvoltages. The isload
locking range
Useequivalent
LDB20C500A1900),
inductors and the and PAoutput
toapplied
then drive to itself!
load, and the RFThat’s
PA. capacitors
larger power and an oscillator,
at the
measured to beoutput right?
490 MHz,nodes isYes.
centering designed
at about 1.9suchGHz.
that a
• Usefact,injection
was measured
switches. In
switch
size to reduce
1.98 GHz.
the
at the
the
The output
switch locking
output ports.
50- transistors
typical plot of the output power versus
to power
turnincreases
on-resistance
areto Fig.
inject
often
off transmission.
loss. The
9 maximized
shows a
phaseinTo modulation.
, measured at tions, the
input capacitance of
verify
in phaseits potential
to control
mode-locking
circuit
Need
in practical
class-Ethe
is concerned,
“off”
communication
the composite
PAoperation
was tested is
from 49 mW to 1.0 minimum shift keying (GMSK) [21] modulated input signal.
switch.applica-
with
As far a
a Gaussian
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W transistors
monotonicallyis asusually tuned
the supply out by
is swept frominductors.
0.6 to 2 VHowever,
and GMSK and its close relative, Gaussian frequency shift keying
at gigahertz frequencies,
is approximately beyond
proportional to a certain transistor size the
. The maximum (GFSK),thearecurrent
constantoriginally circulating
envelope modulation at each
schemes tuned lo
in which
inductance values
used in this caserequired for tuning
is determined may
by the become
peak drain too
voltage to utilized
smallinformation to assist
is carried switching
in the of the other
phase variation of the half
signal,circu
on chip, which
be realizable.
Ali M. Niknejad In is estimatedthe
addition, to be slightly
large above 5 V capacitance
gate-to-drain makingthe
at 2-VBerkeley
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capacitance
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switching power now be significan
amplification.
Slide: 19
supply, approaching the drain-gate oxide breakdown limit of These modulation schemes are used by popular cellular and
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Ali M. Niknejad %! University of California, Berkeley Slide: 20
%'
 from Consider
the
the locked half the
locked half
mode interconnection
mode
4.8GHz4.8GHz of twoA A/0 tanks as
reference.
reference.
hown
ntional in Fig.single
conventional
single 1. Each
mode mode
VCO tank
VCO isisa also
is also parallel /0ascircuit,
fabricated
fabricated as butFig.1
they
Fig.1 Capacitive-coupledparallel
Capacitive-coupled parallel/0
/0tank
tank
reference to show the power saving advantage of the
re
nce coupled
to show together
the power through
saving a coupling
advantage capacitor 01. By
of the
structure.
ure.
is
Example: Dual Mode VCO
arying the value of coupling capacitor, differentis dynamic
that it
The most important feature for this coupled /0 tank
The most important feature for this coupled /0 tank
that it inherently
inherently hashas
twotwo resonantfrequencies.
resonant frequencies.AAsimple
simple
henomenon
ndex Term – can
Index Term – be observed.
Coupled
Coupled LC tank, dual-mode,
LC tank, dual-mode, calculation yields the following expression for the two
voltage-controlled oscillator, injection locking. calculation yields the following expression for the two
e-controlled oscillator, injection locking. resonant frequencies
resonant frequencies
I. INTRODUCTION 22 " ! 22 % !
" ! 2 % !
$ # 2 $ # 2 Eq. 1
I. INTRODUCTION $/ # / 2
22 3 $3 # 3
22 3 Eq. 1
22 3 22 3
Generation of a low phase noise spectrally pure tone where
Generation
has been a majorof a low phase noise
challenge spectrally pure
for communication tone where
circuits 2
+ 03 03 01 022( 0 2
Eq. 2a
en a majorinchallenge
fabricated for communication
CMOS technology. The lack circuits
of a high Q !+#0)) 0" 0 " 0 % ( && % 40 2 3

ated in resonator
CMOS technology. ! # )) *3 /"1 3 /"2 1 /%2 2/&&1 '% 4 /31/2 Eq. 2a
stable necessitates The high lack
power of consumption
a high Q in
resonator
the form ofnecessitates
a phase-locked highlooppower consumption
frequency in As
synthesizer. * /1 0 3/2 0 3/2 01/1 '0 2 /1/2 Eq. 2b
22 # % % %
m of a phase-locked loop frequency synthesizer. As 0 0 0 0 Eq. 2b
we move to higher frequencies, the problem is exacerbated 2 2 # 3 /%1 3 /%2 1/%2 2/1
due theFig.1
ve totohigher increasing Capacitive-coupled
frequencies, powerthe problem is of
consumption parallel
exacerbated /0 tank
the prescalar 23 / #10301/%2 030/22 % 01/01 2 Eq. 2c
frequency
the increasingdividers powerin the frequency synthesizer.
consumption of the prescalarSince # 0301 the % 0differential Eq. 2c
2 3 shows
Fig.2 302 % 0102 dual-mode /0 tank used
digital
ncy logicmost
dividers
The isinoften employed synthesizer.
theimportant
frequency tofeature
perform forthisSince
task,
thisthecoupledinFig.2 /0 tank
this design.
shows The /0 tank coredual-mode
the differential is simply the /0 differential
tank used
power consumption increases as
logic is often employed to perform this task, thewe operate at a closer
sfraction
that it inherently
of the process . has
. two
Injection resonant
locked frequencies.
dividers A
version
in this simple
of Fig.
design. The 1. /0Thetankcomponents
core is simply valuestheare carefully
differential

• AFrom
consumption increasesT as we operate at a closer calculated and1.selected for desired resonant
alculation yields the following expression version
for the of two
Fig. The components values frequencies.
are carefully /1
consume
require an
less power,
additional
coupled tank has two resonant modes.
but have
n of the process .T. Injection locked dividers
oscillator.
narrow locking range and
and /2 and
calculated areselected
on chipforspiraldesiredinductors.
resonant The center tap
frequencies. /1
esonant
me frequencies
less power, each port of the oscillator, one mode is
but have narrow locking range and connection of the two inductors
and /2 are on chip spiral inductors. The center tapis used as the dc current
While multimode
e an additional oscillator. oscillator have been proposed
path which allows the active circuits presented at current
the two
before [1] [2], in
While multimode oscillator thisdominant.
2 2 " !have been proposed
paper we present a coupled /0 connection
2 2 % ! ports to of the
share
Eq.allows
two
the
inductors
same dc
is
current.
used
By
as
1 the active circuits presented at the two
the dc
terminating each
(a)
$ # $ #
•
oscillator with dual frequency outputs that naturally path which
/
provides a technique 22 In a fully differential version shown to the
[1] [2], in this paper we present a coupled /0
tor with dual frequency outputs
for combining
3 the
3
VCO
that naturally
and a22 3
port with a negative resistance, generated for example by a
ports to share the same dc current. By terminating each
cross-coupled active device, both oscillation modes can be
where
es
useathetechnique
higher mode
right, the impedance variation with frequency
frequency divider in a phase-locked loop. Typically, we port with a negative resistance, generated for example by a
for combining
to drive a mixer the VCO a mode to activated at the same time. This is the basic idea behind the
andlower
and the cross-coupled active device, both oscillation modes can be
ncy divider in
drive the PLL dividers.a
+
is shown.
phase-locked
0 0
loop.
0
Typically,
0 (
2 we
0 2
dual-mode oscillator.
activatedThe at the same /0 time. This iscanthealso
basic idea phase
behindnoise
the

•
e higher mode to drive 3 a mixer 3 and1 the lower mode to coupled
Eq.oscillator.
2a network benefit
! # )) " " % && % 4 2
Can we build an oscillator that sustains both
3
dual-mode
performance. Analytical analysis shows that this higher
he II.
PLL dividers. / / / / / /
DUAL-MODE * 1VCO2WITH2 INJECTION 1 ' LOCK The resonant
coupled /0 network can can also benefit phase noise
modes?
0 DESIGN
0 0 0
1 2 order
performance.
quality factor
network
Analytical
thereby analysis
enhance
improving shows
the equivalent
that this
the phase
tank
higher
noise. An
DUAL-MODE 22 # VCO 3 WITH
% 3 I NJECTION
% 1
% 2 L OCK order Eq.
resonant
intuitive
2b
waynetwork can enhance
of understanding thisthe equivalent
approach tanka
is that
The authors are withDthe /ESIGN / 2 /of2 Electrical
1 Department /1 Engineeringquality “zero” factor thereby
is designed improving
at the vicinity of the phase noise.
the resonant An (b)
frequency,
and Computer Science, University of California at Berkeley,intuitive shown way
in Fig.of understanding
2(b), so that it this
increases
Fig.the
2 roll-off
(a) Differential
approach is that
rate froma dual-mode !" tank (b)
Berkeley,
thors are CA
with 2the3 #Department
94720 0301Email:
USA. % 0of30 2 % 0102Engineering
dengzm@eecs.berkeley.edu
Electrical
Eq. 2c impedance over frequency
Ali M. Niknejad “zero”
the is designed
peak resulting
University of California, at the
in avicinity
Berkeley sharper of the resonant
transition and a frequency,
narrower Slide: 21
omputer Science, University of California at Berkeley,
 Dual Mode VCO (cont)

Source: [Deng]

• Two cross-coupled pairs are used to sustain each mode by

providing sufficient negative resistance. The PMOS side is
running at a lower frequency whereas the NMOS side runs at
the higher frequency.
• Transistors M3a/M3b are used for injection locking.
Ali M. Niknejad University of California, Berkeley Slide: 22
 Dual Mode VCO Spectrum

• Without injection locking, each mode runs independently. The

frequencies are not integrally related, so the unlocked spectrum contains
not only the two modes and harmonics, but also every intermodulation
component.
• When the modes are locked, the intermodulation components
disappear. The high frequency VCO is divided by two in this
configuration.
• More on injection locking dividers to come...
Ali M. Niknejad University of California, Berkeley Slide: 23
 ter 2: Overview of Electrical Clock Distribution 14

Clock Distribution
Chapter 2: Overview of Electrical Clock Distribution 16

PLL

Figure 2.7: A clock grid driven by buffers.

igure 2.6: A buffered H-tree. Source: [Mahony]
2.3.1.3
distribution is completely symmetric to simplify the Local
design and provide nominally

• source of power consumption. Figures of merit include skew,

kew (assuming no Delivering a clock
loading variations). in acommonly
The most large chip
The final isa clock
a major
level topology
used of challenge
distribution
is a buff- andlevel,
network is the local a big
which is the portion o
the network that follows the clock pin. This network drives the final loads of the clock dis
H-tree [7] which is shown in Figure 2.6. H-trees are an extremely popular choice at
jitter, and power. tribution and hence consumes the most power. As a rule of thumb, the power at the loca

•
evel of the clock distribution because they are a simple pattern that efficiently and
A buffered H-tree or a grid are common approaches. The grid
level is about one order of magnitude larger than the power in the global and regional lev

has skew and larger capacitance.

metrically covers large areas. H-trees minimize the els
distance fromwith
combined, thethe
PLL to notable
only the fur-exceptions being clock networks that use a
low-impedance
clock pins (without using diagonal traces) and thereby grid atthe
minimize theinterconnect
regional level [2].

cy. The number of buffer levels within the global network − which
The layout of the local
alsogrid is generally included in the design of the macro block and
determines
is not the responsibility of global and regional clock network designer. Because of its rela
tency − depends on the signal dispersion, loss and on the required power fanout.
tively limited span, it is sufficient to use automatic layout for this portion of the clock
Ali M. Niknejad University of California, Berkeley Slide: 24
 ould be expected based on the delay between points on the clock network. Despite
vantages, however, an analysis of the relationship between skew and interconnect

Clock Distribution: Distributed

ndicates that wire loss will limit the use of standing-waves in an on-chip, global
distribution. This type of clock distribution also requires limiting amplifiers to con-
2.5: Directions in global clock distribution 27
he sinusoidal standing waves to digital levels, which could add additional skew and

2.5: Directions in global clock distribution 2

l << λ VCO and loop filter

Phase detector

Regional
÷N Clock
Distribution

Vc
Clock load PD, LPF & CP
Figure 2.13: Clock distribution using a coupled array of PLLs [44].System Clk (to VCOs)
gure 2.12: Standing-wave clock distribution [41].
Source: [Mahony]
algorithm is used to avoid instability during the phase locking process. There are two main
advantages to this topology. First, the PLLs filter the noise of the global H-tree and VCO
Coupling
Coupled oscillator arrays replace it with the noise of the local VCOs, thereby reducing the jitter that accumulates in wires

• Standing wave oscillators tune out the

the H-tree. The second advantage is that, like in [44], the skew is a function of the error in
he research that has been described to this point generally concentrates on minimiz-
the phase detectors rather than the accumulated skew between branches of the H-tree. This

capacitance of the line and form a resonant

e skew of a global clock distribution. However, based on the scaling analysis in
means that the scaling of this type of distribution does not depend on the latency of the
on 2.4, it appears that jitter may be more difficult to reduce for future high-perfor- Figure 2.15: Clock distribution using a coupled array of VCOs [48].
network.
e microprocessors. Several clock distributions based
H-tree but rather on the scaling of the VCO and phase detector. The presence of the global
on coupled oscillator arrays

•
H-tree also allows for low-frequency testing by bypassing the PLLs. The only drawbacks

A distributed approach locks an array of

been proposed that have the potential to reduce both jitter and skew by eliminating
to this approach are the additional resources necessary for multiple2.5.3.3 Coupled
PLLs and distributed oscillators
the com-

ying a phase-averaging effectVCO’s totheit’s

impactneighbors.
amounts of latency from the clock network. Some also reduce skew and jitter by
plexity of synchronization. This approach has not yet been prototyped so no measured
The last type of coupled-oscillator clock distributions uses coupled arrays of distrib
that tends to reduce of uncorrelated static
data is available.

•
uted oscillators. The oscillators are distributed in the sense that the coupling wires are pa

The neighbors can also be injection locked

2.5.3.2 VCO arrays of the oscillators themselves, so their free-running frequency depends to some degree o

to one another to eliminate the phase the geometry of the interconnects. The cooperative ring oscillator (CRO) clock distribu
The global clock distributions described in [47] and [48] are similar to the PLL array
tion described in [49] uses overlapping ring oscillators. The frequency of the oscillato
detectors. designs, except that they use a single control loop with multiple VCOs. The clock distribu-
depends on both the buffer and interconnect delays around the ring. Figure 2.16 shows
tion shown in Figure 2.15 and described in detail here is based on [48], but the same basic
three-phase CRO grid and its electrical equivalent. The oscillators are allowed to run ope
concepts are used in [47]. A control voltage is distributed to all of the VCOs around the
loop, and they phase lock to each other due to mutual coupling between rings, similar
die to set their frequency. A clock signal is fed back from a regional clock tap (driven by a
[47] and [48].

Ali M. Niknejad University of California, Berkeley Slide: of25

A similar approach is proposed in [50], which implements coupled arrays rotar
the line, so they are optimized for maximum gd/cd. The relative sizes ered
of the“keep-out”
PMOS andregions, areas where the signal amplitude is too low to be tapped b
NMOS devices can also be optimized, but a good rule of thumb is tobuffers. Thetovoltage
size them be standing-wave pattern for a portion of the grid is shown in Figu
roughly equal.
Standing Wave Oscillators (SWO) Note that the largest magnitude occurs around the square portion of the grid and t
nodes of the standing-wave are pushed onto the stubs.
4.2.3 Design example

Single SWO (folded)

63µm:0.18 µm
Clkinj
Differential interconnect
Cross-coupled pair
Injection-locked
cross-coupled pair
Clock buffer
63µm:0.18 µm 14µm 14µm
Chapter 5: Standing-Wave Clock Distribution Network
3.5mA
3.5µm 4µm
5.1.1 SWO coupling
Figure 5.3: A resonant clock grid of coupled SWOs.

Figure 4.8: SWO and transmission line cross-section for design example.
This clock grid of coupled oscillators
ccp solves
ccp two
ccpof theccp
fundamental
ccp problem

• The
A SWO is straightforward to design from (4.11) and (4.2). Table 4.1H-trees:
lists the the accumulation of timing uncertainty and sensitivity to buffer delay. A
parame-
negative resistance to sustain
ters that will be used to design a SWO with five equally sized andcussed in spaced
equally Chapter 2, H-trees accumulate timing uncertainty because the clock si
oscillation is distributed along the line. generatedfor
cross-coupled pairs. The transmission-line cross-section (Figure 4.8) is optimized bymin-
a single source and then regenerated by each ccp
buffer along the tree. I

• One
ccpccp ccp ccp
disadvantage is that the amplitude of
imum loss given a total track width of 32µm and a distance of 3.5µm totrast,
the ground
each plane.
SWO in the grid locally generates the clock signal and only uses the
the clock varies along the line.
A unit cross-coupled pair (ccp) is defined to have NMOS and PMOS devices that are Figure 5.1: Two coupled SWOs.

Source: [Mahony]
• SWO’s
18µm wide and 0.18µm long and is optimized for maximum gd/cd with 1.0mA of bias cur-
can be injection locked together
to form larger clock trees.
Multiple SWOs can be coupled together by simply connecting their transmission li
Two coupled SWOs are shown in Figure 5.1. Ideally, the two oscillators are matche
frequency and a transient current between the two oscillators brings them into per
phase lock. If the oscillators are detuned, they will still lock if they are within their mu

Ali M. Niknejad University of California, Berkeley locked,26

locking range. A steady-state coupling current will keep them frequencySlide: altho
 ROUFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN

Quadrature Locked VCOs (QVCO)

270° 0°
90° 180°
180°
0°
Fig. 20. (a) Q
showing the re
across the reso
Source: [Rofoug]
•lators
Two
Fig. 19.VCO’s
shown.
are coupled
Quadrature together
oscillator comprises
If the oscillators
synchronized
using
a pair extra transistors
of cross-coupled
in frequency. are identical, we expect that the
LC oscil-as

amplitude and frequency of oscillation should be identical.

• Becausebalanced
recently, of the phase of the outputs
quadrature
lock in quadrature...
coupling,
areit obtained
can be shown that they
from two
cross-coupled relaxation oscillators [30]. Another oscillator
Ali M. Niknejad consists of two LC biquad
Universityfilters inBerkeley
of California, feedback [31]. Four-stage Slide: 27
UM WIRELESS TRANSCEIVER IN 1- m CMOS—PART I 525
QVCO: Quadrature Lock

Source: [Rofoug]

• Note that the tank “A” (a)

the tank voltage of “B”.
is driven by the tank voltage VA plus (b)

• The
Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and
rightthe
showing tank, though,
resonator is driven
currents; by the
and (b) voltage V phases
relative but voltage
B -V .
of the voltages A

• Assuming that the LC

across the resonators tanks
required forand FETs are
symmetric identical, then the
operation.
phasor currents flowing into the tanks must have equal
pled LC oscil-
magnitude:
|vA + vB | = | − vA + VB |
|1 + ejθ | = |1 − ejθ |
cos θ = 0 → θ = ±90◦
d from two
Ali M. Niknejad University of California, Berkeley Slide: 28
 (a) (b)

QVCO: Lead/Lag Ambiguity

Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and
showing the resonator currents; and (b) the relative phases of the voltages
across the resonators required for symmetric operation.

r of cross-coupled LC oscil-

are obtained from two

30]. Another oscillator
edback [31]. Four-stage
at taps two stages apart
lthough apparently not
ite low phase noise in

ture oscillator. It com- Source: [Rofoug]

d above, labeled A and
ted in parallel with the

• NoteFig.that
Oscillator A is direct-
the tank
21. Magnitude current/voltage
and phase has a 90°
of a realistic resonator’s impedance, show- relation, or the
llator B, and the output ing three possible oscillation frequencies. The oscillator selects the highest
Oscillator A (Fig. phase of the
19). frequency impedance
because the feedback loop is
gain±45°. Three frequencies satisfy this
is largest here.
ctly the same frequency constraint, but f3 has the highest loop gain.
•
y the coupling topology. circuit impedance is
It’s clear that there are two andpossible
its phase is solutions:
plains how, owing only or 45 (Fig. 20). In an LC resonator with series loss in the
phaseinductor,
between “A” and “B”.
either 45 lead or lag in
n quadrature. these phases appear at three different frequencies, ,
• In
ctively, are the steady-
any , real
and oscillator, the
(Fig. 21). However, two
amongoscillators
them only
with reference polarities because at this frequency the impedance is largest, and thus the
symmetric, and it can be shown that there is only one unique
is are
stable,not perfectly

rrent into the tuned load

is solution (where the loop gain
feedback factor in the oscillator is strongest. At
is
into of the resonator’s impedance is 45 , which means that highest and the net phase shift
the phase

around
the differential average must the
lead loopby 90is, as
0°)
is shown in Fig. 20. Note also that the
ET’s. Arguing purely by oscillation frequency is higher than the resonance of the tuned
s Ali
inM.the
Niknejad
two circuits are University of California, Berkeley Slide: 29
 performances of the S-QVCO compared to the P-QVCO.
possible oscillation The
frequencies and , both differing f
measurement results for a prototype of thethe S-QVCO fabricated
natural tank Further, the same LC:
resonance frequency noise also
in a standard 0.35- m CMOS process
YSIS AND DESIGN OF A 1.8-GHz CMOS LC QUADRATURE VCO QVCO Loop Gain
Fig. 6.show an oscillation
Fair phase-noise
frequency of 1.8 GHz, a tuning range of 18%, a phase noise of transconductance
comparison between
which P-QVCO and S-QVCO. , whic
modulates
e P-QVCO, in the presence of different values for .
140 dBc/Hz or less at a 3-MHz offset frequency across the we obtain
• Linear
tuning
ption, there will
range,
for ashown.
model
and an
be noconsumption
current The
ofequivalent
QVCO isphasepossible
doubt that theofS-QVCO
loop gain 25 is easily
mA from
error ofoscillation
the natural
at most 0.25 frequencies
tank resonance
a 2-V power
,
supply. frequency
and , both differing f
LC:
m the P-QVCO.5
computed and the frequency at
which the loop gain is zero is
II. A SIMPLIFIED QVCO MODEL APPENDIX A
the oscillation frequency. To estimate the effect on th
These equations can be simplified noting that
•
duces a linear model for the P-QVCO, where
InNotice that the
this appendix, weoscillation
the transconductance of the negative-resistance
resonance.
is offoscillation frequencies to define
find the possible
appears squared in (17)
in the expres
d for the linearized This
the transconductance QVCO results
circuit in
of the coupling in lower
Fig.
pair 7. The loop gain is easily
ng to this
phase
calculated noise.
as
figure and also in the following, we
onverted baseband signals and LO leakage at 1.75 GHz carrier
Fig. 7. Linear model for a QVCO. Source: [Andreani]
ge and
URE VCO current signals to be fully differential:
56 dB). 1745

wing into the tank is the difference between the These equations can be simplified noting that
two branches of the differential stage. As a As shown in Appendix A, the oscillation frequency re-
possible oscillation frequencies and , both differing
sults from displaced
slightly
LC from the and tank therefore
resonance
isthe
thenatural
loss resistance of one half-tank. and assuming that (17) . Using (20), we can approxim
tank resonance frequency LC:
by anthe offset
inner square , whose magnitude
root in (18) asdepends on . According. This canto (
According to Barkausen’s criteria, thealso circuit oscillates
be explained when
in thelarger
following,
this term is much than intuitive way. Referring
, which can be neglecto
baseband thesignals
condition
and LO leakage at 1.75 GHz is carrier
satisfied; further,
in there
Fig. 7,using
Finally, the lossesare in
two
(19) and tank- are balanced by a current in
the approximation
B).
matters even further, an additional variable is the value of the phase withfor , , which is provided by
valid , we arrive at
or widths, . The results shown in . The tank is now lossless, and the current from acts on
d when both P-QVCO and S-QVCO shared the same value
r, can be largely reduced for the P-QVCO, in which an ideal (18) LC-parallel. This second current, , is thus in quadra-
e decreases by approximately 2 dB in the region, but
andwith
ture assuming that in turn implies
, which . Using
that (20),
andwe can areapproxim
phase
l decibels in the the inner
region. It should be noted that a lower shifted by square . Fig.root in (18)
8 shows phasors of the. According
the as voltage across to (
ows the P-QVCO to achieve
can abehigher maximum oscillation this termand is ofmuch larger than
These equations simplified noting that
d to the S-QVCO, or, when the oscillation frequency and the the tank, the currents entering the, tank.
whichTocanfindbetheneglec
re-
whichusing
Finally, is the same as the
(2). approximation
e Ali
same for both P-QVCO and S-QVCO, the capacitanceUniversity
M. Niknejad in lation between
of California, Berkeley (19)and and , we consider the loop in Fig.Slide: 7 as
30
 both transistors h

Fig. 2. QVCO in the Literature

Schematic view of the quadrature VCO presented in [7].

To see how the

(SSB) upconvers
so that the overal
very difficult to m
into the ratio of th
image band [to b
In the case of the
of 0.1% between
IBR of 70 dB for
and to 49 dB for
Source: [Andreani]
quickly larger wh
• Several
Fig. 3. modifications toquadrature
Schematic view of the
improved performance
the QVCO have inbeen
VCO proposed proposed P-QVCO
this work. for is weak
easy to check that
• In particular, it has been shown that if a weaker coupling isdecreasing . Th
The present
introduced, thepaper
phase analyzes
noise an alternative
improves waycircuit
(the [16] oflocks
cross closer
noise performanc
tocoupling
the tanktworesonance),
differential VCOsbut attothe obtain cost of imperfect
a QVCO, in which quadrature
the error performanc
generation
coupling transistor is placed in series with , rather P-QVCO present
• A than
seriesin parallel
bysideration
connected
[Andreani]
(Fig. quadrature
3). This choice
in the phase
that has better P-QVCO
is motivated
generation
is responsible
noise
by the con-
scheme
performance.
proposed
noise FoM, the h
for a large choosing
contribution to the overall phase noise, and connecting to unity. Slide: 31
Ali M. Niknejad University of California, Berkeley
in series with , in a cascode-like fashion, should greatly
 CK out,I

Static Frequency Dividers CK out,Q

/0102&34536$-0'780)$9:(;<=(<$-(8<)&'>
tD Q
23456738
(
!"#$%&' !"#$%&1
( ) ( ) /0# Fig. 5.22 (a) Typical static divider, (b) its waveform
#-.
) ) /0#
*+, *+,
-.
-. dition. As frequency goes up, the idle time d
-. /0#

VDD
!
• master/slave
!"#$%&%'()*%+,%-".(/$&$'$0-(1.("20"3$-4(560(275"#%'(
This is a simple divider structure uses a
8$9%9:(7(*%4$'5%*;($-(-%475$&%()%%/17"3
topology.
R R D D
Dout
RC

!
• negative
Two <75"#%'(=7.(1%($=>2%=%-5%/($-(&7*$0,'(67.'(
latches are cascaded into a
7""0*/$-4(50('>%%/?>06%*(*%+,$*%=%-5'
feedback loop (the output will M3 M4 D in
therefore toggle). D in M 1 M2

• Since two clock cycles are required to

pass the data from one latch to the CKin M5 M6 CKin
CKin

next, it naturally divides by 2.

!"#"$%&''()) !*+$,-.

(a)
Ali M. Niknejad University of California, Berkeley Slide: 32
 device capacitance of the former can be absorbed as part of the latter. This topology
thus becomes attractive and popular at moderate to high frequencies.
Miller Divider (Regenerative)
! in , 3 ! in
2 2
x (t ) LPF y (t )

! in
2

• The
Fig. 5.25 Regenerative divider.
output signal of the feedback loop is mixed with the input
signal. The output of the (ideal) mixer has the sum and
Let usdifference components.
first examine the division behavior and estimate the operation range. For
•
the circuitOnly
and
the difference
to divide component
properly, the loop gain atis!amplified (due tounity.
in /2 must exceed the LPF)
Redrawing
the divider in gained up. with simple RC filter and input amplitude A, we have
Fig. 5.26(a)
• Ifdegrees,
the loop gain is greater! than one
the system regenerates
"A !
and the loop phase is zero
! !the input.
!
in
!H( j )! ≥ 1, (5.36)
• The output frequency2in steady2 state must therefore satisfy:
where " denotes the conversion gain=
fout of f
the − fout
inmixer. It can be further derived that
# 1 $2
2fout = !infin 2
"
A≥ 1+ 2 ≥ . (5.37)
" 2 !c "
Ali M. Niknejad University of California, Berkeley Slide: 33
 " xy M6
L C R y (t ) 2/ " M5
! in t ! in M3 M
= B cos t ! in4

Miller Divider Circuit Details

2 Vin 2! n
! in
2 Op. Range
A B
190
(a) (b)
VDD
M1 M2 VDD
L1 L2 L L L
C1 Vout Vout
C2 (c)
Y
X
Fig. 5.28 (a) M 6 with bandpass filter; (b) its input sensitivity, (c) typical CMOS
M 5 Regenerative divider M4
M3 M4 M3 M4
realization.
Vin M
M5 M6 5
!I
A B A B inj

M1
It is interesting
M1 to note
M 2that a mixer has two V
input
in M 1ports, that leads
M 2 to two pos-
Vin
sible configurations of Miller dividers. As illustrated in Fig. 5.29, the output could
(c)
(a) (
8 (a) Regenerative divider with bandpass filter; (b) its input sensitivity, (c) typical CMOS
ion. Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injecti
LO Port LO Port

s interesting to note that

V ina mixer has two input ports, that leads
Filter V outto two
be pos-
redrawn as that inFilter
Fig. 5.30(b). V
It out
in fact resembles an i
onfigurations of Miller dividers. As illustrated in Fig. 5.29, the output(which
could will be discussed in the next section): M3 and M4 for
and M5 and M6 appear as diode-connected transistors to lo
RF Port and
RFincrease
Port the locking range. The differential injection in
LO Port lieved to help
LO Port V inenlarge the range of operation to some extent
self-resonance frequency of the circuit if (W /L)3,4 > (W /L)
in Filter V out (a) Filter V out (b)

RF Port
• Use a double-balanced Gilbert cell mixer to realize divider
Fig. 5.29 Regenerative divider with the output fed back to (a) RF port, (b) LO port.
RF Port
V in
5.8 Injection-Locked Dividers
Ali M. Niknejad University of California, Berkeley Slide: 34
 .
terms with freq
Injection Locked Dividers [IL-Div]
Fig. 2. Model for a free-running LC oscillator.
an th-order s
intermodulation
equal to o
which is the co
written as

• An
Fig. 3. Model for an injection-locked oscillator.
injection locked divider is nothing but an injection locked
system where the input frequency is at a harmonic of the free- Using a comp
running frequency
Measurements of the oscillator.
on a single-ended ILFD (SILFD) are compared and applying th
• Model
with the system
simulations.
transferare
function
The as a non-linearity
simulation
H(ω).
results off(e) and a bandpass
a differential ILFD be written as
(DILFD) reported as well.
• Assume that the free-running loop has a stable oscillation
frequency. The system is injection locked to a super-harmonic
II. MODEL FOR INJECTION-LOCKED OSCILLATORS
of the free-running frequency.
• An non-linearity
The LC oscillator in
products thatby
, followed
canthebeloop
falla infrequency
modeled
must as
the passband
a nonlinear
create
of the
selective
block
intermodulation
loop.
block (e.g., an RLC or
tank) , in a positive feedback loop as shown in Fig. 2.
The nonlinear block models all the nonlinearities in the
oscillator, including any amplitude-limiting mechanism. To
Ali M. Niknejad University of California, Berkeley
have a steady-state oscillation, a loop gain of unity should be Slide: 35
 IL-Div Analysis
• Suppose the injection signal is a sinusoidal signal which is
added to the oscillator’s signal (at a sub-harmonic of the
injection). The non-linearity acts on both signals and is filtered
by the RLC circuit:
vi (t) = Vi cos(ωi t + φ) vo (t) = Vo cos(ωo t)
H0
u(t) = f (e(t)) = f (vo (t) + vi (t)) H(ω) =
1 + j2Q ω−ω
ωr
r

• Itharmonics
can be shown that if the output signal contains various
and intermodulation terms which can be written
as:
∞ !
! ∞
u(t) = Km,n cos(mωi t + mφ) cos(nω0 t)
m=0 n=0

• where K m,n is the intermodulation component of f(vi+vo)

Ali M. Niknejad University of California, Berkeley Slide: 36

 IL-Div Fourier Analysis
• To see this, write the signals in the following form:
vi = Vi cos(β)
vo = Vo cos(α)
f (e) = f (vi + vo )

• which means that f is periodic in α and β. For every β define a

periodic function g(α) as follows
g(α) = f (vo + Vi cos(α))
• Note that: g(α + 2π) = g(α)
g(−α) = g(α)

• So that we can write: !

1 2π
∞
! L0 (β) = f (Vo cos(β) + Vi cos(α))dα
g(α) = Lm (β) cos(mα) ! 2π 0
1 2π
m=0 Lm (β) = f (Vo cos(β) + Vi cos(α)) cos(mα)dα
π 0

Ali M. Niknejad University of California, Berkeley Slide: 37

 IL-Div [Fourier Analysis cont.]
• But since L m is a periodic and even function of β we can write:

!
∞
! 1 2π

Lm (β) = Km,n cos(nβ) Km,0 = Lm (β)dβ

2π 0
n=0 ! 2π
1
Km,n = Lm (β) cos(nβ)dβ
π 0
• which results in:
∞ !
! ∞
f (vi + vo ) = Km,n cos(mα) cos(nβ)
m=0 n=0

• Assume that the tank filters out all frequencies except the
ones around ω . That means that only intermodulation terms
o
that fall at ωo are relevant:
|mωi − nω0 | = ω0

Ali M. Niknejad University of California, Berkeley Slide: 38

 IL-Div [Fourier cont]
• Ifintermodulation
the injection signal is an N’th superharmonic, then only the
terms
n = Nm ± 1
• possess a frequency equal to 1/N the incident frequency. This
means that our summation can be written in terms of m as
!∞
1
uω0 (t) = K0,1 cos(ω0 t) + Km,N m±1 cos(ωo t + mφ)
2 m=1
• Using complex notation and applying the oscillation condition,
the output signal can be written as
! ∞
#
H 0 ejωo t
1 "
vo = Vo ejω0 t
= K 0,1 + K m,N m±1 ejmφ
1 + j2Q ωr∆ω 2 m=1
! " # ∞
%
∆ω 1 $
Vo 1 + j2Q = H0 K0,1 + Km,N m±1 ejmφ
ωr 2 m=1
! ∞
#
1 "
Real Part: Vo = H0 K0,1 + Km,N m±1 cos(mφ)
2 m=1
∞
Imag Part: ∆ω H0 !
2Vo Q = Km,N m±1 sin(mφ)
ωr 2 m=1
Ali M. Niknejad University of California, Berkeley Slide: 39
 IL-Div Locking Range
• The two equations can be solved for the unknown oscillation
amplitude and phase for any incident amplitude and incident
frequency, or any offset frequency:
∆ω = (ωi /N ) − ωr

• The second equation can

!
be re-written as:
#
∞
"
H0
∆ω = ∆ωA Km,N m±1 sin(mφ)
2Vi m=1

• where Adler’s locking range has been identified:

ω r Vi
∆ωA =
2Q Vo

• Unlike static dividers, the locking range is limited.

Ali M. Niknejad University of California, Berkeley Slide: 40
 IL Divide by 2 Circuit
• The equations can be solved analytically for a divide by 2 with
cubic non-linearity
( )= 10+ + 2
2
+ 3
3

2Q ∆ω
sin(φ) =
H0 a2 Vi ωr
! ! ! !
! ∆ω ! ! H0 a2 Vi !
| sin(φ)| < 1 → !! !<! !
ωr ! ! 2Q !
! " # $%
4 1 3
Vo = 1 − H0 a1 + a3 Vi2 + a2 Vi cos(φ)
3 a3 H0 2

• Locking range is improved by using a large H0/Q or a larger

injection amplitude. For an LC oscillator, this is equivalent to
using a larger inductor:
H0
= ωL
Q

• Ato high impedance node is a convenient place to inject the signal

limit the injection power.
Ali M. Niknejad University of California, Berkeley Slide: 41
 Fig. 7. Schematic of the single-ended injection-locked frequency divider.

IL-Div Circuit Details

a first-order differential

(23)
to the output phase (23)
ig. 6, it is clear that an
ion as a first-order PLL.
shaped by the low-pass
unction, and the output
he incident signal within
. However, unlike a
of an ILO is a function Fig. 8. Schematic of the differential injection-locked frequency divider.

• The
ger for a larger incident
coupled
injection signal is applied as a current to the tail of a cross-
differential oscillator.
nsfer function is a little ity, the biasing circuitry is not shown in this figure. A Colpitts
• The
e ILO itself. Within
LO is suppressed the
thetransistor
oscillator currents
output
by the signal
injected into (feedback)
of
forms the core M1/M2
the gate of M1. and
are
of the SILFD. a non-linear
The
the injected
Transistors M1 and current
function
incident signal
M2 are used
is
of M3.
of

•
dent power. Outside
n increases by 20 M3
the
dB per
in cascode, mainly to provide more isolation between the input
Interestingly,
and evenTransistor
output.
is moving at twice ω
in the absence
M2 is oftoanbeinjection
sized smaller signal,
than M1
o to reduce the parasitic capacitance
bynode
phase noise region is almost a factor of three
Ali M. Niknejad
at the output node (drain of M2). As a result, a larger
University of California, Berkeley Slide: 42
 little phase synchronization occurs. The lock range in this case is the mixer conversion gain) at direc
thebe
can zero crossings
obtained fromof(6)
theorinput
(8): fall on the peaks of the output, oscillator.
at into
If node
and is equivalent to injection
switch abruptly and theofca
little phase synchronization occurs. The lock range in this case nodeis the is mixer conversion
neglected, then gain) at, and (9) can dir
be
NG IN OSCILLATORS
can be obtained from (6) or (8):
IL-Div Intuitive Picture
(9)
oscillator. If and
node is neglected, then
1417
switch abruptly and the c
, and (9) can b
(9)
The subtle difference between (6) and (9) plays a critical role in
quadrature oscillators (as explained below). If referred to the input, this range must be doubled:
The
Fig.subtle difference
4 plots betweenphase
the input-output (6) and (9) playsacross
difference a criticaltherole
lockin
quadrature
range. oscillators
In contrast (as explainedinjection
to phase-locking, below). locking to If referred to the input, this range must be doubled
Fig. 4 plots
mandates the input-output
operation away from phase difference
the tank across the lock
resonance.
range. In contrasttotoQuadrature
1) Application phase-locking, injection With
Oscillators: locking theto aid of a
mandates
feedback modeloperation
[13] or aaway frommodel
one-port the tank resonance.
[14], it can be shown Confirmed by simulations, (13) represents the uppe
that1) Application
“antiphase” to Quadrature
(unilateral) coupling Oscillators: With oscillators
of two identical the aid of a
feedback model [13] or a one-port model [14], it can be shown the lock range of injection-locked dividers.
forces them to operate in quadrature. It can also be shown [14] Confirmed by simulations, (13) represents the up
thatthis
that
forces •
“antiphase”
them to
(unilateral)
type ofIntuitively
coupling
operate
coupling
we canItsee
(injection
in quadrature.
of twoshifts
locking)
can
from resonance so that each tank produces a phase shift of
identical
thatbe the
also
the oscillators the lock range of injection-locked dividers.
frequency
shown
injection
[14]
at the tail III. of Ithe MOS
NJECTION PULLING
that this type cross-coupled
of coupling (injectionpair locking)is mixed due to the switching action of M1/
shifts the frequency
from resonance M2. Fig. each
so that 5. (a) Injection-locked
tank produces a phase divider. (b)of
shift Equivalent If the injected signal
circuit. III. frequency
INJECTIONlies out of, but n
PULLING

• For a strong mixing signal, 2/π component

flow into the tank, at
(10)
from the lock range, the oscillator is “pulled.” We
If theby
behavior ofcomputing
thissignal
injected current will
frequency
the
the ω
output lies out
phase of an of,osci
but
thealockfrequency
range exceeds shift
(10) of by
from
low-level
(9) harmonics
lock range, of
theinjection.
3.3%. In other o. In is “pulled.” W
oscillator
particular, aforsignal at
by 2 oneω o will be down-converted intotheω o, phase of an osc
behavior by computing output
where denotes the current
words, injected
a 90 phase oscillator
difference into
between its input and output,
the other and where the tank has high impedance. This signal therefore
low-level injection.
is an
theinjection-locked
current produced by the
oscillator core of
need eachnot A.
operatePhaseat Shift
the Through
edge of thea Tank
. where
Equations
oscillator. Use
(5)
experiences
denotes the current
of (5) therefore a
gives large
injected
the loop
by
required gain
onefrequency
oscillatorand can For
into
shift lock the oscillator.
the other and lock
is the range.
current produced by the core of each A. subsequent
Phase Shift derivations,
Through a we need an express
Tank
as phase shift introduced by a tank in the vicinity of re
2) Application
oscillator. Use of (5) therefore gives the required frequencyFig.
to Dividers: shift 5(a) shows
For subsequent
an injec-
derivations, we need an ,expre
as tion-locked oscillator operating as a phase second-order
stage parallel
[15]. tank
While consisting of , and
(11) a phase shift shift introduced
of by a tank in the vicinity of
(8) previous work has treated the circuit as asecond-order nonlinear function to consisting of , , and
parallel tank
derive the lock range [15], it is possible (11) to adoptshift
a phase a time-variant
of
Ali M.Interestingly, (9) would imply that each oscillator is pushed Slide: 43
Niknejad
view to simplify the analysis. Switching at a rate equal to the
University of California, Berkeley
 Miller Divider / Injection Locked Divider
190 Jri Lee

VDD VDD

L L L L
Vout

M4 M3
M3 M4
M5 M6 M5 M6
!I +I
A B inj inj

M1 M2
Vin M 1 M2 Vin

(a) (b)

Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injection locking.

• The same circuit topology can be seen to be an injection

be redrawn as that in Fig. 5.30(b). It in fact resembles an injection-locked divider
locked divider or a Miller divider.
(which will be discussed in the next section): M3 and M4 form a cross-coupled pair,

• The
and M5 and M6 appear as diode-connected transistors to lower the Q of the tank
devices M5/M6 are not needed in the normal injection
and increase the locking range. The differential injection in such a manner is be-
locked divider, but here they act to lower the Q of the tank,
lieved to help enlarge the range of operation to some extent. It is possible to find a
increasing the lock range.
self-resonance frequency of the circuit if (W /L)3,4 > (W /L)5,6 [22].

• A Miller divider can be designed so that it does not oscillate in

the absence of an inputDividers
5.8 Injection-Locked signal.
The operation speed of dividers can be further boosted up if we simplify the struc-
ture at the circuit level. Since a cross-coupled VCO provides ultimate simplicity in
Ali M. Niknejad generating differential oscillation,
University ofone may think
California, of injecting a periodic signal (ap-
Berkeley Slide: 44
 References
B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J. of Solid-State Circuits, vol. 39, no. 9,
[Razavi] Sept. 2004, pp. 1415-1424.

R. Adler, “A Study Locking Phenomena in Oscillators,” Proc. of the I.R.E. and Waves and Electronics, June 1946, pp.
[Adler]
351-357.

[Paciorek] L. J. Paciorek, “Injection Locking of Oscillators,” Proc. of the IEEE, vol. 53, no. 11, Nov. 1965, pp.1723-1728.

K.-C. Tsai and P. R. Gray, “A 1.9-GHz, 1-W CMOS Class-E Power Amplifier for Wireless Communications,”
[Tsai]
JSSC, vol. 34, July 1999

Y. H. Chee, Ultra Low Power Transmitters for Wireless Sensor Networks, Ph.D. Dissertation, U. C. Berkeley, Spring
[Chee]
2006.

Z. Deng, A.M. Niknejad, “9.6/4.8 GHz dual-mode voltage-controlled oscillator with injection locking,”
[Deng]
Electronics Letters, vol. 42, Nov. 9 2006, pp. 1344-1343.

Frank P. O’Mahony, 10GHZ GLOBAL CLOCK DISTRIBUTION USING COUPLED STANDING-WAVE OSCILLATORS,
[Mahony]
Ph.D. Dissertation, 2003, Stanford University

A. Rofougaran et al, “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1- m CMOS—Part I:

[Rofoug]
Architecture and Transmitter Design,” IEEE J. of Solid-State Circuits, vol. 33, no. 4, April 1998, pp. 515-533.

P. Andreani et al, “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO”, IEEE J. of Solid-State Circuits,
[Andreani]
vol. 37, no. 12, Dec. 2002, pp. 1737-1747.

H. Ratech and T. H. Lee, “Superharmonic Injection-Locked Frequency Dividers,” IEEE J. of Solid-State Circuits,
[Rategh]
vol. 34, no. 6, June 1999, pp. 813-821.

Ali M. Niknejad University of California, Berkeley Slide: 45