project report ELE2213 Digital Circuits

Final project

4-bit synchronous
counter

Student name:

Submitted to: Dr. Ahmed Khodary

Submitted on: 14/4/2021

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project report ELE2213 Digital Circuits

Introduction:
In course of digital circuit we had learned how to design a tool that can count, and
store bits and the numbers of times, this device is based on clock signal, so the
device is asynchronies logic circuit devise. In this report I had designed a 4-Bit
binary counter, this circuit is the most common kind of counters with a single input
clock and multi outputs. The clock pulse is control the output either rising or
decreasing the value bit. Our counter is 4-Bit counter as we said previously which
is (0,1,3,8,6,13,10), and we will have to use a Karnaugh map to detect the equation
of the output pin, the type of flip-flop that we had used is D-flip flop. The program
simulation that we used to build the counter is proteus program.

Objectives:
This project’s main goal is to design a 4-bit synchronous irregular counter with
(0,1,3,8,6,13,10) sequence. Drawing the pin configuration of the IC used. As
well, display the counter output using 7-segment display device.
1- AND gate
2- OR gate
3- Labels Components:
4- Vcc.
5- Ground
6- Clock pulse
7- D-flip-flop
8- 7447N IC.
9- 7-segment display

Procedure:

Design a 4-bit synchronous irregular counter

2 in the following sequence
0,1,3,8,6,13,10
a. Draw the pin configuration of the IC used
b. Display the counter output using 7-segment display device
project report ELE2213 Digital Circuits

Steps of design:
Present State Next State
Step 1: A B
state diagram C D A+ B+ C+ +
D
0 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1 1
3 0 0 1 1 1 0 0 0
8 1 0
0000 0 0 0 1 1 0
0001
6 0 1 1 0 1 1 0 1
13 1 1 0 1 1 0 1 0
10 1 0 1 0 0 0 0 0

1010 0011

1000
1101

0110

Step 2: next-state table:

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project report ELE2213 Digital Circuits

Step 3: flip-flop transition table:

Output Flip-flop
transition inputs
Q(t) Q(t+1 D
)
0 0 0
0 1 1
1 0 0
1 1 1

Q(t +1)=D

Input Equations
DA DB DC DD
0 0 0 0 1
Step 4: Karnaugh maps and logic
1 expression
0 0 for
1 F-F 1inputs:
3 1 0 0 0
8 0 1 1 0
DA-map: 6 1 1 0 1
C D 00 01 11 10 1 1 0 1 0
3
AB 0 0 1 0 1 0 ' 0' ' 0 ' 0 '
D A=
0 AB C D+ A B CD + A BC D
00 0 0 0 1
01
0 1 0 0
11
0 0 0 0
10

DB-map:
C D 00 01 11 10
AB 0 0 0 0
00 D B= AB' C ' D ' + A ' BCD '
0 0 0 1

0 0 0 0

1 0 0 0 01

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project report ELE2213 Digital Circuits

11
10

DC-map:
C D 00 01 11 10
AB 0 1 0 0
00
0 0 0 0 D c= A B' C ' D' + AB C ' D+ A' B' C' D
01 0 1 0 0

1 0 0 0 11

10

DD-map:
C D 00 01 11 10
AB
1 1 0 0
00 D D¿ C ' A ' B '+ A ' BCD
0 0 0 1
0 0 0 0
0 0 0 0 01

11
10

Simulation Program:

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project report ELE2213 Digital Circuits

Fig.1

Fig.2

Discussion & Analysis:

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project report ELE2213 Digital Circuits

At be beginning, we learned how to build a synchronous counter by using the six

steps of synchronous counter design. Firstly, drawing a state diagram for the given
sequence. Secondly, doing a next-state table as present and next. Thirdly make a
flip flop transition table for each Js and Ks. Then create a Karnaugh map with the
help of the flip-flop transition table, it makes the simplifying of the equations much
easier which help us. After that, write the logic expression from the Karnaugh map
and simplified it. Last but not least, perform the counter to produce a specified
sequence of states. After doing these steps I build the counter in proteus software
to determine if the equations are correct and if the counter gives the required
sequence. In the software we had used labels instead of probs. Finally, they turned
out to be giving the same components.

Conclusion:
At the end, this project was so useful and beneficial because we have learned more
knowledge about synchronous counter. Also, in this project we gain the ability to
make counter counts with different states and then reset to its initial states whether
its 4-bit, 3-bit or 2-bit.