Module 1 – 1.

1 1b (The F-D-E Cycle

-A computer follows the F-D-E cycle to accomplish tasks

Fetch Phase :
o The PC is checked for address of next instruction
o Which is then copied into MAR
o Address sent along to address bus to main memory where it waits to receive a signal from the control bus
o Control unit sends signal to read what is at that address to main memory
o Memory reads data at that address and sends it to MDR via data bus
o Memory received from main memory is stored in CIR
o Fetching has now been done so PC contents has now been changed to the address of the next piece of data

Decode Phase :
o Instruction is ready to be decoded by Decode unit
o Instruction is made up of two parts operand and opcode
o Opcode: is What to do
o Operand: What to do it to
o The operand could contain data or an address where the data is found
o By decoding this instruction , we can see that the operation we need is a “load” operation
o We need to load contents of memory location 0101 into the CPU’s accumulator

Execute Phase :
o We now send address 0101 to the MAR
o We send address down the address bus to the main memory
o The control unit sends a read signal along the control bus to the main memory
o So now content stored in memory at address 0101 can now be sent along the data bus to the memory data
register.
o The contents of MDR are now copied to the accumulator
o Instruction is now complete