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Dr. Babasaheb Ambedkar Marathwada University

Aurangabad

A Major-Project Report on

“MULTILEVEL INVERTER WITH

REDUCED SWITCHES”
Submitted in partial fulfillment of requirements for the award of degree of

Bachelor of Technology
in
Electrical Engineering

Submitted by:

Mayuri Sunil Ethape [Roll No: 13]

Kshitija Shivajirao Kalyankar[Roll No: 22]
Saiprasad Gangaram Konda[Roll No: 25]

Under the Guidance of

Mr. B. Raja Guru
Assistant Professor, Dept. of EE,
MIT-T, Aurangabad

DEPARTMENT OF ELECTRICAL ENGINEERING

MAHARASHTRA INSTITUTE OF TECHNOLOGY

AURANGABAD – 431010
2020-21
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MAHARASHTRA INSTITUTE OF TECHNOLOGY

AURANGABAD – 431010
DEPARTMENT OF ELECTRICAL ENGINEERING

Certificate
Certified that the major-project work entitled “Multilevel Inverter With
Reduced Switches” is bonafide work carried out by Mayuri Sunil Ethape, Kshitija
Shivajirao Kalyankar and Saiprasad Gangaram Konda in partial fulfillment of
requirements for award of the Degree of Bachelor of Technology in Electrical
Engineering from Dr. Babasaheb Ambedkar Marathwada University, Aurangabad during
the year 2020-2021. It is certified that all the suggestions indicated for internal assessment
have been incorporated in the report. The Major-project report has been approved as it
satisfies the academic requirements in respect of Major-project work prescribed for the
Bachelor of Technology degree.

Signature of Guide Signature of HOD Signature of Principal

Mr. B. Raja Guru Dr. R.K. Kanhe Dr. S.P. Bhosle
Assistant Professor Associate Professor and Head Principal
Dept. of EE, MIT-T Dept. of EE, MIT-T MIT-T, Aurangabad

Signature of External:

1)

2)

3)
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DECLARATION

We, Mayuri Sunil Ethape, Kshitija Shivajirao Kalyankar and Saiprasad

Gangaram Konda are studying in the seventh semester of Bachelor of Technology in
Electrical Engineering at Maharashtra Institute of Technology, Aurangabad, hereby
declare that this major-project work entitled “Multilevel Inverter With Reduced
Switches” which is being submitted by us in the partial fulfillment for award of the
Degree of Bachelor of Technology in Electrical Engineering from Dr. Babasaheb
Ambedkar Marathwada University, Aurangabad is an authentic record of us carried out
during the academic year 2019-2020, under the guidance of  Mr. B. Raja Guru,
Department of Electrical Engineering, Maharashtra Institute of Technology, Aurangabad.

    We further undertake that the matter embodied in the report has not been
submitted previously for the award of any degree or diploma by us to any other university
or institution.

Place: Aurangabad                                                  Mayuri Sunil Ethape

Date: Kshitija Shivajirao Kalyankar

Saiprasad Gangaram Konda

ACKNOWLEDGEMENT
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The satisfaction that accompanies the successful completion of this project would
be incomplete without the mention of the people who made it possible, without whose
constant guidance and encouragement would have made efforts go in vain. We consider
our privileged to express gratitude and respect towards all those who guided us through
the completion of this project.
We convey thanks to our Major-Project guide Mr. B. Raja Guru of Electrical
Engineering Department for providing encouragement, constant support and guidance
which was of a great help to complete this Major-project successfully.
We grate Dr. R. K. Kanhe, Head of the Department Electrical Engineering for
giving us the support and encouragement that was necessary for the completion of this
Major-project.
    We would also like to express our gratitude to Dr. S. P. Bhosle, Principal,
Maharashtra Institute of Technology, Aurangabad for providing us congenial
environment to work in.

ABSTRACT
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Multilevel inverters are used to convert DC supply into AC supply for the medium
and high voltage and power applications. It generates output voltage with less harmonic
distortion and quality of power is improved. Their performance is highly superior to that
of the conventional inverters due to reduced harmonic distortion. Circuit complexity is
major issue in most of the topologies of multilevel inverter. As the number of level
increases the number of switches increases and the switching method becomes more
complicated. The main objective of the proposed topology is to increase number of levels
in the output voltage with reduced number of switches. This concept helps to reduce the
complexity of switching method and overall cost compared to other multilevel inverters.
The topology we used requires three dc voltage sources and nine switches to get 15 levels
output and four dc voltage sources and ten switches to get 25 levels output. The operation
and performance of the single-phase 15-level multilevel inverter and single-phase 25-
level multilevel inverter is verified by the simulation. Simulation analysis of the inverter
topology is carried out by using MATLAB/SIMULINK software. The results for THD
are validated by using the FFT window.

INDEX
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Chapter. No. Contents Page

No.
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1 Introduction 1
1.1 Introduction 1
1.2 Types of MLI 3
1.2.1 Diode Clamped Multilevel Inverter 3
1.2.2 Flying Capacitor Multilevel Inverter 4
1.2.3 Cascaded H-bridge Multilevel Inverter 4
1.3 Configurations 5
1.3.1 Symmetrical Configuration 5
1.3.2 Asymmetrical Configuration 5
1.4 Necessities 6
1.5 Objective 6
1.6 Theme 6
2 Literature Survey 7
2.1 Literature Survey 7
2.2 Problem Statement 9
3 System Development 10
3.1 Methodology 10
3.1.1 Control Strategy 10
3.1.2 The Switching Technique 10
3.1.2. Pulse Width Modulation (PWM) Technique 11
1
3.1.3 Switching Angles Calculation 12
3.2 Working 13
3.2.1 15 Levels MLI 13
3.2.2 Conduction Mode of 15 Level MLI 15
3.2.2. Positive Circuits 15
1
3.2.2. Negative Circuits 20
2
3.2.3 25 level MLI 21
3.2.4 Conduction Mode of 25 Level MLI 23`
3.2.4. Positive Circuits 23
1
3.2.4. Negative Circuits 30
2
4 Performance Analysis 32
4.1 Simulation 32
4.1.1 Software Requirement 32
4.1.1. Matlab/Simulink 32
1
4.2 Circuit Building 33
4.3 Simulation Circuits 34
4.3.1 Existing Systems 34
4.3.2 Proposed 15 Level MLI Topology 37
4.3.2. Firing Pulse 38
1
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4.3.2. Output Voltage 39

2
4.3.3 Proposed 25 Level MLI Topology 40
4.3.3. Firing Pulse 41
1
4.3.3. Output Voltage 43
2
5 Result And Comparison 44
5.1 FFT Analysis 44
5.1.1 FFT Analysis of 3-Level MLI 44
5.1.2 FFT Analysis of 5-Level MLI 45
5.1.3 FFT Analysis of 11-Level MLI 45
5.2 FFT Analysis of Proposed 15-Level MLI Topology 46
5.3 FFT Analysis of Proposed 25-Level MLI Topology 47
5.4 Comparison of Multilevel Inverters 48
6 Conclusion 49
6.1 Conclusion 49
6.2 Advantages 49
6.3 Applications 50
6.4 Future Scope 50
7 References 51

LIST OF FIGURES

Fig. No. Name of Figure Page No.

1 Classification of DC-AC Converter 3
2 PWM Technique 11
3 Proposed DC to AC Converter 12
4 Different switching states in positive halfcycle 14
5 Different switching states in negative half cycle 17
6 Simulation circuit of 3 Level MLI in Simulink 21
7 Output voltage and THD of 3-level MLI 21
8 Simulation circuit of 5 Level MLI in Simulink 22
9 Output voltage and THD of 5-level MLI 22
10 Simulation circuit of 11 Level MLI in Simulink 23
11 Output voltage and THD of 11-level MLI 23
12 Simulation circuit of 15 Level MLI in Simulink 24
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13 Firing Pulses for S1, S2, S3 24

14 Firing Pulses for S4, S5, S6 25
15 Firing Pulses for S7, S8, S9 25
16 Output voltage of proposed 15-level MLI topology 25
17 FFT analysis and THD of 3-level MLI 26
18 FFT analysis and THD of 5-level MLI 27
19 FFT analysis and THD of 11-level MLI 27
20 FFT analysis and THD of 15-level MLI 28
21 Comparison of different topologies 29
22
23
24
25
26
27
28
29
30
31
32
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LIST OF TABLES

Table. Name of Table Page No.

No.
1 Switching pattern for proposed 15-level MLI 13
2 Switching pattern for proposed 25-level MLI
3 Comparison of different topologies 31
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LIST OF NOTATIONS and ABBREVATIONS

Sr. No. Name of Notation and Abbreviation Page No.

1 MLI- Multilevel Inverter 1
2 THD- Total Harmonic Distortion
3 PWM- Pulse Width Modulation 2
4 NPC- Neutral Point Clamped 4
5 FC- Flying Capacitor 4
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CHAPTER I
INTRODUCTION

This project is about multilevel inverter (MLI). The multilevel inverters are used
to convert the DC power into AC power which is connected to AC loads .This chapter
gives a brief summary about the project.

1.1 Introduction

Multilevel inverters are very popular now days because of lesser harmonic
content, high voltage operation capability, low switching losses and high efficiency. The
word ‘multilevel converter’ refers to the converter itself. Power which flow from the ac
side to the dc side of the multilevel converter operated in rectification mode. Vice-versa,
the power also can flow from the dc side to the ac side of the converter. This mode is
called as inverting mode of operation. The ‘multilevel inverter’ term basically is a
‘multilevel converter’ that uses the inverting mode of operation. Multilevel inverters are
developed for producing desired output at different levels from DC voltage sources. By
increasing the number of dc voltage sources, close to sinusoidal waveform can be
generated. Multilevel inverters have a number of applications such as ups, in power grid,
as solar inverter, induction heating and number of other applications.
Multilevel inverter is an arrangement of power semiconductor switches and
voltage sources. Multilevel inverters are suitable for high-voltage and high-power
applications because of their ability to synthesize output voltage waveforms with a better
harmonic spectrum and attain higher voltages. There are three main types of multilevel
inverters: diode-clamped, capacitor-clamped and cascaded H-bridge inverter. From this,
cascade MLI has more amount of interest in industry because it requires fewer
components with high power quality waveform due to reduction in harmonic distortion
and also the reduction of dv/dt stresses on the load.
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A multilevel converter has several advantages over a conventional two-level converter

that uses high switching frequency pulse width modulation (PWM). The attractive
features of a multilevel converter can be briefly summarized as follows.
 Staircase waveform quality: Multilevel converters not only generate the output
voltages with very low distortion, but also reduce the dv/dt stresses.
 Input current: Multilevel converters can draw input current with low distortion.
 Switching frequency: Multilevel converters can operate at both fundamental
switching frequency and high switching frequency PWM.
As MLI has many advantages it has drawbacks also in higher level voltage because of
using more number of semiconductor switches. This may cause the overall system to be
complex and more expensive. So, to minimize this drawback the new multilevel inverter
topology is proposed with reduced number of semiconductor switches. In the
conventional type of cascaded multilevel inverter for 5 levels 8 switches, 7 levels 12
switches, 9 levels 16 switches and for 15 levels 28 switches are required to generate
output.
In this project, a MLI with reduced switches is proposed. The proposed topology
requires lesser number of power semiconductor switches and DC voltage sources, which
results in decreased complexity and cost of the inverter. These abilities obtained by
comparing the proposed topology with the conventional topologies. The performance of
the proposed topology for generating all levels of 15-Level MLI and 25-Level MLI is
confirmed by simulation and results.
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1.2 Types of MLI

There are three main types of the MLI:

1. Diode Clamped multilevel inverters

2. Flying Capacitor multilevel inverters

3. Cascaded H-bridge multilevel inverters

Figure 1: Classification of DC-AC Converter

1.2.1 Diode clamped multilevel inverter

The diode clamped inverter produce multiple outputs voltages utilizing the
technique of connection of the phases to a series bank of capacitors. The first diode
clamped inverter was limited to three levels but nowadays the level can be extended by
increasing the number of capacitor connected across the dc bus resulting in additional
voltage levels. The diode is used as the clamping device to clamp the dc bus voltage so as
to achieve steps in the output voltage; however the number of level of multilevel inverter
must be odd number because in the case of even number level the neutral point can’t be
accessed.
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Advantages:
 All of the phases share a common dc bus, which minimizes the capacitance
requirements of the converter.
 The capacitors can be pre-charged as a group.
 Efficiency is high for fundamental frequency switching.

1.2.2 Flying capacitor multilevel inverter

Another multilevel inverter topology is the flying capacitor which utilizes a series
connection of capacitor. The main concept of this inverter is to use capacitors as clamping
switching cells. The capacitors transfer the limited amount of voltage to electrical
devices. This inverter uses the same switching states as the diode clamping inverter but it
doesn’t require any clamping diode it uses capacitor instead. This topology has several
unique and attractive features when compared to the diode-clamped inverter. One feature
is that added clamping diodes are not needed. Furthermore, the flying capacitor inverter
has switching redundancy within the phase which can be used to balance the flying
capacitors so that only one dc source is needed.

Advantage:
 Each branch can be analyzed separately and individually.
Disadvantage:
 Pre-charging of capacitors is necessary and difficult.

1.2.3 Cascaded H-bridge Multilevel Inverter

As the name suggest, a cascaded H-bridge inverter is constructed by a series of

H-bridge inverter in cascade configuration. Basically, a three-phase inverter has a same
structure as single H-bridge inverter which use unipolar PWM. This type of topology is
relatively a new configuration after the NPC and FC structure. The topology proposed a
concept with a uses of separate dc source connected for each H-bridge to generate an ac
voltage waveform. The final ac output waveform is produced by cascading the individual
H-bridge output waveform.
 Page |5

Advantages:
 The number of possible output voltage levels is more than twice the number of dc
sources.
 The series of H-bridges makes for modularized layout and packaging. This will
enable this manufacturing process to be done more quickly and cheaply.

1.3 Configurations

The number of levels of the MLI depends upon the magnitude of the dc voltage
source. The selection of the voltage sources can be done in two ways as:

1.3.1 Symmetrical Configuration

In this configuration, each dc voltage source has the same magnitude, i.e. V 1 = V2 =
Vdc. With such configuration, seven levels with the 3S-15L topology and nine levels with
the 4S-25L topology are achieved at the output.

1.3.2 Asymmetrical Configuration

In the asymmetrical configuration, the magnitudes of dc voltage sources have

different magnitude, i.e. V1 and V2 have a different magnitude. For the proposed topology
with asymmetrical configuration, the magnitude of dc voltage sources are chosen as V 1
=Vdc, and V2 =3Vdc for 3S-15L topology and V1 =Vdc, and V2 =5Vdc for 4S-25L topology.
With this configuration, the topology 3S-15L generates 15 output voltage levels, i.e., zero,
±Vdc, ±2Vdc, ±3Vdc, ±4Vdc, ±5Vdc, ±6Vdc, ±7Vdc and the topology 4S-25L generates 25
output voltage levels, i.e., zero, ±Vdc, ±2Vdc, ±3Vdc, ±4Vdc, ±5Vdc, ±6Vdc, ±7Vdc, ±8Vdc,
±9Vdc, ±10Vdc, ±11Vdc, ±12Vdc.
 Page |6

1.4 Necessities

AC loads require constant or adjustable voltages at their input terminals. When

such loads are fed by inverters, it’s essential that output voltage of the inverters is so
controlled as to fulfill the requirements of AC loads. There are various techniques to vary
the inverter output voltage. The most efficient method of controlling the output voltage is
to incorporate pulse-width modulation (PWM) control within the inverters. Multilevel
inverters are commonly used for DC to AC conversion in renewable energy conversion.

1.5 Objective

This project aims to:-

1) To design multilevel inverter that will eliminate the shortcomings of
conventional single level inverter.
2) To simulate MLI topology and compare the characteristics.
3) To propose MLI technology with less number of switches.
4) To reduce the complexity of the switching method of the MLI.
5) To reduce the overall cost of the MLI.
6) To produce output voltage waveform of the Multilevel Inverter (MLI) with
less harmonic distortion compared to the two levels inverter.
7) To produce almost sinusoidal waveform without using any filtering circuit.

1.6 Theme

Multilevel Inverter is a power electronic device which is capable of providing

desired alternating voltage level at the output using multiple lower levels of DC voltages
sources as an input.
 Page |7

CHAPTER II
Literature Survey

2.1 Literature Survey

In the recent years, multilevel inverter has been attracted a large interest in heavy
duty industries and high voltage applications. The utilization of multilevel inverter has
become a good solution for high-power and power quality demanding applications. The
term multi-level implies that an n-level inverter is capable of producing an n-voltage level
rather than producing two levels as in the conventional two levels inverter. Beside that the
multilevel inverter can draw an input current with low distortion, operate at higher
switching frequency and lower switching frequency with lower switching loss and
achieving higher efficiency and resulting lower total harmonic distortion in the in the
output waveform without using any filter circuit.
Nowadays, with rapid growth in the industry and introducing the higher power
application equipment which reaches the megawatt level it is hard to connect a single
power semiconductor switch directly to medium voltage grids about 6.9Kv. Due to these
reasons a new family of multi-level inverters was proposed as a solution for working with
high power application. The first proposed multilevel inverter was to use three levels
inverter. Subsequently several multilevel inverter has been introduced including a n-level
of inverter. The main concept implies in multilevel inverter is to use several
semiconductors switches to produces several voltage levels.

 A 5-Level Three-Phase Cascaded Hybrid Multilevel Inverter P. Thongprasri

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6,
December 2011----This paper presents a 5-level three-phase cascaded hybrid
multilevel inverter that consists of a standard 3-leg (one leg for each phase) and
H-bridge in series with each inverter leg with separate DC voltage sources. The
control signals for this hybrid multilevel inverter are implemented by a FPGA
controller using PWM signal modulated technique and digital technique.
 Page |8

 Seven Level Inverter Topologies: A Comparative Study International Journal of

Innovative Research in Electrical, Electronics, Instrumentation and Control
Engineering nCORETech LBS College of Engineering, Kasaragod Vol. 3, Special
Issue 1, February 2016 Sanoop P1., Vinita Chellappan2 -----This paper presents
different topologies, emphasizing mainly on seven level inverters. The different
topologies compared are the diode-clamped inverter (neutral-point clamped),
capacitor clamped (flying capacitor), and cascaded multi-cell with separate DC
sources. Emerging topologies like asymmetric hybrid cells and soft-switched
multilevel inverters are also discussed. Finally a seven level inverter topology
with lesser number of switches is discussed and compared along with the other
seven level inverter topologies. Simulation studies of diode clamped seven level
inverter, cascade seven level inverter and seven levels inverter with reduced
number of switches are done. The seven levels inverter with reduced number of
switch with PWM (Pulse Width Modulation) switching is also simulated.

 A Topology for 9-Level Multilevel Inverter with Converting Its Optimal Structure
IDevkant Sharma, IIAnurag Mondal I,IIDept. of Electronics & Communication
Engineering, Institute of Technology & Management, Gwalior, India----This
paper presents a noble multilevel inverter topology using one bidirectional switch
and other unidirectional switches which is used in single phase 9-level multilevel
inverter.. By this topology, number of power switches can be minimized with
minimum complexity as compare to other conventional multilevel inverter
methods.

 A New Multilevel Inverter Topology With Reduce Switch Count

MARIF DAULA SIDDIQUE1, (Student Member, IEEE), SAAD MEKHILEF 1,2, (Senior
Member, IEEE), NORAISYAH MOHAMED SHAH1, ADIL SARWAR3, ATIF IQBAL 4,

(Senior Member, IEEE), AND MUDASIR AHMED MEMON1 ---- In this paper, two new
topologies for the staircase output voltage generations have been proposed with a
lesser number of switch requirement. First topology requires 3 DC sources to get
15 levels of output by using 10 switches. And the second topology, which consists
of 4 DC sources with 12 switches to synthesize 25 level of output.
 Page |9

2.2 Problem Statement

In the past decades, most of researches have focused in finding renewable energy
resources which is environmentally friendly and reduce the dependency on the fossil fuel
resources which is the main factor for global warming and environmental pollution. Since
most of the renewable energy resources produces a DC power in nature the invention of
inverter has offered a great solution to use these DC power as an AC power which is most
frequently used by appliances and machinery.
The inverter has attracted a large interest to be used in heavy duty industries and high
power application but with the rapid growth in the industry and introducing the higher
power application equipment which reaches the megawatt level it is hard to connect a
single power semiconductor switch (conventional two level inverter) directly to medium
voltage grids, also the two level inverter with higher harmonic distortion which need a
complex filtering circuit to get the sinusoidal waveform. Due to this drawbacks of the
conventional two level inverter, it recommended to use the multilevel inverter(MLI)
which has many advantages compared to single stage inverter like minimum harmonic
distortion which produce almost sinusoidal waveform without filtering circuit, also the
MLI can operate with high power applications and produce high level output voltage with
less switching losses. Thus the MLI is recommended not only for the use in high power
applications but it can be used for industrial applications as alternative in high power and
medium voltage situations.
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CHAPTER III
System Development

3.1 Methodology

The project starts by collecting the required and relevant information on

multilevel inverter topologies and its modulation methods. From the literature review four
different multilevel inverter topologies proposed and one of the topology are chosen as
the focus of the project for comparison purposes in terms of operation and characteristics.
MATLAB software is used for simulation of these topologies. Simulink blocks are used
to construct these MLI topologies and the modulation technique. Simulation of MLI
allows generation of the respective output voltage waveforms which are used to obtain
the required data for further analysis of the proposed topology.

3.1.1 Control Strategy

Generally the power electronic inverters are operated in the “switched mode”.
This means the switches within the inverter are always in either one of the two states -
turned on or turned off. Any operation of inverter to produce an ac voltage from a dc
source the semiconductors switches must alternate between these two states on and off in
organized and time sequencing manner to generate an ac supply which consist positive
and negative portions from a dc source only one portion .This happens by proposing
different control strategy and modulation techniques that will control and trigger the
inverter switches at different time portion.

3.1.2 The Switching Technique

There are many ways and techniques have been developed to control multilevel
inverter switching, from the very basic fundamental switching up to the most advance
space vector pulse width modulation switching scheme. But, the most famous and applied
by industries is the pulse width modulation (PWM) switching control scheme. PWM
 P a g e | 11

switching control scheme comes with advantages over the traditional multilevel
fundamental switching scheme.
One benefit of PWM methods employing much higher switching frequencies
concerns harmonics. The harmonics filtering exercise is much easier and cheaper due to
the fact that the undesirable harmonics occur at much higher switching frequencies. Also,
the produced harmonics might be above the bandwidth of some actual system. This
means that there is no power dissipation caused by the harmonics. On the contrary,
multilevel fundamental switching scheme creates harmonics at lower switching
frequencies and this increased the complexity of the filtering activity.

3.1.2.1 Pulse Width Modulation (PWM) Technique

The output voltage levels of MLI depend on the switching technique of the
switches. There are many techniques have been developed to control multilevel inverter
switching like pulse width modulation technique and space vector pulse width modulation
technique. The most efficient technique to control the output voltage is PWM control
technique for inverters. In this technique, a fixed DC voltage is supplied to inverter and a
controlled AC output voltage is obtained by controlling on-off period of the
semiconductor switches of the inverter.
In PWM technique one reference signal (modulating signal) is compared with the
carrier signal and the pulses are obtained as shown in fig.2. There is one pulse of fixed
magnitude in every PWM period. However, the width of the pulse changes from pulse to
pulse according to a reference signal. When a PWM signal is applied to the gate terminal
of a switch, it causes the turn on and turns off of the switch to change from one PWM
period to another PWM period according to the modulating signal. This is the most
widely used PWM technique for inverters.
 P a g e | 12

Figure 2: PWM Technique

3.1.3 Switching Angles Calculation

The switching angles are a factor for deciding the performance of the MLI. It can be
rectified by using any optimization methods such as Genetic algorithm, Resultant theory
and Newton Rapson method but with the use of these methods we go through under more
mathematical calculation regardless to go to the Property of the sinusoidal wave to allow
proper switching angles so that its leads to resemblance output waveforms to sinusoidal
waveforms. These angles for V level inverter can be obtained by,

360°
∝=β ×
2× ν

Where,
α= Switching angle,
β= 1, 2, 3, ---------- (ν -1),
ν=Level of output voltage
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3.2 Working

3.2.1 15 Levels MLI:

The circuit diagram of proposed 15 levels DC to AC converter is shown in

Figure.3. It is one type of inverter which has input from constant DC voltage source and
it provides magnified voltage to satisfy the load requirement.

Figure.3:15 Levels MLI

The circuit is built by using three DC voltage sources with nine semiconductor
switches. This DC sources gives required voltage to the each switch. The circuit is
supplied with three asymmetrical DC input voltages means V1 = Vdc, and V2 = 3Vdc. The
circuit consist eight unidirectional switches from S1-S8 along with one bidirectional
switch S9.These switches operate on switching frequency of fs.
 P a g e | 14

There are two cycles are used in this converter to improve the output of the
converter that results the operation of the converter divided into two cases. The cases are
classified according to switching modes of operation are as follows:-
1. Positive half cycle
2. Negative half cycle
According to the switching pulses all the switches are turned ON/OFF. The
following table is a switching pattern for proposed 15 levels MLI topology.

Generation Switching Sequence

of Various Load
Levels Voltage
S1 S2 S3 S4 S5 S6 S7 S8 S9
7 1 0 0 1 1 0 0 1 0 7Vdc
6 0 1 0 1 1 0 0 1 0 6Vdc
5 0 1 0 1 1 0 1 0 0 5Vdc
4 1 0 0 0 1 0 0 1 1 4Vdc
3 0 1 0 0 1 0 0 1 1 3Vdc
2 0 1 0 0 1 0 1 0 1 2Vdc
1 1 0 1 0 1 0 0 1 0 Vdc
0 1 0 1 0 1 0 1 0 0 0Vdc
-1 0 1 0 1 0 1 1 0 0 -Vdc
-2 1 0 0 0 0 1 0 1 1 -2Vdc
-3 1 0 0 0 0 1 1 0 1 -3Vdc
-4 0 1 0 0 0 1 1 0 1 -4Vdc
-5 1 0 1 0 0 1 0 1 0 -5Vdc
-6 1 0 1 0 0 1 1 0 0 -6Vdc
-7 0 1 1 0 0 1 1 0 0 -7Vdc

Table1: Switching pattern for 15-level MLI

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3.2.2 Conduction Mode of 15 Level MLI

The 15 different levels of operation are shown in this section. Based on pulse
signals, semiconductor switches are used in different time periods to create the different
voltage levels. As we can see figure 3, there are three DC voltage sources connected with
nine semiconductor switches and every time the switch connected with respective voltage
sources gets the gate signal, it turns on. Then the DC source provides the respective
voltage level to the circuit. Different conduction mode for proposed topology in positive
and negative half cycle is given as:-

3.2.2.1 Positive Circuits:

A) 0Vdc

In this circuit, switches S1, S3, S5 and S7 are in ON state while all other switches
are OFF; the voltage 0Vdc is across the load. All the three DC sources are in OFF
condition.

a) 0Vdc
B) 1Vdc

In this circuit, switches S1, S3, S5 and S8 are in ON state while all other switches
are OFF; the voltage 1Vdc is across the load. Only one source V1 is in ON condition while
others are in OFF condition.
 P a g e | 16

b) 1Vdc

C) 2Vdc

In this circuit, switches S2, S5, S7 and S9 are in ON state while all other switches
are OFF; the voltage 2Vdc is across the load. In this two DC sources are in ON condition
while one in OFF condition.

c) 2Vdc

D) 3Vdc

In this circuit, switches S2, S5, S8 and S9 are in ON state while all other switches
are OFF; the voltage 3Vdc is across the load. In this one source is in ON condition while
other two DC sources are in OFF condition.
 P a g e | 17

d) 3Vdc
E) 4Vdc

In this circuit, switches S1, S5, S8 and S9 are in ON state while all other switches
are OFF; the voltage 4Vdc is across the load. In this two DC sources are in ON condition
while one in OFF condition.

e) 4Vdc

F) 5Vdc

In this circuit, switches S2, S4, S5 and S7 are in ON state while all other switches
are OFF; the voltage 5Vdc is across the load. All the three DC sources are in ON
condition.
 P a g e | 18

f) 5Vdc

G) 6Vdc

In this circuit, switches S2, S4, S5 and S8 are in ON state while all other switches
are OFF; the voltage 6Vdc is across the load. In this two DC sources are in ON condition
while one in OFF condition.

g) 6Vdc

H) 7Vdc

In this circuit, switches S1, S4, S5 and S8 are in ON state while all other switches
are OFF; the voltage 7Vdc is across the load. All the three DC sources are in ON
condition.
 P a g e | 19

h) 7Vdc

Figure 4: Different switching states of proposed 15 level MLI to get different voltages as
0Vdc, 1Vdc,------7Vdc in positive half cycle respectively

3.2.2.2 Negative Circuits:

As previously we have seen switches conduction for positive circuits. Similarly, it

conducts for negative circuits also.
 P a g e | 20

a) 0Vdc b) -1Vdc

c) -2Vdc d)-3Vdc

e) -4Vdc f) -5Vdc

g) -6Vdc h) -7Vdc

Figure 5: Different switching states of proposed 15 level MLI to get different voltages as
0Vdc, -1Vdc,------7Vdc in negative half cycle respectively
3.2.3 25 Levels MLI:

The circuit diagram of proposed 25 levels DC to AC converter is shown in Figure.3.

It is one type of inverter which has input from constant DC voltage source and it
provides magnified voltage to satisfy the load requirement.
 P a g e | 21

Figure 6:25 Levels MLI

The circuit is built by using four DC voltage sources with ten semiconductor
switches. This DC sources gives required voltage to the each switch. The circuit is
supplied with four asymmetrical DC input voltages means V1 = Vdc, and V2 = 5Vdc. The
circuit consist nine unidirectional switches from S1-S9 along with one bidirectional
switch S10. These switches operate on switching frequency of fs.

There are two cycles are used in this converter to improve the output of the
converter that results the operation of the converter divided into two cases. The cases are
classified according to switching modes of operation are as follows:-
3. Positive half cycle
4. Negative half cycle
According to the switching pulses all the switches are turned ON/OFF. The
following table is a switching pattern for proposed 25 levels MLI topology.
 P a g e | 22

Generation
of Various Switching Sequence Load
Levels Voltage
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

12 1 0 0 1 1 0 0 1 0 0 12Vdc
11 0 0 0 1 1 0 0 1 0 1 11Vdc
10 1 0 0 1 1 0 1 0 0 0 10Vdc
9 0 0 0 1 1 0 1 0 0 1 9Vdc
8 0 1 0 1 1 0 1 0 0 0 8Vdc
7 1 0 0 0 1 0 0 1 1 0 7Vdc
6 0 0 0 0 1 0 0 1 1 1 6Vdc
5 1 0 0 0 1 0 1 0 1 0 5Vdc
4 0 0 0 0 1 0 1 0 1 1 4Vdc
3 0 1 0 0 1 0 1 0 1 0 3Vdc
2 1 0 1 0 1 0 0 1 0 0 2Vdc
1 0 0 1 0 1 0 0 1 0 1 Vdc
0 1 0 1 0 1 0 1 0 0 0 0Vdc
-1 0 0 0 1 0 1 0 1 0 1 -Vdc
-2 0 1 0 1 0 1 1 0 0 0 -2Vdc
-3 1 0 0 0 0 1 0 1 1 0 -3Vdc
-4 0 0 0 0 0 1 0 1 1 1 -4Vdc
-5 0 1 0 0 0 1 0 1 1 0 -5Vdc
-6 0 0 0 0 0 1 1 0 1 1 -6Vdc
-7 0 1 0 0 0 1 1 0 1 0 -7Vdc
-8 1 0 1 0 0 1 0 1 0 0 -8Vdc
-9 0 0 1 0 0 1 0 1 0 1 -9Vdc
-10 0 1 1 0 0 1 0 1 0 0 -10Vdc
-11 0 0 1 0 0 1 1 0 0 1 -11Vdc
-12 0 1 1 0 0 1 0 1 0 0 -12Vdc

Table2: Switching pattern for proposed 25-level MLI

3.2.4 Conduction Mode of 25 Level MLI

The 25 different levels of operation are shown in this section. Based on pulse
signals, semiconductor switches are used in different time periods to create the different
voltage levels. As we can see figure 6, there are four DC voltage sources connected with
ten semiconductor switches and every time the switch connected with respective voltage
sources gets the gate signal, it turns on. Then the DC source provides the respective
 P a g e | 23

voltage level to the circuit. Different conduction mode for proposed topology in positive
and negative half cycle is given as:-

3.2.4.1 Positive Circuits:

A) 0Vdc

In this circuit, switches S1, S3, S5 and S7 are in ON state while all other switches
are OFF, the voltage +Vdc is across the load. All the four DC sources are in OFF
condition.

a) 0Vdc
B) 1Vdc

In this circuit, switches S3, S5, S8 and S10 are in ON state while all other
switches are OFF; the voltage 1V dc is across the load. Only one source is in ON condition
while others are in OFF condition.
 P a g e | 24

b) 1Vdc

C) 2Vdc

In this circuit, switches S1, S3, S5 and S8 are in ON state while all other switches
are OFF; the voltage 2Vdc is across the load. In this two DC sources are in ON condition
while other two are in OFF condition.

c) 2Vdc

D) 3Vdc

In this circuit, switches S2, S5, S7 and S9 are in ON state while all other switches
are OFF; the voltage 3Vdc is across the load. In this three sources are in ON condition
while one DC source is in OFF condition.
 P a g e | 25

d) 3Vdc

E) 4Vdc

In this circuit, switches S5, S7, S9 and S10 are in ON state while all other
switches are OFF; the voltage 4Vdc is across the load. In this two DC sources are in ON
condition while other two are in OFF condition.

e) 4Vdc
F) 5Vdc

In this circuit, switches S1, S5, S7 and S9 are in ON state while all other switches
are OFF; the voltage 5Vdc is across the load. Only one DC source is in ON condition
while other three sources are in OFF condition.
 P a g e | 26

f) 5Vdc

G) 6Vdc

In this circuit, switches S5, S8, S9 and S10 are in ON state while all other
switches are OFF; the voltage 6Vdc is across the load. In this two DC sources are in ON
condition while other two are in OFF condition.

g) 6Vdc
H) 7Vdc

In this circuit, switches S1, S5, S8 and S9 are in ON state while all other switches
are OFF; the voltage 7Vdc is across the load. In this three DC sources are in ON condition
while one is in OFF condition.
 P a g e | 27

h) 7Vdc

I) 8Vdc

In this circuit, switches S2, S4, S5 and S7 are in ON state while all other switches
are OFF; the voltage 8Vdc is across the load. In this all four DC sources are in ON
condition.

i) 8Vdc
J) 9Vdc

In this circuit, switches S4, S5, S7 and S10 are in ON state while all other
switches are OFF; the voltage 9V dc is across the load. In this three DC sources are in ON
condition while one is in OFF condition.
 P a g e | 28

j) 9Vdc

K) 10Vdc

In this circuit, switches S1, S4, S5 and S7 are in ON state while all other switches
are OFF; the voltage 10Vdc is across the load. In this two DC sources are in ON condition
while other two are in OFF condition.

k) 10Vdc
L) 11Vdc

In this circuit, switches S4, S5, S8 and S10 are in ON state while all other
switches are OFF; the voltage 11Vdc is across the load. In this three DC sources are in ON
condition while one is in OFF condition.
 P a g e | 29

l) 11Vdc

M) 12Vdc

In this circuit, switches S1, S4, S5 and S8 are in ON state while all other switches
are OFF; the voltage 12Vdc is across the load. In this all four DC sources are in ON
condition.

m) 12Vdc

Figure 7: Different switching states of proposed 25 MLI to get different voltages as

0Vdc, 1Vdc,------7Vdc in positive half cycle respectively
3.2.4.2 Negative Circuits:

As previously we have seen switches conduction for positive circuits. Similarly, it

conducts for negative circuits also.
 P a g e | 30

a) 0Vdc

b) -1Vdc c) -2Vdc

d) -3Vdc e) -4Vdc

f) -5Vdc g) -6Vdc
 P a g e | 31

h) -7Vdc i) -8Vdc

j) -9Vdc k) -10Vdc

l) -11Vdc m) -12Vdc

Figure 8: Different switching states of proposed 25 level MLI to get different voltages as
0Vdc,-1Vdc,------12Vdc in negative half cycle respectively
CHAPTER IV
Performance Analysis
4.1 Simulation
Simulation and modeling are a way to create a virtual representation of real world
system that includes software and hardware. If the software components of this model are
driven by mathematical relationships, we can simulate this virtual representation under a
wide range of conditions to see how it behaves.
 P a g e | 32

Simulation and modeling are especially valuable for testing conditions that might
be difficult to reproduce with hardware prototype alone, especially in the early phase of
the design process when hardware may not be available. Iterating between simulation and
modeling can improve the quality of the system design early, thereby reducing the
number of errors found later in the design process.

4.1.1 Software Requirement

1. Matlab/Simulink

4.1.1.1 Matlab/Simulink

Matrix Laboratory is a multi-paradigm numerical computing environment and

proprietary programming language developed by MathWorks, allows matrix
manipulations, plotting of functions and data, implementation of algorithms, creation of
user interfaces, and interfacing with programs written in other language.
Simulink is a simulation and model based design environment for dynamic and
embedded systems, integrated with MATLAB. Simulink also developed by MathWorks,
it is a data flow graphical programming language tool for modeling, simulating and
analyzing multi domain dynamic systems. It is basically a graphical block diagramming
tool with customizable set of block libraries. It supports system-level design, simulation,
automatic code generation, and continuous test and verification of embedded systems.
Simulink provides a graphical editor, customizable block libraries, and solvers modeling
and simulating dynamic systems.

4.2 Circuit Building

In simulink, taking all the required blocks in the model file, arranging and
connecting the blocks to each other circuit construction is completed. For measuring the
parameter like current and voltage at particular branch, need to connect current
measurement block in series with that branch/element and voltage measurement block
across the branch/element respectively. Output of the measurement blocks has only one
node that connects to the scope, to getting results in the waveforms. Powergui block must
be available in the model file as that converts the output circuit into the readable format.
 P a g e | 33

Flow Chart

4.3 Simulation Circuits

4.3.1 Existing Systems

A) 3 Level Multilevel Inverter (3-Level, 4 Switches):

The circuit which is shown in figure 9 is built with one DC voltage source, four
semiconductor switches and two diodes which produce the steps of 3 levels for positive
and negative half cycles.
 P a g e | 34

C
Discrete, P1
Ts = 5e-05 s. S1

E
powergui

m
a
k

+
D1

C
RC
P2
S2

E
DC +
+
R1 v
-
Voltage Measurement Scope

C
+
P3
S3

E
C2

D2
m
a
k

C
P4
S4

E
Figure 9: Simulation circuit of 3 Level MLI

Output Voltage:

Figure 10: Output Voltage of 3-level MLI

B) 5 Level Multilevel Inverter (5-Level, 8 Switches):

Figure 11 shows 5 level multilevel inverter simulation circuit. The circuit is built
with one DC voltage source consists of an H-Bridge which consists of two DC voltage
sources (Vdc1 & Vdc2) with eight semiconductor switches which produces the steps of 5
levels, for positive and negative half cycles.
 P a g e | 35

g
C

C
Discrete,
P1 P3 Ts = 5e-05 s.
S3
S1
powergui

m
E

E
DC

g
C

C
P4 P2

S4 S2

m
E

+
+
LOAD -
v

Voltage MeasurementScope

g
C

C
P5 P7

S5 S7

m
E

E
DC1

g
C

C
P8
P6
S8 S6
m

m
E

E
Figure 11: Simulation circuit of 5 Level MLI

Output Voltage:

Figure 12: Output Voltage of 5-level MLI

C) 11 Level Multilevel Inverter (11-Level, 9 Switches):

The circuit which is shown in figure 13 is built with five DC sources. The circuit
consists of nine semiconductor switches and five diodes which produce the steps of 11
levels, for positive and negative half cycles.
 P a g e | 36

DC1

k
m
E
m
D1

a
S1

C
g
P1

DC2 P6 P7

k
m

m
S2 D2

a
C
g
P2

Discrete,

g
C

C
Ts = 5e-05 s.

k
m
S8 powergui
DC3 S6

m
D3

E
a
E
m

+
S3

C
g
+
LOAD v
P3 -
Voltage Measurement Scope

g
C

C
S7 S9

m
E

E
k
m
DC4
E
m

D4

a
S4
C
g

P4

DC5
k
m
E
m

D5
P5
a

S5
C
g

Figure 13: Simulation circuit of 11 Level MLI

Output Voltage:

Figure 14: Output Voltage of 11-level MLI

4.3.2 Proposed 15 Level MLI Topology

The simulation circuit of the fifteen levels multilevel inverter is shown in figure
15. The proposed topology is simulated in MATLAB. It consists of nine semiconductor
switches (S1-S9) which are connected with a three DC voltage sources of rating V 1=25V,
V2=75V, V2=75V are connected as shown in the circuit. The Switching pulses are given
 P a g e | 37

to the circuit by pulse width modulation technique for the generation of positive and
negative cycles.
PWM1 Discrete,
Ts = 5e-05 s.

powergui

C
P1

S1

E
PWM5
PWM7

E
m
Scope
PWM3
S3

C
g
PWM9 P5

g
C

C
v
P7

+
-
VM1
P9 P3 S5 S7

m
E

E
V2
V1
g m m g
+
C E E C
PWM6 LOAD

C
S9 S10 P6

C
V3 P8
S6 PWM8

E
S8

E
PWM2

E
m
PWM4 S4

C
g
P2
g

S2 P4
m

Figure 15: Simulation circuit of 15 Level MLI

4.3.2.1 Firing Pulses:

The angles at which gate terminal of switches are triggered are the firing angles.
These pulses are obtained according to the given formulas and the switching table. Figure
16, 17 and 18 shows all gate pulses applied to different switches for conduction.

For S1, S2, S3

 P a g e | 38

Figure 16: Firing Pulses for S1, S2, S3

For S4, S5, S6

Figure 17: Firing Pulses for S4, S5, S6

For S7, S8, S9

 P a g e | 39

Figure 18: Firing Pulses for S7, S8, S9

4.3.2.2 Output Voltage:

The magnitude of AC voltage has been varied based on the proportion of supply
side DC source.

Figure 19: Output voltage of proposed 15-level MLI

4.3.3 Proposed 25 Level MLI Topology

 P a g e | 40

The proposed topology is simulated in MATLAB. It consists of ten semiconductor

switches (S1-S10) which are connected with a four DC voltage sources rating V 1=25V,
V1=25V, V2=125V and V2=125V are connected as shown in the circuit. The Switching
pulses are given to the circuit by pulse width modulation technique (for the generation of
positive and negative cycles).The simulation circuit of the twenty five level multilevel
inverter is shown as below.

PWM1
Discrete,
Ts = 5e-05 s.

powergui
g

C
P1

S1
m

PWM5

E
m
V1
PWM3 PWM7
Scope
S3

C
g
P5

g
C

C
v
P10 PWM10 P7

+
-
PWM9 P9 VM1
P3 S5 S7

m
E

E
V3

g m m g g m m g
+
C E E C C E E C
LOAD

C
S11 S12 S9 S10 P6

C
V4 P8
S6

E
PWM6 S8

E
PWM8
E
m

PWM2

PWM4 S4
C
g

V2

P2
g

S2 P4
m

Figure 20: Simulation circuit of 25 Level MLI

4.3.3.1 Firing Pulses:

 P a g e | 41

The angles at which gate terminal of switches will triggered are the firing angles.
These pulses are obtained according to the given formulas and the switching table. Figure
21, 22, 23, 24 and 25 shows all gate pulses applied to different switches for conduction.

For S1, S2

Figure 21: Firing Pulses for S1, S2

For S3, S4

Figure 22: Firing Pulses for S3, S4

For S5, S6
 P a g e | 42

Figure 23: Firing Pulses for S5, S6

For S7, S8

Figure 24: Firing Pulses for S7, S8

For S9, S10

Figure 25: Firing Pulses for S9, S10

4.3.3.2 Output Voltage:
 P a g e | 43

The magnitude of AC voltage has been varied based on the proportion of supply
side DC source.

Figure 26: Output voltage of proposed 25-level MLI

CHAPTER V
 P a g e | 44

Result and Comparison

According to the output of the proposed MLI the following results are obtained
for the different levels of MLI.

5.1 FFT Analysis

To determine the output of multilevel inverter, five different multilevel inverter

circuits are simulated. The performance of the output voltage of the MLI topologies is
measured based on its THD .The different levels output voltage, harmonic order and FFT
analysis is as shown in figures given below. The total harmonic distortion value is
analyzed by using FFT window for the proposed topologies as shown in Table 2. The
comparison table has been created by comparing different topologies to show that
proposed topology is better than others. Comparison of FFT analysis with different levels
is shown in Table 2.

5.1.1 FFT Analysis of 3-Level MLI

Figure 27 shows the output voltage and the harmonic analysis for the 3-level
inverter using 4 switches and 2 diodes. For 3-level MLI, the THD value is 69.26%.

Figure 27: FFT analysis and THD of 3-level MLI

5.1.2 FFT Analysis of 5-Level MLI
 P a g e | 45

Figure 28 shows the output voltage and the harmonic analysis for the 5-level
inverter using 8 switches with 2 DC sources. For 5-level MLI, the THD value is 42.93%.

Figure 28: FFT analysis and THD of 5-level MLI

5.1.3 FFT Analysis of 11-Level MLI

Figure 29 shows the output voltage and the harmonic analysis of the 11-level
inverter using 8 switches and 2 DC voltage sources. For 11-level MLI, the THD value is
25.45%.

Figure 29: FFT analysis and THD of 11-level MLI

5.2 FFT Analysis of Proposed 15-Level MLI Topology

 P a g e | 46

Figure 30 shows the output voltage and the harmonic analysis of the proposed 15
level multilevel inverter using 9 switches and 3 DC voltage sources. When compared to
the existing method we get more accurate sinusoidal output in the proposed method. The
THD is less in the proposed topology compared to existing topology. The higher order
harmonics are also very less compared to the existing topology. In the proposed topology
the THD value is 18.88%.

Figure 30: FFT analysis and THD of 15-level MLI

5.3 FFT Analysis of Proposed 25-Level MLI Topology

 P a g e | 47

Figure 31 shows the output voltage and the harmonic analysis of the proposed 25
level multilevel inverter using 10 switches and 4 DC sources. When compared to the
existing method we get more accurate sinusoidal output in the proposed method. The
THD is less in the proposed topology compared to existing topology. The higher order
harmonics are also very less compared to the existing topology. In the proposed topology
the THD value is 15.93%.

Figure 31: FFT analysis and THD of 25-level MLI

5.4 Comparison of Multilevel Inverters

 P a g e | 48

The various topologies are compared according to the levels associated with the
numbers of switches used. The required number of switches and DC sources for the
different topologies are as shown below. The graph is based on the number of sources and
switches used versus THD values.

Configuration No of switches No of DC sources THD%

3 level MLI 4 1 69.26%

5 level MLI 8 2 41.90%

11 level MLI 9 5 25.45%

15 level MLI 9 3 18.88%

25 level MLI 10 4 15.93%

Table 3: Comparison of different topologies

80

70

60

50 3 level
5level
40
11 level
30 15 level
25 level
20

10

0
Switches DC Sources THD

Figure 32: Comparison of different topologies

CHAPTER VI
 P a g e | 49

Conclusion

6.1 Conclusion

In this project, multilevel inverters with reduced switch topology are proposed.
The fifteen levels and twenty five levels asymmetric multilevel inverters are presented.
The projected inverters can create high quality output voltage close to sinusoidal
waveform. It gives improved performance than the conventional multilevel inverter. And
also this proposed method is used to minimize the switching losses. The total harmonic
distortion (THD) calculations are done by FFT analysis of output waveform of each
inverter and it has found that, as the levels of inverter are increased the THD is decreased.
In this project single phase 15 levels MLI and single phase 25 levels MLI with
reduced switch topology is introduced and its various modes of operation are studied. The
results for proposed topologies are summarized as follows:
 The proposed MLI uses only 9 switches to give 15 level of output and 10 switches
to give 25 level of output.
 It is seen from the simulation results that the THD for the output voltages of the
proposed system is lower than the conventional one.
 The inverter can be easily expanded by increasing the levels with minimum
number of switches. Thus, overall cost gets reduced.

6.2 Advantages

1) Better waveform quality of output voltage.

2) Lower voltage rating devices can be used.
3) Multilevel inverter can operate at both fundamental switching frequencies that are
higher switching frequency and lower switching frequency.
4) Higher efficiency.
5) Reduces harmonic distortion.
6) Reduces dv/dt stresses.

6.3 Applications
 P a g e | 50

1) Hybrid electric vehicle

2) PV system
3) Static var compensation
4) Variable speed motor drives
5) High voltage system interconnections
6) High voltage DC and AC transmission lines

6.4 Future Scope

In this project work, two different circuits of MLI with reduced switch topology have
been proposed and tested with the simulation. However, the following points are helpful
for further extension of this research work in future.
 The proposed topology can be extended in the area of modular multilevel inverter
so that the multiple DC sources are replaced by capacitors.
 The proposed topology can be integrated with renewable energy sources like
solar, wind, fuel and biomass.
 Design a suitable current controller for proposed topology in grid connected
operation.
 Testing of low voltage ride through capability and reliability for the proposed MLI
topology when it is integrated with renewable energy sources like solar and wind.
 Testing of the proposed MLI topology with FACTS devices for eliminating the
power quality problems.

CHAPTER VII
 P a g e | 51

References

 A 5-Level Three-Phase Cascaded Hybrid Multilevel Inverter P. Thongprasri

International Journal of Computer and Electrical Engineering, Vol. 3, No. 6,
December 2011.

 Seven Level Inverter Topologies: A Comparative Study International Journal of

Innovative Research in Electrical, Electronics, Instrumentation and Control
Engineering nCORETech LBS College of Engineering, Kasaragod Vol. 3,
Special Issue 1, February 2016 Sanoop P1., Vinita Chellappan2.

 A Topology for 9-Level Multilevel Inverter with Converting Its Optimal

Structure IDevkant Sharma, IIAnurag Mondal I,IIDept. of Electronics &
Communication Engineering, Institute of Technology & Management, Gwalior,
India.

 A New Multilevel Inverter Topology With Reduce Switch CountMARIF DAULA

SIDDIQUE1, (Student Member, IEEE), SAAD MEKHILEF 1,2, (Senior
Member, IEEE), NORAISYAH MOHAMED SHAH1, ADIL SARWAR3, ATIF
IQBAL 4, (Senior Member, IEEE), AND MUDASIR AHMED MEMON1.