L5 Instruction Set Part 3

Microprocessors and
Microcontrollers (EC3L007)
Instruction set of 8085 – Part 3

Logical Instructions
2
• These instructions perform logical operations on data
stored in registers, memory and status flags.
• The logical operations are:

• AND
• OR
• XOR
• Rotate
• Compare
• Complement
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AND, OR, XOR
• Any 8-bit data, or the contents of register, or memory

location can logically have
• AND operation
• OR operation
• XOR operation
with the contents of accumulator.
• The result is stored in accumulator.

Rotate
• Each bit in the accumulator can be shifted either left or
right to the next position.

Compare
• Any 8-bit data, or the contents of register, or memory
location can be compared for:
• Equality
• Greater Than
• Less Than
with the contents of accumulator.
• The result is reflected in status flags.

Complement
• The contents of accumulator can be complemented.
• Each 0 is replaced by 1 and each 1 is replaced by 0.

Opcode Operand Description

CMP R Compare register or memory
M with accumulator
• The contents of the operand (register or memory) are

compared with the contents of the accumulator.
• Both contents are preserved.
• The result of the comparison is shown by setting the

flags of the PSW as follows:

CMP R Compare register or memory
M with accumulator
• if (A) < (reg/mem): carry flag is set

• if (A) = (reg/mem): zero flag is set
• if (A) > (reg/mem): carry and zero flags are reset.
• Example: CMP B or CMP M

Example

Example


CPI 8-bit data Compare immediate with
accumulator
• The 8-bit data is compared with the contents of

accumulator.
• The values being compared remain unchanged.
• The result of the comparison is shown by setting the

flags of the PSW as follows:


CPI 8-bit data Compare immediate with
accumulator
• if (A) < data: carry flag is set
• if (A) = data: zero flag is set
• if (A) > data: carry and zero flags are reset
• Example: CPI 89H, Immediate Addressing mode, 7T

ANA R Logical AND register or memory
M with accumulator
• The contents of the accumulator are logically ANDed bit
by bit with the contents of register or memory.
• The result is placed in the accumulator.
• If the operand is a memory location, its address is
specified by the contents of H-L pair.
• CY is always reset and AC is set.
• S, Z, P are modified to reflect the result of the operation.
• Example: ANA B or ANA M.
Example:


ANI 8-bit data Logical AND immediate with
accumulator
• The contents of the accumulator are logically ANDed

with the 8-bit data.
• S, Z, P are modified to reflect the result.
• CY is reset, AC is set.
• Example: ANI 86H.
ORA R Logical OR register or memory
M with accumulator
• The contents of the accumulator are logically ORed with the
contents of the register or memory.
• If the operand is a memory location, its address is specified

by the contents of H-L pair.
• S, Z, P are modified to reflect the result. CY and AC are

always reset.
• Example: ORA B or ORA M.

Example


ORI 8-bit data Logical OR immediate with
accumulator
• The contents of the accumulator are logically ORed with

the 8-bit data.
• CY and AC are reset.
• Example: ORI 86H.

XRA R Exclusive OR register or memory
M with accumulator
• The contents of the accumulator are XORed with the contents

of the register or memory. The result is placed in the
accumulator.
• If the operand is a memory location, its address is specified

by the contents of H-L pair.
• S, Z, P are modified to reflect the result of the operation.CY

and AC are reset.
• Example: XRA B or XRA M.

Example:


XRI 8-bit data XOR immediate with
accumulator
• The contents of the accumulator are XORed with the 8-

bit data.
• CY and AC are reset.
• Example: XRI 86H.

RLC None Rotate accumulator left
• Each binary bit of the accumulator is rotated left by one

position.
• Bit D7 is placed in the position of D0 as well as in the
Carry flag.
• Only CY is modified according to bit D7.
• S, Z, P, AC are not affected.
• Example: RLC.
Example:


RRC None Rotate accumulator right
• Each binary bit of the accumulator is rotated right by one

position.
• Bit D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.
• Example: RRC.
Example:


RAL None Rotate accumulator left through
carry
• Each binary bit of the accumulator is rotated left by one

position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
• Example: RAL.
Example:


RAR None Rotate accumulator right through
carry
• Each binary bit of the accumulator is rotated right by one

position through the Carry flag.
• Bit D0 is placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.
• Example: RAR.

Example:


CMA None Complement accumulator
• The contents of the accumulator are complemented.

• No flags are affected.
• One byte instruction, Implied addressing, 4T
• Example: CMA.


CMC None Complement carry
• The Carry flag is complemented.

• No other flags are affected (Only the carry flag is
affected).
• One byte instruction, Implied addressing, 4T
• Example: CMC.

STC None Set carry
• The Carry flag is set to 1.

• No other flags are affected ( Only carry flag is affected by this
instruction).
• One byte instruction, Implied addressing, Opcode fetch 4T.
• Example: STC.

Branching Instructions
34
• The branching instruction alter the normal sequential
flow.
• These instructions alter either unconditionally or

conditionally.


JMP 16-bit Jump unconditionally
address
• The program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand.
• Example: JMP 2034 H.


Jx 16-bit Jump conditionally
address
• The program sequence is transferred to the memory

operand based on the specified flag of the PSW.
• Example: JZ 2034 H.

Jump Conditionally
Opcode Description Status Flags

JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S=0
JM Jump if Minus S=1
JZ Jump if Zero Z=1
JNZ Jump if No Zero Z=0
JPE Jump if Parity Even P=1
JPO Jump if Parity Odd P=0

Example:


CALL 16-bit Call unconditionally
address
 The program sequence is transferred to the memory

operand.
 Before the transfer, the address of the next instruction

after CALL (the contents of the program counter) is
pushed onto the stack.
 Example: CALL 2034 H.

Example:


Cx 16-bit Call conditionally
address
 The program sequence is transferred to the memory

operand based on the specified flag of the PSW.
 Before the transfer, the address of the next instruction

after the call (the contents of the program counter) is
pushed onto the stack.
 Example: CZ 2034 H.
Example:

Call Conditionally

CC Call if Carry CY = 1
CNC Call if No Carry CY = 0
CP Call if Positive S=0
CM Call if Minus S=1
CZ Call if Zero Z=1
CNZ Call if No Zero Z=0
CPE Call if Parity Even P=1
CPO Call if Parity Odd P=0


RET None Return unconditionally
• The program sequence is transferred from the

subroutine to the calling program.
• The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
• Example: RET.
Example:


Rx None Return conditionally
 The program sequence is transferred from the

subroutine to the calling program based on the specified
flag of the PSW.
 The two bytes from the top of the stack are copied into
the program counter, and program execution begins at
the new address.
 Example: RZ.
Return Conditionally

RC Return if Carry CY = 1
RNC Return if No Carry CY = 0
RP Return if Positive S=0
RM Return if Minus S=1
RZ Return if Zero Z=1
RNZ Return if No Zero Z=0
RPE Return if Parity P=1
Even
RPO Return if Parity P=0
Odd
Example:


RST 0–7 Restart (Software Interrupts)
• The RST instruction jumps the control to one of eight

memory locations depending upon the number.
• These are used as software interrupts in a program to
transfer program execution to one of the eight locations.
• Example: RST 3.

Restart Address Table
Instructions Restart Address

RST 0 0000 H
RST 1 0008 H
RST 2 0010 H
RST 3 0018 H
RST 4 0020 H
RST 5 0028 H
RST 6 0030 H
RST 7 0038 H

Example:

Machine Control Instructions
53
Control Instructions
• The control instructions control the operation of
microprocessor.


DI None Disable interrupt
• The interrupt enable flip-flop is reset and all the

interrupts except the TRAP are disabled.
• One byte instruction, Opcode fetch (4T)
• Example: DI


EI None Enable interrupt
• The interrupt enable flip-flop is set and all interrupts are

enabled.
• This instruction is necessary to re-enable the interrupts

(except TRAP).
• Example: EI

SIM None Set Interrupt Mask
• This is a multipurpose instruction and used to implement

the 8085 interrupts 7.5, 6.5, 5.5, and serial data output.
• The instruction interprets the accumulator contents as
follows.
• Example: SIM

SIM Instruction


RIM None Read Interrupt Mask
• This is a multipurpose instruction used to read the status

of interrupts 7.5, 6.5, 5.5 and read serial data input bit.
• The instruction loads eight bits in the accumulator with
the following interpretations.
• Example: RIM

RIM Instruction


NOP None No operation
• No operation is performed.
• The instruction is fetched and decoded but no operation
is executed.
• Example: NOP


HLT None Halt
• The CPU finishes executing the current instruction and

halts any further execution.
• An interrupt or reset is necessary to exit from the halt
state.
• Example: HLT

Thank you, done for today !!!
References
• Ramesh Gaonkar, “Microprocessor, Architecture,
Programming, & Applications with the 8085 6/e”
• Various online resources.
• Reading:
Chapter 6 & 7, Ramesh Gaonkar

L5 Instruction Set Part 3

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Microprocessors and

Instruction set of 8085 – Part 3

• The logical operations are:

[02/08/2019, IIT BBS] | [Srinivas Boppu] | [SES] | [EC3L007] 3

• Any 8-bit data, or the contents of register, or memory

with the contents of accumulator.

• The result is stored in accumulator.

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with the contents of accumulator.

• The result is reflected in status flags.

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• Each 0 is replaced by 1 and each 1 is replaced by 0.

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Opcode Operand Description

• The contents of the operand (register or memory) are

• Both contents are preserved.

• The result of the comparison is shown by setting the

Opcode Operand Description

• if (A) < (reg/mem): carry flag is set

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Opcode Operand Description

• The 8-bit data is compared with the contents of

• The values being compared remain unchanged.

• The result of the comparison is shown by setting the

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Opcode Operand Description

• if (A) < data: carry flag is set

• if (A) = data: zero flag is set

• if (A) > data: carry and zero flags are reset

• Example: CPI 89H, Immediate Addressing mode, 7T

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Opcode Operand Description

• The contents of the accumulator are logically ANDed

• The result is placed in the accumulator.

• If the operand is a memory location, its address is specified

• S, Z, P are modified to reflect the result. CY and AC are

• Example: ORA B or ORA M.

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Opcode Operand Description

• The contents of the accumulator are logically ORed with

• The result is placed in the accumulator.

• S, Z, P are modified to reflect the result.

• CY and AC are reset.

• Example: ORI 86H.

• The contents of the accumulator are XORed with the contents

• If the operand is a memory location, its address is specified

• S, Z, P are modified to reflect the result of the operation.CY

• Example: XRA B or XRA M.

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Opcode Operand Description

• The contents of the accumulator are XORed with the 8-

Opcode Operand Description

• Each binary bit of the accumulator is rotated left by one

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Opcode Operand Description

• Each binary bit of the accumulator is rotated right by one

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Opcode Operand Description