Apple Macbook A1181 13 - 7559 820-2279 K36A MLB 051RevH (02-15-2008) Schematics

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
K36A MLB SCHEMATIC

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
H 581757 PRODUCTION RELEASED 04/15/08

?
REFERENCED FROM K36

02/15/2008 D
D (.csa) Date (.csa) Date
Page
TABLE_TABLEOFCONTENTS_HEAD
1
Contents Sync 09/05/2006
Page
TABLE_TABLEOFCONTENTS_HEAD
51
Contents Sync 06/01/2006
TABLE_TABLEOFCONTENTS_ITEM
1 2
Table of Contents RX USB
05/11/2006 TABLE_TABLEOFCONTENTS_ITEM
46 52
LPC+ Debug Connector LD WFERRY
06/01/2006
2 3
System Block Diagram RX WFERRY-WF
47 53
SMBUS CONNECTIONS LD WFERRY
07/17/2006
3 4
Power Block Diagram MK POWER
48 55
CPU Current & Voltage Sense ES GPU
06/21/2006
4 5
CONFIGURATION OPTIONS RX SMC
N/A TABLE_TABLEOFCONTENTS_ITEM
49 56
TEMPERATURE SENSE ES GPU
11/10/2005
5 7
Revision History RX N/A
50 59
Fan LD ENET
08/23/2005
6 8
FUNC TEST 1 OF 2 RX TP
51 61
SMS MK SMC
04/26/2006
7 9
Power Aliases MK WFERRY
52 62
SPI ROMs RX WFERRY
03/12/2007
8 10
SIGNAL ALIAS /RESET RX GPU
53 66
AUDIO: CODEC RX M70AUDIO
03/12/2007
9 11
CPU FSB RX T9_MLB_NOME
54 67
AUDI0: SPEAKER AMP RX M70AUDIO
03/12/2007
10 12
CPU Power & Ground RX T9_MLB_NOME
55 68
AUDIO: JACK RX M70AUDIO
03/12/2007
11 13
CPU Decoupling & VID RX MSARWAR
56 69
AUDIO: JACK TRANSLATORS RX M70AUDIO
07/13/2005
12 14
CPU ITP700FLEX DEBUG ES MASTER
57 70
DC-In & Battery Connectors RX POWER
05/31/2006
13 15
NB CPU Interface ES T9_MLB
58 71
S0 FETS & Power Sequencing MK DSIMON-WF
07/13/2005
14 16
NB PEG / Video Interfaces ES T9_MLB
59 72
IMVP6 CPU VCore Regulator MK POWER
06/29/2006
15 17
NB Misc Interfaces ES T9_MLB
60 73
Render VCore Supplies MK GPU
07/13/2005
16 NB DDR2 Interfaces ES T9_MLB 61 1.5V / 1.05V Supplies MK POWER
C TABLE_TABLEOFCONTENTS_ITEM
17 18
NB Power 1 ES T9_MLB
62 75
1.8V/0.9V Supplies MK POWER
07/13/2005 C
19 10/30/2006 TABLE_TABLEOFCONTENTS_ITEM
76 07/13/2005
18 20
NB Power 2 ES T9_MLB
63 77
5V/3.3V Supplies MK POWER
12/06/2005
19 21
NB Grounds ES T9_MLB
64 78
3.42V/1.25V Switcher MK ENET
06/12/2006
20 22
NB Standard Decoupling ES WFERRY
65 79
S3 FET & S3/S5 Control MK DSIMON-WF
08/19/2005
21 23
NB Graphics Decoupling ES WFERRY
66 90
PBUS Supply/Battery Charger MK SMC
06/23/2006
22 24
SB Enet, Disk, FSB, LPC RX T9_MLB
67 92
INVERTER,LVDS,TMDS MK GPU
06/06/2005
23 25
SB PCI, PCIe, DMI, USB RX T9_MLB
68 94
EXTERNAL TMDS ES GRAPHIC
05/21/05
24 26
SB Pwr Mgt, GPIO, Clink RX T9_MLB
69 100
MINI-DVI CONNECTOR ES EUGENE
06/08/2006
25 27
SB Power & Ground RX T9_MLB
70 101
CPU/FSB Constraints ES WFERRY
06/12/2006
26 28
SB Decoupling RX WFERRY
71 102
NB Constraints RX WFERRY
06/08/2006
27 29
SB Misc RX NB
72 103
Memory Constraints ES WFERRY
06/12/2006
28 30
Clock (CK505) DK DSIMON
73 104
SB Constraints (1 of 2) LD WFERRY
06/12/2006
29 31
Clock Termination DK DSIMON-WF
74 105
SB Constraints (2 of 2) RX WFERRY
06/12/2006
30 DDR2 SO-DIMM Connector A LD MEMORY 75 Clock Constraints RX WFERRY
31 32
DDR2 SO-DIMM Connector B LD MEMORY
76 106
FireWire & SMC Constraints DK WFERRY
06/12/2006
K36A EE DRIS:
33 06/20/2005 TABLE_TABLEOFCONTENTS_ITEM
32 34
Memory Active Termination LD MEMORY
08/19/2005
33 37
AIRPORT CONNECTOR LT ENET
10/07/2006
DK-DINESH KUMAR
B TABLE_TABLEOFCONTENTS_ITEM
34 38
Ethernet (Yukon) LT USB
10/07/2006
B
35 39
Yukon Power Control LT USB
09/14/2006
36 40
ETHERNET CONNECTOR LT USB
08/30/2005
37 43
FIREWIRE CONTROLLER LT ENET
07/17/2006
38 44
FIREWIRE PORT LT GPU
07/17/2006
39 45
PATA CONNECTOR DK GPU
07/17/2006
40 46
SATA CONNECTOR RX GPU
06/30/2006
41 47
USB EXTERNAL CONNECTORS LT USB
06/29/2006
42 48
CONNECTOR MISC LT USB
09/05/2006
43 49
IR CONTROLLER & BT INTERFACE LT USB
10/30/2006
44 50
SMC LD T9_MLB
07/17/2006
45 SMC SUPPORT LD GPU
DIMENSIONS ARE IN MILLIMETERS
METRIC APPLE INC.

XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
Schematic / PCB #’s ANGLES
QA APPD DESIGNER
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TITLE
DO NOT SCALE DRAWING
051-7559 1 SCHEM,MLB,K36A SCH CRITICAL
820-2279 1 PCBF,MLB,K36 PCB CRITICAL
RELEASE SCALE
NONE
SCHEM,MLB,K36A
SIZE DRAWING NUMBER
MATERIAL/FINISH
NOTED AS D 051-7559 REV.
H
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 106
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U1000
CPU U2900
2.? GHz CK 505
Core ~1.2V
Clocks TERMS
Pg 10 J1302 Pg 28 Pg 29
Pg 9 ITP CONN
PG 12
D 64-Bit
FSB J6900/50
DC/Batt Power
D
800/1066? MHz
Conn Supply
PG 57 PG 57-67
Pg 13
J3101
U1400 J3201
Main Memory
PCI-E
U9200
NB-GMCH
Pg 15/16
SDVO DIMM Parallel
TMDS Core DDR2 - Dual Channel Term
Pg 14 Temp Sense
1.05 - 1.25V 1.8V - 64 Bits Pg 32
CPU U5520 PG 49
533/667/800? MHz
Out
TV
PG 68 Pg30,31
HEAT-PIPE/FIN U5500 PG 49
RGB
GPIO
Misc
J9401 Pg 15
Pg 17,18,19
LVDS
DMI CLnk 0
DVI-I MUX U5920 SUDDEN MOTION DETECT PG 51
Pg 14 Pg 15 Pg 15
POWER SENSE PG 48
PG 69
J9001 U6100/50 J5601

FAN CONN PG 50
SPI
Int Disp
Boot ROM
Conn x4 DMI
C PG 67 2.5 GHz
PG 54
A B,0 BSA BSB ADC Fan Ser
C
Prt J5100
SMC
LPC Conn
U4900 PG 44 PG 46
DMI CLnk 0 SPI
Pg 22
SATA-0
LPC
J4501
Pg 23 Pg 24 Pg 23
SATA U2300
Conn J4600 J4601
SATA
Pg 22
SATA-1
U4800
J4850 J4700 J4810
GPIOs
PG 40 USB
Pg 24
IR 3G Geyser Bluetooth Connectors
J4401 CONTROLLER CONNECTOR Trackpad/Keyboard
SB-ICH8
SATA-2
PG 43 PG 42 PG 43 PG 41
PG 44
UATA Core 1.05V
Conn
1 2 3 4 5 6 7 8 9
UATA
Pg 22
PG 39
Pg 23
USB
Ln1 Ln2
CAMERA
PCI-E
Ln3 Ln4
Pg 23
B B
Pg 24
SMB
Core
Ln5
Pg 25
Ln6
E-NET CLnk 1 PCI AZALIA DIMM’s Clk Gen

Pg 22 Pg 24 Pg 23 Pg 22
J3101 U2900
J3201 UC500
33 MHz
32-Bit
U6200
U4000
Audio
FW32306 Codec
Pg 53
Pg 37
JACK
U6600/10/20
System Block Diagram
U3700
TRANSLATORS Speaker SYNC_MASTER=WFERRY-WF SYNC_DATE=05/11/2006
A NINEVEH Amps
NOTICE OF PROPRIETARY PROPERTY
A
PG 56 PG 54
E-NET THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Pg 34 AGREES TO THE FOLLOWING
J3400 J3900 J4300
J6701 INTERNAL MIC III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
J6702/03 INTERNAL SPEAKER
J6750/00 LINE IN/OUT
Mini PCI-E E-NET FireWire SIZE DRAWING NUMBER REV.
Audio
AirPort
Pg 33
Conn
Pg 36
Conn
PG 38
Conns
PG 55 APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 2 106
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K36 POWER SYSTEM ARCHITECTURE SMC PWRGD

RN5VD30A-F SMC_RESET_L
04
U5000
D6901 (PAGE 45)
PPDCIN_G3H
02 ENABLE
3.425V G3HOT 03
PBUSB_VSENSE LT3470 PP3V42_G3H_REG
ENRGYSTR LDO
VIN U7790
D SMC_ENRGYSTR_LDO_EN
MAX8719
U7950
D7950
PPVBAT_G3H_CHGR_REG
7A FUSE
PPBUS_G3H
V Q5350 (PAGE 64)
D
SHGN* VOUT 02 CLOCK
(PAGE 66)
PWRGD
VIN
R7302 18 CLK_PWRGD SLG8LP537V
1.05V PP1V05_S0_REG
17 1V05S0_RUNSS
(S0)
ENA1 VOUT1 PP1V05_S0_REG_R U2900
01 CHGR_EN (8A MAX CURRENT) (PAGE 28)
(S5) 1.5VVOUT2
U7970 17 1V5S0_RUNSS
(S0)
ENA2 PP1V5_S0_REG
18
6A FUSE ENABLES (4A MAX CURRENT)
AC ICH8M
ADAPTER
IN
DCIN
A VIN
VOUT
U7975
TPS51124
U7300
(PAGE 61) U2803 CK_PWRGD
PWRBTN*
06-1
SMC_BATT_ISENSE PGOOD1 PGOOD2 VR_PWRGD_CK505 VRMPWRGD

PBUS CONVERTER/ PGOOD_1V5S0 19 29
SMC_DCIN_ISENSE
BATTERY CHARGER A PGOOD_1V05S0
19
PLTRST* PLT_RST_L
27 RSMRST*
ISL6257HRZ SMC_CPU_VSENSE
U7900 01 02
U5300 V PM_SB_PWROK
PWROK CPU_PWRGD
(PAGE 66) CPUVCORE
VIN
VOUT A SMC_CPU_ISENSE PPVCORE_CPU_S0
(36A MAX CURRENT)
24
CPUPWRGD(GPIO49)
U2300 28
ISL9504 25 (PAGE 22)
BATTERY 3S2P CLKEN# VR_PWRGD_CK505_L
IMVP_VR_ON U2801
VR_ON
23 VR_PWRGOOD_DELAY 26 VR_PWRGOOD_DELAY
BATT_POS_F
PGOOD CPU
U7100
C (PAGE 59) Q7000 PWRGOOD C
PP5V_S0_FET 16
RESET*
PPBUS_G3H 4.5V AUDIO
17-1 U1000
P5VS0_EN 15 VINTPS79501
U6201 PP4V5_AUDIO_ANALOG (PAGE 9)
12 Q7865 13 ENA VOUT
(PAGE 53)
ICH RC P5VS3_EN_L
11 Q7860 DELAY (S3) SMC PP5V_S3
PM_S4_STATE_L
CHGR_EN 17 1.25V S0
RC P3V3S3_EN_L P25 LOGIC 1V25S0_RUNSS
DELAY
(S3)
02 P5VS3_EN_L 12 TPS62510
ENA 18
12 U7720 PP1V25_S0_REG
Q7859 VIN 08 VIN VOUT
PM_SLP_S3_L U4900 06 Q7860 07 PP5V_S5_REG PP5V_S5 (PAGE 64)
5VS5_RUNSS ENA1 5V VOUT1
(7.5A MAX CURRENT)
SMC_PM_G2_EN (S5)
PM_SLP_S4_L P60
(S5) PP3V3_S5_REG 08 PP3V3_S5 CRESTLINE 30
(PAGE 45) 3V3S5_RUNSS ENA2 3.3V VOUT2 (5A MAX CURRENT)
(S5) PWROK FSB_CPURST_L
Q7859 07 Q7866 13 1.9V S3
HCPURST*
TPS51120 TPS79501DRB
U7600 PP3V3_S3 VIN 17 U1400
(PAGE 63) U3820 PP1V9_ENET_REG (PAGE 13)
PGOOD1,2 VREG3 PP3V3_ENET_FET
ENA VOUT
(PAGE 35)
RSMRST_PWRGD P3V3S3_EN_L 12
09
1.2V YUKON
VIN U3830 10
B MAX8516 PP1V2_ENET_REG TPS3808-1.25V 22 SMC B
17-1 PM_ENET_EN_L
VOUT 18 PP1V25_S0_FET
MR* U7200 RSMRST_OUT(P15) PM_RSMRST_L
ENA (PAGE 35) ALL_SYS_PWRGD
Q7001 RESET* PWRGD(P12) 99ms DLY
PP3V3_S0_FET 16 SENSE IMVP_VR_ON(P16)
IMVP_VR_ON
23
14 Q3801 (PAGE 58) 09 RSMRST_PWRGD RSMRST_IN(P13)
PLT_RST*
SMC_ONOFF_L
PP3V3ENET_SS Q7004 PWR_BUTTON(P90)
15 P3V3S0_EN 15 PM_PWRBTN_L
P17(BTN_OUT)
P1V8_S0_FET 16 Q3810 BATTERY ONLY: 05
MCH DPLL RST* SMC_RESET_L
TPS731125 P3V3_ENET_FET 16
VIN U2265 18 ADAPTER IN : 10-1
P1V8S0_EN ENA
(PAGE 21) P1V25_S0_NB_DPLL
VOUT
Q3802 15 SLP_S5_L
SLP_S5_L(P95)
PM3V3ENET_SS 15 SLP_S4_L
WOL_EN SLP_S4_L(P94)
PM_ENET_EN_L SLP_S3_L
SMC_ADAPTER_EN 04-1 SLP_S3_L(P93)
PP1V5_S0_REG PGOOD_1V5S0
U4900
19 PGOOD_1V05S0
02 (PAGE 44)
U7870
12 PGOOD_SEQUENCER
VIN VLDOIN
1V8S3_RUNSS 1.8V PP1V8_S3_REG
13 R7502 PP1V8_S3_REG_R
S5 VOUT1
(10.75A MAX CURRENT) RST*
PM_SLP_S3_L S3 0.9V VOUT2 PGOOD_1V8S3 GATE A P5VS0_EN 15
15
PP0V9_S0_REG
18
UVLO_A Power Block Diagram
Q7006 Q7007 14 PP5V_S0_FET UVLO_B GATE B P3V3S0_EN
A RUNSS_GATE_D 15 SYNC_MASTER=POWER SYNC_DATE=06/30/2005
SOFT
START
1V5S0_RUNSS
(S0) 17 TPS51116
U7500
PP3V3_S0_FET UVLO_C
A
(PAGE 62) PP1V8_S0_FET UVLO_D GATE C P1V8S0_EN 15
Q7007 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SOFT 1V05S0_RUNSS 14 PM_SLP_S3_L AGREES TO THE FOLLOWING
START (S0) 17 ENA* GATE D RUNSS_GATE_D
15
02 ISL6130IRZA
Q7006 U7000 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SOFT 1V25S0_RUNSS GPU_VCORE (PAGE 58)
START (S0) 17 VIN ISL6263
SIZE DRAWING NUMBER REV.
U7200 PPVCORE_S0_NB_GFX_IMVP
GFX_VR_EN
20
ENA VOUT
(PAGE 60) (7.7A MAX CURRENT)
21
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 3 106
8 7 6 5 4 3 2 1
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PAGE_BORDER=TRUE
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
BOM OPTION
K36 GOOD K36 BETTER K36 BEST M70 GOOD
BOMOPTION 630-9104 630-9105 630-9106 630-7935
D PVT PVT PVT CONCEPT D
COMMON
>>
>>
>>
>>
ALTERNATE
ARB_ONLY
K36
>
>
>
>>>
LPCPLUS
BOARD STACK-UP AND CONSTRUCTION

INVERTER_BUF BOM OPTION REMOVED BOM OPTION REMOVED BOM OPTION REMOVED
INVERTER_UNBUF BOM OPTION REMOVED BOM OPTION REMOVED BOM OPTION REMOVED
ITP
>
NO_REBOOT_MODE
Top SIGNAL MLB STACKUP NBCFG_DMI_REVERSE
LAYER THICKNESS TRACE WIDTH NBCFG_DMI_X2
2 GROUND (MM) (MM) NBCFG_DYN_ODT_DISABLE
3 SIGNAL(High Speed) CONFORMAL_COAT 0.018 NBCFG_PEG_REVERSE
NBCFG_SDVO_AND_PCIE
4 SIGNAL(High Speed) L1 SIGNAL(TOP) 0.047 0.1 GOOD
>
>
L1-L2 0.07 BETTER
5 GROUND
>
L2 GROUND --- BEST
>>
C 0.014 C
6 POWER K36_PGM
>
>
>
L2-L3 0.076 YUKON_EC
7 POWER L3 SIGNAL 0.014 0.079 YUKON_ULTRA
>>
>
>>
>>
NORMAL
8 GROUND L3-L4 0.156 FANCY
>> >
L4 SIGNAL 0.014 0.079
9 SIGNAL(High Speed) STANDOFF
>>
>>
>>
L4-L5 0.076 ODD_PWR_CORE
10 SIGNAL(High Speed) L5 GND 0.014 ---
ODD_PWR_RESUME
ISL6126
11 GROUND L5-L6 0.07 ISL6130
BOM OPTION
BOM OPTION
REMOVED
REMOVED
BOM OPTION REMOVED BOM OPTION REMOVED
BOM OPTION REMOVED BOM OPTION REMOVED
>
L6 POWER
BOTTOM SIGNAL 0.031 ---
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
L6-L7 0.076
337S3592 1 IC,PDC,SLAPS,PRQ,M0/3M,2.1/0.8G,479FCBGA U1000 CRITICAL GOOD
TABLE_5_ITEM
L7 POWER 0.031 ---

0.07 BOM TABLE FOR HF POSCAPS
TABLE_5_ITEM
337S3576
337S3576
1
1
IC,PDC,SLAPR,PRQ,M0/3M,2.4/0.8G,479FCGBA
IC,PDC,SLAPR,PRQ,M0/3M,2.4/0.8G,479FCBGA
U1000
U1000
CRITICAL
CRITICAL
BETTER
BEST
TABLE_5_ITEM
L7-L8
L8 GROUND 0.014 ---
TABLE_5_HEAD
TABLE_5_ITEM

337S3586 1 IC,PDC,Q7ZF,QS,C0,2.1/0.8G,3M,479FCBGA U1000 CRITICAL GOOD_FUSED
L8-L9
TABLE_5_ITEM
0.076 128S0147 4 HF VERSION OF 128S0057 C4610,C4611,C6830,C6831 CRITICAL K36

TABLE_5_ITEM
B 337S3587 1 IC,PDC,Q7ZF,QS,NON-DTS,M0,2.1/0.8G,3M,479FCBGA U1000 CRITICAL GOOD_NON_DTS

TABLE_5_ITEM
128S0164 3 HF VERSION OF 128S0073 C2130,C2716,C7543 CRITICAL K36

TABLE_5_ITEM
B
337S3561 1 IC,PDC,Q7ZF,QS,C0,2.4/0.8G,3M,479FCBGA U1000 CRITICAL BETTER_FUSED
TABLE_5_ITEM
L9 SIGNAL 0.014 0.1 128S0148 1 HF VERSION OF 128S0085 C6605 CRITICAL K36
TABLE_5_ITEM
337S3561 1 IC,PDC,Q7ZF,QS,C0,2.4/0.8G,3M,479FCBGA U1000 CRITICAL BEST_FUSED

L9-L10 0.156
TABLE_5_ITEM
128S0169 3 HF VERSION OF 128S0111 C7220,C7352,C7542 CRITICAL K36

TABLE_ALT_HEAD
TABLE_5_ITEM
PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
L10 SIGNAL 0.014 0.1 128S0160 2 HF VERSION OF 128S0113 C2173,C2700 CRITICAL K36
TABLE_5_ITEM
TABLE_ALT_ITEM
128S0150 6 HF VERSION OF 128S0115 C6204,C6205,C7651,C7652,C7691,C7692 CRITICAL K36

337S3598
337S3599
337S3592
337S3586
?
?
U1000
U1000
THERMTRIP SCREENED
THERMTRIP SCREENED
TABLE_ALT_ITEM
L10-L11 0.076 128S0157 1 HF VERSION OF 128S0122 C2220 CRITICAL K36
TABLE_5_ITEM
337S3600 337S3576 ? U1000 THERMTRIP SCREENED

TABLE_ALT_ITEM
L11 GROUND 0.014 0.1 128S0162 1 HF VERSION OF 128S0123 C2140 CRITICAL K36
TABLE_5_ITEM
TABLE_5_ITEM
L11-L12 0.07 128S0135 2 HF VERSION OF 128S0129 C6601,C6603 CRITICAL K36

TABLE_ALT_ITEM
337S3604 337S3561 ? U1000 THERMTRIP SCREENED
L12 SIGNAL(BOTTOM)0.047 0.1

CONFORMAL_COAT 0.018
TABLE_5_HEAD
338S0516 1 IC,CRESTLINE,GM965,667 U1400 CRITICAL K36

TABLE_5_ITEM
TOTAL 1.276 ---

TABLE_5_ITEM
338S0434 1 IC,ICH8,BGA U2300 CRITICAL K36

TABLE_5_ITEM
516-0162 2 IN-LINE SODIMM CONNECTOR J3101,J3201 CRITICAL K36

TABLE_5_HEAD
CONFIGURATION OPTIONS
SYNC_MASTER=SMC SYNC_DATE=07/18/2005
A
TABLE_5_ITEM
341S2273
341S2060
1
1
IC,16MBIT 8PIN SPI FLASH ROM,FOR K36A
IC,EEPROM,SERIAL IIC,8KBIT,SO8
U6100
U3780
CRITICAL
CRITICAL
K36_PGM
K36_PGM
TABLE_5_ITEM

A
TABLE_5_ITEM
341S2275 1 IC,SMC,HS8/2116 FOR K36A U4900 CRITICAL K36_PGM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
TABLE_5_ITEM

341S2093 1 IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR U4800 CRITICAL K36_PGM
LOCKED BOOTROM PN 341S2274 FOR K36A II NOT TO REPRODUCE OR COPY IT
TABLE_5_HEAD
D 051-7559
TABLE_5_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM EEE:0PH CRITICAL GOOD H

TABLE_5_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM EEE:0PJ CRITICAL BETTER APPLE INC. SCALE SHT OF
4 106
TABLE_5_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM EEE:0PK CRITICAL BEST NONE
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Revision History 7/10/2007
CSA PAGE 4:
- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.
M70 PROTO TO EVT CHANGES - SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.
- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.
CSA PAGE 8:
- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3.
- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357 CSA PAGE 29:
- ADD CRITICAL TO U2900.
- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO CSA PAGE 44:
- ADD CRITICAL TO U4401.
PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903 CSA PAGE 46:
- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)
- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755 - ADD R4670 & R4671. (USB BYPASS ROUTING).
CSA PAGE 49:
- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD - REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.
CSA PAGE 50:
- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500 - CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.
CSA PAGE 52:
D
- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858
- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888
- ICH8-M ME SMBUS:
- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.´
- THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.
- SMC MANAGEMENT SMBUS CONNECTION:
D
- NO STUFF 3G CONNECTOR CIRCUITRY - ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.´
- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.
- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252) CSA PAGE 59:
-ADD 2ND SMS (U5930).
- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING CSA PAGE 62:
- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.
MICROPHONE THROUGH LVDS CABLE - MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.
CSA PAGE 67:
- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT - REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.
- STUFFED R6740.
- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553 - MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771´ CRITICAL.
CSA PAGE 68:
- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913 - NO STUFFED R6854
CSA PAGE 72:
- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB - CHANGE R7208 FROM 8.66K TO 15.8K.
- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481
7/11/2007
CSA PAGE 9:
M70 EVT TO DVT CHANGES - CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).
CSA PAGE 31:
- STUFF C3110 AND C3111.
3/5/2007 CSA PAGE 32:
- STUFF C3210 AND C3211.
CSA PAGE 8: CSA PAGE 39:
- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS. - UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.
- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN. - REMOVE R5077 (BECOMES R5931).
- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL. CSA PAGE 59:
CSA PAGE 49: - ADD R5930, 10K PU ON SMC_SMS_INT.
- 5040728 STUFF C9421 FOR EMI. - ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.
CSA PAGE 62,66,67,68: - STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.
- SYNC FROM AUDIO TEAM.
CSA PAGE 67:
- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT. 7/12/2007
CSA PAGE 79:
- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558. CSA PAGE 43:
- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).
- UPDATE BOM OPTION TABLE FOR J4300.
3/8/2007 - NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.
CSA PAGE 46:
CSA PAGE 22: - CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).
- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603). - UPDATE BOM OPTION TABLE FOR J4600 AND J4601.
CSA PAGE 25: - NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477.
- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5. CSA PAGE 62:
CSA PAGE 77: - ADD PAGE_TITLE AUDIO: CODEC.
- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0, CSA PAGE 67:
C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF, - CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).
AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A) - UPDATE BOM OPTION TABLE FOR J6700.
C 3/12/2007
- NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479.
- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).
- UPDATE BOM OPTION TABLE FOR J6750.
- NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478.
C
- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP. - CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.
- UPDATE SYMBOL FOR J4501. - UPDATE BOM OPTION TABLE FOR J9401.
CSA PAGE 62,66,67,68: - NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481.
- SYNC FROM AUDIO TEAM.
CSA PAGE 94:
- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K. 7/13/2007
CSA PAGE 4:
3/14/2007 - CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ).
CSA PAGE 38:
CSA PAGE 47: - CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS).
- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY.
CSA PAGE 69:
- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY. 7/17/2007
CSA PAGE 90:
- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH. CSA PAGE 59:
CSA PAGE 94: - UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.
- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.
7/24/2007
M70 DVT TO K36 CHANGES CSA PAGE 4:
- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).
CSA PAGE 22:
6/29/2007 - STUFF R2242 AND NOSTUFF R2247.
CSA PAGE 92:
CSA PAGE 4: - CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.
- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G). - CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.
- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).
- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).
- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M).
- CHANGE SB FROM 338S0427 TO 338S0434.
CSA PAGE 16:
- DISCONNECT GFX_VID<0> TO GND.
K36 EVT TO DVT1 CHANGES
- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.
- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND. 8/9/2007
CSA PAGE 22:
- 5282756 ADD C2207 (0.1UF, 0402). PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.
- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT. - ALL 128S0057 BECOME 128S0147.
- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>. - ALL 128S0073 BECOME 128S0164.
- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>. - ALL 128S0085 BECOME 128S0148.
CSA PAGE 39: - ALL 128S0111 BECOME 128S0169.
- CHANGE J3900 FROM 514S0143 TO 514-0443. - ALL 128S0113 BECOME 128S0160.
- EDIT BOM OPTION TABLE. - ALL 128S0115 BECOME 128S0150.
CSA PAGE 46: - ALL 128S0122 BECOME 128S0157.
- CHANGE U4600 FROM 353S1245 TO 353S1728. - ALL 128S0123 BECOME 128S0162.
B
- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.
- ADD NOSTUFF R4660 AND R4661.
CSA PAGE 47:
- CHANGE J4700 FROM 516S0251 TO 516S0588.
- ALL 128S0129 BECOME 128S0135.
- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.
CSA PAGE 4:
- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.
B
CSA PAGE 69:
- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR. 8/10/2007
CSA PAGE 94:
- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348. CSA PAGE 12:
- C1235 SYMBOL CORRECTED TO REFLECT 20% TOLERANCE.
7/5/2006 CSA PAGE 79:
- CHANGE R7920 FROM 107S0077(EOL) TO 107S0110.
CSA PAGE 4: - CHANGE R7952 FROM 103S0189 TO 103S0200 FOR HF.
- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS).
CSA PAGE 21:
- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE. 8/13/2007
CSA PAGE 27:
- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE. CSA PAGE 34:
CSA PAGE 28: - CHANGE J3400 FROM 516S0406 TO 516S0635 TO ADD ACON AS 2ND SOURCE.
CSA PAGE 46:
- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).
CSA PAGE 48:
CSA PAGE 55:
K36 DVT1 TO DVT2 CHANGES 9/13/2007
- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT. CSA PAGE 52:
- J5550 CHANGES FROM 2PIN TO 4PIN. 8/30/2007 - CHANGE R5280 AND R5281 TO 1K (RDAR:5188703).
- CHANGE J5601 FROM 518S0369 TO 518S0521. CHANGE ALL 138S0578 TO 138S0614 FOR ADDITIONAL VENDORS. - NOSTUFF C9401 FOR EMC (RDAR:5475926).
CSA PAGE 67: (C2205,C4800,C4804,C7305,C7500,C7605,C7902,C7911,C7912)
- CHANGE J6702 FROM 518S0487 TO 518S0519. CSA PAGE 43:
- CHANGE J6703 FROM 518S0369 TO 518S0521. - ADD ALTERNATE TABLE TO MAKE 155S0369 ALTERNATE OF 155S0326. 9/25/2007
- CHANGE J9000 FROM 518S0369 TO 518S0521. - ADD ALTERNATE TABLE TO MAKE 155S0310 ALTERNATE OF 155S0322. CSA PAGE 9:
CSA PAGE 72: - IN BOM TABLE, CHANGE PART NUMBER OF Z0903,Z0904,Z0905 AND Z0921 FROM 860-0876 TO 860-0964.
7/6/2006 - CHANGE C7210 FROM 150PF(131S111) TO 220PF(131S2225). CSA PAGE 73:
- CHANGE C7208 FROM 0.0018UF(132S400) TO 0.001UF(132S0045). - CHANGE L7320 AND L7360 FROM 152S0432 TO 152S0685 TO ADD TDK.
CSA PAGE 8: CSA PAGE 94: CSA PAGE 75:
- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS. - ADD OMIT TO L9405, L9406 AND L9407. - CHANGE L7520 FROM 152S0432 TO 152S0685 TO ADD TDK.
- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN. - ADD BOM TABLE TO CHANGE L9405, L9406 AND L9407 FROM 155S0303 TO 155S0371.
- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N. - ADD ALTERNATE TABLE TO MAKE 155S0370 ALTERNATE OF 155S0348.
- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R. 9/27/2007
CSA PAGE 9:
- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN. 9/3/2007 CSA PAGE 22:
- REMOVE ALIAS FOR =FWPWR_PWRON. - UNSTUFF R2242 AND STUFF R2247.
- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P. CSA PAGE 9:
- ADD SPN ALIASES FOR CK505_PCI2/4_CLK. - NOSTUFF C0930.
CSA PAGE 12: 10/1/2007
- REMOVE R1290 TO R1296 ON CPU_VID<0:6>.
CSA PAGE 13:
- DELETE TEXT NOTE AND WITH RESET BUTTON. K36 DVT2 TO PVT CHANGES CSA PAGE 72:
- CHANGE R7208 FROM 15.8K TO 4.99K 1%.
H
CSA PAGE 15: - CHANGE R7210 FROM 2.94K TO 499 OHM 1%.
A - RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L.
CSA PAGE 25:
- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).
- CHANGE R2514 TO 100K.
9/3/2007
CSA PAGE 73:
SYNC_MASTER=N/A
SYNC_DATE=N/A
A
CSA PAGE 29: - DELETE XW7320.
- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907. - PP1V5_S0_REG_P BECOMES =PP1V5_S0_REG.
- NOSTUFF C2907, C2910, C2916, C2911, C2914. CSA PAGE 76: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM. - DELETE XW7620. PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
- CHANGE R2902 FROM 1OHM TO 0OHM. - PP3V3_S5_REG_P BECOMES =PP3V3_S5_REG. AGREES TO THE FOLLOWING
CSA PAGE 44: - DELETE XW7660.
- REMOVE TEXT NOTE WILL CHANGE TO 606P. - PP5V_S5_REG_P BECOMES =PP5V_S5_REG. I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CSA PAGE 53:
- RE-DRAW CPU VOLTAGE SENSE RC FILTERING. 9/7/2007 II NOT TO REPRODUCE OR COPY IT
CSA PAGE 62:
- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN. CSA PAGE 4: III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1. - CHANGE U1400 FROM 343S0448 TO 338S0516(NB667, PRQ).
- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224). - CHANGE 2.2GHZ CPU FROM 337S3500 TO 337S3502 (2.2GHZ CPU, PRQ).
CSA PAGE 67: - UNCHECK BOM OPTIONS ITP AND LPCPLUS IN TABLE. SIZE DRAWING NUMBER REV.
- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES). CSA PAGE 30:
- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.
- REMOVED DZ6772.
- ADDED R6740 NO STUFF.
CSA PAGE 68:
- ADD BOMOPTION ITP TO R3004 AND R3005.
CSA PAGE 46:
- NOSTUFF U4675,C4675.
- STUFF R4670 AND R4671. APPLE INC.
D 051-7559 H
- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854. CSA PAGE 59: SCALE SHT OF
- ADDED R6856 NO STUFF. - NOSTUFF U5930,C5931,C5932. 5 106
CSA PAGE 71: - NOSTUFF R5931 AND STUFF R5930. NONE
- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
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Functional Test Points

Power Supply NO_TESTs Fan Connectors Battery Digital Connector
NO_TEST
IMVP6_RBIAS FUNC_TEST FUNC_TEST
I93 59A4 59B7
I94 IMVP6_COMP 59A4 59B7 I12 TRUE =PP5V_S0_FAN_RT 7A7 50C4 I1 TRUE SMC_BS_ALRT_L 44C5 45C5 57A2
5VS5_RUNSS I15 TRUE FAN_RT_PWM 50B3 I3 TRUE SMBUS_BATT_SCL_F 57A5

I95
1V5S0_RUNSS
63B5 65C5
I16 TRUE FAN_RT_TACH 50C3 I4 TRUE SMBUS_BATT_SDA_F 57A5
I96 58B1 61B5
TRUE =PP3V3_S0_FAN_RT
D
I157
I158 TRUE SMC_FAN_1_CTL
7C4 50C4
44A8 50B4 I177 TRUE BATT_POS 57B5 D

I159 TRUE SMC_FAN_1_TACH 44A8 50C4 I180 TRUE BATT_NEG 57A5
LPC+ Debug Connector I9

Audio FUNC_TEST
TRUE =PP5V_S0_AUDIO_AMP 7A7 54B8 54C8 54D8
FUNC_TEST I11 TRUE =PP5V_S0_AUDIO 7A7 53A7 56C4
=PP3V42_G3H_LPCPLUS TRUE GND_AUDIO_AMP

I20 TRUE 7B1 46C6
I10
TRUE GND_AUDIO_CODEC
8A4
CLOCK NO_TESTS I19 TRUE

TRUE
=PP5V_S0_LPCPLUS
LPC_AD<0>
7A7 46C6
I21
I22 TRUE ACZ_SDATAIN<0>

8B4
8A5 53C7
NO_TEST I18
LPC_AD<1>
22D4 44C8 46C6
TRUE ACZ_SDATAOUT
I17 TRUE 22D4 44C8 46C6
I24
TRUE ACZ_BITCLK
8A5 53C7
TRUE CK505_CPU0_N TRUE LPC_FRAME_L I23

ACZ_RST_L
8A5 53C7
I111
TRUE CK505_CPU0_P
28C4 29D6 75D3 I71
TRUE PM_CLKRUN_L
22D4 44C8 46B6
I25 TRUE 8A5 53B7
I112
CK505_CPU1_N
28C4 29D6 75D3 I72
BOOT_LPC_SPI_L
24C8 37A5 44C5 46B6
TRUE ACZ_SYNC
I113 TRUE 28C4 29D6 75D3 I73 TRUE 23B5 46B6
I45 8A5 53C7
I115 TRUE CK505_CPU1_P 28C4 29D6 75D3 I74 TRUE SMC_TMS 44B5 45C5 46B6 Battery FUNC_TEST
I114 TRUE CK505_CPU2_ITP_SRC10_N 28C4 29D6 75D3
I75 TRUE DEBUG_RESET_L 27D1 46B6 I29 TRUE SMC_BATT_ISET 44B5 66A8
I116 TRUE CK505_CPU2_ITP_SRC10_P 28C4 29D6 75D3

I76 TRUE SMC_TRST_L 44C1 46B6 I32 TRUE SMC_BATT_CHG_EN 44C8 45B6 66A4
I117 TRUE CK505_DOT96_27M_N 28A4 29B6 75D3 I77 TRUE SMC_TDO 44B5 45C5 46B6 I31 TRUE SMC_BC_ACOK 66A6
44C5 45B6 57C3
I118 TRUE CK505_DOT96_27M_P 28A4 29B6 75D3 I78 TRUE SMC_MD1 44D1 46B6 I33 TRUE SMC_ADAPTER_EN 45B3 57C4
57C7
33C7 35C7 38C6
I119 TRUE CK505_LVDS_N 28B4 29C6 75C3 I79 TRUE SMC_TX_L 41A8 44B8 44C5 45D5 I36 TRUE SMC_BATT_TRICKLE_EN_L 44D5
44C8 45B6
CK505_LVDS_P FWH_INIT_L SYS_ONEWIRE

46B6 66A3
I120 TRUE 28B4 29C6 75D3 I80 TRUE 46C5 I38 TRUE 44B8 45D5 57C8
I81 TRUE PCI_CLK33M_LPCPLUS 29B3 46C4 75C3
TRUE CK505_PCIF1_CLK TRUE LPC_AD<2>

I122 28B6 29B6 75D3 I82
TRUE LPC_AD<3>
22D4 44C8 46C4
USB FUNC_TEST
I83
INT_SERIRQ
22D4 44C8 46C4
TRUE TP_USB_EXCARD_P
TRUE
8B2
I44
CK505_SRC2_N
I84
PM_SUS_STAT_L
24C8 44C8 46B4
TRUE TP_USB_EXCARD_N
TRUE TRUE
8B2
I47
TP_USB_EXTC_P
C TRUE
C
I125 28B4 29C6 75C3 I85 24D5 44C5 46B4
TRUE CK505_SRC2_P TRUE SMC_TDI I46

TP_USB_EXTC_N
8B2
I183 28B4 29C6 75C3 I86
TRUE SMC_TCK
44B5 45C5 46B4
I48 TRUE 8B2
I87
SMC_RESET_L
44B5 45C5 46B4
TRUE USB2_BT_F_P
I88 TRUE 44C3 45D7 46B4
I224
TRUE USB2_BT_F_N
43C2
TRUE CK505_SRC4_N TRUE SMC_NMI I225

USB2_3G_F_N
43C2
I186
TRUE CK505_SRC4_P
28B4 29C6 75C3 I89
TRUE SMC_RX_L
44C1 46B4
I240 TRUE 43A4
I187
CK505_SRC5_N
28B4 29C6 75C3 I91
LINDACARD_GPIO
41A8 44B8 44C5 45D5
46B4 TRUE USB2_3G_F_P
I188 TRUE 28B4 29C6 75C3 I90 TRUE 24A7 24D5 46B4
I241 43A4
I189 TRUE CK505_SRC5_P 28B4 29C6 75C3
TRUE CK505_SRC6_N
I190
I191 TRUE CK505_SRC6_P
28B4 29B6 75C3
28B4 29C6 75C3 Other Func Test Points DC-JACK FUNC_TEST

TRUE ACIN_ENABLE_GATE
FUNC_TEST I57 57C3 66A6
I194 TRUE CK505_SRC8_N 28A4 29B6 75C3 I92 TRUE =PP1V05_S0_REG 7D8 61B8
Battery charger FUNC_TEST
TRUE CK505_SRC8_P
I195
PPVBAT_G3H_CHGR_OUT
28A4 29B6 75C3
I58 TRUE 66B5 66C2
I182
SMBus FUNC_TEST
TRUE SMBUS_SMC_B_S0_SCL 47C5 76C3
INVERTER CONNECTOR FUNC_TEST
I151 TRUE SMBUS_SMC_B_S0_SDA 47C5 76C3
I60 TRUE PPBUS_ALL_INV_CONN 67D3
I59 TRUE INV_GND 67D2

FIREWIRE FUNC_TEST PP5V_INV_F
FIREWARE NO_TESTS I152 TRUE PPFW_SWITCH 38D3
I61
I63
TRUE
TRUE INV_BKLIGHT_PWM_L
67D3
67D2
NO_TEST SLEEP LED FUNC_TEST

TRUE FW_B_TPA_N_SPN MIC FUNC_TEST
I199
FW_B_TPA_P_SPN
8D1
TRUE SYS_LED_ANODE
I200 TRUE 8D1
I155 40C5 45A3
TRUE MIC_HI
I201 TRUE FW_B_TPBIAS_SPN 8D1 SMC FUNC_TEST I221
TRUE MIC_LO
55B3 56A6
TRUE FW_B_TPB_N_SPN I220

MIC_SHIELD
55B3 56A6
B I202
I203 TRUE FW_B_TPB_P_SPN
8D1
8D1
I153 TRUE
TRUE
SMC_LID
SMC_MANUAL_RST_L
42C3 44B5 45C5 57A8 I222 TRUE
MIC_HI_CONN
B
TRUE FW_C_TPA_N_SPN I154
SMC_CPU_VSENSE
45D8
TRUE
TRUE I238 55B1 55D3
I204 8D1
I205 TRUE FW_C_TPA_P_SPN 8D1

I156 44C5 48B1
I237 TRUE MIC_LO_CONN 55B1 55D3
I206 TRUE FW_C_TPBIAS_SPN 8D1 Power Supply FUNC_TEST I239 TRUE MIC_SHLD_CONN 55A1 55D3 56A6
TRUE FW_C_TPB_N_SPN ALL_SYS_PWRGD

I207
TRUE FW_C_TPB_P_SPN
8D1
I160 TRUE 27A5 44D8 58A3
SPEAKER FUNC_TEST
I208 8D1
I161 TRUE PPVCORE_S0_CPU 7D7
TRUE PP1V05_S0_R TRUE SPKRCONN_L_N_OUT

LVDS NO_TESTS I227
7D7 54C1 55C2
I244
I162 TRUE PP1V05_S0 7D7 45D2 I226 TRUE SPKRCONN_L_P_OUT 54C1 55C2
TRUE PP1V5_S0 TRUE SPKRCONN_R_N_OUT

NO_TEST I163
TRUE PP1V8_S0
7C7
7B7
I228
TRUE SPKRCONN_R_P_OUT
54C1 55C2
54D1 55C2
I164 I230
I209 TRUE LVDS_B_CLK_N_SPN 8D5 I169 TRUE PP3V3_S0 7D4 45D1 I229 TRUE SPKRCONN_SUB_N_OUT 54B1 55C2
I210 TRUE LVDS_B_CLK_P_SPN 8D5 I166 TRUE PP5V_S0 7A7 I231 TRUE SPKRCONN_SUB_P_OUT 54B1 55C2
I211 TRUE LVDS_B_DATA_N0_SPN 8D5 I167 TRUE PP1V2_ENET_S0 7B5
I212 TRUE LVDS_B_DATA_N1_SPN 8D5 I168 TRUE PP1V8_S3 7B4

THERMAL FUNC_TEST
I213 TRUE LVDS_B_DATA_N2_SPN 8D5
I214 TRUE LVDS_B_DATA_P1_SPN 8D5 I174 TRUE PP3V3_S3 7A4 I232 TRUE THRM_HEATPIPE_P 49D6
I215 TRUE LVDS_B_DATA_P2_SPN 8D5 I171 TRUE PP5V_S3 7A4 I233 TRUE THRM_HEATPIPE_N 49D6
I172 TRUE PP3V3_S5 7D1 I234 TRUE THRM_DIMM_DX_F_N 49B6
I173 TRUE PP5V_S5 7C1 I235 TRUE THRM_DIMM_DX_F_P 49B6
I175 TRUE PP3V42_G3H 7C1 I242 TRUE THRM_FINSTACK_P 49C6
I176 TRUE PPBUS_G3H 7B1 I243 TRUE THRM_FINSTACK_N 49C6
I178 TRUE PP18V5_G3H

FUNC TEST 1 OF 2
7B1
I181 TRUE PP0V9_S0 7D7
TRUE PP3V3_S3_BT_F
A A
I223 43D2
I236 TRUE GND_BT_F 43C2

NO_TEST AGREES TO THE FOLLOWING
I219 TRUE SMC_FAN_3_TACH 44A4 44A8

APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 7 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
"S0,S0M" RAILS 58D3 58C4 58C3 58B8 58B3 58A3 =PP3V3_S0_FET PP3V3_S0
MIN_LINE_WIDTH=0.6 mm
6A2 45D1 "S5" RAILS
MIN_NECK_WIDTH=0.2 mm
(REGULATOR OUTPUT CPU VCORE PWR) VOLTAGE=3.3V
MAKE_BASE=TRUE
59D1 =PPVORE_S0_CPU_REG PPVCORE_S0_CPU 6B2
MIN_LINE_WIDTH=0.3 mm =PP3V3_S0_NB_VCCHV 15B7 15C7 18B3 20A8 21B7
MIN_NECK_WIDTH=0.3 MM 63B1 =PP3V3_S5_REG PP3V3_S5 6A2
(CPU VCOR PWRE) VOLTAGE=0.9V =PP3V3_S0_NB_FOLLOW 20B2 MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm
=PP3V3_S0_SB_GPIO 22D2 22D7 24B3 24D8 VOLTAGE=3.3V
=PPVCORE_S0_CPU 10B5 10D7 11D7 48B3 48B5 MAKE_BASE=TRUE
(REGULATOR OUTPUT CPU 0.90V PWR) =PP3V3_S0_SB_VCCGLAN3_3 25A6
=PP3V3_S5_SB_PM 27C5
=PP3V3_S0_SB_VCC3_3_PCI
D 62B8 =PP0V9_S0_REG PP0V9_S0
6A2
=PP3V3_S0_SB_VCC3_3_IDE
25B3 26B4
25C3 26B4
=PP3V3_S5_SB_USB
=PP3V3_S5_SB_GPIO
23C8
24D8
D
VOLTAGE=0.9V =PP3V3_S0_SB_VCC3_3_VCCPCORE 25C3 26A6 26C6
(DDR2 TERMINATION 0.9V PWR) MAKE_BASE=TRUE =PP3V3_S5_SB 24A3 24A8 26D8 35C7
=PP3V3_S0_SB_VCC3_3_SATA 25C3 26B8
=PP0V9_S3M_MEM_TERM 32D4 =PP3V3_S5_FET 58C5 65A5 65C4
=PP3V3_S0_SB_VCC3_3_DMI 25C3 26A8
=PP3V3_S5_SB_VCCSUS3_3_USB 25A3 26D2
=PP3V3_S0_SB 26D8 39C8
61B8 6B2 =PP1V05_S0_REG PP1V05_S0 6B2 45D2 =PP3V3_S5_SB_VCCSUS3_3 25A3 26B6 26D2
MIN_LINE_WIDTH=0.6 mm =PP3V3_S0_SB_PM 27B6 27B8
MIN_NECK_WIDTH=0.2 mm =PP3V3_S5_SB_3V3_VCCSUSHDA 25B3 26B2
VOLTAGE=1.05V =PP3V3_S0_RSTBUF 27D4
MAKE_BASE=TRUE =PP3V3_S5_FWLATEVG 38A6 38A8
=PP3V3_S0_AIRPORT 33C6
=PP1V05_S0_SB_CPU_IO 22D2 25C3 26C4
=PP3V3_S0_FW 38C6
=PP3V3_S5_SMBUS_SB_ME 47A7
=PPVCORE_S0_SB 25D3 26D2 =PP3V3_S0_PATA 39C2
=PP3V3_S5_ROM
=PP3V3_S0_SMC_LS 45D4
52C6
61C7 =PP1V05_S0_REG_R PP1V05_S0_R 6B2 =PP3V3_S5_LCD 67C7

MIN_LINE_WIDTH=0.6 mm =PP3V3_S0_LPCPLUS 46C4
MIN_NECK_WIDTH=0.2 mm =PP3V3_S5_SB_CLINK1 24B1
VOLTAGE=1.05V =PP3V3_S0_SMBUS_SB 47D8
MAKE_BASE=TRUE =PP3V3_S5_1V25S0 64B6
=PP3V3_S0_SMBUS_SMC_0_S0 47D5
=PP1V05_S0_CPU 9B5 9B6 9C5 9D5 10C7 11A3 12B3 12C5 =PP3V3_S5_AIRPORT_AUX 33C7 33D6 33D7
=PP3V3_S0_SMBUS_SMC_B_S0 47C5
=PP1V05_S0_NB_PCIE 20D5
=PP3V3_S0_THRM_SNR 49C2 49D2
=PPVCORE_S0_NB 17D3 17D7 20B4 20D8 63B8 =PP5V_S5_REG PP5V_S5 6A2
=PP3V3_S0_FAN_RT 6D2 50C4 MIN_LINE_WIDTH=0.6 mm
=PP1V25R1V05_S0_FSB_NB 13B7 29B6 29C6 MIN_NECK_WIDTH=0.2 mm
=PP3V3_S0_ENET 8A4 VOLTAGE=5V
=PP1V25R1V05_S0_NB_VTT 18D3 20C8 MAKE_BASE=TRUE
=PP3V3_S0_AUDIO 53A7 53D7 55D8 56B5
=PP1V05_S0M_NB_VCCAXM 17B3 17C1 20D8 =PP5V_S5_SB
=PP3V3_S0_IMVP 59D8
26D8
=PP5V_S5_PATA 39D6
=PP3V3_S0_NB_GFX_IMVP 60C7
=PP5V_S5_USB 41C8
64B2 =PP1V25_S0_REG PP1V25_S0 =PP3V3_S0_PDCISENS 60C2 61C5 66C3
MIN_LINE_WIDTH=0.6 mm =PP5V_S5_1V51V05S0
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_LCD 67B5 67B7 67C6
61C4
VOLTAGE=1.25V =PP5V_S5_1V8S30V9S0
MAKE_BASE=TRUE =PP3V3_S0_TMDS 7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8
62C5
=PP5V_S5_PWRCTL
=PP1V25_S0_NB_PLL 7C7 20B4 20D3 =PP3V3_S0_CPUPOWER 48D2
65B6
=PP5V_S5_FET
=PP1V25_S0_NB_VCCDMI =PP3V3_S0_PBATTISENS 66B3
58B3 58C6 58D5 65B5
18C3 20A8
C =PP1V25_S0_SB_DMI
=PP1V25_S0_NB_VCCAXF
25C3 26A6
=PP3V3R1V5_S0_SB_VCCHDA
=PP3V3_S0_SB_PCI
25B3 26C4
23A3
C
20D4
=PP3V3_S0_NB_VCCA_PEG_BG
"G3H" RAILS
18C6 20A6
=PP1V25_S0_NB_PLL 7C7 20B4 20D3
=PPSPD_S0_MEM 30A7 31A3 31A7
=PP1V25_S0_NB_VCC 20A8
=PP3V3_S0MWOL_SB_VCCCL3_3 25A6 26B2
=PP1V25_S0_NB_VCCA 20B8
=PP3V3_S0MWOL_SB_VCCLAN3_3 25A3 26D3
=PP1V25_S0_FET 58A3
=PP3V3_S0MWOL_SB_CLINK0 24C1
=PP3V3_S0_CK505 64C4 =PP3V42_G3H_REG PP3V42_G3H 6A2

28C8 28D3 28D8 29B2 29D2 MIN_LINE_WIDTH=0.3 mm
62C5 61B1 =PP1V5_S0_REG PP1V5_S0 6B2
=PP3V3_S0_NB_VCCSYNC MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm 18D6 21B5 VOLTAGE=3.42V
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_NB MAKE_BASE=TRUE
VOLTAGE=1.5V 69C8
MAKE_BASE=TRUE =PP3V3_S0_TMDS =PP3V42_G3H_SMC 44D4 45C1 45D4 45D8 51B8
7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C2 69C8
=PP1V5_S0_CPU 10B7 11B3 =PP3V42_G3H_SMCVREF 45C8
=PP1V5_S0_NB_TVDAC 21D8
35C1 =PP1V2_ENET_REG PP1V2_ENET_S0 35D1 35B2 =PP1V9_ENET_REG PP1V9_ENET_S0 =PP3V42_G3H_SMBUS_SMC_BSA 47C3
6A2
=PP1V5_S0_SB 26A8 26C8 26D6 MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm =PP3V42_G3H_ACIN 57C4 66A5 66A8 66B8
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
=PP1V5_S0_SB_VCC1_5_A_ARX 25B6 26D5 VOLTAGE=1.2V VOLTAGE=2.5V =PP3V42_G3H_LIDSWITCH 57A8
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP1V5_S0_SB_VCC1_5_A_ATX 25B6 26C6
=PP1V2_ENET_PHY 34D6 =PP1V8_S0_YUKON =PP3V42_G3H_PWRCTL 65C7
36D8
=PP1V5_S0_SB_VCC1_5_A 25B6 26C2 =PP3V42_G3H_SB_RTC 27D7
=PP1V5_S0_SB_VCCUSBPLL 25A6 26B6

PP3V3_ENET_FET =PP3V3_ENET_PHY =PP1V8R2V5_ENET_PHY 34C7 =PP3V42_G3H_SMCUSBMUX 41A6
35D4 34D6
=PP1V5_S0_SB_VCC1_5_A_USB_CORE 25B6 26C2 MIN_LINE_WIDTH=0.6 mm
=PP3V42_G3H_LPCPLUS 6D2 46C6
=PP1V5_S0_AIRPORT VOLTAGE=3.3V
33D2 MAKE_BASE=TRUE
=PP1V5_S0_NB_FOLLOW 21D5
57D1 =PP18V5_G3H_INRUSH PP18V5_G3H 6A2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP1V8_S0_FET PP1V8_S0
58C4 58B8
VOLTAGE=1.8V
MAKE_BASE=TRUE
6B2
"S3" RAILS 57D3 =PPDCIN_G3H

=PP18V5_G3H_CHGR
PPDCIN_G3H
66D8
=PP1V8_S0_NB_LVDS 21C5 62B2

=PP1V8_S3_REG PP1V8_S3 6A2
B =PP1V8_S0_NB_DPLL
=PP1V8_S0_TMDS
21A7
68D6
VOLTAGE=1.8V
MAKE_BASE=TRUE
VOLTAGE=18.5V
MAKE_BASE=TRUE
=PPVIN_G3H_P3V42G3H 64C6
B
=PP1V8_S3_FET 58C5
60C2 =PPVCORE_S0_NB_GFX_IMVP PPVCORE_S0_NB_GFX =PP1V8_S3_MEMVREF 20A5 20A6 66C2 =PPBUSA_G3H PPBUS_G3H 6A2
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm =PP1V8_S3_MEM 30B2 30D4 30D6 31B2 31D4 31D6 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V VOLTAGE=18.5V
MAKE_BASE=TRUE =PP1V8_ENET_P1V8ENETFET 35C3 MAKE_BASE=TRUE
=PPVIN_S0_NB_DPLL
=PPVCORE_S0_NB_GFX 17B7 17D5 21C5 48B3
=PPBUS_S5_FWPWRSW 38D5
62C4 =PP1V8_S3_REG_R PP1V8_S3_MEM_NB =PPVIN_S5_CPU_IMVP 48D7 59C2 59D4 59D8

MIN_NECK_WIDTH=0.4 mm 66C2 =PPBUSB_G3H =PPVIN_S5_NB_GFX_IMVP 60C2
VOLTAGE=1.8V =PPBUS_S5_INV
MAKE_BASE=TRUE 67D4
=PP1V8_S3M_MEM_NB 15D2 17D7 20C8 30D2 31D2 =PPVIN_S5_1V8S30V9S0 62B3
=PP1V8_S3_NB_VCC 20A4 =PPVIN_S5_5VS5 63A6 63B6
=PPVIN_S5_3V3S5 63B3
65C3 65A4 =PP3V3_S3_FET PP3V3_S3 6A2

=PPVIN_S5_1V5S0 61B3
MIN_LINE_WIDTH=0.6 mm =PPVIN_S5_1V05S0
MIN_NECK_WIDTH=0.2 mm 61B5
58D4 58C8 =PP5V_S0_FET PP5V_S0 6A2 VOLTAGE=3.3V =PPVIN_S5_IMVP
MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE 45A6
VOLTAGE=5V =PP3V3_S3_AIRPORT_AUX 33C2
MAKE_BASE=TRUE
=PP3V3_S3_FW 37D5
=PP5V_S0_SB 26D8
=PP3V3_S3_PCI 37C5
=PP5V_S0_SATA 40C6
=PP3V3_S3_BT 43D3
=PP5V_S0_3G 43B5
=PP3V3_S3_SMS 51C7
=PP5V_S0_LPCPLUS 6D2 46C6
=PP3V3_S3_SMBUS_SMC_A_S3 47D3
=PP5V_S0_ISENSECAL 48B8
=PP3V3_S3_PDCISENS
Power Aliases
62A2 62C2
=PP5V_S0_FAN_RT 6D2 50C4
=PP3V3_S3_ENETPWRCTL 35D7
=PP5V_S0_AUDIO 6D1 53A7 56C4
=PP3V3_S3_SMBUS_SMC_MGMT
A
47C3 51B6
=PP5V_S0_AUDIO_AMP SYNC_MASTER=WFERRY SYNC_DATE=06/15/2006
=PP5V_S0_CPU_IMVP
6D1 54B8 54C8 54D8
59D8
=PP3V3_ENET_P3V3ENETFET 35D3

A
=PP5V_S0_NB_GFX_IMVP 60D2
=PP5V_S0_LCD 67D7 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

=PP5V_S0_TMDS 69D7 AGREES TO THE FOLLOWING
=PP5V_S0_NB_TVDAC 21D6 65B4 =PP5V_S3_FET PP5V_S3 6A2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
=PP5V_S0_IDE_RESET 39B7 MIN_NECK_WIDTH=0.2 mm II NOT TO REPRODUCE OR COPY IT
VOLTAGE=5V
MAKE_BASE=TRUE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
=PP5V_S3_SYSLED 40B6 45A4
=PP5V_S3_GEYSER
051-7559
42D6
=PP5V_S3_IR 43D8 D H
=PP5V_S3_CAMERA 67A5
APPLE INC. SCALE SHT OF
NONE 8 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
(EMI PAD FOR INVERTER GONNECTOR)
LVDS ALIASES
67C2 INVT_CHGND ZS0920
1 EMI-SPRING NO-CONNECT UNUSED LVDS INTERFACE PORTS
SATA ALIASES FIREWIRE ALIASES
NO-CONNECT UNUSED SATA INTERFACE PORTS
VOLTAGE=0V CLIP-SM-M42
NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS
MAKE_BASE=TRUE 14C5 LVDS_B_CLK_N LVDS_B_CLK_N_SPN 6A7 22B6 SATA_B_D2R_N SATA_B_D2R_N_SPN
MAKE_BASE=TRUE
43B5 43A5 =GND_CHASSIS_3GPOWER 14C5 LVDS_B_CLK_P LVDS_B_CLK_P_SPNMAKE_BASE=TRUE
6A7 22B6 SATA_B_D2R_P SATA_B_D2R_P_SPN 37B3 FW_B_TPBIAS FW_B_TPBIAS_SPN 6B7
MAKE_BASE=TRUE
14C5 LVDS_B_DATA_N<0> MAKE_BASE=TRUE
LVDS_B_DATA_N0_SPN 6A7 22B6 SATA_B_R2D_C_N SATA_B_R2D_C_N_SPN 37B3 FW_B_TPA_P FW_B_TPA_P_SPNMAKE_BASE=TRUE
6B7
CHASSIS GND
MAKE_BASE=TRUE
14C5 LVDS_B_DATA_N<1> MAKE_BASE=TRUE
LVDS_B_DATA_N1_SPN 6A7 22B6 SATA_B_R2D_C_P SATA_B_R2D_C_P_SPN 37B3 FW_B_TPA_N FW_B_TPA_N_SPNMAKE_BASE=TRUE
6B7
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND 14C5 LVDS_B_DATA_N<2> LVDS_B_DATA_N2_SPN 6A7
SATA_C_D2R_N SATA_C_D2R_N_SPN 37B3 FW_B_TPB_P FW_B_TPB_P_SPN 6B7
MAKE_BASE=TRUE 22B6
15C6 TP_LVDS_B_DATAN3 LVDS_B_DATA_N3_SPN SATA_C_D2R_P SATA_C_D2R_P_SPN
MAKE_BASE=TRUE 37B3 FW_B_TPB_N FW_B_TPB_N_SPNMAKE_BASE=TRUE
6B7
22B6
OMIT MAKE_BASE=TRUE
37B3 FW_C_TPBIAS
MAKE_BASE=TRUE
FW_C_TPBIAS_SPN
GND_CHASSIS_IO Z0906 D
MAKE_BASE=TRUE
LVDS_B_DATA_P<0> LVDS_B_DATA_P0_SPN SATA_C_R2D_C_N SATA_C_R2D_C_N_SPN 6B7
D
22B6
FW_C_TPA_P_SPNMAKE_BASE=TRUE
14C5
MAKE_BASE=TRUE 37B3 FW_C_TPA_P
5R2P3-7SQBNP 14C5 LVDS_B_DATA_P<1> MAKE_BASE=TRUE
LVDS_B_DATA_P1_SPN 6A7 22B6 SATA_C_R2D_C_P SATA_C_R2D_C_P_SPN 6B7
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 37B3 FW_C_TPA_N FW_C_TPA_N_SPN 6B7
=GND_BATT_CHGND 1 LVDS_B_DATA_P<2> LVDS_B_DATA_P2_SPN
57A6 14C5 6A7
37B3 FW_C_TPB_P FW_C_TPB_P_SPNMAKE_BASE=TRUE
PCI_EXP ALIASES
MAKE_BASE=TRUE 6B7
=GND_CHASSIS_AUDIO_JACK TP_LVDS_B_DATAP3 LVDS_B_DATA_P3_SPN
55C3 15C6
MAKE_BASE=TRUE 37B3 FW_C_TPB_N FW_C_TPB_N_SPNMAKE_BASE=TRUE
6B7
56A4 =GND_CHASSIS_AUDIO_MIC MAKE_BASE=TRUE
15C6 TP_LVDS_A_DATAP3 LVDS_A_DATA_P3_SPN NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS
30A5 =GND_CHASSIS_DIPDIMM_LEFT MAKE_BASE=TRUE
15C6 TP_LVDS_A_DATAN3 LVDS_A_DATA_N3_SPN
MAKE_BASE=TRUE 23D5 TP_PCIE_A_D2R_N PCIE_A_D2R_N_SPN
MAKE_BASE=TRUE
23D5 TP_PCIE_A_D2R_P PCIE_A_D2R_P_SPN
MAKE_BASE=TRUE
23D5 TP_PCIE_A_R2D_C_N PCIE_A_R2D_C_N_SPN
PCI_EXPRESS GRAPHICS ALIASES 23D5 TP_PCIE_A_R2D_C_P
MAKE_BASE=TRUE
PCIE_A_R2D_C_P_SPN
NO-CONNECT UNUSED SDVO INTERFACE PORTS 23D5 TP_PCIE_B_D2R_N PCIE_B_D2R_N_SPN MAKE_BASE=TRUE
SATA,LVDS CONNECTOR CHASSIS GND 14D3 PEG_D2R_N<0> PEG_D2R_N0_SPN 23D5 TP_PCIE_B_D2R_P PCIE_B_D2R_P_SPN MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB PORT [0] = External USB2.0 Port A
GND_CHASSIS_SATA OMIT 14D3 PEG_D2R_N<2> PEG_D2R_N2_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_B_R2D_C_N PCIE_B_R2D_C_N_SPN 41A8 =USB2_EXTA_P USB2_EXTA_P USB_EXTA_P 23C2 73B3
VOLTAGE=0V
40C8
Z0907 14D3 PEG_D2R_N<3> PEG_D2R_N3_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_B_R2D_C_P
MAKE_BASE=TRUE
PCIE_B_R2D_C_P_SPN 41A8 =USB2_EXTA_N
MAKE_BASE=TRUE
USB2_EXTA_N USB_EXTA_N 23C2 73B3
MAKE_BASE=TRUE 6P5R2P6-7SQB PEG_D2R_N<4> PEG_D2R_N4_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_EXCARD_D2R_N PCIE_C_D2R_N_SPN MAKE_BASE=TRUE 41C8 =EXTAUSB_OC_L
MAKE_BASE=TRUE
EXTAUSB_OC_L USB_EXTA_OC_L 23C8
67B2 67A6 67A4 67A2 =GND_CHASSIS_LVDS 1 14D3
PEG_D2R_N<5> PEG_D2R_N5_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_EXCARD_D2R_P PCIE_C_D2R_P_SPN

14D3
1 C0907
0.1UF
1 C0908
0.01UF
14D3 PEG_D2R_N<6> PEG_D2R_N6_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
PCIE_C_R2D_C_N_SPN
MAKE_BASE=TRUE 33B3 =USB2_AIRPORT_P
USB PORT [1] = PCI-E Mini Card
USB2_AIRPORT_P USB_MINI_P 23C2 73B3
10% 10% 14D3 PEG_D2R_N<7> PEG_D2R_N7_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_EXCARD_R2D_C_P PCIE_C_R2D_C_P_SPN MAKE_BASE=TRUE
33B3 =USB2_AIRPORT_N USB2_AIRPORT_N USB_MINI_N
16V
2 X5R 16V
2 CERM 14D3 PEG_D2R_N<8> PEG_D2R_N8_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_FW_D2R_N PCIE_D_D2R_N_SPN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
23C2 73B3
402 402 PEG_D2R_N<9> PEG_D2R_N9_SPN

MAKE_BASE=TRUE
23D5 TP_PCIE_FW_D2R_P PCIE_D_D2R_P_SPN MAKE_BASE=TRUE
14D3
MAKE_BASE=TRUE USB PORT [2] = 3G USB
14C3 PEG_D2R_N<10> PEG_D2R_N10_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_FW_R2D_C_N PCIE_D_R2D_C_N_SPN
43A4
=USB2_3G_P USB2_3G_P USB_EXTD_P 23C2
MAKE_BASE=TRUE
PEG_D2R_N<11> PEG_D2R_N11_SPN MAKE_BASE=TRUE 23D5 TP_PCIE_FW_R2D_C_P PCIE_D_R2D_C_P_SPN =USB2_3G_N USB2_3G_N MAKE_BASE=TRUE USB_EXTD_N 23C2
DCIN CONNECTOR CHASSIS GND OMIT 14C3
PEG_D2R_N<12> PEG_D2R_N12_SPN MAKE_BASE=TRUE

MAKE_BASE=TRUE 43A4
MAKE_BASE=TRUE
GND_CHASSIS_DCIN Z0902 14C3
PEG_D2R_N<13> PEG_D2R_N13_SPN MAKE_BASE=TRUE

VOLTAGE=0V USB PORT [3] = CAMERA
=GND_DCIN_CHGND
MAKE_BASE=TRUE 7X7R2P3-5B
1
14C3
14C3 PEG_D2R_N<14> PEG_D2R_N14_SPN MAKE_BASE=TRUE CLOCK ALIASES 67B4 =USB2_CAMERA_P USB2_CAMERA_P USB_CAMERA_P 23C2 73B3
57C8
14C3 PEG_D2R_N<15> PEG_D2R_N15_SPN MAKE_BASE=TRUE NO-CONNECT UNUSED CLOCK INTERFACE PORTS MAKE_BASE=TRUE
67A4 =USB2_CAMERA_N USB2_CAMERA_N USB_CAMERA_N 23C2 73B3
=GND_CHASSIS_RJ45 NOSTUFF
PEG_D2R_P<0> PEG_D2R_P0_SPN MAKE_BASE=TRUE TP_CK505_SRC1_N CK505_SRC1_N_SPN
C0930
28B4 MAKE_BASE=TRUE
C
1
C
36B2 14C3
PEG_D2R_P<2> PEG_D2R_P2_SPN MAKE_BASE=TRUE TP_CK505_SRC1_P CK505_SRC1_P_SPN MAKE_BASE=TRUE

=GND_CHASSIS_TMDS_UPPER 0.1UF 14C3
28B4
TP_CK505_SRC3_N CK505_SRC3_N_SPN
MAKE_BASE=TRUE
USB PORT [4] = IR CONTROLLER
69C4 69A4
10%
16V 14C3 PEG_D2R_P<3> PEG_D2R_P3_SPN MAKE_BASE=TRUE 28B4
2 X5R
PEG_D2R_P<4> PEG_D2R_P4_SPN MAKE_BASE=TRUE 28B4 TP_CK505_SRC3_P CK505_SRC3_P_SPN MAKE_BASE=TRUE 43C4 =USB2_IR_P
73B3 23C2
8C1 USB_IR_P USB_IR_P 8C2 23C2 73B3
402 14C3
14C3 PEG_D2R_P<5> PEG_D2R_P5_SPN

MAKE_BASE=TRUE 28B4 TP_CK505_SRC7_N CK505_SRC7_N_SPN MAKE_BASE=TRUE 43C4 =USB2_IR_N USB_IR_N MAKE_BASE=TRUE USB_IR_N 8C2 23C2 73B3
MAKE_BASE=TRUE
14C3 PEG_D2R_P<6> PEG_D2R_P6_SPN MAKE_BASE=TRUE 28B4 TP_CK505_SRC7_P CK505_SRC7_P_SPN MAKE_BASE=TRUE
I/O CONNECTOR CHASSIS GND OMIT 14C3 PEG_D2R_P<7> PEG_D2R_P7_SPN MAKE_BASE=TRUE 75D3 28B6 CK505_PCI2_CLK MAKE_BASE=TRUE
CK505_PCI2_CLK_SPN USB PORT [5] = Trackpad(Geyser)
MAKE_BASE=TRUE
GND_CHASSIS_IO CK505_PCI4_CLK CK505_PCI4_CLK_SPN
VOLTAGE=0V Z0908 8D7 14C3 PEG_D2R_P<8> PEG_D2R_P8_SPN MAKE_BASE=TRUE
PEG_D2R_P9_SPN MAKE_BASE=TRUE
75D3 28B6
=ENET_CLKREQ_L ENET_CLKREQ_L
MAKE_BASE=TRUE
42C7 =USB2_GEYSER_P
42C7 =USB2_GEYSER_N
USB2_GEYSER_P
MAKE_BASE=TRUE
USB_TPAD_P
USB_TPAD_N
23C2 73B3
MAKE_BASE=TRUE 5P0R2P3-7BLB 14C3 PEG_D2R_P<9> 34B8 28A4

MAKE_BASE=TRUE
USB2_GEYSER_N
MAKE_BASE=TRUE
23C2 73B3
1 14C3 PEG_D2R_P<10> PEG_D2R_P10_SPN MAKE_BASE=TRUE

=GND_CHASSIS_FW_DOWN PEG_D2R_P<11> PEG_D2R_P11_SPN MAKE_BASE=TRUE USB PORT [6] = BLUETOOTH
38B1
=GND_CHASSIS_USB
1 C0910 1 C0911 14C3
PEG_D2R_P12_SPN MAKE_BASE=TRUE
73B3 23C2
41C4 41C2 41A4 41A2
0.1UF
10%
0.01UF 10%
14C3 PEG_D2R_P<12>
PEG_D2R_P<13> PEG_D2R_P13_SPN MAKE_BASE=TRUE SB ALIASES 43C3 =USB2_BT_P
43C3 =USB2_BT_N
8C1 USB_BT_P
MAKE_BASE=TRUE
USB_BT_N
USB_BT_P
USB_BT_N
8C2 23C2 73B3
8B2 23C2 73B3

2 16V 2 16V
14C3
X5R CERM PEG_D2R_P<14> PEG_D2R_P14_SPN MAKE_BASE=TRUE NO-CONNECT UNUSED CLOCK INTERFACE PORTS MAKE_BASE=TRUE
402 402 14C3
14C3 PEG_D2R_P<15> PEG_D2R_P15_SPN MAKE_BASE=TRUE 24C5 VR_PWRGD_CLKEN VR_PWRGD_CK505 27A8

USB PORT [7] = External USB2.0 Port B
PEG_R2D_C_N<4> PEG_R2D_C_N4_SPNMAKE_BASE=TRUE MAKE_BASE=TRUE 41B5 =USB2_EXTB_P USB2_EXTB_P USB_EXTB_P 23C2
DIP DIMM CONNECTOR CHASSIS GND =SB_CLINK_MPWROK CLINK_MPWROK 73B3
OMIT 14B3
24C3 8B1 27A6 MAKE_BASE=TRUE
GND_CHASSIS_CENTER Z0910 PEG_R2D_C_N<5> PEG_R2D_C_N5_SPNMAKE_BASE=TRUE MAKE_BASE=TRUE 41B5 =USB2_EXTB_N USB2_EXTB_N USB_EXTB_N 23C2
14B3
MAKE_BASE=TRUE
24C5 SB_SATA_CLKREQ_L SB_CLK100M_SATA_OE_L 28B4 MAKE_BASE=TRUE
73B3
VOLTAGE=0V
MAKE_BASE=TRUE 5R2P3-7SQB 14B3 PEG_R2D_C_N<6> PEG_R2D_C_N6_SPN 24C5 24B5 EXTGPU_RST_L TP_SB_GPIO17
MAKE_BASE=TRUE 41C8 =EXTBUSB_OC_L EXTBUSB_OC_L
MAKE_BASE=TRUE
USB_EXTB_OC_L 23C8
31A5 30D5 =GND_CHASSIS_DIPDIMM_CENTER 1 14B3 PEG_R2D_C_N<7> PEG_R2D_C_N7_SPNMAKE_BASE=TRUE MAKE_BASE=TRUE
PEG_R2D_C_N<8> PEG_R2D_C_N8_SPNMAKE_BASE=TRUE USB PORT [8] = Unused

1 C0916 1 C0917
0.1UF 0.01UF
14B3
14B3 PEG_R2D_C_N<9> PEG_R2D_C_N9_SPNMAKE_BASE=TRUE SO-DIMM ALIASES 6C1

TP_USB_EXCARD_P USB_EXCARD_P 23C2 73B3
10% 10% PEG_R2D_C_N<10> PEG_R2D_C_N10_SPN MAKE_BASE=TRUE NO-CONNECT UNUSED ADDRESS INTERFACE PORTS MAKE_BASE=TRUE
2 16V
TP_USB_EXCARD_N USB_EXCARD_N
2 16V
14B3 23C2 73B3
X5R CERM PEG_R2D_C_N<11> PEG_R2D_C_N11_SPN MAKE_BASE=TRUE
MEM_A_A<15> MEM_A_A15_SPN
6C1
402 402 14B3
MAKE_BASE=TRUE
30C4 MAKE_BASE=TRUE
14B3 PEG_R2D_C_N<12> PEG_R2D_C_N12_SPN 31C4 MEM_B_A<15> MEM_B_A15_SPN MAKE_BASE=TRUE USB PORT [9] = Unused
MAKE_BASE=TRUE
PEG_R2D_C_N<13> PEG_R2D_C_N13_SPN TP_MEM_CLKP2 MEM_CLK_P_2_SPNMAKE_BASE=TRUE TP_USB_EXTC_P USB_EXTC_P
DIP DIMM CONNECTOR CHASSIS GND
23C2 73B3
14B3 15C6
6C1
OMIT PEG_R2D_C_N<14> PEG_R2D_C_N14_SPN MAKE_BASE=TRUE
TP_MEM_CLKN2 MEM_CLK_N_2_SPNMAKE_BASE=TRUE MAKE_BASE=TRUE
GND_CHASSIS_RIGHT Z0909
14B3
MAKE_BASE=TRUE
15C6
TP_USB_EXTC_N USB_EXTC_N 23C2 73B3
PEG_R2D_C_N<15> PEG_R2D_C_N15_SPN 15C6 TP_MEM_CLKP5 MEM_CLK_P_5_SPNMAKE_BASE=TRUE 6C1
5R2P3-7SQB
14B3 MAKE_BASE=TRUE
VOLTAGE=0V
B 31D4 =GND_CHASSIS_DIPDIMM_RIGHT MAKE_BASE=TRUE 1 14B3
14B3
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P4_SPNMAKE_BASE=TRUE
PEG_R2D_C_P5_SPNMAKE_BASE=TRUE
15C6 TP_MEM_CLKN5 MEM_CLK_N_5_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUE
ANALOG SWITCH GPIO B
1 C0914 1 C0915 14B3 PEG_R2D_C_P<6> PEG_R2D_C_P6_SPN
MAKE_BASE=TRUE 44B8 15B7 PM_EXTTS_L<0>
MAKE_BASE=TRUE
DIMM_OVERTEMPA_L 30C4
0.1UF
10%
0.01UF
10% 14B3 PEG_R2D_C_P<7> PEG_R2D_C_P7_SPNMAKE_BASE=TRUE 44B8 15B7 PM_EXTTS_L<1>
MAKE_BASE=TRUE
DIMM_OVERTEMPB_L 31C4
16V
2 X5R 16V
2 CERM PEG_R2D_C_P<8> PEG_R2D_C_P8_SPNMAKE_BASE=TRUE
402 402
14B3
14B3 PEG_R2D_C_P<9> PEG_R2D_C_P9_SPNMAKE_BASE=TRUE NB ALIASES

MAKE_BASE=TRUE =GFX_VR_EN GFX_VR_EN
PEG_R2D_C_P<10> PEG_R2D_C_P10_SPN 15B3 60C6
OMIT
Z0901
OMIT
Z0911
14B3
14B3 PEG_R2D_C_P<11> PEG_R2D_C_P11_SPN MAKE_BASE=TRUE XW0801

SM
15A3 =NB_CLINK_MPWROK CLINK_MPWROK MAKE_BASE=TRUE
8B3 27A6
MAKE_BASE=TRUE =NB_CLK96M_DOT_P NB_CLK96M_DOT_P MAKE_BASE=TRUE
5R2P3-7SQBNP 5R2P3-7B 14A3 PEG_R2D_C_P<12> PEG_R2D_C_P12_SPN 56B4 56B1 56A8 56A4 55B3
53D3 53B7 53A7 =GND_AUDIO_CODEC 6D1 GND_AUDIO_CODEC 1 2
15C3
=NB_CLK96M_DOT_N MAKE_BASE=TRUE
29B3 75B3
GND_CHASSIS_CPU GND_CHASSIS_FANSCREW PEG_R2D_C_P<13> PEG_R2D_C_P13_SPN MAKE_BASE=TRUE 54C8 54B8 54A8 NB_CLK96M_DOT_N

1 1
XW0802
56C4 56B8 56B5 MAKE_BASE=TRUE 15C3 29B3 75B3
14A3
15C3 =NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_P MAKE_BASE=TRUE
MAKE_BASE=TRUE 29C3 75B3
14A3 PEG_R2D_C_P<14> PEG_R2D_C_P14_SPN SM 15C3 =NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_N MAKE_BASE=TRUE
29C3 75B3
14A3 PEG_R2D_C_P<15> PEG_R2D_C_P15_SPN MAKE_BASE=TRUE
54C8 54B8 54A8 54A5 =GND_AUDIO_AMP 6D1 GND_AUDIO_AMP 1 2 19D2 =NB_TDE_SENSE
MAKE_BASE=TRUE
1 C0912
0.1UF
1 C0913
0.01UF
1 C0918
0.1UF 1 C0919
19C2 =NB_TDE_FORCE
10% 10% 10% 0.01UF 19C2 =NB_TDB_FORCE
2 16V
X5R 2 16V
CERM 2 16V
X5R
10%
16V 19C2 =NB_TDB_SENSE
402 402 402 2 CERM 73C3 22C8 HDA_BIT_CLK ACZ_BITCLK 6C1 53C7
402 73C3 22C8 HDA_SYNC ACZ_SYNC MAKE_BASE=TRUE
6C1 53C7
Ethernet ALIASES
MAKE_BASE=TRUE
HDA_RST_L ACZ_RST_L TABLE_5_HEAD
CPU HEATSINK STANDOFF SCREW HOLE

73C3 22C8 6C1 53B7
MAKE_BASE=TRUE
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
73C3 22C8 HDA_SDIN0 ACZ_SDATAIN<0> 6D1 53C7 TABLE_5_ITEM
OMIT OMIT 73B3 22B8 HDA_SDOUT ACZ_SDATAOUT MAKE_BASE=TRUE

6D1 53C7
860-0964 4 THERMAL STANDOFF Z0903,Z0904,Z0905,Z0921 STANDOFF
Z0903 Z0904 MAKE_BASE=TRUE
860-0723 1 STANDOFF WIRELESS Z0912 STANDOFF
TABLE_5_ITEM
STDOFF-4.2OD3.95H-5.52R3.37-6B STDOFF-4.2OD3.95H-5.52R3.37-7SQB 22C8 TP_HDA_SDIN1 HDN_SDIN1_SPN 7C4 =PP3V3_S0_ENET =ENET_VMAIN_AVLBL 34C2 TABLE_5_ITEM
MAKE_BASE=TRUE
NB_RIGHT_DOWN_SCREW 1 CPU_THERMAL_SCREW_UP1 22C8 TP_HDA_SDIN2 HDN_SPIN2_SPN 860-0749 1 STANDOFF W/THRU HOLES,WIRELESS Z0913 STANDOFF
MAKE_BASE=TRUE 34C7 =YUKON_EC_PP2V5_ENET
TP_HDA_SDIN3 HDN_SPIN3_SPN
1
R0912 1
R0910 22C8
MAKE_BASE=TRUE
0 0 SIGNAL ALIAS /RESET
5%
1/16W
5%
Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL
1/16W NB CFG ALIASES
A MF-LF
2402
FOR LAYOUT PLACEMENT
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL 2
MF-LF
402
NB_CFG<3> TP_NB_CFG<3>
SYNC_MASTER=GPU

SYNC_DATE=07/17/2006
A
OMIT OMIT 15B6
MAKE_BASE=TRUE
AIRPORT CARD STANDOFF SCREW HOLE
Z0905 Z0921 15B6 NB_CFG<4> TP_NB_CFG<4>
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
STDOFF-4.5OD3.95H-1.1-3.2-TH STDOFF-4.5OD3.95H-1.1-3.2-TH 15B6 NB_CFG<6> TP_NB_CFG<6>

MAKE_BASE=TRUE
CPU_THERMAL_SCREW_RIGHT 15B6 NB_CFG<7> TP_NB_CFG<7>
1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CPU_THERMAL_SCREW_DOWN
1 NB_CFG<8> TP_NB_CFG<8>
MAKE_BASE=TRUE
OMIT OMIT
Z0912 Z0913
15B6
1
R0911
1
R0921 MAKE_BASE=TRUE
STDOFF-4.2OD2.15H-1.2-3.2-TH
STDOFF-4.2OD3.95H-5.52R3.37-6B
0 0
5% GND_CHASSIS_IO1
5%
1/16W
1/16W
MF-LF
VOLTAGE=0V
MAKE_BASE=TRUE NC 1 NC 1 SIZE DRAWING NUMBER REV.
MF-LF
2402
2402
69A3 =GND_CHASSIS_TMDS_DOWN
=GND_CHASSIS_FW_UPPER APPLE INC.

D 051-7559 H
38B1 SCALE SHT OF
NONE 9 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
OMIT
70C3 13D3 BI FSB_A_L<3> J4 A3* U1000 ADS* H1 FSB_ADS_L BI 13C3 70D3
70C3 13D3 BI FSB_A_L<4> L5 A4* MEROM BNR* E2 FSB_BNR_L BI 13C3 70D3
70C3 13D3 BI FSB_A_L<5> L4 A5* FCBGA

BPRI* G5 FSB_BPRI_L BI 13C3 70D3
1 OF 4
70C3 13D3 BI FSB_A_L<6> K5 A6*
=PP1V05_S0_CPU 7C7 9B5 9B6 9C5 10C7 11A3 12B3 12C5
70C3 13D3 BI FSB_A_L<7> M3 A7* DEFER* H5 FSB_DEFER_L BI 13B3 70D3
70C3 13D3 BI FSB_A_L<8> N2 A8* DRDY* F21 FSB_DRDY_L BI 13B3 70D3

1
70C3 13D3 FSB_A_L<9> J1 A9* DBSY* E1 FSB_DBSY_L 13B3 70D3
R1002 PLACE TESTPOINT ON
BI BI 54.9
70C3 13D3 BI FSB_A_L<10> N3 A10* 1% FSB_IERR_L WITH A GND
ADDR GROUP0
1/16W
70C3 13D3 BI FSB_A_L<11> P5 A11* BR0* F1 FSB_BREQ0_L BI 13B3 70D3 MF-LF 0.1" AWAY
2 402
D
CONTROL
D 70C3 13D3 BI FSB_A_L<12> P2 A12*
70C3 13D3 BI FSB_A_L<13> L2 A13* IERR* D20 70C3 CPU_IERR_L
70C3 13D3 BI FSB_A_L<14> P4 A14* INIT* B3 CPU_INIT_L IN 22C4 46B2 70B3
70C3 13D3 BI FSB_A_L<15> P1 A15*

70C3 13C3 BI FSB_A_L<16> R1 A16* LOCK* H4 FSB_LOCK_L BI 13B3 70D3
70C3 13C3 BI FSB_ADSTB_L<0> M1 ADSTB0*
RESET* C1 FSB_CPURST_L IN 12B5 13A5 70D3
70C3 13A3 BI FSB_REQ_L<0> K3 REQ0* RS0* F3 FSB_RS_L<0> IN 13A3 70D3
70C3 13A3 BI FSB_REQ_L<1> H2 REQ1* RS1* F4 FSB_RS_L<1> IN 13A3 70D3
70C3 13A3 BI FSB_REQ_L<2> K2 REQ2* RS2* G3 FSB_RS_L<2> IN 13A3 70D3
70C3 13A3 BI FSB_REQ_L<3> J3 REQ3* TRDY* G2 FSB_TRDY_L IN 13B3 70D3
70C3 13A3 BI FSB_REQ_L<4> L1 REQ4*

OMIT
HIT* G6 FSB_HIT_L BI 13B3 70D3
=PP1V05_S0_CPU 7C7 9B5 9B6 9D5 10C7 11A3 12B3 12C5
70C3 13C3 BI FSB_A_L<17> Y2 A17* HITM* E4 FSB_HITM_L BI 13B3 70D3 70D3 13D5 BI FSB_D_L<0> E22 D0* U1000 D32* Y22 FSB_D_L<32> BI 13C5 70C3
70C3 13C3 BI FSB_A_L<18> U5 A18* 70D3 13D5 BI FSB_D_L<1> F24 D1* MEROM D33* AB24 FSB_D_L<33> BI 13C5 70C3
70C3 13C3 BI FSB_A_L<19> R3 A19* BPM0* AD4 XDP_BPM_L<0> BI 12B2 70A3

1 70D3 13D5 BI FSB_D_L<2> E26 D2* FCBGA D34* V24 FSB_D_L<34> BI 13C5 70C3
70C3 13C3 BI FSB_A_L<20> W6 A20* BPM1* AD3 XDP_BPM_L<1> BI 12B2 70A3

R1003 70D3 13D5 BI FSB_D_L<3> G22 D3* D35* V26 FSB_D_L<35> BI 13C5 70C3
54.9 2 OF 4
FSB_A_L<21> XDP_BPM_L<2> FSB_D_L<4> FSB_D_L<36>
XDP/ITP SIGNALS
70C3 13C3 BI U4 A21* BPM2* AD1 BI 12B2 70A3 1% 70D3 13D5 BI F23 D4* D36* V23 BI 13C5 70C3
1/16W
ADDR GROUP1
70C3 13C3 BI FSB_A_L<22> Y5 A22* BPM3* AC4 XDP_BPM_L<3> BI 12B3 70A3 MF-LF 70D3 13D5 BI FSB_D_L<5> G25 D5* D37* T22 FSB_D_L<37> BI 13C5 70C3
402
70C3 13C3 BI FSB_A_L<23> U1 A23* PRDY* AC2 XDP_BPM_L<4> BI 12B2 70A3
2
70D3 13D5 BI FSB_D_L<6> E25 D6* D38* U25 FSB_D_L<38> BI 13C5 70C3
70C3 13C3 BI FSB_A_L<24> R4 A24* PREQ* AC1 XDP_BPM_L<5> BI 12B2 70A3 70D3 13D5 BI FSB_D_L<7> E23 D7* D39* U23 FSB_D_L<39> BI 13B5 70C3
70C3 13C3 BI FSB_A_L<25> T5 A25* TCK AC5 XDP_TCK IN 9A7 12B2 12B3 70B3 70D3 13D5 BI FSB_D_L<8> K24 D8* D40* Y25 FSB_D_L<40> BI 13B5 70C3
70C3 13C3 BI FSB_A_L<26> T3 A26* TDI AA6 XDP_TDI IN 9B7 12B3 70B3 70D3 13D5 BI FSB_D_L<9> G24 D9* D41* W22 FSB_D_L<41> BI 13B5 70C3
DATA GRP 0
DATA GRP 2
70C3 13C3 BI FSB_A_L<27> W2 A27* TDO AB3 XDP_TDO OUT 9A7 12B5 70B3 70D3 13D5 BI FSB_D_L<10> J24 D10* D42* Y23 FSB_D_L<42> BI 13B5 70C3
70C3 13C3 BI FSB_A_L<28> W5 A28* TMS AB5 XDP_TMS IN 9B7 12B2 70B3 70D3 13D5 BI FSB_D_L<11> J23 D11* D43* W24 FSB_D_L<43> BI 13B5 70C3
FSB_A_L<29> A29* TRST* XDP_TRST_L FSB_D_L<12> D12* D44* FSB_D_L<44>

C
Y4 AB6 H22 W25
C
70C3 13C3 BI IN 9A7 12B3 70A3 70D3 13D5 BI BI 13B5 70C3
70C3 13C3 BI FSB_A_L<30> U2 A30* DBR* C20 XDP_DBRESET_L OUT 12B4 27C6
1 70D3 13C5 BI FSB_D_L<13> F26 D13* D45* AA23 FSB_D_L<45> BI 13B5 70C3
70C3 13C3 BI FSB_A_L<31> V4 A31* R1004 70D3 13C5 BI FSB_D_L<14> K22 D14* D46* AA24 FSB_D_L<46> BI 13B5 70C3
68
70C3 13C3 BI FSB_A_L<32> W3 A32* 5% 70D3 13C5 BI FSB_D_L<15> H23 D15* D47* AB25 FSB_D_L<47> BI 13B5 70C3
1/16W
70C3 13C3 FSB_A_L<33> AA4 A33* THERMAL MF-LF 70D3 13B3 FSB_DSTB_L_N<0> J26 DSTBN0* DSTBN2* Y26 FSB_DSTB_L_N<2> 13B3 70C3
BI BI BI
FSB_A_L<34> 2 402 FSB_DSTB_L_P<0> FSB_DSTB_L_P<2>
70C3 13C3 BI AB2 A34* 70D3 13B3 BI H26 DSTBP0* DSTBP2* AA26 BI 13A3 70C3
70C3 13C3 BI FSB_A_L<35> AA3 A35* PROCHOT* D21 CPU_PROCHOT_L OUT 45B5 45C3 59C8 70C3 70D3 13B3 BI FSB_DINV_L<0> H25 DINV0* DINV2* U22 FSB_DINV_L<2> BI 13B3 70C3
70C3 13C3 BI FSB_ADSTB_L<1> V1 ADSTB1* THERMDA A24 CPU_THERMD_P OUT 49C7
THERMDC B25 CPU_THERMD_N OUT 49B7
70C3 22C4 IN CPU_A20M_L A6 A20M* 70C3 13C5 BI FSB_D_L<16> N22 D16* D48* AE24 FSB_D_L<48> BI 13B5 70C3
70C3 22C2 OUT CPU_FERR_L A5 FERR* THERMTRIP* C7 PM_THRMTRIP_L OUT 15A6 22C2 45B3 70B3 PM_THRMTRIP# 70C3 13C5 BI FSB_D_L<17> K25 D17* D49* AD24 FSB_D_L<49> BI 13B5 70C3
70B3 22C4 IN CPU_IGNNE_L C4 IGNNE* SHOULD CONNECT TO ICH AND 70C3 13C5 BI FSB_D_L<18> P26 D18* D50* AA21 FSB_D_L<50> BI 13B5 70C3
FSB_D_L<19> FSB_D_L<51>
ICH
GMCH WITHOUT T (NO STUB) 70C3 13C5 BI R23 D19* D51* AB22 BI 13B5 70C3
H CLK
70B3 22C4 IN CPU_STPCLK_L D5 STPCLK* 70C3 13C5 BI FSB_D_L<20> L23 D20* D52* AB21 FSB_D_L<52> BI 13B5 70C3
70C3 22C4 IN CPU_INTR C6 LINT0 70C3 13C5 BI FSB_D_L<21> M24 D21* D53* AC26 FSB_D_L<53> BI 13B5 70C3
70C3 22C4 IN CPU_NMI B4 LINT1 BCLK0 A22 FSB_CLK_CPU_P IN 29D3 75C3 70C3 13C5 BI FSB_D_L<22> L22 D22* D54* AD20 FSB_D_L<54> BI 13B5 70C3
LAYOUT NOTE:
70B3 22C4 IN CPU_SMI_L A3 SMI* BCLK1 A21 FSB_CLK_CPU_N IN 29D3 75C3 70C3 13C5 BI FSB_D_L<23> M23 D23* D55* AE22 FSB_D_L<55> BI 13B5 70C3
COMP0,2 CONNECT WITH ZO=27.4OHM,
FSB_D_L<24> FSB_D_L<56>
DATA GRP 1
DATA GRP 3
70C3 13C5 BI P25 D24* D56* AF23 BI 13B5 70C3
MAKE TRACE LENGTH SHORTER THAN 0.5".
TP_CPU_RSVD0 M4 RSVD0 70C3 13C5 BI FSB_D_L<25> P23 D25* D57* AC25 FSB_D_L<57> BI 13B5 70C3
COMP1,3 CONNECT WITH ZO=55OHM,
TP_CPU_RSVD1 N5 RSVD1 70C3 13C5 BI FSB_D_L<26> P22 D26* D58* AE21 FSB_D_L<58> BI 13B5 70C3
MAKE TRACE LENGTH SHORTER THAN 0.5".
TP_CPU_RSVD2 T2 RSVD2 70C3 13C5 BI FSB_D_L<27> T24 D27* D59* AD21 FSB_D_L<59> BI 13B5 70C3
TP_CPU_RSVD3 V3 RSVD3 70C3 13C5 BI FSB_D_L<28> R24 D28* D60* AC22 FSB_D_L<60> BI 13B5 70C3
RESERVED
TP_CPU_RSVD4 B2 RSVD4 70C3 13C5 BI FSB_D_L<29> L25 D29* D61* AD23 FSB_D_L<61> BI 13B5 70C3
R1016
12C5 12B3 11A3 10C7 9D5 9C5 9B6 7C7 =PP1V05_S0_CPU 27.4
TP_CPU_RSVD5 C3 RSVD5 70C3 13C5 BI FSB_D_L<30> T25 D30* D62* AF22 FSB_D_L<62> BI 13B5 70C3
TP_CPU_RSVD6 D2 RSVD6 70C3 13C5 BI FSB_D_L<31> N25 D31* D63* AC23 FSB_D_L<63> BI 13B5 70C3 1%
1
TP_CPU_RSVD7 D22 RSVD7 R1005 70C3 13B3 BI FSB_DSTB_L_N<1> L26 DSTBN1* DSTBN3* AE25 FSB_DSTB_L_N<3> BI 13B3 70C3
R1017 1/16W
MF-LF
1K 54.9 402
TP_CPU_RSVD8 D3 RSVD8 1% 70C3 13B3 BI FSB_DSTB_L_P<1> M26 DATBP1* DSTBP3* AF24 FSB_DSTB_L_P<3> BI 13A3 70C3
B TP_CPU_RSVD9 F6 RSVD9 NC B1 NC
1/16W
MF-LF
402
2
0.5" MAX LENGTH FOR CPU_GTLREF
70C3 13B3 BI FSB_DINV_L<1> N24 DINV1* DINV3* AC20 FSB_DINV_L<3> BI 13B3 70C3 1%
1/16W
MF-LF R1018 B
402 27.4
70B3 CPU_GTLREF AD26 GTLREF COMP0 R26 70B3 CPU_COMP<0>
MISC
CPU_TEST1 C23 TEST1 COMP1 U26 70B3 CPU_COMP<1> 1%
CPU_TEST2 70B3 CPU_COMP<2> R1019 1/16W

R1006 1 D25 TEST2 COMP2 AA1
54.9
MF-LF
402
2.0K TP_CPU_TEST3 C24 TEST3 COMP3 Y1 70B3 CPU_COMP<3>
R1020 =PP1V05_S0_CPU 7C7 9B5 9C5 9D5 10C7 11A3 12B3 12C5
1%
1/16W CPU_TEST4 AF26 TEST4 1%
54.9 MF-LF 1/16W
70B3 12B2 9C6 XDP_TMS 402 2 NOSTUFF TP_CPU_TEST5 AF1 TEST5 DPRSTP* E5 CPU_DPRSTP_L IN 15B6 22C4 59C7 70B3 MF-LF
402
1% 1
C1000 TP_CPU_TEST6 A26 TEST6 DPSLP* B5 CPU_DPSLP_L IN 22C4 70B3
R1021 1/16W
MF-LF 0.1uF DPWR* D24 FSB_DPWR_L IN 13B3 70D3
54.9 402 10%
70B3 12B3 9C6 XDP_TDI 2
16V
X5R 70B3 29C6 OUT CPU_BSEL<0> B22 BSEL0 PWRGOOD D6 CPU_PWRGD IN 12B1 22C4 70C3
1% 402
70B3 29B6 OUT CPU_BSEL<1> B23 BSEL1 SLP* D7 FSB_CPUSLP_L IN 13A5 70B3
1/16W
R1024 PLACE C1000 CLOSE TO CPU_TEST4
MF-LF 70B3 29A6 OUT CPU_BSEL<2> C21 BSEL2 PSI* AE6 CPU_PSI_L OUT 27B3
402 54.9 PIN. MAKE SURE CPU_TEST4 IS
70B3 12B5 9C6 XDP_TDO
REFERENCED TO GND
PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1%
1/16W NOSTUFF
MF-LF
402
R1030
0
R1022
54.9 NOSTUFF 5% NOSTUFF
70B3 12B3 12B2 9C6 XDP_TCK 1
1/16W
1
1% R1012 MF-LF
402 R1007
R1023 1/16W 1K 1K
MF-LF 5% 5%
649 402 1/16W 1/16W
70A3 12B3 9C6 XDP_TRST_L MF-LF MF-LF
402 402
1% 2 2
1/16W
MF-LF
402 CPU FSB
A SYNC_MASTER=T9_MLB_NOME

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 10 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
A4 P6
A8 P21
(CPU CORE POWER) OMIT
A11 P24
=PPVCORE_S0_CPU 7D7 10B5 11D7 48B3 48B5 A14
U1000 R2
A16
MEROM R5
Standard Voltage: Low Voltage: Ultra Low Voltage: FCBGA
D
A19 R22
4 OF 4
D A7 AB20
44.0 A (Design Target) 23.0 A (Design Target) 17.0 A (Design Target) A23
AF2
R25
T1
A9 OMIT AB7 41.0 A (HFM) 21.0 A (HFM) TBD A (HFM)
B6 T4
A10
U1000 AC7 30.4 A (LFM) 18.7 A (LFM) TBD A (LFM)
B8 T23
A12
MEROM AC9 25.5 A (SuperLFM) TBD A (SuperLFM)
B11 T26
A13 FCBGA AC12
27.4 A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant HFM) B13 U3
A15 AC13
3 OF 4 17.0 A (Auto-Halt/Stop-Grant SuperLFM) TBD A (Auto-Halt/Stop-Grant SuperLFM) TBD A (Auto-Halt/Stop-Grant LFM) B16 U6
A17 AC15
B19 U21
A18 AC17 27.4 A (Sleep HFM) TBD A (Sleep HFM) TBD A (Sleep HFM)
B21 U24
A20 AC18 16.8 A (Sleep SuperLFM) TBD A (Sleep SuperLFM) TBD A (Sleep LFM)
B24 V2
B7 AD7
25.0 A (Deep Sleep HFM) TBD A (Deep Sleep HFM) TBD A (Deep Sleep HFM) C5 V5
B9 AD9
16.0 A (Deep Sleep SuperLFM) TBD A (Deep Sleep SuperLFM) TBD A (Deep Sleep LFM) C8 V22
B10 AD10
C11 V25
B12 AD12 11.5 A (Deeper Sleep) TBD A (Deeper Sleep) TBD A (Deeper Sleep)
C14 W1
B14 AD14
9.4 A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep) C16 W4
B15 AD15
C19 W23
B17 AD17
C2 W26
B18 AD18
C22 Y3
B20 AE9
VCC C25 Y6
C9 AE10
D1 Y21
C10 AE12
D4 Y24
C12 AE13
D8 AA2
C13 AE15
D11 AA5
C15 AE17
D13 AA8
C17 AE18
D16 AA11
C18 AE20
D19 AA14
C
D9 AF9
C D10
D12
AF10
AF12
D23
D26
AA16
AA19
E3 AA22
D14 AF14
E6 AA25
D15 VCC AF15
E8 AB1
D17 AF17
E11 AB4
D18 AF18
(CPU IO POWER 1.05V) E14 VSS VSS AB8
E7 AF20
E16 AB11
E9 =PP1V05_S0_CPU 7C7 9B5 9B6 9C5 9D5 11A3 12B3 12C5
E19 AB13
E10 G21
4500 mA (before VCC stable) E21 AB16
E12 V6
2500 mA (after VCC stable) E24 AB19
E13 J6
F5 AB23
E15 K6
F8 AB26
E17 M6
F11 AC3
E18 J21
F13 AC6
E20 K21
F16 AC8
F7 M21
VCCP F19 AC11
F9 N21
F2 AC14
F10 N6
F22 AC16
F12 R21
F25 AC19
F14 R6
G4 AC21
F15 T21
G1 AC24
F17 T6
G23 AD2
F18 V21
(CPU INTERNAL PLL POWER 1.5V) G26 AD5
F20 W21
H3 AD8
AA7 =PP1V5_S0_CPU 7C7 11B3
H6 AD11
AA9 B26
B
130 mA
B
H21 AD13
AA10 VCCA C26
H24 AD16
AA12
J2 AD19
AA13 VID0 AD6 CPU_VID<0> OUT 59C7 70A3
J5 AD22
AA15 VID1 AF5 CPU_VID<1> OUT 59C7 70A3
J22 AD25
AA17 VID2 AE5 CPU_VID<2> OUT 59C7 70A3 =PPVCORE_S0_CPU 7D7 10D7 11D7 48B3 48B5
J25 AE1
AA18 VID3 AF4 CPU_VID<3> OUT 59C7 70A3
K1 AE4
AA20 VID4 AE3 CPU_VID<4> OUT 59C7 70A3
1
R1100 K4 AE8
AB9 VID5 AF3 CPU_VID<5> OUT 59C7 70A3 100
1% K23 AE11
AC10 VID6 AE2 CPU_VID<6> OUT 59C7 70A3 1/16W
MF-LF K26 AE14
AB10 402
2 L3 AE16
AB12 PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
L6 AE19
AB14 VCCSENSE AF7 CPU_VCCSENSE_P OUT 59A4 59A5 70A3
L21 AE23
AB15
L24 AE26
AB17
M2 A2
AB18 VSSSENSE AE7 CPU_VCCSENSE_N OUT 59A4 59A5 70A3
M5 AF6
M22 AF8
1
R1101 M25 AF11
100
1% N1 AF13
1/16W
MF-LF N4 AF16
402
2 N23 AF19
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
N26 AF21
P3 A25
AF25
CPU Power & Ground

A SYNC_MASTER=T9_MLB_NOME

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 11 106
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
CPU VCORE HF AND BULK DECOUPLING

4x 330uF. 20x 10uF 0805
D 48B5 48B3 10D7 10B5 7D7 =PPVCORE_S0_CPU D
LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE) 1 C1200 1 C1201 1 C1202 1 C1203 1 C1204 1 C1205 1 C1206 1 C1207 1 C1208 1 C1209
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2
LAYOUT NOTE:
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE) 1 C1210 1 C1211 1 C1212 1 C1213 1 C1214 1 C1215 1 C1216 1 C1217 1 C1218 1 C1219
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2 805-2
C C
VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE: CRITICAL CRITICAL CRITICAL CRITICAL LAYOUT NOTE:
PLACE ON BOTTOMSIDE 1
C1250 1
C1251 1
C1252 1
C1253 =PP1V5_S0_CPU
330UF 330UF 330UF 330UF PLACE ON BOTTOMSIDE
10B7 7C7
1x 10uF, 1x 0.01uF
10% 10% 10% 10%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
TANT TANT TANT TANT
D2T D2T D2T D2T C1280 1 1 C1281
10uF 0.01UF
20% 10% LAYOUT NOTE:
6.3V 2 16V
2 CERM
X5R
603 402 PLACE C1281 NEAR PIN B26 OF U1000
C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.
B B
VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU
12C5 12B3 10C7 9D5 9C5 9B6 9B5 7C7
1X 330UF, 6X 0.1UF
CRITICAL
C1235 1 1 C1236 1 C1237 1 C1238 1 C1239 1 C1240 1 C1241
330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20%
2.5V 2 3 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
TANT
D2T 402 402 402 402 402 402
LAYOUT NOTE:
PLACE C1235 CLOSE TO CPU
CPU Decoupling & VID
A SYNC_MASTER=MSARWAR

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 12 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
CPU ITP700FLEX DEBUG SUPPORT
C C
ITP
=PP1V05_S0_CPU CRITICAL
J1302
12B3 11A3 10C7 9D5 9C5 9B6 9B5 7C7
NOSTUFF
QT500306-L021-9F
R1301
1 M-ST-SM
54.9
1%
32 31
1/16W
MF-LF
2402 70B3 9C6 9B7 XDP_TDI 2 1 70B3 9C6 9B7 XDP_TMS
ITP OUT
XDP_TRST_L 4 3 LVDS_CTRL_DATA
OUT
R1302
70A3 9C6 9A7 14D5 67A7
OUT
22.6 70B3 12B2 9C6 9A7 XDP_TCK

(TCK) 6 5 LVDS_CTRL_CLK 14D5 67A7
XDP_TDO ITP_TDO
OUT
70B3 9C6 9A7 1 2 8 7
CPU_XDP_CLK_N
IN
1% 29D3 10 9 70B3 12B3 9C6 9A7 XDP_TCK
(FBO)
CPU_XDP_CLK_P XDP_BPM_L<5>
IN OUT
ITP 1/16W (FROM CK505 HOST 133/167MHZ) 12
MF-LF 11
R1300
29D3 70A3 9C5
IN IO
402 14 13
70D3 13A5 9D6 FSB_CPURST_L 22.6
1 2 ITPRESET_L 16 15 70A3 9C6 XDP_BPM_L<4>
IN
1% 70A3 9C6 XDP_BPM_L<3> 18 17
IO
XDP_BPM_L<2>
IO
1/16W 20
MF-LF 19 70A3 9C6
IO
402
27C6 9C6 XDP_DBRESET_L 22 21
XDP_BPM_L<1>
OUT
24 23 70A3 9C6
=PP1V05_S0_CPU
IO
12C5 11A3 10C7 9D5 9C5 9B6 9B5 7C7
26 25
28 27 70A3 9C6 XDP_BPM_L<0>
CPU_PWRGD
IO
30 29 9B2 22C4 70C3
ITP
B 1 C1300 34 33 B
0.1UF
10%
2 16V
516S0394
X5R
402
(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.
(DEBUG PORT ACTIVE)
(DBR#)
TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)
ITP TCK SIGNAL LAYOUT NOTE:

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
CONNECTOR’S FBO PIN.
CPU ITP700FLEX DEBUG

SYNC_MASTER=MASTER SYNC_DATE=5/23/05
A NOTICE OF PROPRIETARY PROPERTY
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 13 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
OMIT
U1400
CRESTLINE
70D3 9C4 BI FSB_D_L<0> E2 H_D0* FCBGA H_A3* J13 FSB_A_L<3> BI 9D8 70C3
FSB_D_L<1> FSB_A_L<4>
D
70D3 9C4 BI G2 H_D1* (1 OF 10) H_A4* B11 BI 9D8 70C3
D FSB_D_L<2> FSB_A_L<5>
HOST
70D3 9C4 BI G7 H_D2* H_A5* C11 BI 9D8 70C3
70D3 9C4 BI FSB_D_L<3> M6 H_D3* H_A6* M11 FSB_A_L<6> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<4> H7 H_D4* H_A7* C15 FSB_A_L<7> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<5> H3 H_D5* H_A8* F16 FSB_A_L<8> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<6> G4 H_D6* H_A9* L13 FSB_A_L<9> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<7> F3 H_D7* H_A10* G17 FSB_A_L<10> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<8> N8 H_D8* H_A11* C14 FSB_A_L<11> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<9> H2 H_D9* H_A12* K16 FSB_A_L<12> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<10> M10 H_D10* H_A13* B13 FSB_A_L<13> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<11> N12 H_D11* H_A14* L16 FSB_A_L<14> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<12> N9 H_D12* H_A15* J17 FSB_A_L<15> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<13> H5 H_D13* H_A16* B14 FSB_A_L<16> BI 9D8 70C3
70D3 9C4 BI FSB_D_L<14> P13 H_D14* H_A17* K19 FSB_A_L<17> BI 9C8 70C3
70D3 9C4 BI FSB_D_L<15> K9 H_D15* H_A18* P15 FSB_A_L<18> BI 9C8 70C3
70C3 9C4 BI FSB_D_L<16> M2 H_D16* H_A19* R17 FSB_A_L<19> BI 9C8 70C3
70C3 9C4 BI FSB_D_L<17> W10 H_D17* H_A20* B16 FSB_A_L<20> BI 9C8 70C3
70C3 9C4 BI FSB_D_L<18> Y8 H_D18* H_A21* H20 FSB_A_L<21> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<19> V4 H_D19* H_A22* L19 FSB_A_L<22> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<20> M3 H_D20* H_A23* D17 FSB_A_L<23> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<21> J1 H_D21* H_A24* M17 FSB_A_L<24> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<22> N5 H_D22* H_A25* N16 FSB_A_L<25> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<23> N3 H_D23* H_A26* J19 FSB_A_L<26> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<24> W6 H_D24* H_A27* B18 FSB_A_L<27> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<25> W9 H_D25* H_A28* E19 FSB_A_L<28> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<26> N2 H_D26* H_A29* B17 FSB_A_L<29> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<27> Y7 H_D27* H_A30* B15 FSB_A_L<30> BI 9C8 70C3
C 70C3 9B4
70C3 9B4
BI
BI
FSB_D_L<28>
FSB_D_L<29>
Y9
P4
H_D28*
H_D29*
H_A31*
H_A32*
E17
C18
FSB_A_L<31>
FSB_A_L<32>
BI
BI
9C8 70C3
9C8 70C3
C
70C3 9B4 BI FSB_D_L<30> W3 H_D30* H_A33* A19 FSB_A_L<33> BI 9C8 70C3
70C3 9B4 BI FSB_D_L<31> N1 H_D31* H_A34* B19 FSB_A_L<34> BI 9C8 70C3
70C3 9C2 BI FSB_D_L<32> AD12 H_D32* H_A35* N19 FSB_A_L<35> BI 9C8 70C3
70C3 9C2 BI FSB_D_L<33> AE3 H_D33*

70C3 9C2 BI FSB_D_L<34> AD9 H_D34* H_ADS* G12 FSB_ADS_L BI 9D6 70D3
70C3 9C2 BI FSB_D_L<35> AC9 H_D35* H_ADSTB0* H17 FSB_ADSTB_L<0> BI 9D8 70C3
70C3 9C2 BI FSB_D_L<36> AC7 H_D36* H_ADSTB1* G20 FSB_ADSTB_L<1> BI 9C8 70C3
70C3 9C2 BI FSB_D_L<37> AC14 H_D37* H_BNR* C8 FSB_BNR_L BI 9D6 70D3
70C3 9C2 BI FSB_D_L<38> AD11 H_D38* H_BPRI* E8 FSB_BPRI_L OUT 9D6 70D3
70C3 9C2 BI FSB_D_L<39> AC11 H_D39* H_BREQ* F12 FSB_BREQ0_L BI 9D6 70D3
70C3 9C2 BI FSB_D_L<40> AB2 H_D40* H_DEFER* D6 FSB_DEFER_L OUT 9D6 70D3
70C3 9C2 BI FSB_D_L<41> AD7 H_D41* H_DBSY* C10 FSB_DBSY_L BI 9D6 70D3
70C3 9C2 BI FSB_D_L<42> AB1 H_D42* HPLL_CLK AM5 FSB_CLK_NB_P IN 29D3 75C3
70C3 9C2 BI FSB_D_L<43> Y3 H_D43* HPLL_CLK* AM7 FSB_CLK_NB_N IN 29D3 75C3
70C3 9C2 BI FSB_D_L<44> AC6 H_D44* H_DPWR* H8 FSB_DPWR_L BI 9B2 70D3
70C3 9C2 BI FSB_D_L<45> AE2 H_D45* H_DRDY* K7 FSB_DRDY_L BI 9D6 70D3
70C3 9C2 BI FSB_D_L<46> AC5 H_D46* H_HIT* E4 FSB_HIT_L BI 9C6 70D3
70C3 9C2 BI FSB_D_L<47> AG3 H_D47* H_HITM* C6 FSB_HITM_L BI 9C6 70D3
70C3 9C2 BI FSB_D_L<48> AJ9 H_D48* H_LOCK* G10 FSB_LOCK_L IN 9D6 70D3
70C3 9C2 BI FSB_D_L<49> AH8 H_D49* H_TRDY* B7 FSB_TRDY_L OUT 9D6 70D3
70C3 9C2 BI FSB_D_L<50> AJ14 H_D50*

70C3 9B2 BI FSB_D_L<51> AE9 H_D51*
70C3 9B2 BI FSB_D_L<52> AE11 H_D52*
70C3 9B2 BI FSB_D_L<53> AH12 H_D53*
H_DINV0* K5 FSB_DINV_L<0> BI 9C4 70D3
FSB_D_L<54>
B H_D54*
B
70C3 9B2 BI AJ5
H_DINV1* L2 FSB_DINV_L<1> BI 9B4 70C3
70C3 9B2 BI FSB_D_L<55> AH5 H_D55*
H_DINV2* AD13 FSB_DINV_L<2> BI 9C2 70C3
70C3 9B2 BI FSB_D_L<56> AJ6 H_D56*
H_DINV3* AE13 FSB_DINV_L<3> BI 9B2 70C3
70C3 9B2 BI FSB_D_L<57> AE7 H_D57*
70C3 9B2 BI FSB_D_L<58> AJ7 H_D58*
29C6 29B6 7C7 =PP1V25R1V05_S0_FSB_NB H_DSTBN0* M7 FSB_DSTB_L_N<0> BI 9C4 70D3
70C3 9B2 BI FSB_D_L<59> AJ2 H_D59*
H_DSTBN1* K3 FSB_DSTB_L_N<1> BI 9B4 70C3
70C3 9B2 BI FSB_D_L<60> AE5 H_D60*
H_DSTBN2* AD2 FSB_DSTB_L_N<2> BI 9C2 70C3
70C3 9B2 BI FSB_D_L<61> AJ3 H_D61*
R1421 1 1
R1420 R1410 1
H_DSTBN3* AH11 FSB_DSTB_L_N<3> BI 9B2 70C3
70C3 9B2 BI FSB_D_L<62> AH2 H_D62*
54.9 54.9 221
1% 1% 1% 70C3 9B2 BI FSB_D_L<63> AH13 H_D63* H_DSTBP0* L7 FSB_DSTB_L_P<0> BI 9C4 70D3
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF H_DSTBP1* K2 FSB_DSTB_L_P<1> BI 9B4 70C3
402 402 402
2 2 2
H_DSTBP2* AC2 FSB_DSTB_L_P<2> BI 9C2 70C3
NB_FSB_SWING B3 H_SWING H_DSTBP3* AJ10 FSB_DSTB_L_P<3> BI 9B2 70C3
NB_FSB_RCOMP C2 H_RCOMP
H_REQ0* M14 FSB_REQ_L<0> BI 9D8 70C3
NB_FSB_SCOMP W1 H_SCOMP H_REQ1* E13 FSB_REQ_L<1> BI 9D8 70C3
NB_FSB_SCOMP_L W2 H_SCOMP* H_REQ2* A11 FSB_REQ_L<2> BI 9D8 70C3
1 H_REQ3* H13 FSB_REQ_L<3> BI 9D8 70C3

R1425 70D3 12B5 9D6 OUT FSB_CPURST_L B6 H_CPURST* H_REQ4* B12 FSB_REQ_L<4> BI 9C8 70C3
1K
1% 70B3 9A2 OUT FSB_CPUSLP_L E5 H_CPUSLP*
1/16W
MF-LF H_RS0* E12 FSB_RS_L<0> OUT 9D6 70D3
402 2
H_RS1* D7 FSB_RS_L<1> OUT 9D6 70D3
NB_FSB_VREF B9 H_AVREF H_RS2* D8 FSB_RS_L<2> OUT 9D6 70D3
A9 H_DVREF
1 1 1
R1426
2.0K
1
C1425 R1415
24.9
R1411
100
1
C1410 NB CPU Interface
1%
0.1uF 1% 1%
0.1uF
A A
10% 10%
1/16W 16V 1/16W 1/16W 16V SYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
MF-LF 2 X5R MF-LF MF-LF 2 X5R
402 402 402
2 402 2 2 402
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 14 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
PP1V05_S0_NB_VCCPEG 18B3 20D3
1
R1510
OMIT 24.9
1%
1/16W
U1400 MF-LF
402
2
LVDS Disable CRESTLINE
LVDS_BKLT_CTL PEG_COMP
L_BKLT_CTRL PEG_COMPI
D
67C6 OUT J40 FCBGA N43
D Can leave all signals NC if LVDS is not implemented.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.
67D8
67A7 12B1
OUT
BI
LVDS_BKLT_EN
LVDS_CTRL_CLK
H39
E39
L_BKLT_EN
L_CTRL_CLK
(3 OF 10) PEG_COMPO M43 SDVO Alternate Function
PEG_RX0* J51 PEG_D2R_N<0> IN 8D6 SDVO_TVCLKIN#

67A7 12B1 BI LVDS_CTRL_DATA E40 L_CTRL_DATA
If SDVO is used, VCCD_LVDS must remain powered with proper PEG_RX1* L51 PEG_D2R_N<1> IN 68B6 71D3 SDVO_INT#
67B6 BI LVDS_DDC_CLK C37 L_DDC_CLK
decoupling. Otherwise, tie VCCD_LVDS to GND also. PEG_RX2* N47 PEG_D2R_N<2> IN 8C6 SDVO_FLDSTALL#
67B6 BI LVDS_DDC_DATA D35 L_DDC_DATA
PEG_RX3* T45 PEG_D2R_N<3> IN 8C6
67B8 OUT LVDS_VDD_EN K40 L_VDD_EN
PEG_RX4* T50 PEG_D2R_N<4> IN 8C6
PEG_RX5* U40 PEG_D2R_N<5> IN 8C6

71C3 67A8 BI LVDS_IBG L41 LVDS_IBG
PEG_RX6* Y44 PEG_D2R_N<6> IN 8C6
TP_LVDS_VBG L43 LVDS_VBG
PEG_RX7* Y40 PEG_D2R_N<7> IN 8C6
IN TP_LVDS_VREFH N41 LVDS_VREFH
PEG_RX8* AB51 PEG_D2R_N<8> IN 8C6
IN TP_LVDS_VREFL N40 LVDS_VREFL
PEG_RX9* W49 PEG_D2R_N<9> IN 8C6
71D3 67B3 OUT LVDS_A_CLK_N D46 LVDSA_CLK*
PEG_RX10* AD44 PEG_D2R_N<10> IN 8C6
71D3 67B3 OUT LVDS_A_CLK_P C45 LVDSA_CLK
PEG_RX11* AD40 PEG_D2R_N<11> IN 8C6
8D6 OUT LVDS_B_CLK_N D44 LVDSB_CLK*
PEG_D2R_N<12>
LVDS
PEG_RX12* AG46 IN 8C6
8D6 OUT LVDS_B_CLK_P E42 LVDSB_CLK
PEG_RX13* AH49 PEG_D2R_N<13> IN 8C6
PEG_RX14* AG45 PEG_D2R_N<14> IN 8C6
PEG_RX15* AG41 PEG_D2R_N<15> IN 8C6

71D3 67B2 OUT LVDS_A_DATA_N<0> G51 LVDSA_DATA0*
71D3 67B2 OUT LVDS_A_DATA_N<1> E51 LVDSA_DATA1* PEG_RX0 J50 PEG_D2R_P<0> IN 8C6 SDVO_TVCLKIN
71D3 67B2 OUT LVDS_A_DATA_N<2> F49 LVDSA_DATA2* PEG_RX1 L50 PEG_D2R_P<1> IN 68B6 71D3 SDVO_INT
PEG_RX2 M47 PEG_D2R_P<2> IN 8C6 SDVO_FLDSTALL
71D3 67B2 OUT LVDS_A_DATA_P<0> G50 LVDSA_DATA0
PEG_RX3 U44 PEG_D2R_P<3> IN 8C6
71D3 67B2 OUT LVDS_A_DATA_P<1> E50 LVDSA_DATA1
PEG_RX4 T49 PEG_D2R_P<4> IN 8C6
71D3 67B2 OUT LVDS_A_DATA_P<2> F48 LVDSA_DATA2
PEG_RX5 T41 PEG_D2R_P<5>
PCI-EXPRESS GRAPHICS
IN 8C6
PEG_RX6 W45 PEG_D2R_P<6> IN 8C6
PEG_RX7 W41 PEG_D2R_P<7> IN 8C6

LVDS_B_DATA_N<0> LVDSB_DATA0*
C
G44
C
8D6 OUT PEG_D2R_P<8>
PEG_RX8 AB50 IN 8C6
8D6 OUT LVDS_B_DATA_N<1> B47 LVDSB_DATA1*
PEG_RX9 Y48 PEG_D2R_P<9> IN 8C6
8D6 OUT LVDS_B_DATA_N<2> B45 LVDSB_DATA2*
PEG_RX10 AC45 PEG_D2R_P<10> IN 8C6
8D6 OUT LVDS_B_DATA_P<0> E44 LVDSB_DATA0 PEG_RX11 AC41 PEG_D2R_P<11> IN 8C6
8D6 OUT LVDS_B_DATA_P<1> A47 LVDSB_DATA1 PEG_RX12 AH47 PEG_D2R_P<12> IN 8C6
8D6 OUT LVDS_B_DATA_P<2> A45 LVDSB_DATA2 PEG_RX13 AG49 PEG_D2R_P<13> IN 8B6
PEG_RX14 AH45 PEG_D2R_P<14> IN 8B6
PEG_RX15 AG42 PEG_D2R_P<15> IN 8B6
TV-Out Signal Usage: PEG_TX0* N45 PEG_R2D_C_N<0> OUT 68C6 71D3 SDVOB_RED#
PEG_TX1* U39 PEG_R2D_C_N<1> OUT 68C6 71D3 SDVOB_GREEN#
Composite: DACA only 69D8 OUT =TV_A_DAC E27 TVA_DAC
PEG_TX2* U47 PEG_R2D_C_N<2> OUT 68B6 71D3 SDVOB_BLUE#
S-Video: DACB & DACC only 69D8 OUT =TV_B_DAC G27 TVB_DAC
PEG_TX3* N51 PEG_R2D_C_N<3> OUT 68B6 71D3 SDVOB_CLKN
Component: DACA, DACB & DACC 69D8 OUT =TV_C_DAC K27 TVC_DAC
PEG_TX4* R50 PEG_R2D_C_N<4> OUT 8B6 SDVOC_RED#
Unused DAC outputs must remain powered, but can PEG_TX5* T42 PEG_R2D_C_N<5> OUT 8B6 SDVOC_GREEN#
omit filtering components. Unused DAC outputs PEG_TX6* Y43 PEG_R2D_C_N<6> OUT 8B6 SDVOC_BLUE#
=TV_A_RTN
TV
69B8 OUT F27 TVA_RTN
should connect to GND through 75-ohm resistors. PEG_TX7* W46 PEG_R2D_C_N<7> OUT 8B6 SDVOC_CLKN
69A8 OUT =TV_B_RTN J27 TVB_RTN
PEG_TX8* W38 PEG_R2D_C_N<8> OUT 8B6
TV-Out Disable / CRT Enable 69A8 OUT =TV_C_RTN L27 TVC_RTN
PEG_TX9* AD39 PEG_R2D_C_N<9> OUT 8B6
Tie TVx_DAC and TVx_RTN to GND. Must power all PEG_TX10* AC46 PEG_R2D_C_N<10> OUT 8B6
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can PEG_TX11* AC49 PEG_R2D_C_N<11> OUT 8B6
69C8 OUT TV_DCONSEL<0> M35 TV_DCONSEL0
share filtering with VCCA_CRT_DAC. PEG_TX12* AC42 PEG_R2D_C_N<12> OUT 8B6
69C8 OUT TV_DCONSEL<1> P33 TV_DCONSEL1
PEG_TX13* AH39 PEG_R2D_C_N<13> OUT 8B6
CRT Disable / TV-Out Enable PEG_TX14* AE49 PEG_R2D_C_N<14> OUT 8B6
PEG_TX15* AH44 PEG_R2D_C_N<15> OUT 8B6

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
All CRT/TVDAC rails must be powered. All PEG_TX0 M45 PEG_R2D_C_P<0> OUT 68C6 71D3 SDVOB_RED
=CRT_BLUE PEG_R2D_C_P<1>
B
rails must be filtered except for VCCA_CRT. CRT_BLUE PEG_TX1 SDVOB_GREEN
B
69D7 OUT H32 T38 OUT 68C6 71D3
69B8 OUT =CRT_BLUE_L G32 CRT_BLUE* PEG_TX2 T46 PEG_R2D_C_P<2> OUT 68B6 71D3 SDVOB_BLUE
CRT & TV-Out Disable 69D7 OUT =CRT_GREEN K29 CRT_GREEN PEG_TX3 N50 PEG_R2D_C_P<3> OUT 68B6 71D3 SDVOB_CLKP
69A8 OUT =CRT_GREEN_L J29 CRT_GREEN* PEG_TX4 R51 PEG_R2D_C_P<4> OUT 8B6 SDVOC_RED
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
69D7 OUT =CRT_RED F29 CRT_RED PEG_TX5 U43 PEG_R2D_C_P<5> OUT 8B6 SDVOC_GREEN
VSYNC and CRT_TVO_IREF to GND.
69A8 OUT =CRT_RED_L E29 CRT_RED* PEG_TX6 W42 PEG_R2D_C_P<6> OUT 8B6 SDVOC_BLUE
VGA
Can tie the following rails to GND:
PEG_TX7 Y47 PEG_R2D_C_P<7> OUT 8B6 SDVOC_CLKP
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
PEG_TX8 Y39 PEG_R2D_C_P<8> OUT 8B6
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
69B8 BI CRT_DDC_CLK K33 CRT_DDC_CLK PEG_TX9 AC38 PEG_R2D_C_P<9> OUT 8B6
NOTE: Must keep VDDC_TVDAC powered 69B8 BI CRT_DDC_DATA G35 CRT_DDC_DATA PEG_TX10 AD47 PEG_R2D_C_P<10> OUT 8B6
and filtered at all times! 69D7 OUT =CRT_HSYNC_R F33 CRT_HSYNC PEG_TX11 AC50 PEG_R2D_C_P<11> OUT 8B6
69D8 OUT =CRT_TVO_IREF C32 CRT_TVO_IREF PEG_TX12 AD43 PEG_R2D_C_P<12> OUT 8B6
69D7 OUT =CRT_VSYNC_R E33 CRT_VSYNC PEG_TX13 AG39 PEG_R2D_C_P<13> OUT 8B6
PEG_TX14 AE50 PEG_R2D_C_P<14> OUT 8B6
Internal Graphics Disable PEG_TX15 AH43 PEG_R2D_C_P<15> OUT 8A6
Follow instructions for LVDS and CRT & TV-Out Disable above.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
TV_DCONSELx to GND.
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
NB PEG / Video Interfaces

A SYNC_MASTER=T9_MLB

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 15 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
NB_CFG<5> 15B6
NB_CFG<3> RESERVED
NBCFG_DMI_X2
1
R1655 OMIT
NB_CFG<4> RESERVED 3.9K
5%
1/16W
MF-LF
U1400
402
NB_CFG<5> High = DMIx4 2 CRESTLINE
TP_NB_RSVD<1> P36 RSVD1 FCBGA SM_CK0 AV29 MEM_CLK_P<0> OUT 30D4 72D3
DMI x2 Select Low = DMIx2 TP_NB_RSVD<2> P37 RSVD2 (2 OF 10) SM_CK1 BB23 MEM_CLK_P<1> OUT 30A4 72D3
TP_NB_RSVD<3> R35 RSVD3 SM_CK3 BA25 MEM_CLK_P<3> OUT 31D4 72B3
NB_CFG<6> RESERVED NB_CFG<9>

TP_NB_RSVD<4> N35 RSVD4 SM_CK4 AV23 MEM_CLK_P<4> OUT 31A4 72B3
15B6
TP_NB_RSVD<5> AR12 RSVD5
MEM_CLK_N<0>
NBCFG_PEG_REVERSE SM_CK0*
D
AW30 OUT 30D4 72D3
D
TP_NB_RSVD<6> AR13 RSVD6
NB_CFG<7> RESERVED 1
R1659 TP_NB_RSVD<7>
SM_CK1* BA23 MEM_CLK_N<1> OUT 30A4 72D3
AM12 RSVD7
RSVD
3.9K SM_CK3* AW25 MEM_CLK_N<3> OUT 31D4 72B3
5% TP_NB_RSVD<8> AN13 RSVD8
1/16W SM_CK4* AW23 MEM_CLK_N<4> OUT 31A4 72B3
NB_CFG<8> RESERVED MF-LF TP_NB_RSVD<9> J12 RSVD9
402
2 TP_NB_RSVD<10> AR37 RSVD10 SM_CKE0 BE29 MEM_CKE<0> OUT 30C6 32D6 72D3
TP_NB_RSVD<11> AM36 RSVD11 SM_CKE1 AY32 MEM_CKE<1> OUT 30C4 32D6 72D3
NB_CFG<9> High = Normal
TP_NB_RSVD<12> MEM_CKE<3>
DDR MUXING
AL36 RSVD12 SM_CKE3 BD39 OUT 31C6 32D6 72B3
PCIe Graphics
Low = Reversed TP_NB_RSVD<13> AM37 RSVD13 SM_CKE4 BG37 MEM_CKE<4> OUT 31C4 32D5 72B3
Lane Reversal
NB_CFG<16> 15B6 TP_NB_RSVD<14> D20 RSVD14
SM_CS0* BG20 MEM_CS_L<0> OUT 30B4 32D6 72D3 31D2 30D2 20C8 17D7 7A4 =PP1V8_S3M_MEM_NB
NBCFG_DYN_ODT_DISABLE
TP_NB_RSVD<20> H10 RSVD20 SM_CS1* BK16 MEM_CS_L<1> OUT 30B6 32D6 72D3
R1666 TP_NB_RSVD<21> B51 RSVD21 SM_CS2* BG16 MEM_CS_L<2> OUT 31B4 32D6 72B3
3.9K
5% TP_NB_RSVD<22> BJ20 RSVD22 SM_CS3* BE13 MEM_CS_L<3> OUT 31B6 32D6 72B3 R1610 1 1
R1620
NB_CFG<11> RESERVED 1/16W
TP_NB_RSVD<23> 20 1K
MF-LF BK22 RSVD23
402 SM_ODT0 BH18 MEM_ODT<0> OUT 30B4 32D6 72D3 1% 1%
2 TP_NB_RSVD<24> BF19 RSVD24 1/16W 1/16W
SM_ODT1 BJ15 MEM_ODT<1> OUT 30B6 32D6 72D3 MF-LF MF-LF
NB_CFG<12> See Below TP_NB_RSVD<25> BH20 RSVD25
MEM_ODT<2>
402
2 2
402
SM_ODT2 BJ14 OUT 31B4 32D6 72B3
TP_NB_RSVD<26> BK18 RSVD26
SM_ODT3 BE16 MEM_ODT<3> OUT 31B6 32D6 72B3
TP_NB_RSVD<27> BJ18 RSVD27
NB_CFG<13> See Below =PP3V3_S0_NB_VCCHV TP_MEM_CLKP2 MEM_RCOMP
7D4 15B7 15C7 18B3 20A8 21B7 8B4 BF23 SM_CK2 SM_RCOMP BL15
TP_MEM_CLKN2 MEM_RCOMP_L
C1623 1 1
C1622
NBCFG_DMI_REVERSE 8B4 BG23 SM_CK2* SM_RCOMP* BK14
0.01UF 2.2UF 1
NB_CFG<14> RESERVED 1 TP_MEM_CLKP5 10% 20% R1622
R1669 8B4 BC23 SM_CK5
SM_RCOMP_VOH BK31 MEM_RCOMP_VOH 16V
2 2
6.3V
3.01K
3.9K 8B4 TP_MEM_CLKN5 BD24 SM_CK5* CERM CERM1
1%
5% SM_RCOMP_VOL BL31 MEM_RCOMP_VOL 402 603
1/16W
1/16W 72D3 32C6 30C4 OUT MEM_A_A<14> BJ29 SA_MA14 MF-LF
NB_CFG<15> RESERVED MF-LF
MEM_B_A<14> =PP0V9_S3M_MEM_NBVREFA 2
402
2
402 72B3 32A5 31C4 OUT BE24 SB_MA14 SM_VREF0 AR49 IN 20A5
TP_NB_RSVD<34> BH39 RSVD34 SM_VREF1 AW4 =PP0V9_S3M_MEM_NBVREFB IN 20A4

NB_CFG<19> 15B6
NB_CFG<16> High = Enabled TP_NB_RSVD<35> AW20 RSVD35
FSB Dynamic TP_NB_RSVD<36> BK20 RSVD36 C1615 1 1
C1616
Low = Disabled
C ODT
=PP3V3_S0_NB_VCCHV
NBCFG_SDVO_AND_PCIE
7D4 15B7 15C7 18B3 20A8 21B7
8D6
8D6
TP_LVDS_A_DATAN3
TP_LVDS_A_DATAP3
C48
D47
RSVD37
RSVD38
DPLL_REF_CLK
DPLL_REF_CLK*
B42
C42
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
IN 8B2
0.1uF
20%
10V
CERM 2 2
0.1uF
20%
10V
CERM
R1611
20
1%
1
C1625
0.01UF
1 1
C1624
2.2UF
1
R1624
1K
1%
C
IN 8B2
8D6 TP_LVDS_B_DATAN3 B44 RSVD39
=NB_CLK100M_DPLLSS_P
402 402
1/16W
10%
16V
20%
6.3V 1/16W
R1670 8D6 TP_LVDS_B_DATAP3 C44 RSVD40
DPLL_REF_SSCLK H48 IN 8B2 MF-LF
402
CERM 2 2 CERM1 MF-LF
402
3.9K DPLL_REF_SSCLK* H47 =NB_CLK100M_DPLLSS_N IN 8B2
2 402 603 2
5% TP_NB_RSVD<41> A35 RSVD41
NB_CFG<18> RESERVED
CLK
1/16W
MF-LF TP_NB_RSVD<42> B37 RSVD42 PEG_CLK K44 NB_CLK100M_PCIE_P IN 29C3 75B3
402
2 TP_NB_RSVD<43> B36 RSVD43 PEG_CLK* K45 NB_CLK100M_PCIE_N IN 29C3 75B3
NB_CFG<19> High = Reversed NB_CFG<20> 15B6 TP_NB_RSVD<44> B34 RSVD44 Clk used for PEG and DMI
DMI Lane TP_NB_RSVD<45> C34 RSVD45
Low = Normal
Reversal
70B3 29C8 IN NB_BSEL<0> P27 CFG0 DMI_RXN0 AN47 DMI_S2N_N<0> IN 23D2 71D3
70B3 29B8 IN NB_BSEL<1> N27 CFG1 DMI_RXN1 AJ38 DMI_S2N_N<1> IN 23D2 71D3
NB_CFG<20> High = Both active
NB_BSEL<2> DMI_S2N_N<2>
70B3 29B8 IN N24 CFG2 DMI_RXN2 AN42 IN 23D2 71D3
Concurrent Low = Only SDVO
8A6 OUT NB_CFG<3> C21 CFG3 IPU DMI_RXN3 AN46 DMI_S2N_N<3> IN 23D2 71D3
SDVO/PCIe x1 or PCIe x16 NB CFG<8:0> used for debug access
8A6 BI NB_CFG<4> C23 CFG4 IPU
DMI_RXP0 AM47 DMI_S2N_P<0> IN 23D2 71D3
15D7 BI NB_CFG<5> F23 CFG5 IPU
NB_CFG<13:12> NB_CFG<6>
DMI_RXP1 AJ39 DMI_S2N_P<1> IN 23D2 71D3
8A6 OUT N23 CFG6 IPU
DMI_RXP2 AN41 DMI_S2N_P<2> IN 23D2 71D3
00 = RESERVED NB_CFG<7> G23 CFG7 IPU
DMI
8A6 OUT DMI_S2N_P<3>
DMI_RXP3 AN45
CFG
NB_CFG<8> IN 23D2 71D3
01 = XOR Mode Enabled 8A6 OUT J20 CFG8 IPU
10 = All-Z Mode Enabled 15D7 NB_CFG<9> C20 CFG9 IPU DMI_TXN0 AJ46 DMI_N2S_N<0> OUT 23D2 71D3
11 = Normal Operation TP_NB_CFG<10> R24 CFG10 IPU DMI_TXN1 AJ41 DMI_N2S_N<1> OUT 23D2 71D3
TP_NB_CFG<11> L23 CFG11 IPU DMI_TXN2 AM40 DMI_N2S_N<2> OUT 23D2 71D3
TP_NB_CFG<12> J23 CFG12 IPU DMI_TXN3 AM44 DMI_N2S_N<3> OUT 23D2 71D3
NB CFG<13:12> require ICT access TP_NB_CFG<13> E23 CFG13 IPU

DMI_TXP0 AJ47 DMI_N2S_P<0> OUT 23D2 71D3
TP_NB_CFG<14> E20 CFG14 IPU
DMI_TXP1 AJ42 DMI_N2S_P<1> OUT 23D2 71D3
TP_NB_CFG<15> K23 CFG15 IPU
DMI_TXP2 AM39 DMI_N2S_P<2> OUT 23D2 71D3
21B7 20A8 18B3 15C7 7D4 =PP3V3_S0_NB_VCCHV 15D7 NB_CFG<16> M20 CFG16 IPU
DMI_N2S_P<3>
B
DMI_TXP3
B
AM43 OUT 23D2 71D3
TP_NB_CFG<17> M24 CFG17 IPU
TP_NB_CFG<18> L32 CFG18 IPD
GRAPHICS VID
R1630
1 1
R1631 15C7 NB_CFG<19> N33 CFG19 IPD
10K 10K 15C7 NB_CFG<20> L35 CFG20 IPD
5% 5%
1/16W 1/16W
MF-LF MF-LF 24D5 OUT PM_BMBUSY_L G41 PM_BM_BUSY*
402 2 2 402 GFX_VID0 E35 GFX_VID<0> OUT 21B6 60C6
70B3 59C7 22C4 9B2 IN CPU_DPRSTP_L L39 PM_DPRSTP*
GFX_VID1 A39 GFX_VID<1> OUT 21B6 60C6
44B8 8B2 IN PM_EXTTS_L<0> L36 PM_EXT_TS0*
GFX_VID2 C38 GFX_VID<2>
PM
PM_EXTTS_L<1> OUT 21B6 60C6
44B8 8B2 IN J36 PM_EXT_TS1*
GFX_VID3 B39 GFX_VID<3> OUT 21B6 60C6
59C7 27B5 IN VR_PWRGOOD_DELAY AW49 PWROK
GFX_VR_EN E36 =GFX_VR_EN OUT 8B2
27D1 IN NB_RESET_L AV20 RSTIN* R1600
70B3 45B3 22C2 9C6 OUT PM_THRMTRIP_L N20 THERMTRIP*
1
0 2 GFX_VID<4> OUT 60C6
70B3 59D8 24C3 IN PM_DPRSLPVR G36 DPRSLPVR
5% PP1V25_S0M_NB_VCCAXD 18C3 20A6
1/16W
TP_NB_NC<1> BJ51 NC1 MF-LF
402
TP_NB_NC<2> BK51 NC2 1
R1640
CL_CLK AM49 CLINK_NB_CLK BI 24C3 74A3
TP_NB_NC<3> BK50 NC3 1K
ME CL_DATA AK50 CLINK_NB_DATA BI 24C3 74A3 1%
TP_NB_NC<4> BL50 NC4 1/16W
CL_PWROK AT43 =NB_CLINK_MPWROK IN 8B2 MF-LF NOTE: GMCH CL_PWROK input must be PWRGD signal for
TP_NB_NC<5> BL49 NC5 402
CL_RST* AN49 CLINK_NB_RESET_L OUT 24C3 74A3
2
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
TP_NB_NC<6> BL3 NC6
CL_VREF AM50 74A3 NB_CLINK_VREF PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
TP_NB_NC<7> BL2 NC7
If ME/AMT is not used, short CL_PWROK to PWROK.
NC
TP_NB_NC<8> BK1 NC8 1

TP_NB_NC<9> BJ1 NC9 C1640 1 R1641
0.1uF 392
TP_NB_NC<10> E1 NC10 SDVO_CTRL_CLK H35 SDVO_CTRLCLK BI 68A6
20%
1%
1/16W
TP_NB_NC<11> SDVO_CTRLDATA 10V
MISC
A5 NC11 SDVO_CTRL_DATA K36 BI 68A6 CERM 2 MF-LF

TP_NB_NC<12> C51 NC12 CLKREQ* G39 NB_CLKREQ_L OUT 28B4
402 2
402
NB Misc Interfaces
TP_NB_NC<13> B50 NC13 ICH_SYNC* G40 NB_SB_SYNC_L
A
OUT 24B5
TP_NB_NC<14>
TP_NB_NC<15>
A50
A49
NC14
NC15 TEST1 A37 NB_TEST1
SYNC_MASTER=T9_MLB

A
TP_NB_NC<16> BK2 NC16 TEST2 R32 NB_TEST2
R1691 1 1
R1690 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
20K 0
5% 5% II NOT TO REPRODUCE OR COPY IT
1/16W 1/16W
MF-LF MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
402 402
2 2
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 16 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
D OMIT OMIT
D
U1400 U1400
MEM_A_DQ<0> AR43 SA_DQ0 CRESTLINE SA_BS0 BB19 MEM_A_BS<0> MEM_B_DQ<0> AP49 SB_DQ0 CRESTLINE SB_BS0 AY17 MEM_B_BS<0>
72D3 30D4 BI OUT 30B6 32C6 72D3 72B3 31D4 BI OUT 31B6 32A6 72B3
FCBGA FCBGA
72D3 30D6 BI MEM_A_DQ<1> AW44 SA_DQ1 SA_BS1 BK19 MEM_A_BS<1> OUT 30B4 32C6 72D3 72B3 31D6 BI MEM_B_DQ<1> AR51 SB_DQ1 SB_BS1 BG18 MEM_B_BS<1> OUT 31B4 32A6 72B3
(4 OF 10) (5 OF 10)
72D3 30D6 BI MEM_A_DQ<2> BA45 SA_DQ2 SA_BS2 BF29 MEM_A_BS<2> OUT 30C6 32C6 72D3 72B3 31D4 BI MEM_B_DQ<2> AW50 SB_DQ2 SB_BS2 BG36 MEM_B_BS<2> OUT 31C6 32A6 72B3
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B

72D3 30D6 BI MEM_A_DQ<3> AY46 SA_DQ3 72B3 31D6 BI MEM_B_DQ<3> AW51 SB_DQ3
SA_CAS* BL17 MEM_A_CAS_L OUT 30B6 32B6 72D3 SB_CAS* BE17 MEM_B_CAS_L OUT 31B6 32A6 72B3
72D3 30D4 BI MEM_A_DQ<4> AR41 SA_DQ4 72B3 31D6 BI MEM_B_DQ<4> AN51 SB_DQ4
72D3 30D4 BI MEM_A_DQ<5> AR45 SA_DQ5 72B3 31D4 BI MEM_B_DQ<5> AN50 SB_DQ5
SA_DM0 AT45 MEM_A_DM<0> OUT 30D4 72C3 SB_DM0 AR50 MEM_B_DM<0> OUT 31D4 72B3
72D3 30D4 BI MEM_A_DQ<6> AT42 SA_DQ6 72B3 31D4 BI MEM_B_DQ<6> AV50 SB_DQ6
SA_DM1 BD44 MEM_A_DM<1> OUT 30D4 72C3 SB_DM1 BD49 MEM_B_DM<1> OUT 31D4 72B3
72D3 30D6 BI MEM_A_DQ<7> AW47 SA_DQ7 72B3 31D6 BI MEM_B_DQ<7> AV49 SB_DQ7
SA_DM2 BD42 MEM_A_DM<2> OUT 30C6 72C3 SB_DM2 BK45 MEM_B_DM<2> OUT 31C4 72B3
72D3 30D6 BI MEM_A_DQ<8> BB45 SA_DQ8 72B3 31D6 BI MEM_B_DQ<8> BA50 SB_DQ8
SA_DM3 AW38 MEM_A_DM<3> OUT 30C4 72C3 SB_DM3 BL39 MEM_B_DM<3> OUT 31C6 72B3
72D3 30D6 BI MEM_A_DQ<9> BF48 SA_DQ9 72B3 31D4 BI MEM_B_DQ<9> BB50 SB_DQ9
SA_DM4 AW13 MEM_A_DM<4> OUT 30B4 72C3 SB_DM4 BH12 MEM_B_DM<4> OUT 31B4 72B3
72D3 30D6 BI MEM_A_DQ<10> BG47 SA_DQ10 72B3 31D6 BI MEM_B_DQ<10> BA49 SB_DQ10
SA_DM5 BG8 MEM_A_DM<5> OUT 30B6 72C3 SB_DM5 BJ7 MEM_B_DM<5> OUT 31A6 72B3
72D3 30D4 BI MEM_A_DQ<11> BJ45 SA_DQ11 72B3 31D4 BI MEM_B_DQ<11> BE50 SB_DQ11
SA_DM6 AY5 MEM_A_DM<6> OUT 30A6 72C3 SB_DM6 BF3 MEM_B_DM<6> OUT 31A4 72A3
72D3 30D4 BI MEM_A_DQ<12> BB47 SA_DQ12 72B3 31D6 BI MEM_B_DQ<12> BA51 SB_DQ12
SA_DM7 AN6 MEM_A_DM<7> OUT 30A4 72C3 SB_DM7 AW2 MEM_B_DM<7> OUT 31A6 72A3
72D3 30D6 BI MEM_A_DQ<13> BG50 SA_DQ13 72B3 31D6 BI MEM_B_DQ<13> AY49 SB_DQ13
72D3 30D4 BI MEM_A_DQ<14> BH49 SA_DQ14 72B3 31D4 BI MEM_B_DQ<14> BF50 SB_DQ14
SA_DQS0 AT46 MEM_A_DQS_P<0> BI 30D6 72C3 SB_DQS0 AT50 MEM_B_DQS_P<0> BI 31D6 72A3
72D3 30D4 BI MEM_A_DQ<15> BE45 SA_DQ15 72B3 31D4 BI MEM_B_DQ<15> BF49 SB_DQ15
SA_DQS1 BE48 MEM_A_DQS_P<1> BI 30D6 72C3 SB_DQS1 BD50 MEM_B_DQS_P<1> BI 31D6 72A3
72D3 30C4 BI MEM_A_DQ<16> AW43 SA_DQ16 72B3 31C4 BI MEM_B_DQ<16> BJ50 SB_DQ16
SA_DQS2 BB43 MEM_A_DQS_P<2> BI 30C4 72C3 SB_DQS2 BK46 MEM_B_DQS_P<2> BI 31C6 72A3
72D3 30C4 BI MEM_A_DQ<17> BE44 SA_DQ17 72B3 31C6 BI MEM_B_DQ<17> BJ44 SB_DQ17
SA_DQS3 BC37 MEM_A_DQS_P<3> BI 30C6 72C3 SB_DQS3 BK39 MEM_B_DQS_P<3> BI 31C4 72A3
72D3 30C6 BI MEM_A_DQ<18> BG42 SA_DQ18 72B3 31C6 BI MEM_B_DQ<18> BJ43 SB_DQ18
SA_DQS4 BB16 MEM_A_DQS_P<4> BI 30B6 72C3 SB_DQS4 BJ12 MEM_B_DQS_P<4> BI 31B6 72A3
72D3 30C6 BI MEM_A_DQ<19> BE40 SA_DQ19 72B3 31C4 BI MEM_B_DQ<19> BL43 SB_DQ19
SA_DQS5 BH6 MEM_A_DQS_P<5> BI 30B4 72C3 SB_DQS5 BL7 MEM_B_DQS_P<5> BI 31A4 72A3
72D3 30C4 BI MEM_A_DQ<20> BF44 SA_DQ20 72B3 31C6 BI MEM_B_DQ<20> BK47 SB_DQ20
SA_DQS6 BB2 MEM_A_DQS_P<6> BI 30A4 72C3 SB_DQS6 BE2 MEM_B_DQS_P<6> BI 31A6 72A3
72D3 30C6 BI MEM_A_DQ<21> BH45 SA_DQ21 72B3 31C4 BI MEM_B_DQ<21> BK49 SB_DQ21
SA_DQS7 AP3 MEM_A_DQS_P<7> BI 30A6 72C3 SB_DQS7 AV2 MEM_B_DQS_P<7> BI 31A4 72A3
MEM_A_DQ<22> SA_DQ22 MEM_B_DQ<22> SB_DQ22
C
BG40 BK43
C
72D3 30C4 BI MEM_A_DQS_N<0>
72B3 31C6 BI MEM_B_DQS_N<0>
SA_DQS0* AT47 BI 30D6 72C3 SB_DQS0* AU50 BI 31D6 72A3
72D3 30C6 BI MEM_A_DQ<23> BF40 SA_DQ23 72B3 31C4 BI MEM_B_DQ<23> BK42 SB_DQ23
SA_DQS1* BD47 MEM_A_DQS_N<1> BI 30D6 72C3 SB_DQS1* BC50 MEM_B_DQS_N<1> BI 31D6 72A3
72D3 30D6 BI MEM_A_DQ<24> AR40 SA_DQ24 72B3 31C4 BI MEM_B_DQ<24> BJ41 SB_DQ24
SA_DQS2* BC41 MEM_A_DQS_N<2> BI 30C4 72C3 SB_DQS2* BL45 MEM_B_DQS_N<2> BI 31C6 72A3
72D3 30C6 BI MEM_A_DQ<25> AW40 SA_DQ25 72B3 31C4 BI MEM_B_DQ<25> BL41 SB_DQ25
SA_DQS3* BA37 MEM_A_DQS_N<3> BI 30C6 72C3 SB_DQS3* BK38 MEM_B_DQS_N<3> BI 31C4 72A3
72D3 30C4 BI MEM_A_DQ<26> AT39 SA_DQ26 72B3 31C4 BI MEM_B_DQ<26> BJ37 SB_DQ26
SA_DQS4* BA16 MEM_A_DQS_N<4> BI 30B6 72C3 SB_DQS4* BK12 MEM_B_DQS_N<4> BI 31B6 72A3
72D3 30C6 BI MEM_A_DQ<27> AW36 SA_DQ27 72B3 31C6 BI MEM_B_DQ<27> BJ36 SB_DQ27
SA_DQS5* BH7 MEM_A_DQS_N<5> BI 30B4 72C3 SB_DQS5* BK7 MEM_B_DQS_N<5> BI 31B4 72A3
72D3 30C4 BI MEM_A_DQ<28> AW41 SA_DQ28 72B3 31C4 BI MEM_B_DQ<28> BK41 SB_DQ28
SA_DQS6* BC1 MEM_A_DQS_N<6> BI 30A4 72C3 SB_DQS6* BF2 MEM_B_DQS_N<6> BI 31A6 72A3
72D3 30D4 BI MEM_A_DQ<29> AY41 SA_DQ29 72B3 31C6 BI MEM_B_DQ<29> BJ40 SB_DQ29
SA_DQS7* AP2 MEM_A_DQS_N<7> BI 30A6 72C3 SB_DQS7* AV3 MEM_B_DQS_N<7> BI 31A4 72A3
72D3 30C4 BI MEM_A_DQ<30> AV38 SA_DQ30 72B3 31C6 BI MEM_B_DQ<30> BL35 SB_DQ30
72D3 30C6 BI MEM_A_DQ<31> AT38 SA_DQ31 72B3 31C6 BI MEM_B_DQ<31> BK37 SB_DQ31
SA_MA0 BJ19 MEM_A_A<0> OUT 30B4 32C6 72D3 SB_MA0 BC18 MEM_B_A<0> OUT 31B4 32B5 72B3
72D3 30B4 BI MEM_A_DQ<32> AV13 SA_DQ32 72B3 31B6 BI MEM_B_DQ<32> BK13 SB_DQ32
SA_MA1 BD20 MEM_A_A<1> OUT 30B6 32C6 72D3 SB_MA1 BG28 MEM_B_A<1> OUT 31B6 32B5 72B3
72D3 30B6 BI MEM_A_DQ<33> AT13 SA_DQ33 72B3 31B4 BI MEM_B_DQ<33> BE11 SB_DQ33
SA_MA2 BK27 MEM_A_A<2> OUT 30B4 32C6 72D3 SB_MA2 BG25 MEM_B_A<2> OUT 31B4 32B5 72B3
72D3 30B4 BI MEM_A_DQ<34> AW11 SA_DQ34 72B3 31B4 BI MEM_B_DQ<34> BK11 SB_DQ34
SA_MA3 BH28 MEM_A_A<3> OUT 30B6 32C6 72D3 SB_MA3 AW17 MEM_B_A<3> OUT 31B6 32B5 72B3
72D3 30B4 BI MEM_A_DQ<35> AV11 SA_DQ35 72B3 31B6 BI MEM_B_DQ<35> BC11 SB_DQ35
SA_MA4 BL24 MEM_A_A<4> OUT 30B4 32C6 72D3 SB_MA4 BF25 MEM_B_A<4> OUT 31B4 32B5 72B3
72D3 30B6 BI MEM_A_DQ<36> AU15 SA_DQ36 72B3 31B4 BI MEM_B_DQ<36> BC13 SB_DQ36
SA_MA5 BK28 MEM_A_A<5> OUT 30B6 32C6 72D3 SB_MA5 BE25 MEM_B_A<5> OUT 31B6 32B5 72B3
72D3 30B4 BI MEM_A_DQ<37> AT11 SA_DQ37 72B3 31B4 BI MEM_B_DQ<37> BE12 SB_DQ37
SA_MA6 BJ27 MEM_A_A<6> OUT 30C4 32C6 72D3 SB_MA6 BA29 MEM_B_A<6> OUT 31C4 32B5 72B3
72D3 30B6 BI MEM_A_DQ<38> BA13 SA_DQ38 72B3 31B6 BI MEM_B_DQ<38> BC12 SB_DQ38
SA_MA7 BJ25 MEM_A_A<7> OUT 30C4 32C6 72D3 SB_MA7 BC28 MEM_B_A<7> OUT 31C4 32B5 72B3
72D3 30B6 BI MEM_A_DQ<39> BA11 SA_DQ39 72B3 31B6 BI MEM_B_DQ<39> BG12 SB_DQ39
SA_MA8 BL28 MEM_A_A<8> OUT 30C6 32C6 72D3 SB_MA8 AY28 MEM_B_A<8> OUT 31C6 32B5 72B3
72D3 30B4 BI MEM_A_DQ<40> BE10 SA_DQ40 72B3 31A6 BI MEM_B_DQ<40> BJ10 SB_DQ40
SA_MA9 BA28 MEM_A_A<9> OUT 30C6 32C6 72D3 SB_MA9 BD37 MEM_B_A<9> OUT 31C6 32B5 72B3
72D3 30B6 BI MEM_A_DQ<41> BD10 SA_DQ41 72B3 31A4 BI MEM_B_DQ<41> BL9 SB_DQ41
SA_MA10 BC19 MEM_A_A<10> OUT 30B6 32C6 72D3 SB_MA10 BG17 MEM_B_A<10> OUT 31B6 32B5 72B3
72D3 30B6 BI MEM_A_DQ<42> BD8 SA_DQ42 72B3 31B4 BI MEM_B_DQ<42> BK5 SB_DQ42
SA_MA11 BE28 MEM_A_A<11> OUT 30C4 32C6 72D3 SB_MA11 BE37 MEM_B_A<11> OUT 31C4 32A5 72B3
72D3 30A6 BI MEM_A_DQ<43> AY9 SA_DQ43 72B3 31B4 BI MEM_B_DQ<43> BL5 SB_DQ43
SA_MA12 BG30 MEM_A_A<12> OUT 30C6 32C6 72D3 SB_MA12 BA39 MEM_B_A<12> OUT 31C6 32A5 72B3
72D3 30B4 BI MEM_A_DQ<44> BG10 SA_DQ44 72B3 31A6 BI MEM_B_DQ<44> BK9 SB_DQ44
SA_MA13 BJ16 MEM_A_A<13> OUT 30B4 32C6 72D3 SB_MA13 BG13 MEM_B_A<13> OUT 31B4 32A5 72B3
72D3 30A4 BI MEM_A_DQ<45> AW9 SA_DQ45 72B3 31B6 BI MEM_B_DQ<45> BK10 SB_DQ45
72D3 30A6 BI MEM_A_DQ<46> BD7 SA_DQ46 72B3 31A4 BI MEM_B_DQ<46> BJ8 SB_DQ46
SA_RAS* BE18 MEM_A_RAS_L OUT 30B4 32B6 72D3 SB_RAS* AV16 MEM_B_RAS_L OUT 31B4 32A6 72B3
72D3 30A4 BI MEM_A_DQ<47> BB9 SA_DQ47 72B3 31B6 BI MEM_B_DQ<47> BJ6 SB_DQ47
SA_RCVEN* AY20 TP_MEM_A_RCVEN_L SB_RCVEN* AY18 TP_MEM_B_RCVEN_L
72D3 30A4 BI MEM_A_DQ<48> BB5 SA_DQ48 72B3 31A6 BI MEM_B_DQ<48> BF4 SB_DQ48
B 72D3 30A6
72D3 30A4
BI
BI
MEM_A_DQ<49>
MEM_A_DQ<50>
AY7
AT5
SA_DQ49
SA_DQ50
SA_WE* BA19 MEM_A_WE_L OUT 30B6 32B6 72D3
72B3 31A4
72B3 31A6
BI
BI
MEM_B_DQ<49>
MEM_B_DQ<50>
BH5
BG1
SB_DQ49
SB_DQ50
SB_WE* BC17 MEM_B_WE_L OUT 31B6 32A6 72B3 B
72D3 30A6 BI MEM_A_DQ<51> AT7 SA_DQ51 72B3 31A4 BI MEM_B_DQ<51> BC2 SB_DQ51
72D3 30A6 BI MEM_A_DQ<52> AY6 SA_DQ52 72B3 31A6 BI MEM_B_DQ<52> BK3 SB_DQ52
72D3 30A4 BI MEM_A_DQ<53> BB7 SA_DQ53 72B3 31A4 BI MEM_B_DQ<53> BE4 SB_DQ53
72D3 30A4 BI MEM_A_DQ<54> AR5 SA_DQ54 72B3 31A4 BI MEM_B_DQ<54> BD3 SB_DQ54
72D3 30A6 BI MEM_A_DQ<55> AR8 SA_DQ55 72B3 31A6 BI MEM_B_DQ<55> BJ2 SB_DQ55
72D3 30A6 BI MEM_A_DQ<56> AR9 SA_DQ56 72B3 31A6 BI MEM_B_DQ<56> BA3 SB_DQ56
72D3 30A6 BI MEM_A_DQ<57> AN3 SA_DQ57 72B3 31A6 BI MEM_B_DQ<57> BB3 SB_DQ57
72D3 30A4 BI MEM_A_DQ<58> AM8 SA_DQ58 72B3 31A4 BI MEM_B_DQ<58> AR1 SB_DQ58
72D3 30A6 BI MEM_A_DQ<59> AN10 SA_DQ59 72B3 31A4 BI MEM_B_DQ<59> AT3 SB_DQ59
72D3 30A4 BI MEM_A_DQ<60> AT9 SA_DQ60 72B3 31A4 BI MEM_B_DQ<60> AY2 SB_DQ60
72D3 30A4 BI MEM_A_DQ<61> AN9 SA_DQ61 72B3 31A6 BI MEM_B_DQ<61> AY3 SB_DQ61
72D3 30A4 BI MEM_A_DQ<62> AM9 SA_DQ62 72B3 31A4 BI MEM_B_DQ<62> AU2 SB_DQ62
72D3 30A6 BI MEM_A_DQ<63> AN11 SA_DQ63 72B3 31A6 BI MEM_B_DQ<63> AT2 SB_DQ63
NB DDR2 Interfaces

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 17 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
U1400 OMIT
20D8 20B4 17D3 7C7 =PPVCORE_S0_NB CRESTLINE =PPVCORE_S0_NB_GFX 7B7 17B7 21C5 48B3 NCTF balls are Not Critical To Function
AT35 VCC1 VCC_AXG_NCTF1 T17
1310 mA (Ext Graphics) These connections can break without
AT34 VCC2 (6 FCBGA
OF 10) VCC_AXG_NCTF2 T18
1573 mA (Int Graphics) impacting part performance.
AH28 VCC3 VCC_AXG_NCTF3 T19
POWER
AC32 VCC5 VCC_AXG_NCTF4 T21 OMIT
AC31 VCC4 VCC_AXG_NCTF5 T22
VCC CORE
AK32 VCC6 VCC_AXG_NCTF6 T23 U1400
20D8 20B4 17D7 7C7 =PPVCORE_S0_NB CRESTLINE
AJ31 VCC7 VCC_AXG_NCTF7 T25
AB33 VCC_NCTF1
AJ28 U15 FCBGA
VCC8 VCC_AXG_NCTF8 AB36 VCC_NCTF2 (7 OF 10)
AH32 VCC9 VCC_AXG_NCTF9 U16
D
AB37 VCC_NCTF3
POWER
D VCC10
AH31 VCC_AXG_NCTF10 U17
AC33 VCC_NCTF4
AH29 VCC11 VCC_AXG_NCTF11 U19
AC35 VCC_NCTF5
AF32 VCC12 VCC_AXG_NCTF12 U20 VSS_NCTF1 T27
AC36 VCC_NCTF6
VCC_AXG_NCTF13 U21 VSS_NCTF2 T37
AD35 VCC_NCTF7
VCC_AXG_NCTF14 U23 VSS_NCTF3 U24
AD36 VCC_NCTF8
VCC_AXG_NCTF15 U26 VSS_NCTF4 U28
AF33 VCC_NCTF9
R30 VCC13 VCC_AXG_NCTF16 V16 VSS_NCTF5 V31
AF36 VCC_NCTF10
VCC_AXG_NCTF17 V17 VSS_NCTF6 V35
AH33 VCC_NCTF11
VCC_AXG_NCTF18 V19 VSS_NCTF7 AA19
VSS NCTF
AH35 VCC_NCTF12
VCC_AXG_NCTF19 V20 VSS_NCTF8 AB17
AH36 VCC_NCTF13
31D2 30D2 20C8 15D2 7A4 =PP1V8_S3M_MEM_NB VCC_AXG_NCTF20 V21 VSS_NCTF9 AB35
AH37 VCC_NCTF14
AU32 VCC_SM1 VCC_AXG_NCTF21 V23 VSS_NCTF10 AD19
3300 mA (2 ch, 667MHz) AJ33 VCC_NCTF15
AU33 VCC_SM2 VCC_AXG_NCTF22 V24 VSS_NCTF11 AD37
2700 mA (2 ch, 533MHz) AJ35 VCC_NCTF16
AU35 VCC_SM3 VCC_AXG_NCTF23 Y15 VSS_NCTF12 AF17
1700 mA (1 ch, 667MHz) AK33 VCC_NCTF17
AV33 VCC_SM4 VCC_AXG_NCTF24 Y16 VSS_NCTF13 AF35
1395 mA (1 ch, 533MHz) AK35 VCC_NCTF18
AW33 VCC_SM5 VCC_AXG_NCTF25 Y17 VSS_NCTF14 AK17
5 mA (standby) AK36 VCC_NCTF19
AW35 VCC_SM6 VCC_AXG_NCTF26 Y19 VSS_NCTF15 AM17
AK37 VCC_NCTF20
AY35 VCC_SM7 VCC_AXG_NCTF27 Y20 VSS_NCTF16 AM24
AD33 VCC_NCTF21
BA32 VCC_SM8 VCC_AXG_NCTF28 Y21 VSS_NCTF17 AP26
AJ36
VCC NCTF
VCC_NCTF22
BA33 VCC_SM9 VCC_AXG_NCTF29 Y23 VSS_NCTF18 AP28
AM35 VCC_NCTF23
BA35 VCC_SM10 VCC_AXG_NCTF20 Y24 VSS_NCTF19 AR15
AL33 VCC_NCTF24
BB33 VCC_SM11 VCC_AXG_NCTF31 Y26 VSS_NCTF20 AR19
AL35 VCC_NCTF25
BC32 VCC_SM12 VCC_AXG_NCTF32 Y28 VSS_NCTF21 AR28
AA33 VCC_NCTF26
BC33 VCC_SM13 VCC_AXG_NCTF33 Y29
AA35 VCC_NCTF27
BC35 VCC_SM14 VCC_AXG_NCTF34 AA16
AA36 VCC_NCTF28
BD32 VCC_SM15 VCC_AXG_NCTF35 AA17
AP35 VCC_NCTF29
BD35 VCC_SM16 VCC_AXG_NCTF36 AB16
C C
VCC SM
AP36 VCC_NCTF30
VSS SCB
VCC GFX NCTF
BE32 VCC_SM17 VCC_AXG_NCTF37 AB19 VSS_SCB1 A3
AR35 VCC_NCTF31
BE33 VCC_SM18 VCC_AXG_NCTF38 AC16 VSS_SCB2 B2
AR36 VCC_NCTF32
BE35 VCC_SM19 VCC_AXG_NCTF39 AC17 VSS_SCB3 C1
Y32 VCC_NCTF33
BF33 VCC_SM20 VCC_AXG_NCTF40 AC19 VSS_SCB4 BL1
Y33 VCC_NCTF34
BF34 VCC_SM21 VCC_AXG_NCTF41 AD15 VSS_SCB5 BL51
Y35 VCC_NCTF35
BG32 VCC_SM22 VCC_AXG_NCTF42 AD16 VSS_SCB6 A51
Y36 VCC_NCTF36
BG33 VCC_SM23 VCC_AXG_NCTF43 AD17
Y37 VCC_NCTF37
BG35 VCC_SM24 VCC_AXG_NCTF44 AF16
T30 VCC_NCTF38
BH32 VCC_SM25 VCC_AXG_NCTF45 AF19
T34 VCC_NCTF39
BH34 VCC_SM26 VCC_AXG_NCTF46 AH15 =PP1V05_S0M_NB_VCCAXM 7C7 17B3 20D8
T35 VCC_NCTF40
VCC AXM
BH35 VCC_SM27 VCC_AXG_NCTF47 AH16 VCC_AXM1 AT33
U29 VCC_NCTF41 540 mA
BJ32 VCC_SM28 VCC_AXG_NCTF48 AH17 VCC_AXM2 AT31
U31 VCC_NCTF42
BJ33 VCC_SM29 VCC_AXG_NCTF49 AH19 VCC_AXM3 AK29
U32 VCC_NCTF43
BJ34 VCC_SM30 VCC_AXG_NCTF50 AJ16 VCC_AXM4 AK24
U33 VCC_NCTF44
BK32 VCC_SM31 VCC_AXG_NCTF51 AJ17 VCC_AXM5 AK23
U35 VCC_NCTF45
BK33 VCC_SM32 VCC_AXG_NCTF52 AJ19 VCC_AXM6 AJ26
U36 VCC_NCTF46
BK34 VCC_SM33 VCC_AXG_NCTF53 AK16 VCC_AXM7 AJ23
V32 VCC_NCTF47
BK35 VCC_SM34 VCC_AXG_NCTF54 AK19
V33 VCC_NCTF48
BL33 VCC_SM35 VCC_AXG_NCTF55 AL16
V36 VCC_NCTF49
AU30 VCC_SM36 VCC_AXG_NCTF56 AL17
V37 VCC_NCTF50
VCC_AXG_NCTF57 AL19
VCC_AXG_NCTF58 AL20
VCC_AXG_NCTF59 AL21
20D8 17C1 7C7 =PP1V05_S0M_NB_VCCAXM
48B3 21C5 17D5 7B7 =PPVCORE_S0_NB_GFX VCC_AXG_NCTF60 AL23
AL24 VCC_AXM_NCTF1
R20 VCC_AXG1 VCC_AXG_NCTF61 AM15
7700 mA (Int Graphics) AL26 VCC_AXM_NCTF2
T14 VCC_AXG2 VCC_AXG_NCTF62 AM16
B B
AL28 VCC_AXM_NCTF3
W13 VCC_AXG3 VCC_AXG_NCTF63 AM19
AM26 VCC_AXM_NCTF4
VCC AXM NCTF

W14 VCC_AXG4 VCC_AXG_NCTF64 AM20
AM28 VCC_AXM_NCTF5
Y12 VCC_AXG5 VCC_AXG_NCTF65 AM21
AM29 VCC_AXM_NCTF6
AA20 VCC_AXG6 VCC_AXG_NCTF66 AM23
AM31 VCC_AXM_NCTF7
AA23 VCC_AXG7 VCC_AXG_NCTF67 AP15
AM32 VCC_AXM_NCTF8
AM33 VCC_AXM_NCTF9
AP29 VCC_AXM_NCTF10
AB21 VCC_AXG10 VCC_AXG_NCTF70 AP19
AP31 VCC_AXM_NCTF11
AP32 VCC_AXM_NCTF12
AP33 VCC_AXM_NCTF13
AC20 VCC_AXG13 VCC_AXG_NCTF73 AP23
AL29 VCC_AXM_NCTF14
AC21 VCC_AXG14 VCC_AXG_NCTF74 AP24
AL31 VCC_AXM_NCTF15
VCC GFX
AC23 VCC_AXG15 VCC_AXG_NCTF75 AR20

AL32 VCC_AXM_NCTF16
AR31 VCC_AXM_NCTF17
AR32 VCC_AXM_NCTF18
AR33 VCC_AXM_NCTF19
AD20 VCC_AXG20 VCC_AXG_NCTF80 V26
AD28 VCC_AXG23 VCC_AXG_NCTF83 Y31
AF21 VCC_AXG24
AF26 VCC_AXG25
AA31 VCC_AXG26
AH20 VCC_AXG27 NB Power 1
VCC SM LF
AH21 VCC_AXG28 VCC_SM_LF1 AW45 NB_VCCSM_LF1

A AH23
AH24
VCC_AXG29
VCC_AXG30
VCC_SM_LF2
VCC_SM_LF3
BC39
BE39
NB_VCCSM_LF2
NB_VCCSM_LF3
SYNC_MASTER=T9_MLB

A
AH26 VCC_AXG31 VCC_SM_LF4 BD17 NB_VCCSM_LF4
AD31 VCC_AXG32 VCC_SM_LF5 BD4 NB_VCCSM_LF5 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AJ20 VCC_AXG33 VCC_SM_LF6 AW8 NB_VCCSM_LF6
AN14 VCC_AXG34 VCC_SM_LF7 AT6 NB_VCCSM_LF7
C1807 1
C1806 1
C1805 1
C1804 1
C1803 1
C1802 1
C1801 1
0.1uF 0.1uF 0.22UF 0.22UF 0.47UF 1uF 1uF SIZE DRAWING NUMBER REV.
20% 20% 20% 20% 10% 10% 10%
10V
CERM
402
2
10V
CERM
402
2
6.3V
X5R
402
2
6.3V
X5R
402
2
6.3V
CERM-X5R
402
2
6.3V
CERM
402
2
6.3V
CERM
402
2
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 18 106
Current numbers from Crestline EDS, doc #21749.
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
OMIT
U1400
CRESTLINE =PP1V25R1V05_S0_NB_VTT 7C7 20C8 TBD mA @ 1067MHz FSB (1.25V)
=PP3V3_S0_NB_VCCSYNC J32 U13
30 mA 21B5 7C4 VCC_SYNC FCBGA VTT1 850 mA @ 800MHz FSB (1.05V)
(8 OF 10) VTT2 U12 770 mA @ 667MHz FSB (1.05V)
80 mA PP3V3_S0_NB_VCCA_CRTDAC A33
VCCA_CRT_DAC1 VTT3 U11
POWER
21D1
CRT
B33 U9
VCCA_CRT_DAC2 VTT4
VTT5 U8
5 mA 21B1 PP3V3_S0_NB_VCCA_DAC_BG A30

VCCA_DAC_BG VTT6 U7
VTT7 U5
D 21B1 =GND_NB_VSSA_DAC_BG B32

VSSA_DAC_BG VTT8
VTT9
U3
U2
D
VTT10 U1
VTT
VTT11 T13
PP1V25_S0_NB_VCCA_DPLLA B49 T11

21A3 VCCA_DPLLA VTT12
100 mA VTT13 T10
PP1V25_S0_NB_VCCA_DPLLB H49 T9
PLL
21A3 VCCA_DPLLB VTT14
VTT15 T7
PP1V25_S0M_NB_VCCA_HPLL AL2
50 mA 20D1 VCCA_HPLL VTT16 T6
VTT17 T5
PP1V25_S0M_NB_VCCA_MPLL AM2 T3
150 mA 20C1 VCCA_MPLL VTT18
VTT19 T2
VTT20 R3
A LVDS
S0 or S3M is acceptable VTT21 R2
18B3 PP1V8_S0_NB_VCCTXLVDS
A41
10 mA 21C3 VCCA_LVDS VTT22 R1
=GND_NB_VSSA_LVDS B41
21B3 VSSA_LVDS
PP1V25_S0M_NB_VCCAXD 15A2 20A6 515 mA
VCC_AXD1 AT23
VCC_AXD2 AU28
0.4 mA =PP3V3_S0_NB_VCCA_PEG_BG K50

VCCA_PEG_BG VCC_AXD3 AU24
A PEG
20A6 7C4
AXD
VCC_AXD4 AT29
=GND_NB_VSSA_PEG_BG K49 AT25

20A6 VSSA_PEG_BG VCC_AXD5
VCC_AXD6 AT30
PP1V25_S0_NB_PEGPLL U51
100 mA 20B2 VCCA_PEG_PLL
VCC_AXD_NCTF AR29
C 640 mA (667MHz DDR)

550 mA (533MHz DDR)
20B5 PP1V25_S0M_NB_VCCA_SM
AW18
VCCA_SM1 PP1V25_S0_NB_VCCAXF 20D5 495 mA
C
AXF
AV19 B23
VCCA_SM2 VCC_AXF1
AU19 B21
VCCA_SM3 VCC_AXF2
AU18 A21
VCCA_SM4 VCC_AXF3
AU17
VCCA_SM5
A SM
AT22 =PP1V25_S0_NB_VCCDMI
VCCA_SM7 7C7 20A8 100 mA
AT21 AJ50
VCCA_SM8 VCC_DMI
AT19
VCCA_SM9
AT18
VCCA_SM10
AT17 PP1V8_S3M_NB_VCCSMCK
VCCA_SM11 20A2 200 mA
SM CK
VCC_SM_CK1 BK24
AR17 BK23
VCCA_SM_NCTF1 VCC_SM_CK2
AR16 BJ24
VCCA_SM_NCTF2 VCC_SM_CK3
VCC_SM_CK4 BJ23
35 mA PP1V25_S0M_NB_VCCA_SM_CK
A CK
20B5
BC29
VCCA_SM_CK1 S0 or S3M is acceptable
BB29 A43 PP1V8_S0_NB_VCCTXLVDS
VCCA_SM_CK2 VCC_TX_LVDS 18C6 21C3 100 mA
=PP3V3_S0_NB_VCCHV 7D4 15B7 15C7 20A8 100 mA

21B7
PP3V3_S0_NB_VCCA_TVDACC C25
HV
40 mA 21C1 VCCA_TVA_DAC1 VCC_HV1 C40
B25 B40
VCCA_TVA_DAC2 VCC_HV2
CRT
PP3V3_S0_NB_VCCA_TVDACB C27
40 mA 21C1 VCCA_TVB_DAC1
B 40 mA 21D1 PP3V3_S0_NB_VCCA_TVDACA
B27
B28
VCCA_TVB_DAC2
VCCA_TVC_DAC1 PP1V05_S0_NB_VCCPEG 14D2 20D3 1260 mA
B
A28 AD51
VCCA_TVC_DAC2 VCC_PEG1
PEG
VCC_PEG2 W50
VCC_PEG3 W51
VCC_PEG4 V49
TV/CRT
=PP1V5_S0_NB_VCCD_CRT M32 V50
60 mA 21C7 VCCD_CRT VCC_PEG5
PP1V5_S0_NB_VCCD_TVDAC L29
60 mA 21D6 VCCD_TVDAC
N28
PP1V05_S0_NB_VCCRXRDMI 20C3 260 mA
PP1V5_S0_NB_VCCD_QDAC
DMI
5 mA 21C5 VCCD_QDAC AH50
VCC_RXR_DMI1
VCC_RXR_DMI2 AH51
250 mA 20D1 =PP1V25_S0M_NB_VCCD_HPLL

AN2
VCCD_HPLL
VTTLF
D
U48 VTTLF1 A7 NB_VTTLF_CAP1
VCCD_PEG_PLL
VTTLF2 F2 NB_VTTLF_CAP2
LVDS VTTLF3 AH1 NB_VTTLF_CAP3
150 mA 21B3 =PP1V8_S0_NB_VCCD_LVDS

J41
1
C1913 1
C1912 1
C1911
VCCD_LVDS1 0.47UF 0.47UF 0.47UF
H42 10% 10% 10%
VCCD_LVDS2 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
402 402 402
NB Power 2

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 19 106
Current numbers from Crestline EDS, doc #21749.
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
CRESTLINE CRESTLINE
A13 VSS1 VSS100 AW24 C46 VSS199 VSS287 W11
FCBGA FCBGA
A15 VSS2 (9 OF 10) VSS101 AW29 C50 VSS200 (10 OF 10) VSS288 W39
A17 VSS3 VSS102 AW32 C7 VSS201 VSS289 W43
VSS
VSS
A24 VSS4 VSS103 AW5 D13 VSS202 VSS290 W47
AA21 VSS5 VSS104 AW7 D24 VSS203 VSS291 W5
AA24 VSS6 VSS105 AY10 D3 VSS204 VSS292 W7
AA29 VSS7 VSS106 AY24 D32 VSS205 VSS293 Y13
AB20 VSS8 VSS107 AY37 D39 VSS206 VSS294 Y2
D
AB23 VSS9 VSS108 AY42 D45 VSS207 VSS295 Y41
D AB26
AB28
VSS10
VSS11
VSS109
VSS110
AY43
AY45
D49
E10
VSS208
VSS209
VSS296
VSS297
Y45
Y49
AB31 VSS12 VSS111 AY47 E16 VSS210 VSS298 Y5
AC10 VSS13 VSS112 AY50 E24 VSS211 VSS299 Y50 Crestline Thermal Diode Pins
AC13 VSS14 VSS113 B10 E28 VSS212 VSS300 Y11
AC3 B20 E32 P29

Mainly for investigation. If not used,
VSS15 VSS114 VSS213 VSS301
AC39 B24 E47
alias these nets directly to GND.
VSS16 VSS115 VSS214
AC43 VSS17 VSS116 B29 F19 VSS215
AC47 VSS18 VSS117 B30 F36 VSS216 TDE_SENSE VSS302 T29 =NB_TDE_SENSE 8A2
AD1 VSS19 VSS118 B35 F4 VSS217
AD21 B38 F40
NOTE: TDE = _P
VSS20 VSS119 VSS218
AD26 VSS21 VSS120 B43 F50 VSS219 TDE_FORCE VSS303 T31 =NB_TDE_FORCE 8A2
AD29 VSS22 VSS121 B46 G1 VSS220
AD3 VSS23 VSS122 B5 G13 VSS221
AD41 VSS24 VSS123 B8 G16 VSS222 TDB_FORCE VSS304 T33 =NB_TDB_FORCE 8A2
AD45 VSS25 VSS124 BA1 G19 VSS223
AD49 BA17 G24
NOTE: TDB = _N
VSS26 VSS125 VSS224
AD5 VSS27 VSS126 BA18 G28 VSS225 TDB_SENSE VSS305 R28 =NB_TDB_SENSE 8A2
AE10 VSS30 VSS129 BB12 G42 VSS228
AE14 VSS31 VSS130 BB25 G45 VSS229 VSS306 AA32
AE6 VSS32 VSS131 BB40 G48 VSS230 VSS307 AB32
AF20 VSS33 VSS132 BB44 G8 VSS231 VSS308 AD32
AF23 VSS34 VSS133 BB49 H24 VSS232 VSS309 AF28
AF24 VSS35 VSS134 BB8 H28 VSS233 VSS310 AF29
C AF31
AG2
VSS36
VSS37
VSS135
VSS136
BC16
BC24
H4
H45
VSS234
VSS235
VSS311
VSS312
AT27
AV25 C
AG38 VSS38 VSS137 BC25 J11 VSS236 VSS313 H50
AG43 VSS39 VSS138 BC36 J16 VSS237

AH3 VSS42 VSS141 BD13 J28 VSS240
AH9 VSS46 VSS145 BD48
AJ11 VSS47 VSS146 BD5 K12 VSS245

AJ13 VSS48 VSS147 BE1 K47 VSS246
AJ21 VSS49 VSS148 BE19 K8 VSS247
AJ24 VSS50 VSS149 BE23 L1 VSS248
AJ49 VSS55 VSS154 BF12 L3 VSS253
AK20 VSS56 VSS155 BF16 L33 VSS254
AK21 VSS57 VSS156 BF36 L49 VSS255
AK26 VSS58 VSS157 BG19 M28 VSS256
B B
AL1 VSS62 VSS161 BG39 M5 VSS260
AM11 VSS63 VSS162 BG48 M50 VSS261
AM13 VSS64 VSS163 BG5 M9 VSS262
AM3 VSS65 VSS164 BG51 N11 VSS263
AM4 VSS66 VSS165 BH17 N14 VSS264
AN1 VSS69 VSS168 BH46 N32 VSS267
AN38 VSS70 VSS169 BH8 N36 VSS268
AN39 VSS71 VSS170 BJ11 N39 VSS269
AP4 VSS75 VSS174 BJ42 P19 VSS273
AP48 VSS76 VSS175 BJ46 P2 VSS274
AP50 VSS77 VSS176 BK15 P23 VSS275
AR11 VSS78 VSS177 BK17 P3 VSS276
AR2 VSS79 VSS178 BK25 P50 VSS277
AR39 VSS80 VSS179 BK29 R49 VSS278
AR44 VSS81 VSS180 BK36 T39 VSS279
AT10 VSS84 VSS183 BK6 U41 VSS282
AT14 VSS85 VSS184 BK8 U45 VSS283
AT41 BL11 U50
AT49
VSS86
VSS87
VSS185
VSS186 BL13 V2
VSS284
VSS285
NB Grounds
A AU1
AU23
VSS88
VSS89
VSS187
VSS188
BL19
BL22
V3 VSS286 SYNC_MASTER=T9_MLB

A
AU29 VSS90 VSS189 BL37
AU3 VSS91 VSS190 BL47 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
AU36 C12
VSS92 VSS191 AGREES TO THE FOLLOWING
AU49 VSS93 VSS192 C16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
AU51 VSS94 VSS193 C19 II NOT TO REPRODUCE OR COPY IT
AV39 VSS95 VSS194 C28 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
AV48 VSS96 VSS195 C29
AW1 C33
VSS97 VSS196
AW12
AW16
VSS98
VSS99
VSS197
VSS198
C36
C41
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 20 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
I/O voltage Supply

GMCH Core Power Host PLL Digital Supply
18C3 PP1V25_S0_NB_VCCAXF =PP1V25_S0_NB_VCCAXF 7C7
20B4 17D7 17D3 7C7 =PPVCORE_S0_NB MIN_LINE_WIDTH=0.4 MM 20B4 7C7 =PP1V25_S0_NB_PLL =PP1V25_S0M_NB_VCCD_HPLL 18A6
MIN_NECK_WIDTH=0.2 MM 350 mA
VOLTAGE=1.25V
450 mA 250 mA
CRITICAL
C2170 1 1 C2171
D C2100 1
470UF
1 C2101
22UF
1 C2102
0.22uF
1 C2103
0.22uF
1 C2104
0.1UF
10uF
20%
6.3V 2
10%
1UF
1 C2180
0.1UF D
20% 20% 20% 20% 20% 2 6.3V 20%
2.5V 2 3 2 6.3V
CERM
6.3V
2 X5R 2 6.3V
X5R 2 10V
CERM
X5R
603
CERM
402 2 10V
CERM
TANT
D2T 805 402 402 402 402
250mA,0.5ohm
PLACEMENT_NOTE=Place in GMCH cavity
L2181 Host PLL Analog Supply
120-OHM-0.3A-EMI PP1V25_S0M_NB_VCCA_HPLL 18D6
CRITICAL 1 2 MIN_LINE_WIDTH=0.25 MM
GMCH ME Core Power MIN_NECK_WIDTH=0.2 MM
L2173 Analog,I/O logic,and Term Voltage for PCI-E Graphics 0402-LF VOLTAGE=1.25V 50 mA
=PP1V05_S0M_NB_VCCAXM =PP1V05_S0_NB_PCIE 91NH PP1V05_S0_NB_VCCPEG
17C1 17B3 7C7 7C7
1 2 MIN_LINE_WIDTH=0.5 MM
14D2 18B3
C2181 1 1 C2182
540 mA 1450 mA OMIT VOLTAGE=1.05V 1200 mA 22UF 0.1UF
1210 CRITICAL 20% 20%
6.3V 2 2 10V
1 C2110 1 C2111 1 C2112 1 C2113 1 C2114 1 C2115 Layout Note: C2173 1 1 C2174 Layout Note:
CERM
805
CERM
402
22UF 0.22uF 0.22uF 0.1UF 0.1UF 0.1UF 220UF 10uF
20% 20% 20% 20% 20% 20% Place L and C 20% 20% 10uF caps should
6.3V 6.3V
2 6.3V
2 CERM 2 X5R X5R 2 10V
CERM 2 10V
CERM 2 10V
CERM 2.5V 2 2 6.3V
X5R 250mA,0.5ohm
805 402 402 402 402 402 close to MCH POLY
CASE-B2 603 be close to MCH
on opposite side. L2183 MPLL Analog Supply
120-OHM-0.3A-EMI PP1V25_S0M_NB_VCCA_MPLL 18D6
0402-LF VOLTAGE=1.25V 150 mA
GMCH FSB I/O Rail
RX and I/O Logic for DMI R21831 1 C2184
18D3 7C7 =PP1V25R1V05_S0_NB_VTT PP1V05_S0_NB_VCCRXRDMI 18B3 0.51 0.1UF
MIN_LINE_WIDTH=0.3 MM 1% 20%
MIN_NECK_WIDTH=0.2 MM 1/16W 10V
850 mA VOLTAGE=1.05V 250 mA MF-LF 2 CERM
402 402
2
C2121 1 C2122 1 C2123 1 C2124 1 1 C2177 Layout Note: PP1V25_S0M_NB_MPLL_RC PLACEMENT_NOTE=Place C2184 by U1400.AM2
4.7uF 4.7uF 2.2uF 0.47UF 10uF MIN_LINE_WIDTH=0.3 MM
20% 20% 20% 10% 20% 10uF caps should MIN_NECK_WIDTH=0.2 MM
6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM1 2 CERM-X5R 2 2 X5R VOLTAGE=1.25V
603 603 603 402 603 be close to MCH C2183 1
C PLACEMENT_NOTE=Place close to U1400
on opposite side. 22UF
20%
6.3V 2
CERM
These supplies are still needed even using external GPU
C
805
WF: Matanzas has 270uF

GMCH Memory I/O Rail
31D2 30D2 17D7 15D2 7A4 =PP1V8_S3M_MEM_NB
OMIT
2400 mA
CRITICAL
C2130 1 1 C2135 1 C2131 1 C2132
330UF 0.1UF 22UF 22UF
20% 20% 20% 20%
2.5V 2 2 10V
CERM 2 6.3V
CERM 2 6.3V
CERM
POLY
CASE-C2 402 805 805
this is "1 of 2" 1.8V bulk decoupling caps.

PLACEMENT_NOTE=Place close to U1400
WF: "Place where LVDS
and DDR2 taps." (C2125)
D2186 R2186
spec requires "3.9uH ferrite,1A,32mohm max". Memory I/O logic and DLL voltage. 1SS418 10
7C7 =PP1V25_S0_NB_VCCA R2141 PP1V25_S0M_NB_VCCA_SM 18C6
17D7
7C7 =PPVCORE_S0_NB 2 1 PP3V3_S0_NBCORE_FOLLOW_R 1 2 =PP3V3_S0_NB_FOLLOW 7D4
1
0 2
MIN_LINE_WIDTH=0.4 MM 17D3
20D8
OMIT MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 1%
??? mA VOLTAGE=1.25V ??? mA SOD-723 VOLTAGE=3.3V 1/16W
CRITICAL 5%
1/16W
MF-LF
402
C2140 1 MF-LF
402
1 C2142 1 C2143 1 C2144 NOTE: This follower is redundant if VCORE is always 1.05V.
330UF 22UF 4.7UF 1UF
20% 20% 10% 10%
6.3V 6.3V
2.0V 2 2 CERM 2 X5R-CERM 2 6.3V
CERM
POLY
CASE-B2 805 603 402
WF: 220-ohm Analog PLL Voltage for PCI-E GPU

L2190
Memory clock logic voltage. =PP1V25_S0_NB_PLL FERR-220-OHM-2.5A PP1V25_S0_NB_PEGPLL
R2145 PP1V25_S0M_NB_VCCA_SM_CK 18B6
20D3 7C7
18C6
0 1 2
B 1
5%
2
NOSTUFF
VOLTAGE=1.25V ??? mA
100 mA 0603
VOLTAGE=1.25V 100 mA B
1/16W
MF-LF 1 C2145 1 C2147 1 C2148 R21901 1 C2191 1 C2192
402
22UF 2.2UF 0.1UF 1.1 0.1UF 0.1UF
20% 20% 20% WF: Should be 1.0, 1% 1% 20% 20%
6.3V 6.3V 10V 1/16W
2 CERM 2 CERM 2 CERM MF-LF 2 10V
CERM
10V
2 CERM
805 402-LF 402 402 2 402 402
PP1V25_S0_NB_PEGPLL_RC
VOLTAGE=1.25V
5.6nH,0.9A,45mohm max.no bigger than 0603
C2190 1
10uF
Memory voltage supply. 20%
200 mA 6.3V 2
7C7 =PP1V25_S0_NB_VCC
R2109 PP1V25_S0M_NB_VCCAXD 15A2 18C3 X5R
603
1
200 mA VOLTAGE=1.25V
5%
1/16W
NOSTUFF
MF-LF
402
C2150 1 1 C2151 20A5 7B4 =PP1V8_S3_MEMVREF
=PP1V8_S3_MEMVREF
10uF 1UF 20A6 7B4
20%
6.3V
X5R 2
10%
6.3V
2 CERM
R21121 R21101
need to find "1uH,220mA,150mohm max"
1K
603 402 1% PP0V9_S3M_MEM_NBVREFA 1K PP0V9_S3M_MEM_NBVREFB L2195
1/16W
MF-LF
MAKE_BASE=TRUE
1%
1/16W
MAKE_BASE=TRUE
1.0UH-0.23A PP1V8_S3M_NB_VCCSMCK 18B3
4022 MIN_NECK_WIDTH=0.2 mm MF-LF MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.25 MM
7A4 200 mA=PP1V8_S3_NB_VCC
VOLTAGE=0.9V 4022 VOLTAGE=0.9V 1 2 MIN_NECK_WIDTH=0.2 MM
0603 VOLTAGE=1.8V 200 mA
=PP0V9_S3M_MEM_NBVREFA =PP0V9_S3M_MEM_NBVREFB 15C2
R21951 C2196 1 1 C2197
1.1 22UF 0.1UF
R21131 R2111 1 WF: Should be 1.0, 1% 1%
1/16W 20%
6.3V 2
20%
100 mA =PP3V3_S0_NB_VCCHV 1K MF-LF 2 10V
NB Standard Decoupling
15C7 15B7 7D4
21B7 18B3 1% 1K 402 2
CERM CERM
100 mA 18C3 7C7 =PP1V25_S0_NB_VCCDMI =PP3V3_S0_NB_VCCA_PEG_BG 7C4 18C6 1/16W 1%
805 402
MF-LF 1/16W
4022 MF-LF PP1V8_S3_NB_VCCSMCK_RC
A 1 C2160
0.1UF
1 C2161
0.1UF
1 C2165
0.1UF
5 mA 4022
C2195 1
VOLTAGE=1.8V
SYNC_MASTER=WFERRY
A
20% 20% 20%
2 10V 2 10V 2 10V 10uF
CERM CERM CERM 20% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 402 402 6.3V 2
X5R PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
=GND_NB_VSSA_PEG_BG LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH 603 AGREES TO THE FOLLOWING
18C6
Layout Note: Route to caps, then GND II NOT TO REPRODUCE OR COPY IT
APPLE INC.
D 051-7559 H
SCALE SHT OF
Current numbers from Crestline EDS Addendum, doc #20127. NONE 21 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
7A7 =PP5V_S0_NB_TVDAC
205 mA
CRITICAL CRITICAL
1
R2281 C2289
5%
0 U2280 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
L2288
120-OHM-0.3A-EMI
22000pF-1000mA
16V
1/16W TPS79933 VOLTAGE=3.3V NFM18 PP3V3_S0_NB_VCCA_CRTDAC 18D6
MF-LF
6 IN SON OUT 1 PP3V3_S0_NB_TVDAC 205 mA 1 2 PP3V3_S0_NB_CRTDAC_F 1 3
C2280 1 2 402
0402-LF
VOLTAGE=3.3V 80 mA
1UF MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V 2
10% 4 EN
P3V3TVDAC_EN_RC NR 2 P3V3TVDAC_NOISE 80 mA 1 C2288 Layout Note:
D
6.3V 2
CERM
402 1
NO STUFF NC 5 NC THRML C2282 1 1 C2285
0.1UF
20% These 2 caps should be D
C2281 2 10V within 6.35 mm of NB edge
NOTE: This filter is required even if using only external graphics. 1UF
GND PAD 0.01UF
10%
10UF
20%
CERM
402
2 10%
6.3V
3 7 16V 6.3V
VCCD_TVDAC also powers internal thermal sensors. CERM CERM 2 2 X5R
CRITICAL 402 402 603
C2201
22000pF-1000mA CRITICAL
=PP1V5_S0_NB_TVDAC 16V
NFM18 PP1V5_S0_NB_VCCD_TVDAC NO STUFF NO STUFF C2292
7B7
18B6
D2285 L2290 22000pF-1000mA
65 mA
VOLTAGE=1.5V 60 mA 1SS418 R2285 120-OHM-0.3A-EMI 16V
NFM18 PP3V3_S0_NB_VCCA_TVDACA 18B6
2 1 10 MIN_LINE_WIDTH=0.3 MM
2 PP1V5_S0_NB_VCCD_CRT 21C5 =PP1V5_S0_NB_FOLLOW PP3V3_S0_NB_TVDAC_FOLLOW 1 2 1 2 PP3V3_S0_NB_TVDAC_F 1 3 MIN_NECK_WIDTH=0.2 MM
1 C2200 MIN_LINE_WIDTH=0.2 MM
7B7
MIN_NECK_WIDTH=0.2 MM 1% 0402-LF MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V 40 mA
0.1UF VOLTAGE=1.5V 6 mA SOD-723 VOLTAGE=3.3V 1/16W VOLTAGE=3.3V 2
20%
2 10V
MF-LF
402
C2290 1 125 mA 1 C2291
CERM 10uF 0.1UF
402 20% 20%
6.3V 10V
=PP1V5_S0_NB_VCCD_CRT PP1V5_S0_NB_VCCD_CRT X5R 2 2 CERM
R2205
18B6 21D6
1 MAKE_BASE=TRUE
603 402
100
5%
1/16W
MF-LF CRITICAL CRITICAL
2402 C2206 C2294
22000pF-1000mA 22000pF-1000mA
16V 16V
NFM18 PP1V5_S0_NB_VCCD_QDAC 18B6 NFM18 PP3V3_S0_NB_VCCA_TVDACB 18B6
MIN_LINE_WIDTH=0.2 MM MIN_LINE_WIDTH=0.3 MM
PP1V5_S0_NB_QDAC 1 3 MIN_NECK_WIDTH=0.2 MM 1 3 MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.5V 5 mA VOLTAGE=3.3V 40 mA
VOLTAGE=1.5V 1 C2205 2 1 C2207 1 C2293 2
0.1UF
1UF Layout Note: 20% GMCH Graphics Core Power 0.1UF
10% 2 10V 20%
2 10V
X5R These 4 caps should be CERM
402 2 10V
CERM Layout Note:
402-1 48B3 17D5 17B7 7B7 =PPVCORE_S0_NB_GFX 402
within 6.35 mm of NB edge These 8 caps should be
7700 mA within 6.35 mm of NB edge
C CRITICAL
C2210 1 1 C2212 1 C2213 1 C2214 1 C2215 1 C2216 1 C2217 CRITICAL C
470UF 20%
22UF 10uF
20%
1UF
10%
0.47UF
10%
0.1UF
20%
0.1UF
20%
C2296
20% 22000pF-1000mA
2.5V 2 3 2 6.3V
CERM 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM-X5R 2 10V
CERM 2 10V
CERM 16V
TANT
805 603 402 402 402 402 NFM18 PP3V3_S0_NB_VCCA_TVDACC 18B6
D2T MIN_LINE_WIDTH=0.3 MM
1 3 MIN_NECK_WIDTH=0.2 MM
WF: Matanzas has 2x 330uF VOLTAGE=3.3V 40 mA
PLACEMENT_NOTE=Place in GMCH cavity
2
1 C2295
0.1UF
20%
NEED TO FIND A "1£GH, 500MA, 78MOHM" INDUCTOR 2 10V
CERM
WF: Should be 1uH, 30% L2220 WF: Check part properties 402
7B7 =PP1V8_S0_NB_LVDS 1.0UH-0.5A-0.675A PP1V8_S0_NB_VCCTXLVDS 18B3 18C6

=PP3V3_S0_NB_VCCHV MIN_NECK_WIDTH=0.2 MM
20A8 18B3 15C7 15B7 7D4
260 mA 1007 VOLTAGE=1.8V 110 mA CRITICAL
OMIT C2298
CRITICAL1
C2221
1 C2223 22000pF-1000mA
NO STUFF NO STUFF NO STUFF C2220 1
0.001uF 16V
NFM18 PP3V3_S0_NB_VCCA_DAC_BG
220UF 0.001uF 18D6
R2242 R2243
1 1 1
R2244 R2245
1
20% 20%
20%
2 50V 1 3 MIN_LINE_WIDTH=0.2 MM
22K 22K 22K 22K 2.5V 2 2 50V
CERM
CERM
402 VOLTAGE=3.3V 5 mA
5% 5% 5% 5% POLY
CASE-B2-SM 402 =GND_NB_VSSA_LVDS
1/16W 2
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF MF-LF
18C6
1 C2297
2 402 2 402 2 402 2 402 Layout Note: Route to cap, then GND 0.1UF
20%
GFX_VID<0> 2 10V
CERM
OUT 15B3 60C6
402
GFX_VID<1> OUT 15B3 60C6 =GND_NB_VSSA_DAC_BG 18D6
GFX_VID<2> 15B3 60C6
=PP1V8_S0_NB_VCCD_LVDS 18A6
OUT
GFX_VID<3> Layout Note: Route to caps, then GND
OUT 15B3 60C6
150 mA
VID<3:0>=1001=1.05575V NO STUFF
1 C2226
1000=1.08150V R2247 1R2248
1
1
R2249 1
R2250 1UF
10%
B 0011=1.21025V
22K
5%
1/16W
22K
5%
1/16W
5%
22K
1/16W
5%
22K
1/16W
2 6.3V
CERM
402 B
MF-LF MF-LF MF-LF
MF-LF
2 402 2 402 2 402 2 402
18D6 7C4 =PP3V3_S0_NB_VCCSYNC

10 mA 1 C2230
0.1UF
20%
10V
2 CERM
402
CRITICAL
Vout = 1.204V * (Ra + Rb)/Rb
WARNING VOLTAGE DROP U2265 Ra || Rb should be 19Kohms
=PP1V8_S0_NB_DPLL TPS731125
7B7
SOT23-5
(1.7V - 5.5V) 1 IN OUT 5 PP1V25_S0_NB_DPLL R2261 PP1V25_S0_NB_VCCA_DPLLA 18D6
3 EN MIN_LINE_WIDTH=0.4 MM 0 MIN_LINE_WIDTH=0.3 MM
80 mA NR/FB 4 MIN_NECK_WIDTH=0.2 MM 1 2 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V 80 mA VOLTAGE=1.25V
C2265 1 GND 1 C2266
5%
1/16W
1UF P1V25S0NBDPLL_FB MF-LF 1 C2261
2 10UF
10%
6.3V 2
CERM
402
20%
6.3V
2 X5R
402
0.1UF
20% 80 mA
NB Graphics Decoupling
2 10V
A
603 CERM SYNC_MASTER=WFERRY SYNC_DATE=06/15/2006
PP1V25_S0_NB_DPLL_RF
402

A
1 C2267 1
R2266 R2262 PP1V25_S0_NB_VCCA_DPLLB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0.01UF 0.300 0 MIN_LINE_WIDTH=0.3 MM
18D6
10% 5% 1 2 MIN_NECK_WIDTH=0.2 MM
2 16V
CERM 1/10W VOLTAGE=1.25V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
FF 5%
402 1/16W II NOT TO REPRODUCE OR COPY IT
2 603 MF-LF 1 C2262
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0.1UF
20%
10V
WF: Is this the best part to use? 2 CERM SIZE DRAWING NUMBER REV.
WF: Check C2266 value, R2267 value 402
APPLE INC.
D 051-7559 H
SCALE SHT OF
Current numbers from Crestline EDS Addendum, doc #20127. NONE 22 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
24D8 24B3 22D2 7D4 =PP3V3_S0_SB_GPIO
R2310 1 1
R2311
8.2K 10K
26C6 26A4 25D6 23C2 PP1V5_S0_SB_VCC1_5_B 5% 5%
1/16W 1/16W
27D4 26A5 25D6 PP3V3_G3_SB_RTC MF-LF MF-LF
402 402
2 2
D R2300 1 1
R2301 1
R2302 D
332K 332K 24.9
1% 1% 1%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
402 402 402
2 2 2
OMIT
27C8 IN SB_RTC_X1 AG25 RTCX1 U2300 FWH0/LAD0 E5 LPC_AD<0> BI 6D2 44C8 46C6
SB_RTC_X2 RTCX2 ICH8M FWH1/LAD1 LPC_AD<1> =PP3V3_S0_SB_GPIO
INT PU
27C8 OUT AF24 F5 BI 6D2 44C8 46C6 7D4 22D7 24B3 24D8
BGA FWH2/LAD2 G8 LPC_AD<2> BI 6C2 44C8 46C4
27D5 SB_RTC_RST_L AF23 RTCRST* (1 OF 6) FWH3/LAD3 F6 LPC_AD<3> 6C2 44C8 46C4

IN BI
1
27C5 SB_SM_INTRUDER_L AD22 INTRUDER* FWH4/LFRAME* C4 LPC_FRAME_L 6C2 44C8 46B6
R2303 1 R2306
RTC
LPC
IN OUT 8.2K 10K
5% 5%
SB_INTVRMEN AF25 INTVRMEN INT PU LDRQ0* G9 TP_LPC_DRQ0_L 1/16W 1/16W =PP1V05_S0_SB_CPU_IO 7D7 25C3 26C4
MF-LF MF-LF
SB_LAN100_SLP AD21 LAN100_SLP INT PU LDRQ1*/GPIO23 E6 EXTGPU_PWR_EN BI 402
2 2 402
PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
TP_ENET_GLAN_CLK B24 GLAN_CLK A20GATE AF13 SB_A20GATE
A20M* AG26 CPU_A20M_L R2305 1 1
R2309
OUT 9C8 70C3
54.9 54.9
TP_LAN_RSTSYNC D22 LAN_RSTSYNC 1% 1%
DPRSTP* AF26 CPU_DPRSTP_L OUT 9B2 15B6 59C7 70B3 1/16W 1/16W
MF-LF MF-LF
TP_LAN_D2R<0> C21 LAN_RXD0 INT PU DPSLP* AE26 CPU_DPSLP_L OUT 9B2 70B3 402 402
2 2
TP_LAN_D2R<1>
LAN/GLAN
B21 LAN_RXD1 INT PU
FERR* AD24 CPU_FERR_L IN 9C8 70C3
TP_LAN_D2R<2> C22 LAN_RXD2 INT PU
TP_LAN_R2D<0> D21 LAN_TXD0 CPUPWRGD/GPIO49 AG29 CPU_PWRGD OUT 9B2 12B1 70C3
TP_LAN_R2D<1> E20 LAN_TXD1

TP_LAN_R2D<2> CPU_IGNNE_L
CPU
C20 LAN_TXD2 IGNNE* AF27 OUT 9C8 70B3
LAN_ENERGY_DET AH21 GLAN_DOCK*/GPIO13 INIT* AE24 CPU_INIT_L OUT 9D6 46B2 70B3
INTR AC20 CPU_INTR OUT 9B8 70C3
GLAN_COMP GLAN_COMPI RCIN* SB_RCIN_L

C
74B3 D25 AH14
C C25 GLAN_COMPO
NMI AD23 CPU_NMI OUT 9B8 70C3
73C3 8A6 OUT HDA_BIT_CLK R2313 33 1 2 73C3 HDA_BIT_CLK_R AJ16 HDA_BIT_CLK INT PD SMI* AG28 CPU_SMI_L OUT 9B8 70B3
73C3 8A6 OUT HDA_SYNC R2314 33 1 2

5% 1/16W MF-LF 402
73C3 HDA_SYNC_R AJ15 HDA_SYNC INT PD
5% 1/16W MF-LF 402 STPCLK* AA24 CPU_STPCLK_L OUT 9B8 70B3
R2308
73C3 8A6 OUT HDA_RST_L R2315 33 1 2 73C3 HDA_RST_L_R AE14 HDA_RST* 24.9
5% 1/16W MF-LF 402 THRMTRIP* AE27 CPU_THERMTRIP_R 1 2 PM_THRMTRIP_L IN 9C6 15A6 45B3 70B3
IHDA
73C3 8A6 IN HDA_SDIN0 AJ17 HDA_SDIN0 INT PD NO STUFF 1%
1/16W PLACEMENT_NOTE=Place R2308 within 50mm of U2300
8A6 TP_HDA_SDIN1 AH17 HDA_SDIN1 INT PD TP8 AA23 TP_SB_TP8 R2304 1 MF-LF
402
8A6 TP_HDA_SDIN2 AH15 HDA_SDIN2 INT PD 2.2K
5%
8A6 TP_HDA_SDIN3 AD13 HDA_SDIN3 INT PD DD0 V1 IDE_PDD<0> BI 39C5 73D3 1/16W
MF-LF
DD1 U2 IDE_PDD<1> BI 39C5 73D3 402
2
73B3 8A6 OUT HDA_SDOUT R2316 33 1 2 73B3 HDA_SDOUT_R AE13 HDA_SDOUT INT PD DD2 V3 IDE_PDD<2> BI 39C5 73D3
5% 1/16W MF-LF 402
DD3 T1 IDE_PDD<3> BI 39C5 73D3
HDA_DOCK_EN_L AE10 HDA_DOCK_EN*/GPIO33 DD4 V4 IDE_PDD<4> BI 39C5 73D3
TP_HDA_DOCK_RST_L AG14 HDA_DOCK_RST*/GPIO34 DD5 T5 IDE_PDD<5> BI 39C5 73D3
DD6 AB2 IDE_PDD<6> BI 39C5 73D3
TP_SB_SATALED_L AF10 SATALED* INT PU INT PD DD7 T6 IDE_PDD<7> BI 39C5 73D3
DD8 T3 IDE_PDD<8> BI 39C3 73D3
73D3 40D4 IN SATA_A_D2R_N AF6 SATA0RXN DD9 R2 IDE_PDD<9> BI 39C3 73D3
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

73D3 40C4 IN SATA_A_D2R_P AF5 SATA0RXP DD10 T4 IDE_PDD<10> BI 39C3 73D3
73D3 40D4 OUT SATA_A_R2D_C_N AH5 SATA0TXN DD11 V6 IDE_PDD<11> BI 39C3 73D3
SATA_A_R2D_C_P AH6 SATA0TXP DD12 V5 IDE_PDD<12>
IDE
73D3 40D4 OUT BI 39C3 73D3
DD13 U1 IDE_PDD<13> BI 39C3 73D3
8D4 IN SATA_B_D2R_N AG3 SATA1RXN DD14 V2 IDE_PDD<14> BI 39C3 73D3
8D4 IN SATA_B_D2R_P AG4 SATA1RXP DD15 U6 IDE_PDD<15> BI 39C3 73D3
SATA
8D4 OUT SATA_B_R2D_C_N AJ4 SATA1TXN
DA0 AA4 IDE_PDA<0> OUT 39B5 73D3
SATA_B_R2D_C_P
B
SATA1TXP
B
8D4 OUT AJ3
DA1 AA1 IDE_PDA<1> OUT 39B5 73D3
DA2 AB3 IDE_PDA<2> OUT 39B3 73D3

8D4 IN SATA_C_D2R_N AF2 SATA2RXN
8D4 IN SATA_C_D2R_P AF1 SATA2RXP
8D4 OUT SATA_C_R2D_C_N AE4 SATA2TXN DCS1* Y6 IDE_PDCS1_L OUT 39B5 73D3
8D4 OUT SATA_C_R2D_C_P AE3 SATA2TXP DCS3* Y5 IDE_PDCS3_L OUT 39B3 73D3
75B3 29C3 IN SB_CLK100M_SATA_N AB7 SATA_CLKN DIOR* W4 IDE_PDIOR_L OUT 39C3 73D3
75B3 29C3 IN SB_CLK100M_SATA_P AC6 SATA_CLKP DIOW* W3 IDE_PDIOW_L OUT 39B5 73D3
DDACK* Y2 IDE_PDDACK_L OUT 39B3 73D3
40D2 IN SATA_RBIAS_N AG1 SATARBIAS* IDEIRQ Y3 IDE_IRQ14 IN 39B5 73D3
40D2 IN SATA_RBIAS_P AG2 SATARBIAS IORDY Y1 IDE_PDIORDY IN 39B5 73D3
DDREQ W5 IDE_PDDREQ IN 39C3 73D3
HDA SB Enet, Disk, FSB, LPC

A HDA_BIT_CLK 24.000MHZ CLOCK W/INTERNAL WEAK PD
SYNC_MASTER=T9_MLB

A
HDA_RST#
HDA_SDIN[0-2] INTEGRATED PDs PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
HDA_SDOUT INTEGRATED PD I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ACZ_SYNC INTEGRATED PD
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 23 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
OMIT
8D4 TP_PCIE_A_D2R_N P27 PERN1 U2300 DMI0RXN V27 DMI_N2S_N<0> IN 15B3 71D3
8D4 TP_PCIE_A_D2R_P P26 PERP1 ICH8M DMI0RXP V26 DMI_N2S_P<0> IN 15B3 71D3
8D4 TP_PCIE_A_R2D_C_N N29 PETN1 BGA DMI0TXN U29 DMI_S2N_N<0> OUT 15C3 71D3
Spares 8D4 TP_PCIE_A_R2D_C_P N28 PETP1 (2 OF 6) DMI0TXP U28 DMI_S2N_P<0> OUT 15B3 71D3
(x2-capable,
8D4 TP_PCIE_B_D2R_N M27 PERN2 DMI1RXN Y27 DMI_N2S_N<1> IN 15B3 71D3
pull HDA_SYNC
8D4 TP_PCIE_B_D2R_P M26 PERP2 DMI1RXP Y26 DMI_N2S_P<1> IN 15B3 71D3
high for x2)
8C4 TP_PCIE_B_R2D_C_N L29 PETN2 DMI1TXN W29 DMI_S2N_N<1> OUT 15C3 71D3
DIRECT MEDIA INTERFACE

8C4 TP_PCIE_B_R2D_C_P L28 PETP2 DMI1TXP W28 DMI_S2N_P<1> OUT 15B3 71D3
D D
PCI_EXPRESS
8C4 TP_PCIE_EXCARD_D2R_N K27 PERN3 DMI2RXN AB26 DMI_N2S_N<2> IN 15B3 71D3
8C4 TP_PCIE_EXCARD_D2R_P K26 PERP3 DMI2RXP AB25 DMI_N2S_P<2> IN 15B3 71D3

ExpressCard
8C4 TP_PCIE_EXCARD_R2D_C_N J29 PETN3 DMI2TXN AA29 DMI_S2N_N<2> OUT 15B3 71D3
8C4 TP_PCIE_EXCARD_R2D_C_P J28 PETP3 DMI2TXP AA28 DMI_S2N_P<2> OUT 15B3 71D3
8C4 TP_PCIE_FW_D2R_N H27 PERN4 DMI3RXN AD27 DMI_N2S_N<3> IN 15B3 71D3
8C4 TP_PCIE_FW_D2R_P H26 PERP4 DMI3RXP AD26 DMI_N2S_P<3> IN 15B3 71D3

FireWire
8C4 TP_PCIE_FW_R2D_C_N G29 PETN4 DMI3TXN AC29 DMI_S2N_N<3> OUT 15B3 71D3
8C4 TP_PCIE_FW_R2D_C_P G28 PETP4 DMI3TXP AC28 DMI_S2N_P<3> OUT 15B3 71D3
33B6 IN PCIE_MINI_D2R_N F27 PERN5 DMI_CLKN T26 SB_CLK100M_DMI_N IN 29C3 75B3
PCIe Mini Card 33B6 IN PCIE_MINI_D2R_P F26 PERP5 DMI_CLKP T25 SB_CLK100M_DMI_P IN 29C3 75B3
(AirPort) 33B6 OUT PCIE_MINI_R2D_C_N E29 PETN5

33B6 OUT PCIE_MINI_R2D_C_P E28 PETP5 DMI_ZCOMP Y23 R2413 PP1V5_S0_SB_VCC1_5_B 22D7 25D6 26A4 26C6
24.9
7D1 =PP3V3_S5_SB_USB DMI_IRCOMP Y24 DMI_IRCOMP_R 1 2
34C8 IN PCIE_ENET_D2R_N D27 PERN6/GLAN_RXN 1% 1/16W MF-LF 402

Ethernet
34C8 IN PCIE_ENET_D2R_P D26 PERP6/GLAN_RXP INT PD USBP0N G3 USB_EXTA_N BI 8C1 73B3
Yukon-PCIE External A
R2400
1
R2402
1
R2404
1
R2408
1
34C8 OUT PCIE_ENET_R2D_C_N C29 PETN6/GLAN_TXN INT PD USBP0P G2 USB_EXTA_P BI 8C1 73B3
Nineveh-GLCI
10K 10K 10K 10K 34C8 OUT PCIE_ENET_R2D_C_P C28 PETP6/GLAN_TXP INT PD USBP1N H5 USB_MINI_N BI 8C1 73B3
5% 5% 5% 5% AirPort (PCIe Mini-Card)
1/16W 1/16W 1/16W 1/16W INT PD USBP1P H4 USB_MINI_P BI 8C1 73B3
MF-LF MF-LF MF-LF MF-LF
402 2 402 2 402 2 402 2 73A3 52C7 BI SPI_SCLK_R C23 SPI_CLK INT PU INT PD USBP2N H2 USB_EXTD_N BI 8C1
External D / WWAN
73A3 52C7 BI SPI_CE_R_L<0> B23 SPI_CS0* INT PD USBP2P H1 USB_EXTD_P BI 8C1
EHCI0
1 1 1 1
TP_SPI_CE_R_L<1> E22 SPI_CS1* INT PU INT PD USBP3N J3 USB_CAMERA_N BI 8C1 73B3
1
Camera
SPI
R2401 R2403 R2405 R2407 R2409 INT PD USBP3P J2 USB_CAMERA_P BI 8C1 73B3
10K 10K 10K 10K 10K 73A3 52C3 BI SPI_SI_R D23 SPI_MOSI INT PU
5% 5% 5% 5% 5% INT PD USBP4N K5 USB_IR_N BI 8C1 8C2 73B3
1/16W 1/16W 1/16W 1/16W 1/16W 73A3 52C3 BI SPI_SO F21 SPI_MISO INT PU IR
USBP4P USB_IR_P
C
MF-LF MF-LF MF-LF MF-LF MF-LF K4
C
INT PD BI 8C1 8C2 73B3
2 402 2 402 2
402 2 402 2 402 USB_TPAD_N
INT PD USBP5N K2 BI 8C1 73B3
Geyser Trackpad/Keyboard
8C1 IN USB_EXTA_OC_L AJ19 OC0* INT PD USBP5P K1 USB_TPAD_P BI 8C1 73B3
39B8 OUT SB_GPIO40 AG16 OC1*/GPIO40 INT PD USBP6N L3 USB_BT_N BI 8B1 8B2 73B3
Bluetooth
IN USB_EXTD_OC_L AG15 OC2*/GPIO41 INT PD USBP6P L2 USB_BT_P BI 8C1 8C2 73B3
33B6 OUT SB_GPIO42 AE15 OC3*/GPIO42 INT PD USBP7N M5 USB_EXTB_N BI 8B1 73B3
External B
EHCI1
OUT PM_LATRIGGER_L AF15 OC4*/GPIO43 USB INT PD USBP7P M4 USB_EXTB_P BI 8B1 73B3
OUT EXTGPU_LVDS_EN AG17 OC5*/GPIO29 INT PD USBP8N M2 USB_EXCARD_N BI 8B1 73B3

ExpressCard
OUT SB_GPIO30 AD12 OC6*/GPIO30 INT PD USBP8P M1 USB_EXCARD_P BI 8B1 73B3
8B1 IN USB_EXTB_OC_L AJ18 OC7*/GPIO31 INT PD USBP9N N3 USB_EXTC_N BI 8B1 73B3

External C
IN EXCARD_OC_L AD14 OC8* INT PD USBP9P N2 USB_EXTC_P BI 8B1 73B3
IN USB_EXTC_OC_L AH18 OC9*

R2414 NOTE: USBP[0-9]P/N have internal 15K pull-downs.
NOSTUFF USBRBIAS* F2
22.6
R2406 1 USBRBIAS F3 73B3 USB_RBIAS 1 2
100K 1%
5% 1/16W
1/16W MF-LF
MF-LF 402
402 2
NOTE: GNT[0-3]# have internal 20K pull-ups

enabled only when PCIRST# = 0 and PWROK = 1
If used, ensure GNT2# is not low when PWROK

rises, or PCIe ports 5 & 6 will be disabled.
OMIT
U2300
74D3 37C5 BI PCI_AD<0> D20 AD0 ICH8M REQ0* A4 PCI_FW_REQ_L IN 23A4 37A5 74D3
74D3 37C5 BI PCI_AD<1> E19 AD1 BGA INT PU GNT0* D7 PCI_FW_GNT_L OUT 37A5 74D3
MAKE_BASE=TRUE
PCI_AD<2> D19 AD2 (3 OF 6) REQ1*/GPIO50 E18 PCI_REQ1_L
74D3 37C5 BI IN 23A4 74D3
BOOT_LPC_SPI_L SB BOOT BIOS SELECT
B 74D3 37C5
74D3 37C5
BI
BI
PCI_AD<3>
PCI_AD<4>
A20
D17
AD3
AD4
INT PU GNT1*/GPIO51
REQ2*/GPIO52
C18
B19
TP_SB_GPIO51
PCI_REQ2_L IN 23A4 74D3
1
OUT 6C2 46B6
B
74D3 37C5 PCI_AD<5> A21 AD5 INT PU GNT2*/GPIO53 F18 TP_SB_GPIO53 R2415 I/F GNT0#
BI 1K
74D3 37C5 BI PCI_AD<6> A19 AD6 REQ3*/GPIO54 A11 ODD_RST_5VTOL_L OUT 39A8 73D3 5%
1/16W
74D3 37C5 BI PCI_AD<7> C19 AD7 INT PU GNT3*/GPIO55 C10 TP_SB_GPIO55 MF-LF LPC 1
402
74D3 37C5 BI PCI_AD<8> A18 AD8 2
PCI R2415 pull-down on GNT0#
74D3 37C5 BI PCI_AD<9> B16 AD9 C/BE0* C17 PCI_C_BE_L<0> BI 37B5 74D3 SPI 0
selects SPI ROM by default.
74D3 37C5 BI PCI_AD<10> A12 AD10 C/BE1* E15 PCI_C_BE_L<1> BI 37B5 74D3
74D3 37C5 BI PCI_AD<11> E16 AD11 C/BE2* F16 PCI_C_BE_L<2> BI 37B5 74D3 NOTE: GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
74D3 37B5 BI PCI_AD<12> A14 AD12 C/BE3* E17 PCI_C_BE_L<3> BI 37B5 74D3 SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
74D3 37B5 BI PCI_AD<13> G16 AD13
74D3 37B5 BI PCI_AD<14> A15 AD14 IRDY* C8 PCI_IRDY_L BI 23A4 37A5 74D3
74D3 37B5 BI PCI_AD<15> B6 AD15 PAR D9 PCI_PAR BI 37B5 74D3
74D3 37B5 BI PCI_AD<16> C11 AD16 PCIRST* G6 PCI_RST_L OUT 37A6 7C4 =PP3V3_S0_SB_PCI
74D3 37B5 BI PCI_AD<17> A9 AD17 DEVSEL* D16 PCI_DEVSEL_L BI 23A4 37A5 74D3
74D3 37B5 BI PCI_AD<18> D11 AD18 PERR* A7 PCI_PERR_L BI 23A4 37A5 74D3 74D3 37A5 23A6 PCI_FRAME_L R2423 1 2 8.2K
74D3 37B6 BI PCI_AD<19> B12 AD19 PLOCK* B7 PCI_LOCK_L BI 23A4 74D3 74D3 37A5 23A6 PCI_IRDY_L R2424 1 2 8.2K
74D3 37B5 BI PCI_AD<20> C12 AD20 SERR* F10 PCI_SERR_L BI 23A4 37A5 74D3 74D3 37A5 23A6 PCI_TRDY_L R2425 1 2 8.2K
74D3 37B5 BI PCI_AD<21> D10 AD21 STOP* C16 PCI_STOP_L BI 23A4 37A5 74D3 74D3 37A5 23A6 PCI_STOP_L R2426 1 2 8.2K
74D3 37B5 BI PCI_AD<22> C7 AD22 TRDY* C9 PCI_TRDY_L BI 23A4 37A5 74D3 74D3 37A5 23A6 PCI_SERR_L R2427 1 2 8.2K
74D3 37B5 BI PCI_AD<23> F13 AD23 FRAME* A17 PCI_FRAME_L BI 23A4 37A5 74D3 74D3 37A5 23A6 PCI_DEVSEL_L R2428 1 2 8.2K
74D3 37B5 BI PCI_AD<24> E11 AD24 74D3 37A5 23A6 PCI_PERR_L R2430 1 2 8.2K
74D3 37B5 BI PCI_AD<25> E13 AD25 PLTRST* AG24 PLT_RST_L OUT 27D4 67C6 74D3 23A6 PCI_LOCK_L R2429 1 2 8.2K
PCI_AD<26> AD26 PCICLK PCI_CLK33M_SB
74D3 37B5 BI E12 B10 IN 29A5 29B3 75B3
PCI_FW_REQ_L R2432 8.2K
74D3 37B5 BI PCI_AD<27> D8 AD27 INT PU PME* G7 TP_PCI_PME_L
74D3 37A5 23B6
74D3 23B6 PCI_REQ1_L R2431

1
1
2
2 8.2K
SB PCI, PCIe, DMI, USB
PCI_AD<28> A6 AD28 R2433
A
74D3 37B5 BI
A
74D3 23B6 PCI_REQ2_L 1 2 8.2K SYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
74D3 37B5 BI PCI_AD<29> E8 AD29
74D3 37B5 BI PCI_AD<30> D6 AD30 74C3 23A8 INT_PIRQA_L R2437 1 2 8.2K NOTICE OF PROPRIETARY PROPERTY
74D3 37B5 BI PCI_AD<31> A3 AD31 74C3 23A8 INT_PIRQB_L R2436 1 2 8.2K
INTERRUPT I/F 74C3 23A8 INT_PIRQC_L R2438 1 2 8.2K
74C3 23A4 BI INT_PIRQA_L F9 PIRQA* PIRQE*/GPIO2 F8 INT_PIRQE_L BI 23A4 74C3
R2439 AGREES TO THE FOLLOWING
74C3 37A5 23A8 INT_PIRQD_L 1 2 8.2K
INT_PIRQB_L PIRQB* PIRQF*/GPIO3 INT_PIRQF_L
74C3 23A4 BI B5 G11 BI 23A4 74C3
74C3 23A6 INT_PIRQE_L R2440 1 2 8.2K
74C3 23A4 BI INT_PIRQC_L C5 PIRQC* PIRQG*/GPIO4 F12 DVI_HOTPLUG_DET IN 68A4 68B8 Provide a pull-down on this GPIO if not used. R2441 II NOT TO REPRODUCE OR COPY IT
74C3 23A6 INT_PIRQF_L 1 2 8.2K
74C3 37A5 23A4 BI INT_PIRQD_L A10 PIRQD* PIRQH*/GPIO5 B3 ODD_PWR_EN_L OUT 23A4 39C8
R2442 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
39C8 23A6 ODD_PWR_EN_L 1 2 8.2K
FireWire INT*
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 24 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
24B3 22D7 22D2 7D4 =PP3V3_S0_SB_GPIO

7D1 =PP3V3_S5_SB_GPIO
NO_REBOOT_MODE 2
1 1 1 1 1 1 R2535
R2500 R2551 R2553 R2504 R2506 R2510 R2532 2 10K R2533 2 2
R2534
1K 8.2K 8.2K 10K 10K 1K 10K 5% 10K 10K
5% 5% 5% 5% 5% 5% 5% 1/16W 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W OMIT 1/16W MF-LF 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 402 MF-LF MF-LF
1
402 402 402 402 402 402 402 402 402
2 2 2 2 2 2
U2300 1 1 1
73A3 47D8 BI SMB_CLK AJ26 SMBCLK ICH8M SATA0GP/GPIO21 AJ12 RSVD_EXTGPU_LVDS_EN OUT
D R2502
10K
1
R2550
10K
1
R2552
10K
1
R2547
10K
2
R2505
8.2K
1
R2507
8.2K
1
73A3 47D8
74A3
BI
BI
SMB_DATA
CLINK_WLAN_RESET_L
AD19
AG21
SMBDATA
LINKALERT*
(4 OF 6)
BGA
SATA1GP/GPIO19
SATA2GP/GPIO36
AJ10
AF11
SATA_B_DET_L
SB_GPIO36
D
SATA
GPIO
5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 73A3 47A8 BI SMB_ME_CLK AC17 SMLINK0 SATA3GP/GPIO37 AG11 SB_CRT_TVOUT_MUX_L OUT 69A6
SMB
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402 402 73A3 47A8 BI SMB_ME_DATA AE19 SMLINK1
2 2 2 1 2 2
CLK14 AG9 SB_CLK14P3M_TIMER IN 29A5 29D6 75B3
CLOCKS
24A5 IN PM_RI_L AF17 RI* CLK48 G5 SB_CLK48M_USBCTLR IN 29A5 29D6 75B3
46B4 44C5 6C2 OUT PM_SUS_STAT_L F4 SUS_STAT*/LPCPD* SUSCLK D3 SUS_CLK_SB OUT 45A8
44B8 27C5 IN PM_SYSRST_L AD15 SYS_RESET*

SLP_S3* AG23 PM_SLP_S3_L OUT 33C7 35C7 44C5 45A6 58B7 62B8
15B6 IN PM_BMBUSY_L AG12 BMBUSY*/GPIO0 SLP_S4* AF21 TP_PM_SLP_S4_L

SLP_S5* AD18 PM_SLP_S5_L OUT 44C5 45C3
46B4 24A7 6C2 IN LINDACARD_GPIO AG22 SMBALERT*/GPIO11
SYS GPIO
S4_STATE*/GPIO26 AH27 PM_S4_STATE_L OUT 33B7 44C5 65A6 65C4
29C2 28C4 OUT PM_STPPCI_L AE20 STP_PCI*/GPIO15
29C2 28C4 OUT PM_STPCPU_L AG18 STP_CPU*/GPIO25 PWROK AE23 PM_SB_PWROK IN 27A6
NOTE: DPRSLPVR HAS INT 20K PD ENABLED

46B6 44C5 37A5 6C2 BI PM_CLKRUN_L AH11 CLKRUN*/GPIO32 DPRSLPVR/GPIO16 AJ14 PM_DPRSLPVR OUT 15A6 59D8 70B3
AT BOOT/RESET FOR STRAPPING FUNCTION
34B8 33C5 IN PCIE_WAKE_L AE17 WAKE* BATLOW* AE21 PM_BATLOW_L IN 24A5 44B8
PM_LAN_ENABLE must remain deasseted
INT_SERIRQ
POWER MGT
46B4 44C8 6C2 BI AF12 SERIRQ
until VccCL3_3, VccLAN3_3 and VccLAN1_05
PM_THRM_L AC13 THRM* INT PU PWRBTN* C2 PM_PWRBTN_L IN 44C8
have been up for at least 1ms.
8B4 IN VR_PWRGD_CLKEN AJ20 VRMPWRGD LAN_RST* AH20 PM_LAN_ENABLE IN 44D8
TP_SB_TP7 AJ22 TP7 RSMRST* AG27 PM_RSMRST_L IN 44C8
37A5 24A5 IN PCI_PME_FW_L AJ8 TACH1/GPIO1 INT PU CK_PWRGD E1 CLK_PWRGD OUT 28A4
24B5 TP_SB_GPIO6 AJ9 TACH2/GPIO6 INT PU See note below R2524 1 1

R2525
100K 10K
44B8 IN SMC_RUNTIME_SCI_L AH9 TACH3/GPIO7 INT PU CLPWROK E3 =SB_CLINK_MPWROK IN 8B4 5% 5%
1/16W 1/16W
44C5 IN SMC_WAKE_SCI_L AE16 GPIO8 MF-LF MF-LF
402 402
LAN_PHYPC GPIO12 SLP_M* TP_PM_SLP_M_L 2 2
C
AC19 AJ25
C
24A5 OUT
24B5 8B4 OUT EXTGPU_RST_L AG8 TACH0/GPIO17 INT PU
=PP3V3_S0MWOL_SB_CLINK0 7C4
SB_GPIO18 GPIO18 CL_CLK0 CLINK_NB_CLK
GPIO
AH12 F23 BI 15A3 74A3
TP_SB_GPIO20 AE11 GPIO20 INT PD CL_CLK1 AE18 CLINK_WLAN_CLK BI 74A3

1
R2526
CONTROLLER LINK
SB_SCLOCK AG10 SCLOCK/GPIO22
3.24K
24A5 SATA_B_PWR_EN_L AH25 QRT_STATE0/GPIO27 CL_DATA0 F22 CLINK_NB_DATA BI 15A3 74A3 1%
1/16W
24A7 FWH_MFG_MODE AD16 QRT_STATE1/GPIO28 CL_DATA1 AF19 CLINK_WLAN_DATA BI 74A3 MF-LF
402
8B4 OUT SB_SATA_CLKREQ_L AG13 SATACLKREQ*/GPIO35 2
SB_SLOAD AF9 SLOAD/GPIO38 CL_VREF0 D24 74A3 SB_CLINK_VREF0

SB_SDATAOUT<0> AJ11 SDATAOUT0/GPIO39 CL_VREF1 AH23 74A3 SB_CLINK_VREF1
SB_SDATAOUT<1> AD10 SDATAOUT1/GPIO48 1
R2527
INT PU CL_RST* AJ23 CLINK_NB_RESET_L OUT 15A3 74A3 C2500 1
453
SB_SPKR AD9 SPKR INT PD
0.1uF 1%
MEM_LED/GPIO24 AJ27 ARB_DETECT_L BI 24A7
10%
16V 1/16W
2 MF-LF
MISC
15A3 IN NB_SB_SYNC_L AJ13 MCH_SYNC* ME_EC_ALERT/GPIO10 AJ24 SB_GPIO10_CL1 24A5
X5R
402 2
402
EC_ME_ALERT/GPIO14 AF22 SB_GPIO14_CL2 24A5

TP_SB_TP3 AJ21 TP3 INT PU
WOL_EN/GPIO9 AG19 35B7 WOL_EN
Test access required
NOSTUFF
for XOR chain testing.
R2523 1
100K
NOTE: ICH CLPWROK input must be PWRGD signal for 5%
1/16W =PP3V3_S5_SB_CLINK1 7C1
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M, MF-LF
402
2
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. 1
If ME/AMT is not used, short CLPWROK to PWROK. R2528
3.24K
1%
1/16W
MF-LF
402
2
B C2501 1
1
R2529 B
0.1uF 453
=PP3V3_S0_SB_GPIO 7D4 22D2 22D7 24D8
10%
1%
16V 1/16W
X5R 2 MF-LF
402 402
2
R2597
10K
24C5 TP_SB_GPIO6 1 2
1%
1/16W
R2596 MF-LF
402
10K
LAYOUT NOTE: 24C5 8B4 EXTGPU_RST_L 1 2
1%
PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE 1/16W
MF-LF R2530
402 10K
24C5 SATA_B_PWR_EN_L 1 2
1%
35C7 26D8 24A3 7D1 =PP3V3_S5_SB 1/16W
R2531 MF-LF
402
10K
37A5 24C5 PCI_PME_FW_L 1 2
1 1
R2511 1 R2515 1%
10K R2514 10K

1/16W
MF-LF
5% 100K 5% 402
1/16W 5% 1/16W
MF-LF 1/16W MF-LF
2
402 MF-LF
402
2
402
R2536 =PP3V3_S5_SB 7D1 24A8 26D8 35C7
2 10K
FWH_MFG_MODE 24C5 24D5 PM_RI_L 1 2
LINDACARD_GPIO 6C2 24D5 46B4 1%

1/16W
ARB_DETECT_L 24B3 MF-LF
R2544
NOSTUFF ARB_ONLY
44B8 24C3 PM_BATLOW_L
402
1
8.2K
2
SB Pwr Mgt, GPIO, Clink
1 1
R2512 R2516
A 0
5%
1/16W
0
5%
1/16W
R2545
5%
1/16W
MF-LF
402
SYNC_MASTER=T9_MLB

A
MF-LF MF-LF 10K
2
402
2
402 24C5 LAN_PHYPC 1 2
1% PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W AGREES TO THE FOLLOWING
MF-LF
402 R2598 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
10K
24B3 SB_GPIO10_CL1 1 2 II NOT TO REPRODUCE OR COPY IT
1% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W
R2546 MF-LF
402 SIZE DRAWING NUMBER REV.
10K
24B3 SB_GPIO14_CL2 1
1%
1/16W
2
APPLE INC.
D 051-7559 H
MF-LF SCALE SHT OF
402
NONE 25 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
6 uA S0-G3 27D4 26A5 22D7 PP3V3_G3_SB_RTC AD25 VCCRTC U2300 A13 =PPVCORE_S0_SB 7D7 26D2 1130 mA
A23 K7 ICH8M B13
A5
U2300 L1 1 mA 26D7 PP5V_S0_SB_V5REF A16
BGA
C13
(6 OF 6)
AA2 ICH8M L13 T7 V5REF C14
BGA OMIT
AA7 L15 D14
(5 OF 6)
A25 L26 1 mA S0-S5 26C7 PP5V_S5_SB_V5REF_SUS G4 V5REF_SUS E14
OMIT
AB1 L27 F14
AB24 L4 657 mA 26C6 26A4 23C2 22D7 PP1V5_S0_SB_VCC1_5_B AA25 G14
AC11 L5 AA26 L11
AC14 M12 AA27 L12

AC25 M13 AB27 L14
D AC26
AC27
M14
M15
AB28
AB29
VCC1_05
L16
L17
D
CORE
AD17 M16 D28 L18
AD20 M17 D29 M11

AD28 M23 E25 M18
AD29 M28 E26 P11
AD3 M29 E27 P18

AD4 M3 F24 T11
AD6 N1 F25 T18
AE1 N11 G24 U18

AE12 N12 H23 V17
AE2 N13 H24 V14
AE22 N14 J23 V11

AD1 N15 J24 U11
AE25 N16 K24 V18
AE5 N17 K25 V16
VCCA3GP
AE6 N18 L23 V12
AE9 N26 L24 VCC1_5_B

AF14 N27 L25 VCCDMIPLL R29 PP1V5_S0_SB_VCCDMIPLL 26A6 23 mA
AF16 N4 M24
AF18 N5 M25 AE28 =PP1V25_S0_SB_DMI 7C7 26A6 50 mA

AF3 N6 N23 VCC_DMI AE29
AF4 P12 N24
AG5 P13 N25 AC23 =PP1V05_S0_SB_CPU_IO 7D7 22D2 26C4 1 mA

AG6 P14 P24 V_CPU_IO AC24
AH10 P15 P25
VCC3_3 =PP3V3_S0_SB_VCC3_3_DMI
C
AH13 P16 R24 AF29
C
7D4 26A8
AH16 P17 R25
AH19 P23 R26 VCC3_3 AD2 =PP3V3_S0_SB_VCC3_3_SATA 7D4 26B8
AH2 P28 R27
AF28 P29 T23 AC8 =PP3V3_S0_SB_VCC3_3_VCCPCORE 7D4 26A6 26C6
VCCP CORE
AH22 R11 T24 AD8
VCC3_3
(VCC3_3 total)
AH24 VSS VSS R12 T27 AE8
AH26 R13 T28 AF8
AH3 R14 T29

442 mA
AH4 R15 U24 AA3 =PP3V3_S0_SB_VCC3_3_IDE 7D4 26B4
AH8 R16 W25 U7
AJ5 R17 V24 V7
IDE
B11 R18 U25 VCC3_3 W1
B14 R28 Y25 W6

B17 R4 V25 W7
B2 T12 V23 Y7
B20 T13
47 mA 26D5 PP1V5_S0_SB_VCCSATAPLL AJ6 VCCSATAPLL A8 =PP3V3_S0_SB_VCC3_3_PCI 7D4 26B4
B22 T14
B15
B8 T15
26D5 7B7 =PP1V5_S0_SB_VCC1_5_A_ARX AE7 B18
C24 T16
AF7 B4
C26 T17
ARX
PCI
C27 T2
AG7 VCC1_5_A B9
AH7 VCC3_3 C15

C6 U12
AJ7 D13
D12 U13
D5
D15 U14
(VCC1_5_A total)
26C6 7B7 =PP1V5_S0_SB_VCC1_5_A_ATX AC1 E10

D18 U15
AC2 E7
ATX
D2 U16
B B
AC3 F11
D4 U17
VCC1_5_A
1080 mA AC4 NOTE:
E21 U23
AC5 VCCHDA AC12 =PP3V3R1V5_S0_SB_VCCHDA 7C4 26C4 32 mA VccHDA and VccSusHDA can be 1.5V or 3.3V
E24 U26
depending on VIO of HD Audio interface.
E4 U27 26C2 7B7 =PP1V5_S0_SB_VCC1_5_A AC10 VCCSUSHDA AD11 =PP3V3_S5_SB_3V3_VCCSUSHDA 7D1 26B2 11 mA S0,
E9 U3 AC9 VCC1_5_A 1 mA S3-S5 Current figures provided assume 1.5V.
J6 TP_VCCSUS1_05_INTERNAL_REG1
F15 U5
AA5 VCCSUS1_05 AF20 TP_VCCSUS1_05_INTERNAL_REG2
E23 V13
AA6 VCC1_5_A
F28 V15
VCCSUS1_5 AC16 TP_VCCSUS1_5_INTERNAL_REG1
F29 V28 G12
F7 V29 G17 VCCSUS1_5 J7 TP_VCCSUS1_5_INTERNAL_REG2

VCC1_5_A
G1 W2 26C2 7B6 =PP1V5_S0_SB_VCC1_5_A_USB_CORE H7
VCCSUS3_3 C3 =PP3V3_S5_SB_VCCSUS3_3
(VCCSUS3_3 total)
7D1 26B6 26D2
E2 W26
AC7
G10 W27 AC18
AD7 VCC1_5_A
G13 Y28 AC21
VCCPSUS
117 mA S0,
G19 Y29 10 mA 26B6 7B7 =PP1V5_S0_SB_VCCUSBPLL D1 VCCUSBPLL VCCSUS3_3 AC22
44 mA S3-S5
G23 Y4 AG20
G25 AB4 F1 AH28

USB CORE
G26 AB23 L6
G27 AB5 L7
VCC1_5_A P6 =PP3V3_S5_SB_VCCSUS3_3_USB 7D1 26D2
H25 AB6 M6 P7
H28 AD5 M7 C1
H29 U4 N7
H3 W24 W23 VCC1_5_A24 P1

VCCPUSB
H6 P2
VCCSUS3_3
J1 A1 TP_VCCLAN1_05_INTERNAL_REG1 F17 P3 SB Power & Ground
J25 A2 TP_VCCLAN1_05_INTERNAL_REG2 G18 VCCLAN1_05 P4
A J26
J27
A28
A29 19 mA S0,26B2 7C4 =PP3V3_S0MWOL_SB_VCCCL3_3 F20

P5
R1
SYNC_MASTER=T9_MLB

A
J4 AH1 63 mA M1 & WOL G21 VCCCL3_3 R3 C2600 1 1
C2601
1uF 0.1uF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
J5 AH29 R5
10% 20%
VSS_NCTF AGREES TO THE FOLLOWING
K23 AJ1 23 mA 26B7 PP1V5_S0_SB_VCCGLANPLL A24 VCCGLANPLL R6
6.3V
CERM 2 2
10V
CERM
402 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
K28 AJ2
80 mA 26A4 =PP1V5_S0_SB_VCCGLAN1_5 B27 VCCCL1_05 G22 TP_VCCCL1_05_INTERNAL_REG II NOT TO REPRODUCE OR COPY IT
GLAN POWER
K29 AJ28
A27 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
K3 AJ29
B28 VCCCL1_5 A22 VCCCL1_5V
K6 B1 VCCGLAN1_5 SIZE DRAWING NUMBER REV.
051-7559
B26
B29
A26
VCCLAN3_3
F19 =PP3V3_S0MWOL_SB_VCCLAN3_3 7C4 26D3 19 mA S0, D H
G20 51 mA M1 & WOL APPLE INC.
1 mA 7D4 =PP3V3_S0_SB_VCCGLAN3_3 B25 VCCGLAN3_3 SCALE SHT OF
NONE 26 106
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
39C8 7D4 =PP3V3_S0_SB
=PP5V_S0_SB ICH V5REF BYPASS ICH VCCSUS3_3 BYPASS

7A7
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT) ICH VCC1_5_A/ARX BYPASS ICH CORE/VCC1_05 BYPASS (ICH SUSPEND 3.3V PWR)
2 (ICH LOGIC&IO[ARX] 1.5V PWR) PLACEMENT NOTE: (ICH CORE 1.05V PWR)
R2702 3
D2702 25B6 7B7 =PP1V5_S0_SB_VCC1_5_A_ARX PLACE CAPS AT EDGE OF SB
26B6 25A3 7D1 =PP3V3_S5_SB_VCCSUS3_3
2 HN2S02JE
100 SOT-665 =PPVCORE_S0_SB 7D7 25D3
NC
1/16W
MF-LF
402 4 PLACEMENT NOTE: 1 C2711 OMIT
1 5% PLACE < 2.54MM OF SB ON SECONDARY OR 1UF
10%
6.3V 1 C2718 1 C2702 CRITICAL 1 C2731 1 C2734
PP5V_S0_SB_V5REF 3.56MM ON PRIMARY NEAR PINS AE7..AJ7 2 CERM 1
C2716 PLACEHOLDER 0.1UF 0.1UF
VOLTAGE=5V
25D6
402 0.1UF 0.1UF 330UF FOR 270UF PLACEMENT NOTE: 10% 10%
MIN_LINE_WIDTH=0.3MM 10% 10% 20% 2 16V 2 16V
MIN_NECK_WIDTH=0.25MM 2 16V
X5R 2 16V
X5R 2 2.5V PLACE CAPS NEAR PINS X5R
402
X5R
402
L2702 MAY HAVE CHANGE TO 1.0UH PART POLY
1 C2703 402 402 CASE-C2 AC18..AH28
D 0.1UF
10% PLACEMENT NOTE: L2702
10UH-100MA
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
D
2 16V
X5R PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB MIN_NECK_WIDTH=0.25MM
402 ON SECONDARY SIDE OR 3.56MM ON PRIMARY =PP1V5_S0_SB 1 2 PP1V5_S0_SB_VCCSATAPLL
26C8 26A8 7B7
0805
ICH VCC_PAUX/VCCLAN3_3 BYPASS ICH USB/VCCSUS3_3 BYPASS
ICH V5REF_SUS BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
1 C2735 C2717 (ICH LAN I/F BUFFER 3.3V PWR) (ICH SUSPEND USB 3.3V PWR)
10UF 1UF
35C7 24A8 24A3 7D1 =PP3V3_S5_SB 20%
6.3V
10%
6.3V 25A3 7C4 =PP3V3_S0MWOL_SB_VCCLAN3_3 25A3 7D1 =PP3V3_S5_SB_VCCSUS3_3_USB
PLACEMENT NOTE: 2 X5R CERM
7C1 =PP5V_S5_SB PLACE < 2.54MM OF SB ON SECONDARY OR 603 402
3.56MM ON PRIMARY NEAR PIN AJ6 PLACEMENT NOTE: 1 C2719

PLACE CAP UNDER SB NEAR PINS 0.1UF
R2701
2
1
D2702 F19 AND G20
10%
2 16V 1 C2733
10 2 HN2S02JE X5R PLACEMENT NOTE:
1/16W SOT-665
402 4.7uF
NC
MF-LF PLACE CAP NEAR PINS 20%

6.3V
402 5 ICH VCC3_3 BYPASS 2 CERM
1
5% P6..R6 603
(ICH IO BUFFER 3.3V PWR)
PP5V_S5_SB_V5REF_SUS 25D6 26A6 25C3 7D4 =PP3V3_S0_SB_VCC3_3_VCCPCORE
VOLTAGE=5V
1 C2704 PLACEMENT NOTE: 1 C2713 ICH VCCHDA BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR 0.1UF (ICH INTEL HDA CORE 3.3V/1.5V PWR)
0.1UF PLACEMENT NOTE: 10%
10% 3.56MM ON PRIMARY NEAR PIN AH11 2 16V
2 16V
X5R PLACE C2704 < 2.54MM OF PIN G4 OF SB X5R
402 25B3 7C4 =PP3V3R1V5_S0_SB_VCCHDA
402 ON SECONDARY SIDE OR 3.56MM ON PRIMARY ICH VCC1_5A BYPASS
(ICH LOGIC&IO 1.5V PWR)
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY 1 C2721 =PP1V5_S0_SB_VCC1_5_A
OR 3.56MM ON PRIMARY NEAR PIN AC12 0.1UF 25B6 7B7
10%
26A8 7B7 =PP1V5_S0_SB L2700 MAY HAVE CHANGE TO 0.5UH PART 2 16V
X5R
26D6 ICH VCC1_5_A/ATX BYPASS
L2700 ICH VCCA3GP(VCC1_5_B BYPASS 402 1 C2710
C FERR-330-OHM-1.5A (ICH IO,LOGIC 1.5V PWR)
0805-1 25B6 7B7
(ICH LOGIC&IO[ATX] 1.5V PWR)
=PP1V5_S0_SB_VCC1_5_A_ATX
PLACEMENT NOTE:
PLACE CAP NEAR PINS
0.1UF
10%
2 16V
C
X5R
1 2 PP1V5_S0_SB_VCC1_5_B AC10..AD7 OF SB 402
OMIT
VOLTAGE=1.5V
22D7 23C2 25D6 26A4
MIN_LINE_WIDTH=0.5MM PLACEMENT NOTE:

1 C2714 ICH V_CPU_IO BYPASS
MIN_NECK_WIDTH=0.25MM 1UF
CRITICAL NOSTUFF PLACE < 2.54MM OF SB ON SECONDARY OR 10% (ICH CPU I/O 1.05V PWR)
2 6.3V
1
C2700 1 C2705 1 C2706 1 C2707 3.56MM ON PRIMARY NEAR PIN AC1..AC5 CERM
402 =PP1V05_S0_SB_CPU_IO
220UF 22UF 22UF 2.2UF 25C3 22D2 7D7
20% 20% 20% 20% ICH USB CORE/VCC1_5_A BYPASS

6.3V 6.3V 6.3V
2 2.5V 2 CERM 2 CERM 2 CERM1
POLY
CASE-B2 805 805 603 PLACEMENT NOTE: (ICH USB CORE 1.5V PWR)
PLACE NEAR PINS AC23,AC24 OF SB =PP1V5_S0_SB_VCC1_5_A_USB_CORE
25B6 7B6
PLACEMENT NOTE: ICH VCCSUS3_3 BYPASS

PLACE C2700 & C2705-07 < 2.54MM OF SB (ICH SUSPEND 3.3V PWR)
ON SECONDARY SIDE OR 3.56MM ON PRIMARY =PP3V3_S5_SB_VCCSUS3_3 PLACEMENT NOTE:
DISTRIBUTED BETWEEN AA25..V23
26D2 25A3 7D1
1 C2723 1 C2722 1 C2724 PLACE < 2.54MM OF SB ON SECONDARY OR
1 C2712
0.1UF 0.1UF 4.7UF 0.1UF
10% 10% 20% 3.56MM ON PRIMARY NEAR PINS F1..M7 10%
PLACEMENT NOTE:
1 C2720 1 C2743 2 16V
X5R 2 16V
X5R 2 6.3V
CERM 2 16V
X5R
M70 DOES NOT USE GIGABIT IN SB, SO NO NEED FOR PLL FILTERING 0.1UF 0.1UF 402 402 603 402
PLACE CAPS NEAR PIN C2..AH28 10% 10%
VOLTAGE=1.5V 2 16V
X5R 2 16V
X5R
MIN_LINE_WIDTH=0.5MM 402 402
25A6 PP1V5_S0_SB_VCCGLANPLL
NOSTUFF ICH IDE/VCC3_3 BYPASS
PLACEMENT NOTE:
1 C2742 1 C2732 (ICH IDE I/O 3.3V PWR) =PP3V3_S0MWOL_SB_VCCCL3_3
10UF 2.2uF 25A6 7C4
PLACE CAPS < 2.54MM OF SB ON SECONDARY 20% 20% ICH VCCUSBPLL BYPASS
6.3V
2 X5R
6.3V
2 CERM1 25C3 7D4 =PP3V3_S0_SB_VCC3_3_IDE
OR 3.56MM ON PRIMARY NEAR PIN A24 603 603 (ICH USB PLL 1.5V PWR)
=PP1V5_S0_SB_VCCUSBPLL PLACEMENT NOTE: PLACEMENT NOTE:
25A6 7B7
1 C2725 1 C2740
B PLACEMENT NOTE:
1 C2715
0.1UF
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS AA3...Y7
0.1UF
10%
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS F20,G21 10%
0.1UF B
10% 2 16V
X5R
16V
2 X5R
PLACE C2715 NEAR PIN D1 OF SB
2 16V
X5R
402 402
402
25C3 7D4 =PP3V3_S0_SB_VCC3_3_SATA
PLACEMENT NOTE: ICH PCI/VCC3_3 BYPASS

ICH VCC3_3/VCCHDA BYPASS
PLACE < 2.54MM OF SB ON SECONDARY 1 C2738 ICH VCC3_3 BYPASS (ICH PCI I/O 3.3V PWR)
(ICH INTEL HDA CORE 3.3V PWR)
OR 3.56MM ON PRIMARY NEAR PIN AD2 0.1UF (ICH IO BUFFER 3.3V PWR)
10% 25B3 7D4 =PP3V3_S0_SB_VCC3_3_PCI
2 16V
X5R 25B3 7D1 =PP3V3_S5_SB_3V3_VCCSUSHDA
402 26C6 25C3 7D4 =PP3V3_S0_SB_VCC3_3_VCCPCORE
1 C2709 NOSTUFF PLACEMENT NOTE:

PLACEMENT NOTE: 0.1UF PLACEMENT NOTE: 1 C2726 1 C2727 1 C2728 PLACE < 2.54MM OF SB ON SECONDARY 1 C2741
PLACE C2709 NEAR PIN B27 OF SB 10% DISTRIBUTE IN PCI SECTION OF SB 0.1UF 0.1UF 0.1UF
26D6 26C8 7B7 =PP1V5_S0_SB L2703
NEED CHANGE TO 1UH PART 16V
2 X5R 10% 10% 10% OR 3.56MM ON PRIMARY NEAR PIN AD11 0.1UF
NEAR PINS A8 ... F11 2 16V 2 16V 2 16V 10%
L2703 ICH VCCDMIPLL BYPASS 402 X5R
402
X5R
402
X5R
402 2 16V
X5R
R2700 1.0UH-0.5A-0.675A (ICH DMI PLL 1.5V PWR) 402
1
1 2 PP1V5_S0_SB_VCCDMIPLL_F
1 2 PP1V5_S0_SB_VCCDMIPLL 25C3
VOLTAGE=1.5V 1007 VOLTAGE=1.5V
1/16W 5% MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM
MF-LF 402 MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM
1 C2701 1 C2708
0.01UF 10UF
PLACEMENT NOTE: 10% 20%
16V
2 CERM 6.3V
2 X5R PP1V5_S0_SB_VCC1_5_B
PLACE CAPS < 2.54MM OF SB ON 402 603 26C6 25D6 23C2 22D7
MAKE_BASE=TRUE
SECONDARY SIDE OR 3.56MM ON PRIMARY ICH VCCRTC BYPASS
(ICH RTC 3.3V PWR)
SB Decoupling
=PP1V5_S0_SB_VCCGLAN1_5
A
25A6
PP3V3_G3_SB_RTC SYNC_MASTER=WFERRY SYNC_DATE=06/01/2006
27D4 25D6 22D7

A
=PP3V3_S0_SB_VCC3_3_DMI =PP1V25_S0_SB_DMI
1 C2736
25C3 7D4 25C3 7C7
C2730 1 1 C2729 PLACEMENT NOTE: 4.7uF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
20%
0.1UF 0.1UF 6.3V PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
10% 10% PLACE CAP NEAR PIN B27..A26 2 CERM AGREES TO THE FOLLOWING
16V 2 16V
2 X5R 603
PLACEMENT NOTE: PLACEMENT NOTE: X5R
402 402 II NOT TO REPRODUCE OR COPY IT
PLACE CAP < 2.54MM OF SB ON SECONDARY 1 C2737 PLACE < 2.54MM OF SB ON SECONDARY 1 C2739 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
OR 3.56MM ON PRIMARY NEAR PIN AF29 0.1UF OR 3.56MM ON PRIMARY NEAR PIN AE29 22UF
10% 20%
2 16V
X5R
6.3V
2 CERM SIZE DRAWING NUMBER REV.
PLACEMENT NOTE:
402 805
PLACE CAPS NEAR PIN AD25 OF SB
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 27 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
Platform Reset Connections

D2800
Unbuffered R2886
HN2S02JE PLT_RST_L 100
1 2 NB_RESET_L
7B1 =PP3V42_G3H_SB_RTCSOT-665 PP3V3_G3C_SB_RTC_D PP3V3_G3_SB_RTC 22D7 25D6 26A5
67C6 23A6
IN
MAKE_BASE=TRUE 5%
15B6
1 5 MAKE_BASE=TRUE 1/16W
MF-LF
402
2 NC
1 C2810 R2887
0
1UF
10% 1 2 TMDS_RST_L 68B5
D 2 6.3V
CERM
402
5%
1/16W D
D2800 R2885
MF-LF
RTC Battery Connector

402
HN2S02JE R2800 0
SOT-665 1 2 AIRPORT_RST_L
PPVBATT_G3C_RTC_R
3 4 1
20K 2 22D8 SB_RTC_RST_L 5%
33C3
OUT 1/16W
VOLTAGE=3V
CRITICAL MIN_LINE_WIDTH=0.3MM
2 NC
5% 7D4 =PP3V3_S0_RSTBUF MF-LF
J2800 R2807
1 1/16W
MF-LF
402
1 C2805 Buffered
402
78171-0002 1K 1UF
M-RT-SM 5%
1/16W
1
R2806 10%
2 6.3V
CRITICAL
3 NC MF-LF
2402
1M
5%
1/16W
CERM
402 2
A
5 TC7SZ08AFEF
SOT665 R2881
0
1 PPVBATT_G3C_RTC MF-LF U2880Y 4 PLT_RST_BUF_L 1 2 DEBUG_RESET_L 6C2 46B6
VOLTAGE=3V 2 402 1 5% Linda Card represents 3 loads

2 MIN_LINE_WIDTH=0.3MM
22D8 SB_SM_INTRUDER_L
B
3
1
R2880
1/16W
MF-LF R2883
100
C2880 402
OUT
1 100K 1 2 SMC_LRESET_L
4 NC 0.1UF 5%
1/16W 5%
44C8
20% MF-LF 1/16W

518S0519 10V MF-LF
CERM 2 2402 402
402
R2801
0
1 2 ENET_RESET_L 34B8
5%
1/16W
MF-LF
402
SB RTC Crystal Circuit 7D1 =PP3V3_S5_SB_PM
C C2808 R2897
10K
1
C
R2810
0 10PF 5%
SB_RTC_X1 1 2 SB_RTC_X1_R 1 2 1/16W
MF-LF
22D8
5% CRITICAL 5% 1K
R2896 4022
I59
Y2800
1/16W
R2809 1 MF-LF
402 1
50V
CERM 12B4 9C6
IN XDP_DBRESET_L
2 1 XDP_DBRESET_L_R 44B8
24D5 PM_SYSRST_LOUT
MAKE_BASE=TRUE
10M 402 OMIT
5%
1/16W
32.768K
7X1.5X1.4-SM
5%
1/16W
MF-LF R2898 1
MF-LF
4 C2809 402
100K
SB_RTC_X2
22D8
4022
1 2
197S0219 10PF This part is never stuffed,
it provides a set of pads
5%
1/16W
MF-LF
4022
Silk: "SYS RST"
Change Y2800 to 197S019 -7.0mmx1.5mmx1.4mm
In CLOSE=12.5pF 5% on the board to short or
50V
CERM to solder a reset button.
402
CPU VCORE PSI

MAKE_BASE=TRUE
B 27B6 7D4 =PP3V3_S0_SB_PM 27B8 7D4 =PP3V3_S0_SB_PM

9A2 CPU_PSI_L IMVP6_PSI_L 59C7
B
C2811 1
0.1UF20%
10V
C2807
0.1UF
1
1
R2811
CERM 2 20% 1.8K
402 10V 5%
CERM 2 1/16W
402 MF-LF
5 CRITICAL
2402
VCC
TC7SZ08AFEF 5 CRITICAL
VR_PWRGD_CK505
4
U2803 A 2 SOT665 A
2 59C7 15B6 VR_PWRGOOD_DELAY
IN
OUT 8B3
YTC7SH00FEF PM_SB_PWROK OUT
24C3 4
Y U28011
SON B 1 VR_PWRGD_CK505_L
59C7
IN R2812 B 58A3 44D8 6B2 ALL_SYS_PWRGD IN
GND MAKE_BASE=TRUE 1
R2802 3
R2803
100K
1
3 0 10K
5%
5% CLINK_MPWROK1 2
8B3 8B1 1/16W
1/16W MF-LF
5% 402 2
MF-LF 1/16W
4022 MF-LF
402
CK410_PD_VTT_PWRGD_L
OUT
Initial resistor values are based on CRB,
but may change after characterization.
Pulled a new APN for U2803(0.6mm max
2-input NAND gate-APN:311S0304 SB Misc
It may take a few days before this is done through SYNC_MASTER=NB SYNC_DATE=07/26/2005
A This will allow us to sequence this part under wireless card
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 28 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
SELIGO RECOMMEND TO REMOVE L2903,R2900,C2907,C2910
R2901,L2902,C2916,C2911,C2914 and R2902
R2901 R2906
0 0
PP3V3_S0_CK505_VDD48 =PP3V3_S0_CK505
ORIGINAL DESIGN: MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm NOSTUFF
1
5%
2 1
5%
2
NOSTUFF
7C4 28C8 28D8 29B2 29D2
USE 155S0302 FOR L2902(R2906) AND L2903(R2907) VOLTAGE=3.3V 1 C2909 1 C2910

1/16W
MF-LF
1/16W
MF-LF 1 C2911
STUFF C2907,C2910,C2916,C2911,C2914 0.1UF
10%
10UF
20%
402 402
1UF
10%
USE 2.2OHM FOR R2900,R2901 AND 1OHM FOR R2902 2 16V
X5R 2 6.3V
X5R 2 6.3V
CERM
402 603 402
D D
L2901
28D3 28C8 7C4 =PP3V3_S0_CK505 FERR-120-OHM-1.5A
29D2 29B2
1 2 PP3V3_S0_CK505_VDD_CPU_SRC PP3V3_S0_CK505_VDD_PCI
0402-LF MIN_LINE_WIDTH=0.5mm MIN_LINE_WIDTH=0.5mm NOSTUFF
MIN_NECK_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm
C2900 1 VOLTAGE=3.3V
C2901 1 1 C2902 1 C2903 1 C2904 1 C2905 1 C2906 VOLTAGE=3.3V 1 C2912 1 C2913 1 C2914
0.1UF 0.1UF 10UF
1UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10% 10% 20%
10%
6.3V
20%
6.3V
10% 10% 10% 10% 10% 2 16V 2 16V 2 6.3V
2 16V 16V 16V 2 16V
CERM 2 X5R 2 X5R 2 X5R 2 X5R X5R 2 16V
X5R
X5R
402
X5R
402
X5R
603
402 603 402 402 402 402 402
R2907 PP3V3_S0_CK505_VDDA_R R2900 R2902

MIN_LINE_WIDTH=0.5mm
0 VOLTAGE=3.3V 0 0
1 2 MIN_NECK_WIDTH=0.2mm 1 2 PP3V3_S0_CK505_VDDA PP3V3_S0_CK505_VDD_REF 1 2
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm
5% 5% MIN_LINE_WIDTH=0.5mm NOSTUFF MIN_NECK_WIDTH=0.2mm NOSTUFF 5%
1/16W 1/16W MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V 1/16W
MF-LF
402
MF-LF
402
1 C2907 1 C2908 1 C2915 1 C2916 MF-LF
402
10UF 0.1UF 0.1UF 10UF
20% 10% 10% 20%
2 6.3V
X5R 2 16V
X5R 2 16V
X5R 2 6.3V
X5R
603 402 402 603
CRITICAL
43
61
67
49
12
17
28
35
NEED TO CHECK CAP VALUE Y2901
3
14.31818 (EACH POWER PIN PLACED ONE 0.1UF)
VDD_PCI
VDD_48
VDD_REF
VDD_CPU
VDD_SRC
1 2
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
5X3.2-SM
C
1
5%
C2989
18PF
1
5%
C2990
18PF
CRITICAL
C
50V
2 CERM 50V
2 CERM PCI_STOP* 56 PM_STPPCI_L IN 24C8 29C2 (FROM ICH8M GPIO15 STPPCI* )
402 402 U2900 CPU_STOP* 55 PM_STPCPU_L IN 24C8 29C2 (FROM ICH8M GPIO25 STPCPU* )
38 SLG2AP101
VDD_A QFN CPU_0* 44 CK505_CPU0_N
39 OUT 6C7 29D6 75D3
VSS_A
CPU_0 45 CK505_CPU0_P OUT 6C7 29D6 75D3 (CPU HOST 133/167MHZ)
CK505_XTAL_IN 51 XTAL_IN
CPU_1_MCH* 41 CK505_CPU1_N
CK505_XTAL_OUT 50 OUT 6C7 29D6 75D3
XTAL_OUT
CPU_1_MCH 42 CK505_CPU1_P OUT 6C7 29D6 75D3 (GMCH HOST 133/167MHZ)
=PP3V3_S0_CK505 CPU_ITP*/SRC_10* 36 CK505_CPU2_ITP_SRC10_N
29D2 29B2 28D8 28D3 7C4
CK505_FSB_TEST_MODE 8 OUT 6C7 29D6 75D3
29B8 IN FS_B/TEST_MODE
CPU_ITP/SRC_10 37 CK505_CPU2_ITP_SRC10_P OUT 6C7 29D6 75D3 (ITP HOST 133/167MHZ)
1
R2903(FW PCI 33MHZ) 75D3 29B6 OUT CK505_PCI1_CLK 57 PCI_1 SRC_0*/LCD_CLK* 11 CK505_LVDS_N OUT 6C7 29C6 75C3
10K
5%
1/16W
(TPM LPC 33MHZ) 75D3 8C4 OUT CK505_PCI2_CLK 58 PCI_2 SRC_0/LCD_CLK 10 CK505_LVDS_P OUT 6C7 29C6 75D3 (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
MF-LF (SMC LPC 33MHZ) OUT CK505_PCI3_CLK 63 PCI_3
2 402
75D3 29A6
SRC_1* 14 TP_CK505_SRC1_N OUT 8C4
(PCI SLOT) CK505_PCI4_CLK 64 PCI_4
(PORT80 LPC 33MHZ)
75D3 8C4 OUT
CK505_PCI5_FCTSEL1 65 PCI_5/FCT_SEL SRC_1 13 TP_CK505_SRC1_P OUT 8C4 (SLOT F - GPU PCI-E 100 MHZ )
75D3 29B2 BI
(NO INT PD) CLKREQ_1* 9 CK505_SRC_CLKREQ1_L IN 29C2
CK505_PCIF0_CLK 68 PCIF_0/ITP_EN (INT PU)

75D3 29B6 OUT
(NO INT PU) SRC_2* 16 CK505_SRC2_N OUT 6C7 29C6 75C3
(ICH8M PCI 33MHZ) CK505_PCIF1_CLK 1
75D3 29B6 6C7 OUT PCIF_1
SRC_2 15 CK505_SRC2_P OUT 6C7 29C6 75C3 (ICH8M DMI 100 MHZ )
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
IN =SMBUS_CK505_SCL 47 SCL
(ICH SM BUS)
47D6
SRC_3* 19 TP_CK505_SRC3_N OUT 8C4
=SMBUS_CK505_SDA 48
47D6 BI SDA
SRC_3 18 TP_CK505_SRC3_P OUT 8C4 (SLOT D - 4 LANE PCI-E FOR EXPRESSCARD)
CK505_PGMODE 28A4 (INT PU) CLKREQ_3* 59 CK505_SRC_CLKREQ3_L IN 29C2
(INT PU)
SRC_4* 22 CK505_SRC4_N OUT 6C7 29C6 75C3
21 CK505_SRC4_P (ICH SATA 100 MHZ)
B 0 = VTT_PWRGD#/PD
NOSTUFF
R2905
1
5 VSS_48
SRC_4
CLKREQ_4*
(INT PU)
20 SB_CLK100M_SATA_OE_L
OUT
IN
6C7 29C6 75C3
8B3 (FROM ICH8M GPIO35) B

1 = CKPWRGD/PD# 475 46 VSS_CPU SRC_5* 24 CK505_SRC5_N OUT 6C7 29C6 75C3
U2900 HAS INTERNAL PU ON PGMODE

1%
1/16W
MF-LF 62 SRC_5 23 CK505_SRC5_P OUT 6C7 29C6 75C3 (GMCH G_CLKIN 100 MHZ )
2 402 66 VSS_PCI CLKREQ_5*
(INT PU)
60 NB_CLKREQ_L IN 15A3 (FROM GMCH CLK_REQ*)
475 OHM FOR CK410M SRC_6* 27 CK505_SRC6_N OUT 6C7 29B6 75C3
52
COMPATIBILITY
VSS_REF
SRC_6 26 CK505_SRC6_P OUT 6C7 29C6 75C3 (WIRELESS PCI-E 100 MHZ )
STUFF R2905 FOR CK410M MODE 31 VSS_SRC CLKREQ_6* 25 CK505_SRC_CLKREQ6_L IN 33C5
(INT PU)
30 TP_CK505_SRC7_N
69 THRM_PAD
SRC_7*
SRC_7 29 TP_CK505_SRC7_P
OUT
OUT
8C4
8C4
(DB400 SRC )
CLKREQ_7* 40 CK505_PGMODE 28B5
SRC_8* 32 CK505_SRC8_N OUT 6B7 29B6 75C3 (SLOT E )

SRC_8 33 CK505_SRC8_P OUT 6B7 29B6 75C3
CLKREQ_8* 34 =ENET_CLKREQ_L IN 8C4 34B8
7 CK505_DOT96_27M_N
DOT_96*/27M_SS
DOT_96/27M 6 CK505_DOT96_27M_P
OUT
OUT
6C7 29B6 75D3
6C7 29B6 75D3

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(INT PD)
CKPWRGD/PD* 2 CLK_PWRGD IN 24C3
48M/FS_A 4 CK505_USB48_FSA OUT 29D8 75D3 (FROM ICH8M)

54 CK505_CLK14P3M_TIMER
REF_0/FS_C/TEST_SEL
53 CK505_REF1
OUT 29D8 75D3
(ICH8M USB 48MHZ)
GPU_STOP* BI
(ICH8M,SIO,LPC REF. 14.318MHZ)
Clock (CK505)
A FCTSEL1 PIN 6 PIN 7 PIN 10 PIN 11
SYNC_MASTER=DSIMON
A
0 DOT96T DOT96C 100MT_SST 100MC_SST * FOR INT. GRAPHIC SYSTEM
27M NON 27M THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 SPREAD SPREAD SRCT0 SRCC0 * FOR EXT. GRAPHIC SYSTEM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 29 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
75D3 28A4 CK505_USB48_FSA

R3032
1
33 2 SB_CLK48M_USBCTLR 24D3 29A5 75B3
CLK Termination
IN OUT
5%
1/16W
MF-LF
402
R3000
R3033 0
75D3 28C4 6C7 IN CK505_CPU0_P 1 2 FSB_CLK_CPU_P OUT 9B6 75C3
2.2K 2
1 CK505_FSA 5%
R3001
5%
29C8 75B3
1/16W
MF-LF 0
(CPU HOST 133/167MHZ)
1/16W 75D3 28C4 6C7 IN CK505_CPU0_N 402 1 2 FSB_CLK_CPU_N OUT 9B6 75C3
D
MF-LF
D
402 5%
R3002 1/16W
MF-LF
R3034 0 402
75D3 28C4 6C7 IN CK505_CPU1_P 1 2 FSB_CLK_NB_P OUT 13B3 75C3
CK505_CLK14P3M_TIMER 33 SB_CLK14P3M_TIMER
75D3 28A4 IN
1 2
OUT 24D3 29A5 75B3 5%
1/16W R3003 (GMCH HOST 133/167MHZ)
5% MF-LF 0
1/16W 75D3 28C4 6C7 IN CK505_CPU1_N 402 1 2 FSB_CLK_NB_N OUT 13B3 75C3
MF-LF
402 ITP 5%
R3004 1/16W
CLKREQ Controls
MF-LF
R3035 0 402
75D3 28C4 6C7 IN CK505_CPU2_ITP_SRC10_P 1 2 CPU_XDP_CLK_P OUT 12B3
10K ITP
1 2 CK505_FSC 5%
R3005
5%
29A8 75B3
1/16W
MF-LF 0
(ITP HOST 133/167MHZ)
1/16W 75D3 28C4 6C7 IN CK505_CPU2_ITP_SRC10_N 402 1 2 CPU_XDP_CLK_N OUT 12B3
MF-LF 29B2 28D8 28D3 28C8 7C4 =PP3V3_S0_CK505
402 5%
R3006 1/16W
MF-LF
0 402
=PP1V25R1V05_S0_FSB_NB 7C7 13B7 29B6 29C6 75D3 28B4 6C7 IN CK505_LVDS_P 1 2 NB_CLK100M_DPLLSS_P OUT 8B1 75B3
NOSTUFF 5% R3046
1
1/16W
R3007 (Int Gfx LVDS 100MHz) PM_STPPCI_L
10K 5%
R3080 MF-LF
402 0
28C4 24C8
1/16W
1 2
402
1K 75C3 28B4 6C7 IN CK505_LVDS_N 1 2 NB_CLK100M_DPLLSS_N OUT 8A1 75B3 MF-LF
5%
1/16W 5%
R3047
(TO MCH FS_A) R3081
MF-LF
2 402 R3010
1/16W
MF-LF
402 28C4 24C8 PM_STPCPU_L
10K 1 2
5%
1K 0 1/16W 402
70B3 15C6 OUT NB_BSEL<0> 1 2 75C3 28B4 6C7 IN CK505_SRC2_P 1 2 SB_CLK100M_DMI_P OUT 23C2 75B3 MF-LF
5%
1/16W
5%
1/16W R3011 (ICH8M DMI 100MHZ)
MF-LF
R3082 MF-LF 0
402 75C3 28B4 6C7 IN CK505_SRC2_N 402 1 2 SB_CLK100M_DMI_N OUT 23D2 75B3
0
75B3 29D6 CK505_FSA 1 2 CPU_BSEL<0> IN 9B4 70B3 5%
1/16W
5%
R3014 MF-LF
R3050 NOSTUFF
(TO ICH8M USB 48MHZ) R30831
1/16W
MF-LF
402
(FROM CPU FS_A) 75C3 28B4 6C7 IN CK505_SRC4_P 1
0 2
402
SB_CLK100M_SATA_P OUT 22B6 75B3 28B4 CK505_SRC_CLKREQ1_L
10K 1 2
5%
1K 1/16W 402
C 5%
1/16W
MF-LF
402 2 CK505_SRC4_N
5%
1/16W
MF-LF
402
R3015
1
0 2 SB_CLK100M_SATA_N
(ICH8M SATA 100MHZ)
MF-LF
R3051 NOSTUFF C
75C3 28B4 6C7 IN OUT 22B6 75B3
10K 5%
5% 28B4 CK505_SRC_CLKREQ3_L 1 2
R3016 1/16W
MF-LF
1/16W
MF-LF
402
0 402
75C3 28B4 6C7 IN CK505_SRC5_P 1 2 NB_CLK100M_PCIE_P OUT 15C3 75B3
5%
1/16W R3017 (GMCH PEG/DMI 100MHZ)
MF-LF 0
=PP1V25R1V05_S0_FSB_NB 7C7 13B7 29B6 29C6 75C3 28B4 6C7 IN CK505_SRC5_N 402 1 2 NB_CLK100M_PCIE_N OUT 15C3 75B3
5%
1
R3084 R3018 1/16W
MF-LF
0 402
1K 75C3 28B4 6C7 IN CK505_SRC6_P 1 2 PCIE_CLK100M_MINI_P OUT 33C5 75B3
5%
1/16W 5%
R3019 (WIRELESS PCI-E MINI 100MHZ)
(TO MCH FS_B) R3085
MF-LF
2 402 75C3 28B4 6C7 IN CK505_SRC6_N
1/16W
MF-LF
402 1
0 2 PCIE_CLK100M_MINI_N OUT 33C5 75A3
1K
70B3 15C6 OUT NB_BSEL<1> 1 2 5%
5% R3022 1/16W
MF-LF
1/16W 0 402
MF-LF
R3086 75C3 28A4 6B7 IN CK505_SRC8_P 1 2 PCIE_CLK100M_ENET_P OUT 34C8
402
0 5%
R3023
28C6 OUT CK505_FSB_TEST_MODE 1 2 CPU_BSEL<1> IN 9A4 70B3 1/16W
MF-LF 0
(FOR YUKON 100MHZ) 29D2 28D8 28D3 28C8 7C4 =PP3V3_S0_CK505
NOSTUFF 5% 75C3 28A4 6B7 IN CK505_SRC8_N 402 1 2 PCIE_CLK100M_ENET_N OUT 34C8 NOSTUFF
R3087 1
1/16W
MF-LF
402
(FROM CPU FS_B) 5%
1/16W
1
R3067
1K MF-LF
402
10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 R3024 2 402
0
75D3 28A4 6C7 IN CK505_DOT96_27M_P 1 2 NB_CLK96M_DOT_P OUT 8B1 75B3
5%
R3025 CK505_PCI5_FCTSEL1
1/16W
MF-LF 0
(Int GFX DOT 96MHZ) 75D3 28B6 BI
CK505_DOT96_27M_N 1 2 NB_CLK96M_DOT_N
B B
75D3 28A4 6C7 IN 402 OUT 8B1 75B3
5%
1
=PP1V25R1V05_S0_FSB_NB 7C7 13B7 29C6
R3026
1/16W
MF-LF R3066
402 10K
33
1 NOSTUFF 75D3 28B8 IN CK505_PCIF0_CLK 1 2 PCI_CLK33M_LPCPLUS OUT 6C2 (PORT80 LPC 33MHZ) 5%
1/16W
R3088 5%
46C4 75C3 MF-LF
1K 2 402
5%
1/16W
MF-LF R3027
33
(TO MCH FS_C)
1/16W
MF-LF 75D3 28B6 6C7 IN CK505_PCIF1_CLK
402
1 2 PCI_CLK33M_SB OUT 23A6 (TO ICH8M PCI 33MHZ)
R3089 2 402 5%
29A5 75B3
1K R3028 1/16W
70B3 15B6 OUT NB_BSEL<2> 1 2 MF-LF
33
5%
1/16W
75D3 28B6 IN CK505_PCI1_CLK 1 2
402
PCI_CLK33M_FW OUT 29A5
37A5 75B3
(TO FIREWIRE PCI 33MHZ)
MF-LF
402 R3090 5%
1/16W
0 MF-LF
75B3 29D6 CK505_FSC 1 2 CPU_BSEL<2> IN 9A4 70B3 402
5%
(ICH8M 14.318MHZ) R3091 1
1/16W
MF-LF
402
(FROM CPU FS_C) R3030
1K 33
5%
1/16W
75D3 28B6 IN CK505_PCI3_CLK 1 2 PCI_CLK33M_SMC OUT 29A5
44C8 75B3
(TO SMC PCI 33MHZ)
MF-LF 5%
402 2 1/16W
MF-LF
402
Place close to CLK Gen

75B3 44C8 29A3 PCI_CLK33M_SMC For reducing noise coupling to wireless frequencies
75B3 29B3 23A6 PCI_CLK33M_SB
FS_C FS_B FS_A CPU SB_CLK48M_USBCTLR
Clock Termination
75B3 29D6 24D3
0 0 0 266M NOSTUFF R3082, R3086, R3090 75B3 29D6 24D3 SB_CLK14P3M_TIMER

A 0 0 1 133M FOR MANUAL CPU FREQUENCY 75B3 37A5 29B3 PCI_CLK33M_FW SYNC_MASTER=DSIMON-WF
A
0 1 1 166M NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C3000 1 C3001 1 C3002 1 C3003 1 C3004
* 0 1 0 200M CPU speed is currently set to 200MHz 3.3PF
0.25%
2 50V
3.3PF
0.25%
2 50V
3.3PF
0.25%
2 50V
3.3PF
0.25%
2 50V
3.3PF
0.25%
2 50V
CERM CERM CERM CERM CERM
1 1 0 400M 402 402 402 402 402 II NOT TO REPRODUCE OR COPY IT
1 1 1 Resrvd SIZE DRAWING NUMBER REV.
1 0 1 100M
1 0 0 333M APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 30 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
31D6 31D4 31B2 30D4 30B2 7B4 =PP1V8_S3_MEM DIP DIMM CONN201 =GND_CHASSIS_DIPDIMM_CENTER =PP1V8_S3_MEM 7B4 30B2 30D6 31B2 31D4 31D6
1 OMIT 2
MEM_VREF_A VREF
CRITICAL VSS0
30D1
3 4 MEM_A_DQ<4>
C3120 1 C3100
VSS1
J3101 DQ4 16D8 72D3
1
2.2UF
20%
0.1UF
20%
72D3 16D8
72D3
MEM_A_DQ<3>
16D8 MEM_A_DQ<7>
5
7
DQ0
DQ1
F-RT-TH3
DQ5
VSS2
6
8
MEM_A_DQ<5> 16D8 72D3
DDR2 VRef
DDR2-SODIMM-STD
2 4V
X5R 2 10V
CERM
9
VSS4 DM0
10 MEM_A_DM<0>
402 402 MEM_A_DQS_N<0> 11 12
16D5 72C3
One 0.1uF per connector
72C3 16C5 DQS0* VSS5
16C5 MEM_A_DQS_P<0>
13 14 MEM_A_DQ<0>
72C3 DQS0 DQ6 16D8 72D3
15 16 MEM_A_DQ<6> =PP1V8_S3M_MEM_NB
VSS6 DQ7 16D8 72D3 31D2 20C8 17D7 15D2 7A4
72D3 16D8 MEM_A_DQ<1>

17 DQ2 VSS7
18
16D8 MEM_A_DQ<2>
19 20 MEM_A_DQ<12> 1
72D3
21
DQ3 DQ12
22
16C8 72D3 R3100
MEM_A_DQ<14> 1K
D 72D3 16C8 MEM_A_DQ<8>
23
25
VSS8
DQ8
DQ13
VSS9
24
26
16C8 72D3
1%
1/16W
MF-LF
D
16C8 MEM_A_DQ<13> MEM_A_DM<1>
72D3 DQ9 DM1 16D5 72C3
2 402
27 VSS10 VSS11
28
29 30 MEM_VREF_A 30D7
72C3 16C5 MEM_A_DQS_N<1> DQS1* CK0 MEM_CLK_P<0> 15D3 72D3 VOLTAGE=0.9V
31 32 MIN_LINE_WIDTH=0.25 mm
72C3 16C5 MEM_A_DQS_P<1> DQS1 CK0* MEM_CLK_N<0> 15D3 72D3 MIN_NECK_WIDTH=0.25 mm
33 34 1
35
VSS12 VSS13
36
R3101
72D3 16C8 MEM_A_DQ<9> DQ10 DQ14 MEM_A_DQ<11> 16C8 72D3 1K
37 38 1%
72D3 16C8 MEM_A_DQ<10> DQ11 DQ15 MEM_A_DQ<15> 16C8 72D3 1/16W
39 40 MF-LF
VSS14 VSS15 2 402
KEY
41 42
VSS16 VSS17
MEM_A_DQ<24> 43 44 MEM_A_DQ<29>
72D3 16C8 DQ16 DQ20 16C8 72D3
16C8 MEM_A_DQ<25>
45 46 MEM_A_DQ<28>
72D3 DQ17 DQ21 16C8 72D3
47 VSS18 VSS19
48
72C3 16C5 MEM_A_DQS_N<3>
49
DQS2* NC0
50 DIMM_OVERTEMPA_L 8B1 Yellow uses 10K divider and TLV2463
16C5 MEM_A_DQS_P<3>
51 52 MEM_A_DM<3>
72C3
53
DQS2 DM2
54
16C5 72C3
to drive MCH and DIMM connectors.
VSS21 VSS22
72D3 16C8 MEM_A_DQ<31> 55
DQ18 DQ22
56 MEM_A_DQ<26> 16C8 72D3 (See Capell Valley pg 47)
72D3 16C8 MEM_A_DQ<27> 57 DQ19 DQ23
58 MEM_A_DQ<30> 16C8 72D3
59 60
Page Notes
VSS23 VSS24
MEM_A_DQ<23> 61 62 MEM_A_DQ<16>
72D3 16C8 DQ24 DQ28 16C8 72D3
MEM_A_DQ<19> 63 64 MEM_A_DQ<22>
72D3 16C8 DQ25 DQ29 16C8 72D3
65 66 Power aliases required by this page:
VSS25 VSS26
72C3 16C5 MEM_A_DM<2> 67 DM3 DQS3*
68 MEM_A_DQS_N<2> 16C5 72C3 - =PP1V8_S3_MEM
NC 69 70 MEM_A_DQS_P<2> - =PPSPD_S0_MEM (2.5V - 3.3V)
NC1 DQS3 16C5 72C3
71 72
VSS27 VSS28
MEM_A_DQ<18> 73 74 MEM_A_DQ<20> Signal aliases required by this page:
C
DQ26 DQ30
C
72D3 16C8 16C8 72D3
MEM_A_DQ<21> 75 76 MEM_A_DQ<17> - =I2C_MEM_SCL

72D3 16C8 DQ27 DQ31 16C8 72D3
77 78 - =I2C_MEM_SDA
VSS29 VSS30
MEM_CKE<0> 79 80 MEM_CKE<1> BOM options provided by this page:
72D3 32D6 15D3 CKE0 NC/CKE1 15D3 32D6 72D3
81 82 (NONE)
VDD0 VDD1
NC 83 NC2 NC/A15
84 NC MEM_A_A<15> 8B4
MEM_A_BS<2> 85 86 NC MEM_A_A<14>
72D3 32C6 16D5 BA2 NC/A14 15C6 32C6 72D3
87 88
DDR2 Bypass Caps

VDD2 VDD3
MEM_A_A<12> 89 90 MEM_A_A<11>
72D3 32C6 16B5 A12 A11 16B5 32C6 72D3
MEM_A_A<9> 91 92 MEM_A_A<7>
72D3 32C6 16B5 A9 A7 16B5 32C6 72D3
72D3 32C6 16B5 MEM_A_A<8> 93 A8 A6

94 MEM_A_A<6> 16B5 32C6 72D3 (For return current)
95 96
VDD4 VDD5 =PP1V8_S3_MEM
MEM_A_A<5> 97 98 MEM_A_A<4>
31D6 31D4 31B2 30D6 30D4 7B4
72D3 32C6 16B5 A5 A4 16B5 32C6 72D3
16B5 MEM_A_A<3>
99 100 MEM_A_A<2>
72D3 32C6 A3 A2 16B5 32C6 72D3
16C5 MEM_A_A<1>
101 102 MEM_A_A<0>
72D3 32C6
103
A1 A0
104
16C5 32C6 72D3
1 C3109
VDD6 VDD7 4.7uF
MEM_A_A<10> 105 106 MEM_A_BS<1> 20%
A10/AP BA1
2 6.3V
72D3 32C6 16B5 16D5 32C6 72D3
16D5 MEM_A_BS<0>
107 108 MEM_A_RAS_L CERM
72D3 32C6 BA0 RAS* 16B5 32B6 72D3
603
16B5 MEM_A_WE_L
109 110 MEM_CS_L<0>
72D3 32B6 WE* S0* 15D3 32D6 72D3
111 112
VDD8 VDD9
72D3 32B6 16D5 MEM_A_CAS_L 113 CAS* ODT0
114 MEM_ODT<0> 15C3 32D6 72D3
15D3 MEM_CS_L<1>
115 116 MEM_A_A<13>
72D3 32D6
117
NC/S1* NC/A13
118
16B5 32C6 72D3
1 C3110 1 C3111 1 C3112 1 C3113
VDD10 VDD11 0.1UF 0.1UF 0.1UF 0.1UF
MEM_ODT<1> 119 NC/ODT1 NC3
120 NC 20% 20% 20% 20%
72D3 32D6 15C3 10V
2 CERM 10V
2 CERM 2 10V 2 10V
121 122 CERM CERM
VSS31 VSS32 402 402 402 402
MEM_A_DQ<38> 123 124 MEM_A_DQ<37>
72D3 16B8 DQ32 DQ36 16B8 72D3
MEM_A_DQ<39> 125 126 MEM_A_DQ<34>

72D3 16B8 DQ33 DQ37 16B8 72D3
B 72C3 16C5 MEM_A_DQS_N<4>

127
129
VSS33
DQS4*
VSS34
DM4
128
130 MEM_A_DM<4> 16C5 72C3
1 C3114 1 C3115 1 C3116 1 C3117 B
72C3 16C5 MEM_A_DQS_P<4> 131
DQS4 VSS35
132 0.1UF 0.1UF 2.2UF 2.2UF
20% 20% 20% 20%
133 134 MEM_A_DQ<32> 2 10V 2 10V
6.3V
2 CERM 6.3V
2 CERM
VSS36 DQ38 16C8 72D3 CERM CERM
MEM_A_DQ<36> 135 136 MEM_A_DQ<35> 402 402 402-LF 402-LF
72D3 16B8 DQ34 DQ39 16B8 72D3
16C8 MEM_A_DQ<33>
137 138
72D3 DQ35 VSS37
139 VSS38 DQ44
140 MEM_A_DQ<44> 16B8 72D3
MEM_A_DQ<41> 141 142 MEM_A_DQ<40>

72D3 16B8
16B8 MEM_A_DQ<42>
143
DQ40 DQ45
144
16B8 72D3 1 C3130 1 C3131 1 C3132
72D3 DQ41 VSS39 2.2UF 2.2UF 2.2UF
145 146 MEM_A_DQS_N<5> 20% 20% 20%
VSS40 DQS5* 16C5 72C3 6.3V
2 CERM 6.3V
2 CERM 2 6.3V
MEM_A_DM<5> 147 148 MEM_A_DQS_P<5> CERM
72C3 16C5 DM5 DQS5 16C5 72C3 402-LF 402-LF 402-LF
149 VSS41 VSS42
150
MEM_A_DQ<43> 151 152 MEM_A_DQ<47>
72D3 16B8 DQ42 DQ46 16B8 72D3
16B8 MEM_A_DQ<46>
153 154 MEM_A_DQ<45>
72D3 DQ43 DQ47 16B8 72D3
155 VSS43 VSS44
156
72D3 16B8 MEM_A_DQ<56>
157
DQ48 DQ52
158 MEM_A_DQ<60> 16A8 72D3 The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
16B8 MEM_A_DQ<57>
159 160 MEM_A_DQ<61>
DQ49 DQ53
72D3
161 162
16A8 72D3
when they get cheaper.
VSS45 VSS46
NC 163 164 MEM_CLK_P<1>
NC_TEST CK1 15D3 72D3
165 VSS47 CK1*
166 MEM_CLK_N<1> 15D3 72D3
MEM_A_DQS_N<7> 167 168

72C3 16C5 DQS6* VSS48
16C5 MEM_A_DQS_P<7>
169 170 MEM_A_DM<7>
72C3 DQS6 DM6 16C5 72C3
171 172
VSS49 VSS50
72D3 16B8 MEM_A_DQ<59> 173
DQ50 DQ54
174 MEM_A_DQ<62> 16A8 72D3 R3102
72D3 16A8 MEM_A_DQ<63>
175
177
DQ51 DQ55
176
178
MEM_A_DQ<58> 16B8 72D3 30A4 MEM_A_SA0 1
10K 2 DDR2 SO-DIMM Connector A
VSS51 VSS52 5%
A 72D3 16B8 MEM_A_DQ<52>
16B8 MEM_A_DQ<49>
179
181
DQ56 DQ60
180
182
MEM_A_DQ<48>
MEM_A_DQ<53>
16B8 72D3
1/16W
MF-LF
402
SYNC_MASTER=MEMORY
A
DQ57 DQ61
R3103
72D3 16B8 72D3
183 184
VSS53 VSS54
MEM_A_DM<6> 185 186 MEM_A_DQS_N<6> MEM_A_SA1 1
10K 2
72C3 16C5 DM7 DQS7* 16C5 72C3 30A4
187 188 AGREES TO THE FOLLOWING
VSS55 DQS7 MEM_A_DQS_P<6> 16C5 72C3 5%
189 190 1/16W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
72D3 16B8 MEM_A_DQ<51> DQ58 VSS56 MF-LF
191 192 402 II NOT TO REPRODUCE OR COPY IT
72D3 16B8 MEM_A_DQ<55> DQ59 DQ62 MEM_A_DQ<50> 16B8 72D3
31A7 31A3 7C4 =PPSPD_S0_MEM 193 194 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VSS57 DQ63 MEM_A_DQ<54> 16B8 72D3
1 C3122
2.2UF
1 C3121
0.1UF
47D6 =I2C_SODIMMA_SDA 195
SDA VSS58
20%
2 4V
X5R
402
20%
2 10V
CERM
402
47D6 =I2C_SODIMMA_SCL
197
199
SCL
VDDSPD
SA0
SA1
198
200
MEM_A_SA0
MEM_A_SA1
30A4
30A4
APPLE INC.
D 051-7559 H
202=GND_CHASSIS_DIPDIMM_LEFT SCALE SHT OF

516-0135 8D8
ADDR=0xA0(WR)/0xA1(RD) NONE 31 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
31D4 31B2 30D6 30D4 30B2 7B4 =PP1V8_S3_MEM DIP DIMM CONN201 =GND_CHASSIS_DIPDIMM_RIGHT =PP1V8_S3_MEM 7B4 30B2 30D4 30D6 31B2 31D6
31D1 MEM_VREF_B 1
3
VREF
VSS1
OMIT
CRITICAL VSS0
J3201 DQ4
2
4 MEM_B_DQ<5> 16D4 72B3
DDR2 VREF (FOR CONNECTOR B)
1 C3220
2.2UF
1 C3200
0.1UF
72B3 16D4 MEM_B_DQ<1> 5
7
DQ0
F-RT-TH3
DQ5
6
8
MEM_B_DQ<0> 16D4 72B3 One 0.1uF per connector
16D4 MEM_B_DQ<4> DQ1 VSS2
20% 20% 72B3
2 4V 2 10V
DDR2-SODIMM-STD
9 10 MEM_B_DM<0>
X5R CERM VSS4 DM0 16D1 72B3
=PP1V8_S3M_MEM_NB
402 402 MEM_B_DQS_N<0> 11 12 30D2 20C8 17D7 15D2 7A4
72A3 16C1 DQS0* VSS5
MEM_B_DQS_P<0> 13 14 MEM_B_DQ<6>
72A3 16C1 DQS0 DQ6 16D4 72B3
1
15
VSS6 DQ7
16 MEM_B_DQ<2> 16D4 72B3
R3201
17 18 1K
72B3 16D4 MEM_B_DQ<7> DQ2 VSS7 1%
19 20 1/16W
72B3 16D4 MEM_B_DQ<3> DQ3 DQ12 MEM_B_DQ<15> 16C4 72B3 MF-LF
D 72B3 16C4 MEM_B_DQ<13>

21
23
VSS8
DQ8
DQ13
VSS9
22
24
MEM_B_DQ<11> 16C4 72B3
2 402
MEM_VREF_B 31D7
D
25 26 VOLTAGE=0.9V
72B3 16C4 MEM_B_DQ<12> DQ9 DM1 MEM_B_DM<1> 16D1 72B3 MIN_LINE_WIDTH=0.25 mm
27 28 MIN_NECK_WIDTH=0.25 mm
VSS10 VSS11 1
72A3 16C1 MEM_B_DQS_N<1> 29 DQS1* CK0
30 MEM_CLK_P<3> 15D3 72B3
R3202
31 32 1K
72A3 16C1 MEM_B_DQS_P<1> DQS1 CK0* MEM_CLK_N<3> 15D3 72B3 1%
33 34 1/16W
VSS12 VSS13 MF-LF
MEM_B_DQ<10> 35 36 MEM_B_DQ<9> 2 402
72B3 16C4 DQ10 DQ14 16C4 72B3
72B3 16C4 MEM_B_DQ<8>

37 DQ11 DQ15
38 MEM_B_DQ<14> 16C4 72B3
39 VSS14 VSS15
40
KEY
41 VSS16 VSS17
42
MEM_B_DQ<17> 43 44 MEM_B_DQ<21>
72B3 16C4
16C4 MEM_B_DQ<20>
45
DQ16 DQ20
46 MEM_B_DQ<16>
16C4 72B3
Yellow uses 10K divider and TLV2463
72B3 DQ17 DQ21 16C4 72B3
47
VSS18 VSS19
48 to drive MCH and DIMM connectors.
MEM_B_DQS_N<2> 49 50 DIMM_OVERTEMPB_L
72A3 16C1
MEM_B_DQS_P<2> 51
DQS2* NC0
52 MEM_B_DM<2>
8B1
(See Capell Valley pg 47)
72A3 16C1 DQS2 DM2 16C1 72B3
53 54
Page Notes
VSS21 VSS22
MEM_B_DQ<22> 55 56 MEM_B_DQ<23>
72B3 16C4 DQ18 DQ22 16C4 72B3
MEM_B_DQ<18> 57 58 MEM_B_DQ<19>
72B3 16C4 DQ19 DQ23 16C4 72B3
59 60 Power aliases required by this page:
VSS23 VSS24
MEM_B_DQ<29> 61 62 MEM_B_DQ<25> - =PP1V8_S3_MEM
72B3 16C4 DQ24 DQ28 16C4 72B3
MEM_B_DQ<27> 63 64 MEM_B_DQ<28> - =PPSPD_S0_MEM (2.5V - 3.3V)

72B3 16C4 DQ25 DQ29 16C4 72B3
65 66
VSS25 VSS26
MEM_B_DM<3> 67 68 MEM_B_DQS_N<3> Signal aliases required by this page:
72B3 16C1 DM3 DQS3* 16C1 72A3
69 70 MEM_B_DQS_P<3> - =I2C_MEM_SCL
NC NC1 DQS3 16C1 72A3
71 72 - =I2C_MEM_SDA
VSS27 VSS28
C 72B3 16C4
72B3 16C4
MEM_B_DQ<30>
MEM_B_DQ<31>
73
75
DQ26
DQ27
DQ30
DQ31
74
76
MEM_B_DQ<24>
MEM_B_DQ<26>
16C4 72B3
16C4 72B3
BOM options provided by this page:
(NONE) C
77 78
VSS29 VSS30
79 80 NOTE: This page does not supply VREF.
72B3 32D6 15D3 MEM_CKE<3> CKE0 NC/CKE1 MEM_CKE<4> 15D3 32D5 72B3
81 82 The reference voltage must be provided
VDD0 VDD1
83 84 NC MEM_B_A<15> by another page.
NC NC2 NC/A15 8B4
MEM_B_BS<2> 85 86 NC MEM_B_A<14>
72B3 32A6 16D1 BA2 NC/A14 15C6 32A5 72B3
72B3 32A5 16B1 MEM_B_A<12>
16B1 MEM_B_A<9>
87
89
91
VDD2
A12
A9
VDD3
A11
A7
88
90
92
MEM_B_A<11>
MEM_B_A<7>
16B1 32A5 72B3 DDR2 Bypass Caps
72B3 32B5
16B1 MEM_B_A<8>
93 94 MEM_B_A<6>
16B1 32B5 72B3
(For return current)
72B3 32B5 A8 A6 16B1 32B5 72B3
95 VDD4 VDD5
96 31D6 31D4 30D6 30D4 30B2 7B4 =PP1V8_S3_MEM
72B3 32B5 16B1 MEM_B_A<5> 97 A5 A4
98 MEM_B_A<4> 16B1 32B5 72B3
72B3 32B5 16B1 MEM_B_A<3> 99 A3 A2

100 MEM_B_A<2> 16B1 32B5 72B3
72B3 32B5 16C1 MEM_B_A<1>

101 A1 A0
102 MEM_B_A<0> 16C1 32B5 72B3
1 C3209
103 VDD6 VDD7
104 4.7uF
20%
MEM_B_A<10> 105 106 MEM_B_BS<1> 6.3V
2 CERM
72B3 32B5 16B1 A10/AP BA1 16D1 32A6 72B3
72B3 32A6 16D1 MEM_B_BS<0>

107 BA0 RAS*
108 MEM_B_RAS_L 16B1 32A6 72B3
603
16B1 MEM_B_WE_L
109 110 MEM_CS_L<2>
72B3 32A6 WE* S0* 15D3 32D6 72B3
111 112
VDD8 VDD9
MEM_B_CAS_L 113 114 MEM_ODT<2>
72B3 32A6 16D1 CAS* ODT0 15C3 32D6 72B3
72B3 32D6 15C3 MEM_CS_L<3> 115

NC/S1* NC/A13
116 MEM_B_A<13> 16B1 32A5 72B3
1 C3210 1 C3211 1 C3212 1 C3213
117
VDD10 VDD11
118 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20%
72B3 32D6 15C3 MEM_ODT<3> 119
NC/ODT1 NC3
120 NC 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
121 122 402 402 402 402
VSS31 VSS32
MEM_B_DQ<38> 123 124 MEM_B_DQ<36>
72B3 16B4 DQ32 DQ36 16B4 72B3
MEM_B_DQ<32> 125 126 MEM_B_DQ<37>

B
72B3 16C4
127
DQ33
VSS33
DQ37
VSS34
128
16B4 72B3
B
72A3 16C1 MEM_B_DQS_N<4> 129
DQS4* DM4
130 MEM_B_DM<4> 16C1 72B3
1 C3214 1 C3215 1 C3216 1 C3217
72A3 16C1 MEM_B_DQS_P<4>
131
DQS4 VSS35
132 0.1UF 0.1UF 2.2UF 2.2UF
20% 20% 20% 20%
133
VSS36 DQ38
134 MEM_B_DQ<34> 16B4 72B3 2 10V
CERM 2 10V
CERM 2 6.3V
CERM 2 6.3V
CERM
MEM_B_DQ<39> 135 136 MEM_B_DQ<33> 402 402 402-LF 402-LF
72B3 16B4 DQ34 DQ39 16C4 72B3
16B4 MEM_B_DQ<35>
137 138
72B3 DQ35 VSS37
139 140 MEM_B_DQ<43>
VSS38 DQ44 16B4 72B3
MEM_B_DQ<47> 141 142 MEM_B_DQ<42>

72B3 16B4
MEM_B_DQ<45> 143
DQ40 DQ45
144
16B4 72B3 1 C3230 1 C3231 1 C3232
72B3 16B4 DQ41 VSS39 2.2UF 2.2UF 2.2UF
145 146 MEM_B_DQS_N<5> 20% 20% 20%
VSS40 DQS5* 2 6.3V 2 6.3V 2 6.3V
16C1 72A3
147 148 CERM CERM CERM
72B3 16C1 MEM_B_DM<5> DM5 DQS5 MEM_B_DQS_P<5> 16C1 72A3 402-LF 402-LF 402-LF
149 VSS41 VSS42
150
72B3 16B4 MEM_B_DQ<44> 151 DQ42 DQ46
152 MEM_B_DQ<41> 16B4 72B3
16B4 MEM_B_DQ<40>
153 DQ43 DQ47
154 MEM_B_DQ<46>
72B3
155 156
16B4 72B3
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
VSS43 VSS44
72B3 16B4 MEM_B_DQ<48> 157 DQ48 DQ52
158 MEM_B_DQ<53> 16B4 72B3 when they get cheaper.
72B3 16B4 MEM_B_DQ<52>
159 DQ49 DQ53
160 MEM_B_DQ<49> 16B4 72B3
161 VSS45 VSS46
162
NC 163 NC_TEST CK1
164 MEM_CLK_P<4> 15D3 72B3
165 VSS47 CK1*
166 MEM_CLK_N<4> 15D3 72B3
72A3 16C1 MEM_B_DQS_N<6> 167 DQS6* VSS48

168
72A3 16C1 MEM_B_DQS_P<6>
169 DQS6 DM6
170 MEM_B_DM<6> 16C1 72A3
171 172
MEM_B_DQ<50> 173
VSS49 VSS50
174 MEM_B_DQ<51> R3203
72B3 16B4
72B3 16B4 MEM_B_DQ<55>

175
DQ50
DQ51
DQ54
DQ55
176 MEM_B_DQ<54>
16B4 72B3
16B4 72B3
31A4
MEM_B_SA0 10K
1 2 DDR2 SO-DIMM Connector B
177 178 5%
A 72B3 16B4 MEM_B_DQ<56> 179
VSS51
DQ56
VSS52
DQ60
180 MEM_B_DQ<60> 16A4 72B3
1/16W
MF-LF
402
SYNC_MASTER=MEMORY
A
MEM_B_DQ<57> 181 182 MEM_B_DQ<62>
72B3 16B4 DQ57 DQ61 16A4 72B3
183 184 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
VSS53 VSS54
185 186 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
72A3 16C1 MEM_B_DM<7> DM7 DQS7* MEM_B_DQS_N<7> 16C1 72A3 AGREES TO THE FOLLOWING
187 188 =PPSPD_S0_MEM 7C4 30A7 31A7
VSS55 DQS7 MEM_B_DQS_P<7> 16C1 72A3 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
31A3 30A7 7C4 =PPSPD_S0_MEM 189 190
72B3 16A4 MEM_B_DQ<61> DQ58 VSS56 II NOT TO REPRODUCE OR COPY IT
72B3 16A4 MEM_B_DQ<63> 191
DQ59 DQ62
192 MEM_B_DQ<58> 16B4 72B3
1
R3200 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1 C3222
2.2UF
1 C3221
0.1UF
193
195
VSS57 DQ63
194
196
MEM_B_DQ<59> 16B4 72B3 5%
10K
1/16W SIZE DRAWING NUMBER REV.
=I2C_SODIMMB_SDA
051-7559
20% 20% 47C6 SDA VSS58 MF-LF
2 4V
X5R
402
2 10V
CERM
402
47C6 =I2C_SODIMMB_SCL
197
199
SCL SA0
198
200
MEM_B_SA0 31A3 2 402
Resistor prevents pwr-gnd short
D H
VDDSPD SA1 J3201_SA1 APPLE INC. SCALE SHT OF
516-0135 202=GND_CHASSIS_DIPDIMM_CENTER ADDR=0xA4(WR)/0xA5(RD) NONE 32 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it
7D7 =PP0V9_S3M_MEM_TERM
72D3 72B3 31B6 31B4 30B6 30B4 15D3 15C3 IN MEM_CS_L<3..0>

0
RP3300 56 3 6
1 R3301 56 1 2 5% 1/16WSM-LF 1 C3300 1 C3301
RP3301 56 2 7 5% 1/16WMF-LF402 0.1UF 0.1UF
RP3302
2
5% 1/16WSM-LF 20% 20%
15D3 31C4 72B3

3 56 4 5 10V
2 CERM
10V
2 CERM
D
5% 1/16W SM-LF 402 402
D
MEM_CKE<0> RP3303 56 1 8
72D3 30C6 15D3 IN
MEM_CKE<1> RP3304 56 1 8 5% 1/16W SM-LF 1 C3302 1 C3303
72D3 30C4 15D3
72B3 31C6 15D3

IN
IN MEM_CKE<3> RP3305 56 1 8 5% 1/16W SM-LF 0.1UF 0.1UF
20% 20%
IN MEM_CKE<4> R3327 56 1 2
5%
5%
1/16W SM-LF
1/16W MF-LF402
10V
2 CERM
10V
2 CERM
402 402
72D3 72B3 31B6 31B4 30B6 30B4 15C3 IN MEM_ODT<3..0>

0
RP3300 56 4 5
R3309 56 1 2 5% 1/16W SM-LF 1 C3304 1 C3305
1
RP3301 5% 1/16WMF-LF402 0.1UF 0.1UF
2 56 3 6 20% 20%
3 R3311 56 1 2 5% 1/16W SM-LF 10V

2 CERM
402
10V
2 CERM
402
5% 1/16WMF-LF402
72D3 30C6 30C4 30B6 30B4 16C5 16B5 15C6 IN MEM_A_A<14..0> RP3307 56 4 5 1 C3306 1 C3307
RP3308
0
56 4 5 5% 1/16W SM-LF 0.1UF 0.1UF

1
RP3307 56 3 6 5% 1/16W SM-LF 20%
2 10V
20%
10V
2 CERM
RP3308
2
CERM
56 3 6 5% 1/16W SM-LF 402 402
3
RP3307 56 2 7 5% 1/16W SM-LF
RP3308
4
56 2 7 5% 1/16W SM-LF
RP3307
5
56 1 8 5% 1/16W SM-LF
RP3304
6
56 4 5 5% 1/16W SM-LF 1 C3308 1 C3309

7
RP3308 5% 1/16WSM-LF
SM-LF 0.1UF 0.1UF
8 56 1 8 20% 20%
RP3303 56 4 5 5% 1/16WSM-LF
1/16W SM-LF 10V
2 CERM
10V
2 CERM
RP3309
9
5% 1/16WSM-LF
1/16W 402 402
SM-LF
C 10
RP3304
56
56
1
3
8
6 5% 1/16W SM-LF
LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
TO PP0V9_S0_MEM_TERM C
RP3303
11
56 3 6 5% 1/16W SM-LF
12
R3325 56 1 2 5% 1/16W SM-LF 1 C3310 1 C3311
RP3304
13
5% 1/16WMF-LF402
14 56 2 7 0.1UF 0.1UF
5% 1/16W SM-LF 20% 20%
2 10V
10V
CERM 2 CERM
402 402
72D3 30C6 30B6 30B4 16D5 IN MEM_A_BS<2..0> RP3309 56 2 7

RP3300
0
56 1 8 5% 1/16WSM-LF
SM-LF
1
2
RP3303 56 2 7 5% 1/16W SM-LF 1 C3312 1 C3313
5% 1/16W
1/16WSM-LF 0.1UF 0.1UF
20% 20%
2 10V
10V
CERM 2 CERM
402 402
MEM_A_RAS_L RP3300 56 2 7
72D3 30B4 16B5 IN
MEM_A_CAS_L RP3309 56 4 5 5% 1/16W SM-LF
72D3 30B6 16D5 IN
MEM_A_WE_L RP3309 56 3 6 5% 1/16W SM-LF
72D3 30B6 16B5 IN
5% 1/16W SM-LF 1 C3314 1 C3315
0.1UF 0.1UF
20% 20%
2 10V
10V
CERM 2 CERM
402 402
1 C3316 1 C3317
RP3311 0.1UF 0.1UF
MEM_B_A<0> 56 3 6 20% 20%
B
72B3 31B4 16C1
72B3 31B6 16B1

IN
IN MEM_B_A<3> RP3310
RP3311
56 3
56 2
6
7
5%
5%
1/16W SM-LF
1/16W SM-LF
10V
2 CERM
402
10V
2 CERM
402
B
72B3 31B4 16B1 IN MEM_B_A<2>
MEM_B_A<10> R3335 56 1 2 5% 1/16W SM-LF
72B3 31B6 16B1 IN
MEM_B_A<4> RP3311 56 1 8 5% 1/16WMF-LF402
72B3 31B4 16B1 IN
MEM_B_A<5> RP3310 56 2 7 5% 1/16W SM-LF
RP3306 C3318 C3319
72B3 31B6 16B1 IN
5% 1/16W SM-LF 1 1
MEM_B_A<6> 56 4 5
72B3 31C4 16B1 IN
RP3306 5% 1/16W SM-LF 0.1UF 0.1UF
MEM_B_A<7> 56 3 6 20% 20%
RP3310
72B3 31C4 16B1 IN 10V 10V
56 1 8 5% 1/16WSM-LF 2 CERM 2 CERM
MEM_B_A<8>
72B3 31C6 16B1 IN
MEM_B_A<9> RP3305 56 4 5 5% 1/16WSM-LF 402 402
72B3 31C6 16B1 IN
MEM_B_A<1> RP3310 56 4 5 5% 1/16WSM-LF
72B3 31B6 16C1 IN
MEM_B_A<11> RP3306 56 2 7 5% 1/16WSM-LF
72B3 31C4 16B1 IN
MEM_B_A<12> RP3305 56 3 6 5% 1/16W SM-LF
72B3 31C6 16B1 IN
MEM_B_A<13> RP3301 56 4 5 5% 1/16W SM-LF 1 C3320 1 C3321
72B3 31B4 16B1 IN 0.1UF 0.1UF
IN MEM_B_A<14> RP3306 56 1 8 5% 1/16WSM-LF 20%
10V
20%
10V
5% 1/16WSM-LF 2 CERM 2 CERM
402 402
72B3 31C6 31B6 31B4 16D1 IN MEM_B_BS<2..0>

0
RP3302 56 1 8
1
RP3311 56 4 5 5% 1/16WSM-LF 1 C3322 1 C3323
RP3305 5% 1/16W SM-LF 0.1UF 0.1UF
2 56 2 7 20% 20%
2 10V
10V
5% 1/16W SM-LF CERM 2 CERM
402 402
MEM_B_RAS_L RP3301 56 1 8 Memory Active Termination

72B3 31B4 16B1 IN
RP3302 56 5% 1/16W SM-LF
C3324 C3325
A MEM_B_CAS_L 2 7
A
1 1
72B3 31B6 16D1
72B3 31B6 16B1

IN
IN MEM_B_WE_L RP3302 56 3 6 5% 1/16W SM-LF 0.1UF 0.1UF
5% 1/16W SM-LF 20% 20% NOTICE OF PROPRIETARY PROPERTY
10V 10V
2 CERM 2 CERM
APPLE INC.
D 051-7559 H
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CRITICAL
Q3401
FDC638P
SM-LF
6
D 33D7 33C7 7C1

4
=PP3V3_S5_AIRPORT_AUX
5
2 PP3V3_S3_AP_AUX =PP1V5_S0_AIRPORT 7B7
D
33D6 33C7 7C1 =PP3V3_S5_AIRPORT_AUX 1
R3404
C3411
1 C34081 C3407 1 C3404 1 C3405 1 C3406
2
1
100K
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1/16W
MF-LF
0.033UF3
402
20% 20% 20% 20% 20%
5%
10% 10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
10V
2 CERM
2 16V
X5R 402 402 MIN_LINE_WIDTH=0.2MM 402 402 402
R3405 402
1
NOSTUFF VOLTAGE=3.3V
10K C3412
PM_WLAN_EN_L 2 1 PM_WLAN_EN_L_SS
2
5%
1/16W 0.01UF
MF-LF 16V
Q3402 D 6 Q3402 D 3 402 402

10%
SSM6N15FE
SOT563
SSM6N15FE
SOT563
CERM
R3403
1/8W 805
5% MF-LF
0
2 G S 1 5 G S 4 7D4 =PP3V3_S0_AIRPORT 2 1
62B8 58B7 45A6 44C5 35C7 24D3
PM_SLP_S3_L NOSTUFF
57C4 45B3 44D5 38C6 35C7 6C1
SMC_ADAPTER_EN PM_WLAN_EN_L1
Q3403 D 6 CRITICAL
33D7 33D6 7C1 =PP3V3_S5_AIRPORT_AUX
SSM6N15FE
SOT563
J3400
AS0B226-S45B-7F
F-ST-SM
54
R3406
2
100K
2 G S 1
1/16W
MF-LF
402
5%
34B8 24C8 PCIE_WAKE_L 1 2

OUT
PM_WLAN_EN_L2
C
3 4
C
1
5 6
WOW_EN
33B5
28B4 CK505_SRC_CLKREQ6_L 7 8 27D1 AIRPORT_RST_L
ICH8 GPIO42 Q3403 D 3
OUT
9 10
IN
SSM6N15FE 75A3 29B3 PCIE_CLK100M_MINI_N 11 12 =PP3V3_S3_AIRPORT_AUX 7A4

SOT563 IN
75B3 29C3 PCIE_CLK100M_MINI_P 13 14 MIN_NECK_WIDTH=0.2MM
IN
VOLTAGE=3.3V
15 16 1 C34091 C3410
5 G S 4 17 KEY 18 10UF 0.1UF
20% 20%
19 20 2 6.3V 2 10V
X5R CERM
21 22 603 402
74B3 33B5 PCIE_E_D2R_N 23 24

OUT
PCIE_E_D2R_P 25 26
PM_S4_STATE_L 74C3 33B5
OUT
65C4 65A6 44C5 24D3
27 28 R3401MF-LF
402 1/16W
5%
29 30 0
C3400 SMB_AIRPORT_CONN_CLK 1 2 47C3 =SMB_AIRPORT_CLK
74C3 33B5 PCIE_E_R2D_C_N 31 32
IO
IN
21 0.1UF PCIE_E_R2D_N 0
CERM 402
33 34 SMB_AIRPORT_CONN_DATA 1 2 47C3 =SMB_AIRPORT_DATA IO
IN
74C3 33B5 PCIE_E_R2D_C_P
1 2 0.1UF 20% 10V PCIE_E_R2D_P
CERM 402
20% 10V 35 36 R3402402 1/16W
MF-LF 5% 8C2 =USB2_AIRPORT_N
IO
C3401 37 38 8C2 =USB2_AIRPORT_P
IO
PLACE CAPS < 250 MILS FROM (U2100) SB 39 40
41 42 SB HAS INTERNAL 15K PULL-DOWNS
43 44
45 46
47 48
49 50
51 52
B 23C8 SB_GPIO42 WOW_EN

MAKE_BASE=TRUE
33C7
53
B
23D5 PCIE_MINI_D2R_N PCIE_E_D2R_N 33C5 74B3
MAKE_BASE=TRUE
23C5 PCIE_MINI_D2R_P PCIE_E_D2R_P 33B5 74C3
MAKE_BASE=TRUE
23C5 PCIE_MINI_R2D_C_N PCIE_E_R2D_C_N 33B6 74C3
MAKE_BASE=TRUE
23C5
PCIE_MINI_R2D_C_P PCIE_E_R2D_C_P 33B6 74C3
MAKE_BASE=TRUE CONNECT TO M35 MODULE
OLD:516S0406 (FOXCONN ONLY)

NEW:516S0635 (FOXCONN & ACON)
AIRPORT CONNECTOR
A SYNC_MASTER=ENET

A
APPLE INC.
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Page Notes
Power aliases required by this page:
- =PP3V3_ENET_PHY (EC / Ultra)
7B5 =PP1V2_ENET_PHY
- =PP1V8R2V5_ENET_PHY (2.5V / 1.8V)
Yukon EC Yukon Ultra
- =YUKON_EC_PP2V5_ENET (2.5V / GND)
- =PP1V2_ENET_PHY No link: 171 mA No link: 130 mA
10 Mbps: 179 mA 10 Mbps: 130 mA
C3700 1 1 C3701 1 C3702 1 C3703 1 C3704 1 C3705 1 C3706 1 C3707 1 C3708
Signal aliases required by this page: 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.001UF 0.001UF 0.001UF
100 Mbps: 203 mA 100 Mbps: 150 mA 20% 10% 10% 10% 10% 10% 10% 10% 10%
- =ENET_CLKREQ_L (NC/TP for Yukon EC) 6.3V 16V 2 16V 16V 2 16V 2 16V 2 50V 2 50V 2 50V
CERM 2 2 X5R X5R 2 X5R X5R X5R CERM CERM CERM
1000 Mbps: 426 mA 1000 Mbps: 290 mA 603 402 402 402 402 402 402 402 402
- =ENET_VMAIN_AVLBL
D BOM options provided by this page:

YUKON_EC - Selects Yukon EC RSET value.
D
7B5 =PP3V3_ENET_PHY
YUKON_ULTRA - Selects Yukon Ultra RSET.
Yukon EC Yukon Ultra
NOTE: Yukon IC and EEPROM are OMITted
No link: 4 mA No link: 60 mA
on this page. Proper part numbers
10 Mbps: 4 mA 10 Mbps: 70 mA
C3710 1 1 C3711 1 C3712 1 C3713 1 C3714 1 C3715
must be called out elsewhere. 4.7UF 0.1UF 0.1UF 0.1UF 0.001UF 0.001UF
100 Mbps: 4 mA 100 Mbps: 70 mA 20% 10% 10% 10% 10% 10%
6.3V
CERM 2 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 50V
CERM 2 50V
CERM
NOTE: See bottom of page for 1000 Mbps: 4 mA 1000 Mbps: 80 mA 603 402 402 402 402 402
instructions for dual Yukon EC /
Yukon Ultra schematic support.
L3720
FERR-120-OHM-1.5A
7B3 =PP1V8R2V5_ENET_PHY 1 2 PP1V8R2V5_ENET_PHY_AVDD
0402-LF
VOLTAGE=1.8V
Yukon EC (2.5V) Yukon Ultra (1.8V)
(EC:2.5V)
C3720 1 1 C3721 1 C3722 1 C3723 1 C3724
4.7UF 0.1UF 0.1UF 0.1UF 0.001UF
No link: 82 mA No link: 0 mA 20% 10% 10% 10% 10%
6.3V 2
CERM 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 50V
CERM
10 Mbps: 108 mA 10 Mbps: 30 mA 603 402 402 402 402
100 Mbps: 126 mA 100 Mbps: 40 mA
1000 Mbps: 218 mA 1000 Mbps: 150 mA
8A4 =YUKON_EC_PP2V5_ENET
Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps
NC_32 32
NC_51 51
NC_52 52
NC_57 57
NC_64 64
AVDD0 19
AVDD1 22
AVDD2 23
AVDD3 28
VDDO_TTL1 40
VDDO_TTL2 45
VDDO_TTL3 61
VDD2 13
VDD3 33
VDD4 39
VDD5 44
VDD6 48
VDD7 58
Yukon Ultra: Alias to GND
VDDO_TTL0 1
AVDDH 8
VDD0 2
VDD1 7
R37601
4.7K
5%
1/16W
MF-LF
C3735
C
402 2
C PCIE_ENET_D2R_P
23C5
1 2 EC:AVDD 2.5V
OUT
10% 16V X5R 402
0.1UF PCIE_ENET_D2R_C_P 49 TX_P LOM_DISABLE* 10 ENET_LOM_DIS_L
PCIE_ENET_D2R_N C3736 1 2 PCIE_ENET_D2R_C_N CRITICAL
23C5 OUT 50 TX_N
10% 16V X5R 402 VAUX_AVLBL 12
PLACEMENT_NOTE=Place C3730 close to southbridge. 0.1UF
PCIE_ENET_R2D_C_P C3730 1 2 U3700 SWITCH_VAUX 9 NC
Must be high in S0 state (can use PP3V3_S0 as input)
23C5 IN
0.1UF 10% 16V X5R 402
PCIE_ENET_R2D_P 54 RX_P
88E8058 47 =ENET_VMAIN_AVLBL
VMAIN_AVLBL IN 8A3
QFN
23C5 IN PCIE_ENET_R2D_C_N C3731 1 2 PCIE_ENET_R2D_N 53 RX_N SWITCH_VCC 11 NC
10% 16V X5R 402
0.1UF ANALOG
PLACEMENT_NOTE=Place C3731 close to southbridge. EC:CTRL25 CTRL18 4 TP_YUKON_CTRL18 OUT
PCI EXPRESS
CTRL12 3 TP_YUKON_CTRL12 OUT
29B3 IN PCIE_CLK100M_ENET_P 55 REFCLKP
29B3 IN PCIE_CLK100M_ENET_N 56 REFCLKN RSET 16 YUKON_RSET
=ENET_CLKREQ_L Yukon EC: Pin 42 should be NC (or TP) net. YUKON_ULTRA
28A4 8C4 OUT 42 CLKREQ* EC:NO CONNECT
LED_ACT* 59 NC 1
R3765
33C5 24C8 OUT PCIE_WAKE_L 6 WAKE* LED_LINK10/100* 60 NC 4.99K
LED 1%
ENET_RESET_L LED_LINK1000* 62 NC 1/16W If characterization shows eye height is
27C1 IN 5 PERST* MF-LF too small, make R3765 smaller
LED_DUPLEX* 63 NC 2 402
74B3 36B7 BI ENET_MDI_P<0> 17 MDIP0

ENET_MDI_N<0> (IPU) SPI_DO 34 NC
74B3 36B7 BI 18 MDIN0
(IPU) SPI_DI 35 NC
SPI
ENET_MDI_P<1> (IPU) SPI_CLK 37 NC
74B3 36C7 BI 20 MDIP1
ENET_MDI_N<1> (IPU) SPI_CS 36 NC
74B3 36C7 BI 21 MDIN1
MEDIA YUKON_VPD_CLK
(IPU) VPD_CLK 38
74B3 36B7 BI ENET_MDI_P<2> 26 MDIP2 TWSI
(IPU) VPD_DATA 41 YUKON_VPD_DATA
74B3 36C7 BI ENET_MDI_N<2> 27 MDIN2
(IPD) TESTMODE 46
B
74B3 36C7
74B3 36C7
BI
BI
ENET_MDI_P<3>
ENET_MDI_N<3>
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
30 MDIP3
31 MDIN3 TEST/RSVD RSVD_24
RSVD_25
24
25
NC
NC
VPD ROM B
1
R3740 1
R3741 1
R3742 1
R3743 1
R3744 R3745 1 1
R3746 1
R3747 ENET_CLK25M_XTALI 15 XTALI RSVD_29 29 NC
MAIN CLK
1%
49.9 49.9
1% 1%
49.9 49.9
1% 1%
49.9 49.9
1% 1%
49.9 49.9
1%
CRITICAL ENET_CLK25M_XTALO 14 XTALO RSVD_43 43 NC 1 C3780 R37801 1
R3781
THRML_PAD 0.1UF 4.7K 4.7K
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF Y3750 10% 5% 5%
SM-3.2X2.5MM 2 16V 8
65
2 402 402 2 2 402 402 2 2 402 402 2 2 402 402 2
25.0000M X5R 1/16W 1/16W
402 VCC MF-LF
402 2
MF-LF
ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3 3 1 3 E2 2 402
16pF NC 2 NC1 OMIT SDA 5

NC0 U3780 SCL
4 2
1
C3740 1
C3742 1
C3744 1
C3746 C3750 1 1 C3751 NC 1
6
M24C08
NC
NC
0.001UF 0.001UF 0.001UF 0.001UF 15PF 15PF
10%
50V
10%
50V
10%
50V
10%
50V
5%
50V
5%
50V
7 WC* SO8
2 CERM 2 CERM 2 CERM 2 CERM CERM 2 2 CERM
CRITICAL
402 402 402 402 402 402
VSS
4
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

114S0285 1 RES,4.87K,1%,1/16W,0402,LF R3760 YUKON_EC
To support Yukon EC and Ultra on the same board:

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps
-
-
Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY
Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)
Ethernet (Yukon)
A - Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part SYNC_MASTER=USB
A
APPLE INC.
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PP3V3_ENET_FET
ENET Enable Generation 1.9V ENET LDO

35D4 7B6
D D
"ENET" = "S0" || AC 1
R3823 U3820
3.3V ENET FET 15K
5%
1/16W
MF-LF 7A4 =PP3V3_ENET_P3V3ENETFET
LREG_TPS79501DRB
1 IN1
SON
OUT1 3 =PP1V9_ENET_REG 7B4
35B2
2 402 2 IN2 CRITICAL OUT2 4
CRITICAL PP1V9_ENET_EN 8 EN 5 1
R3821
Q3810
NR/FB
C38221 16.9K
1.8A GND THRM_PAD NC 27PF
NTR4101P 0.085ohm 50V
5%
1%
1/16W
SOT-23 1
R3824 C3820
CERM
402 2 MF-LF
C3823
7
1 2 402 1
PP3V3_ENET_FET 7B6 35D4
5%
33K 1UF NC 10UF
7A4
=PP3V3_S3_ENETPWRCTL 2 S D 3 1/16W 10% 20%
MF-LF 2 6.3V
CERM
PP1V9_S3_FB 2 6.3V
X5R
2402 402 1 603
1
1 C3811 G
R3822
R3801 0.033UF 1%
30.1K
100K 10% 1 1/16W
5% 2 16V
X5R
NOSTUFF MF-LF
1/16W
MF-LF R3810 402 C3810 2 402
2 402 10K 0.01UF
35A3 PM_ENET_EN_L 1 2 P3V3ENET_SS 2 1
5%
1/16W 10%
MF-LF 16V
Q3801 D 3
402 CERM
402 Vout = 1.2246V * (1 + R3821 / R3822)
SSM6N15FE
Q3801 D 6 SOT563
SSM6N15FE
SOT563
5 G S 4
2 G S 1
C C
PM_SLP_S3_L PM_ENET_WOL_EN_L
1.2V ENET LDO

62B8 58B7 45A6 44C5 33C7 24D3 IN
57C4 45B3 44D5 38C6 33C7 6C1 IN SMC_ADAPTER_EN

=PP3V3_S5_SB
26D8 24A8 24A3 7D1
CRITICAL
1
R3802 Q3802 D 6
U3830
100K SSM6N15FE 7B4
=PP1V8_ENET_P1V8ENETFET 2 IN0SOP OUT0 8 =PP1V2_ENET_REG 7B6
SOT563
3 9
MAX8516
5%
1/16W
MF-LF
IN1 OUT1 1
R3830
2402
2 G
35B2 PP1V2_ENET_EN 1 EN FB 7 5.11K
1%
S 1
1/16W
24B3
WOL_EN 1 C3830
22UF
1 C3831
4
5
NC0 MF-LF
2 402 1 C3832
20% 4.7UF NC1
4.7UF
20% 10 NC2 PP1V2_S3_FB
2 6.3V
CERM 2 6.3V 20%
805 CERM
603 GND
THRML
PAD 2 6.3V
CERM
1
R3831 603
11
3.65K
1%
1/16W
MF-LF
2 402
Name PM_SLP_S3_L SMC_ADAPTER_EN PM_ENET_EN_L PM_ENET_EN Yukon Power

Logic S0 AC Powered by S3
S0 on Battery High (3.3V) Low (0V) Low (0V) High (3.3V) Power
B S3 on Battery Low (0V) Low (0V) High (3.3V) Low (0V) Power
B
35D1 7B4 =PP1V9_ENET_REG
S0 on AC High (3.3V) High (3.3V) Low (0V) High (3.3V) Power
S3 on AC Low (0V) High (3.3V) Low (0V) High (3.3V) Power
S5 on anything N/A N/A N/A N/A No Power
1
R3832
100K
5%
1/16W
MF-LF
2 402
PP1V2_ENET_EN
35B3
Q3802 D 3
SSM6N15FE
SOT563
5 G S 4
35C6 PM_ENET_EN_L
Yukon Power Control

A SYNC_MASTER=USB
A
APPLE INC.
D 051-7559 H
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NONE 38 106
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D D
L3950
FERR-120-OHM-1.5A PLACE ONE PAIR OF CAPS AT EACH PIN 3 AND 6 OF TRANSFORMERS
7B3 =PP1V8_S0_YUKON
1 2 PP1V8_S0_YUKON_AVDD
0402-LF
1 C3900 1 C3904 1 C3901 1 C3905 1 C3902 1 C3906 1 C3903 1 C3907

0.1UF
10%
0.001UF
10%
0.1UF
10%
0.001UF
10%
0.1UF
10%
0.001UF
10%
0.1UF
10%
0.001UF
10% ETHERNET CONNECTOR
2 50V
16V
2 X5R
16V
2 X5R
50V
2 CERM 2 16V 2 50V
16V
2 X5R 2 50V
CERM X5R CERM CERM
402 402 402 402 402 402 402 402
OMIT
CRITICAL CRITICAL
R3911 T3901 J3900
ENET_MDI_P<1> 1 2
0 1
ENET_MDI_R_P<1> SM 12 ENET_MDI_TRAN_P<1>
RJ45-M71
74B3 34B8
IO 5%1/16W MF-LF
402 F-RT-TH
74B3 34B8 ENET_MDI_N<1>
R3910
1 2
0 2
ENET_MDI_R_N<1> 11 ENET_MDI_TRAN_N<1>
9
SYM_VER-1
IO
5%1/16W MF-LF
402
3 10 ENET_CENTER_TAP<1> 1
R3903
2 75
1
2
TX 1% 1/16W MF-LF
402 3
TLA-6T213LF R3902
2 75
4
C R3909
4 9 ENET_CENTER_TAP<3> 1
1% 1/16W MF-LF
402
5
6 C
74B3 34B8
IO ENET_MDI_P<3> 1 2 0 5
ENET_MDI_R_P<3> 8 ENET_MDI_TRAN_P<3> 7
5%1/16W MF-LF
402

R3908
1 2 0 6
8
IO 5%1/16W MF-LF
402 RX 10
CRITICAL
514-0443
R3907 T3902
SM ENET_MDI_TRAN_N<2>
74B3 34B8
IO ENET_MDI_N<2> 1 2 0 1
ENET_MDI_R_N<2> 12
5%1/16W MF-LF
402
74B3 34B8 ENET_MDI_P<2>

R3906
1 2 0 2
ENET_MDI_R_P<2> 11 ENET_MDI_TRAN_P<2>
IO
5%1/16W MF-LF
402
3 10
R3901
ENET_CENTER_TAP<2> 1 2 75
TX
1% 1/16W MF-LF
402
4 02
4
TLA-6T213LF
9
R3900
ENET_CENTER_TAP<0> 1 2 75
1% 1/16W MF-LF
402

R3905
1 2 0 5
IO 5%1/16W MF-LF
402
74B3 34B8 ENET_MDI_P<0>

R3904
1 2
0 6
ENET_MDI_R_P<0> 7 ENET_MDI_TRAN_P<0>
IO
5%1/16W MF-LF
402 RX
ENET_BOB_SMITH_CAP
CRITICAL
1 C3910
B 1000PF
10%
2KV
2 CERM
B
1206 8C8 =GND_CHASSIS_RJ45
OUT
PLACE C3911 AND C3912 1 C3911 1 C3912

ON EACH SIDE OF J3900 0.001UF
10%
0.001UF
10%
2 50V
CERM 2 50V
CERM
402 402
TABLE_5_HEAD

TABLE_5_ITEM
514-0443 1 CONN,8P RJ-45 JACK,TH,MG3,LF J3900 CRITICAL NORMAL

TABLE_5_ITEM
514-0475 1 CONN,8P RJ-45 JACK,TH,BLACK,LF J3900 CRITICAL FANCY
ETHERNET CONNECTOR
A SYNC_MASTER=USB

A
APPLE INC.
D 051-7559 H
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NONE 39 106
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PAGE NOTES
MOBILE TURNS OFF CONTROLLER POWER DURING SLEEP
INPUT 0.001A DURING SLEEP
=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP) =PP3V3_S3_FW
7A4
PCI_GNT3_L - PCI GRANT FROM SB
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE PLACE ONE CAP PER TWO PINS STARTING WITH C4024 ON VDD0
PCI_RST_L - PCI RESET FROM SB
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER 1 C40241 C40181 C4022 1 C4026 1 C4028 1 C4030 1 C4032
10UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
0.1UF
20%
INPUT/OUTPUT
D PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
2 6.3V
X5R
603
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402
2 10V
CERM
402 D
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS
600-OHM-300MA
L4000 PLACE ONE CAP PER TWO PINS STARTING WITH C4016 ON VDDA0
OUTPUT
PCI_REQ3_L - PCI REQUEST TO SB 1 2 PP3V3_S3_FW_AVDD
0402 VOLTAGE=3.3V
PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL
INT_PIRQD_L - INTERRUPT TO SB
1 C4016
10UF
1 C4017 1 C4029 1 C4025
0.1UF 0.1UF 0.1UF
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1) 20% 10% 10% 10%
2 6.3V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
603 402 402 402
PAGE HISTORY
5/19/2005 - FIRST REVISION OF PAGE
6/20/2005 - BGA VERSION OF FW323-06 ADDED
6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)
6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)
6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE =PP3V3_S3_PCI
6/22/2005 - REMOVED C4421 - REDUNDANT 7A4
6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE
7/26/2005 - CONNECTED PIN E10 TO GND
197S0030 3.2MMX2.5MM
L13
H13
D10
A13
B13
A7
A8
D6
G4
N1
N2
K5
K6
K7
A2
CRITICAL
Y4003
R4000 SM-3.2X2.5MM
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD9
VDDA0
VDDA1
VDDA2
VDDA3
VDDA4
VDDA5
390 24.576MHZ
1 2 FW_XO_R 1 3
G13
CONNECT TO VDD FOR 3.3V OPERATION 5%
PCI_VIOS 1/16W 2 4
MF-LF
PCI_AD<0> F10 402 C4011 1 1 C4012
C
74D3 23B8
C
IO PCI_AD0
IO 74D3 23B8 PCI_AD<1> G10 PCI_AD1
15PF 5% 5%
15PF
IO
74D3 23B8 PCI_AD<2> H10 PCI_AD2 CRITICAL XI A5 FW_XI 50V
CERM 2 2 50V
CERM
PCI_AD<3> 402 402
IO 74D3 23B8
PCI_AD<4>
H12
J13
PCI_AD3
U4000 B5 FW_XO
IO 74D3 23B8
74D3 23B8 PCI_AD<5> J12

PCI_AD4
FW32306 XO
NEED TO CHECK CRYSTAL LOAD CAPACITANCE
IO
74D3 23B8 PCI_AD<6> K13
PCI_AD5 BGA
IO PCI_AD6
IO 74D3 23B8 PCI_AD<7> K10 PCI_AD7 RESET* B4 FW_PWRON_RST_L
IO 74D3 23B8 PCI_AD<8> L12 PCI_AD8
1 C4020 1
IO 74D3 23B8 PCI_AD<9>
PCI_AD<10>
M13 PCI_AD9
FW_R1
1
R4052 0.1UF R4020
IO 74D3 23B8 L11 PCI_AD10 A6 R1 2.1K 10% 510K
5%
IO
74D3 23B8 PCI_AD<11> M12 PCI_AD11 SPEC RECOMMENDS 2.49K 1% 2 16V
X5R 1/16W
PCI_AD<12> FW_R0 1/16W 402 MF-LF
IO 74D3 23B8 M11 PCI_AD12 R0 B7 MF-LF 2402
74D3 23B8 PCI_AD<13> N12 2 402
IO PCI_AD13
IO 74D3 23A8 PCI_AD<14> M10 PCI_AD14 B8 FW_A_TPBIAS
IO 74D3 23A8 PCI_AD<15> N11 PCI_AD15
TPBIAS0
A9
38C6
FW_A_TPA_P
IO
IO
74D3 23A8 PCI_AD<16> M4 PCI_AD16
TPA0_P
B9
38B6
FW_A_TPA_N
IO
IO
74D3 23A8 PCI_AD<17> N5 PCI_AD17
TPA0_N
B10
38B6
FW_A_TPB_P
IO
IO 74D3 23A8 PCI_AD<18> N4 PCI_AD18

TPB0_P
A10
38B6
FW_A_TPB_N
IO
IO
74D3
23A8 PCI_AD<19> M3 PCI_AD19
TPB0_N
D8
38B6
FW_B_TPBIAS
IO
IO
74D3 23A8 PCI_AD<20> M2 PCI_AD20
TPBIAS1
A11
8D2
FW_B_TPA_P
IO
IO
74D3 23A8 PCI_AD<21> N3 PCI_AD21
TPA1_P
B11
8D2
FW_B_TPA_N
IO
IO
74D3 23A8 PCI_AD<22> K4 PCI_AD22
TPA1_N
B12
8D2
FW_B_TPB_P
IO
IO 74D3 23A8 PCI_AD<23> M1 PCI_AD23

TPB1_P
A12
8D2
FW_B_TPB_N
IO
IO
74D3 23A8 PCI_AD<24> K2 PCI_AD24
TPB1_N
C13
8D2
FW_C_TPBIAS
IO
IO
74D3 23A8 PCI_AD<25> J4 PCI_AD25
TPBIAS2
C11
8D2
FW_C_TPA_P
IO
IO 74D3 23A8 PCI_AD<26> K1 PCI_AD26

TPA2_P
C12
8D2
FW_C_TPA_N
IO
B PCI_AD<27> B
8D2
J2 TPA2_N IO
IO
74D3 23A8
PCI_AD<28> J1
PCI_AD27
TPB2_P D13 8D2 FW_C_TPB_P IO
IO
74D3 23A8
74D3 23A8 PCI_AD<29> H2

PCI_AD28
TPB2_N D12 8D2 FW_C_TPB_N IO
IO PCI_AD29
IO
74D3 23A8 PCI_AD<30> H4 PCI_AD30
IO
74D3 23A8 PCI_AD<31> H1 PCI_AD31
IO
74D3 23B6 PCI_C_BE_L<0>
K12 PCI_CBE0*
IO
74D3 23B6 PCI_C_BE_L<1>M9 PCI_CBE1*
IO
74D3 23B6 PCI_C_BE_L<2>L3 PCI_CBE2*
IO
74D3 23B6 PCI_C_BE_L<3>L1 PCI_CBE3*
IO 74D3 23A6 PCI_PAR N10 PCI_PAR MODE_420 M5 MODE FOR EXTERNAL LINK
R40311
IO 74D3 23A6 23A4 PCI_FRAME_L N6 PCI_FRAME* MODE_A B6
22 IO 74D3 23A6 23A4 PCI_IRDY_L M6 PCI_IRDY*
5%
1/16W IO 74D3 23A6 23A4 PCI_TRDY_L N7 PCI_TRDY* PC0 E12 38C8 FW_PC0IO
MF-LF PCI_DEVSEL_L N8 DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)
4022 IO 74D3 23A6 23A4
PCI_DEVSEL* PC1 F13
PCI_STOP_L SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)
IO 74D3 23A6 23A4 M7 PCI_STOP* PC2 F12
FW_PCI_IDSEL L2 PCI_IDSEL CONTENDER G12 LOW = NOT BUS MANAGER
B1 LOW = PCI OPERATION
OUT
74D3 23B6 23A4 PCI_FW_REQ_L E2 PCI_REQ*
CARDBUSN
E10
IN 74D3 23B5 PCI_FW_GNT_L E1 PCI_GNT*
MPCI_ACTN_323
IO 74D3 23A6 23A4 PCI_PERR_L M8 PCI_PERR* TEST0 C2 FW_TEST0

IO 74D3 23A6 23A4 PCI_SERR_L N9 PCI_SERR* TEST1 C1 FW_TEST1
PCI_CLK33M_FWG2
MANUFACTURING TEST PINS
PTEST A4 FW_PTEST 1
FW_SE R4036 R4037
75B3 29B3 29A5
IN PCI_CLK A3 1
R4032 PM_CLKRUN_L D1 SE 47
FIREWIRE CONTROLLER
46B6
100
IO 44C5 24C8 6C2
CLKRUN*
SM B3 FW_SM 1
R4035 47 5%
1/16W
PCI_RST_L1 2 FW_PCI_RST_L F1 47
5%
1/16W MF-LF
R4034
23A6 1
IN PCI_RST*
INT_PIRQD_L D2 1
R4033 5% MF-LF 2402 SYNC_MASTER=ENETSYNC_DATE=08/30/2005
A
74C3
1% 1/16W 402
A
23A8 23A4
1/16W OUT PCI_INTA* 47 2
MF-LF 24C5 24A5 PCI_PME_FW_L F2 PCI_PME*
47
5%
5%
1/16W
MF-LF
2 402
402 OUT
1/16W MF-LF NOTICE OF PROPRIETARY PROPERTY
THIS IS FROM ICH-8 MF-LF 2 402
PLACE R4032 VERY CLOSE TO SB PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSSA0
VSSA1
VSSA2
VSSA3
VSSA4
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

A1
B2
C3
D4
E4
E5
F4
F6
F7
F8
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
K8
K9
N13
E13
E9
D9
D7
D5
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 40 106
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Page Notes
INPUT:
PPBUS_S5_FWPWRSW_F
=PPBUS_FW - PORT POWER VOLTAGE=18.5V
=PP3V3_S5_FW - DIGITAL POWER
MIN_NECK_WIDTH=0.25MM CRITICAL PPFW_SWITCH Cable Power
Q4390
6B2
=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND VOLTAGE=19V
=FWPWR_PWRON - ADDITIONAL POWER CONTROL
CRITICAL MIN_LINE_WIDTH=0.5MM PPFW_PORT0_VP_F
PPFW_PORT0_VP
FL4390 FDC638P MIN_NECK_WIDTH=0.25MM VOLTAGE=16.5V
L4310 VOLTAGE=16.5V
1.1A-24V
SM-LF
D4390
SM
FERR-250-OHM
INPUT/OUTPUT: 7B1 =PPBUS_S5_FWPWRSW
1 2 6
1 2 1 2
5
D
FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS
MINISMDC 4
2
CRS08
SM
D
OUTPUT: 1 CRITICAL 1 C4310
FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW) 0.001UF
10%
R43901 1 C4390 3 2 50V
CERM
4.7K
PAGE HISTORY 5%
1/16W
0.01UF
10%
402
25V
MF-LF 2 X7R
5/19/05 - INITIAL REVISION 402 2 402
6/22/05 - CHANGED DIFF PAIR NAMES TO MATCH REUSE
6/22/05 - REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER FWPWR_EN_L_DIV
6/22/05 - CONNECTED FW_PC0 FOR SINGLE PORT MIN_LINE_WIDTH=0.15MM
7/26/05 - UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1 MIN_NECK_WIDTH=0.15MM
7/26/05
7/26/05
-
-
CHANGED CONNECTOR PORT NAMING TO PORT0
SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR
Enables port power whenever
7/26/05 - REMOVED R4520 - IT HASN’T BEEN STUFFED FOR MANY PRODUCTS machine AC Adapter is plugged
7/26/05
7/26/05
-
-
CHANGED FL4590 TO 1.1A VERSION
REMOVED ETHERNET LOW-POWER MODE CIRCUIT or system at run state with battery only R43911
7/26/05 - UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE 3.3K
5%
1/16W
CRITICAL MF-LF
D4391 402 2
HN2D01JEF FWPWR_EN_L
SOT665
R4394
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03) SMC_ADAPTER_EN
1
10K 2 FWPWR_ACIN 1 5 Q4392 D 6
45B3 44D5 35C7 33C7 6C1
57C4
5%
SSM6N15FE
SOT563
1/16W
MF-LF 3 4
402 "Snapback" & "Late VG" Protection
=PP3V3_S0_FW NC
2
NC FWPWR_EN 2 G S 1
7D4
FWPWR_EN_AND
R4395 Q4392
1
D 3
470K SSM6N15FE
5%
1/16W SOT563
C PORT POWER CLASS
MF-LF
2 402 C
5 G S 4
0 FOR SINGLE PORT
1 FOR DUAL PORT 38A4 FW_PORTPWR_EN
37A3
OUT
FW_PC0
[LATE VG NOTES]
38A7 PP2V4_FWLATEVG
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
CRITICAL CRITICAL
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A 0.5V DROP D4320 D4320
IO
37B3 FW_A_TPBIAS BAV99DW-X-F BAV99DW-X-F
C4320
0.01UF
1
5
SOT-363
C4321
0.01UF
1
2
SOT-363
1 1
1 C4300 10%
16V 3
10%
16V 6 CRITICAL 1394A
R4300 R4301 0.33UF CERM 2
402
CERM 2
402 PORT 0
56.2
1%
56.2
1%
10%
2 6.3V
CERM-X5R
4 1 FL4320 OMIT
CRITICAL
1/16W
MF-LF
1/16W
MF-LF 402 TCM2010-100-4P
2 402 2 402
FW_PORT0_TPA_P SM J4300
1 8 1394A
F-RT-TH3
FW_PORT0_TPA_N
37B3 FW_A_TPA_P FW_PORT0_TPA_P_FL 6 (TPA+)
IO TPO
37B3 FW_A_TPA_N 2 7 FW_PORT0_TPA_N_FL
IO 5 (TPA-)
IO 37B3 FW_A_TPB_P TPO#
37B3 FW_A_TPB_N 3 6 FW_PORT0_TPB_P_FL 4
(TPB+)
IO
FW_PORT0_TPB_P TPI
FW_PORT0_TPB_N_FL 3
TPI# (TPB-)
4 5
1
1
R4303 FW_PORT0_TPB_N 1
VP
R4302 56.2 CRITICAL CRITICAL
56.2 1% D4321 D4321 (PPFW_PORT0_VP) 2
VGND
B
1%
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
BAV99DW-X-F
SOT-363
BAV99DW-X-F
SOT-363 (GND_FW_PORT0_VGND) B
2 5 7 8 514-0456
FW_PORT0_TPB
1
R4304
C4322 1 6
C4323 1 3
1 C4324 C4325 1
1 C4301 0.01UF
10%
1 0.01UF
10%
4 0.01UF
10%
0.01UF
10%
=GND_CHASSIS_FW_UPPER 8A6
220PF 4.99K 16V 16V
5% 1% CERM 2 CERM 2 2 50V
X7R
16V
CERM 2
1/16W 402 402 603-1
2 25V
CERM MF-LF 402
402 2 402 =GND_CHASSIS_FW_DOWN 8C8
LATE-VG DETECTION CIRCUIT

=PP3V3_S5_FWLATEVG
R4350
38A8 7D1 TABLE_5_HEAD

330
38A6 7D1 =PP3V3_S5_FWLATEVG1 2 38C5 PP2V4_FWLATEVG
VOLTAGE=3.3V
1 C4354
0.1UF 514-0456 1 CONN,6P 1394A RCPT,MIDPLANE,MG3,LF J4300 CRITICAL NORMAL
TABLE_5_ITEM
5%
1/16W
MF-LF
402
NO STUFF
R4351
1 R4352
10K
1 10%
2 16V
X5R
R4356
1
2.0M
514-0476 1 CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF J4300 CRITICAL FANCY
TABLE_5_ITEM
10K
3
1 C4352 CRITICAL 5%
1%
1/16W
402 5%
1/16W
0.001UF CRITICAL
10%
50V D4350
SOT23
1/16W
MF-LF
2402
MF-LF
2402 U4350
MF-LF
2402
D4351
2 CERM 2
402 MMBZ5227B 4
PP2V4_FWLATEVG_RC TLV7211
1
- SC70 1SS418 FIREWIRE PORT

TABLE_ALT_HEAD
V+ PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

1 PART NUMBER
LATEVG_EVENT_L 1 2 FW_PORTPWR_EN 38C5
A
3
FWLATEVG_3V_REF
TABLE_ALT_ITEM
+
NC
V-
5
SOD-723
155S0369 155S0326 ? FL4320 MURATA ALTERNATIVE SYNC_MASTER=GPU

A
1 C4353
100PF R4353
1 6 PLACEHOLDER FOR SMALL PACKAGE DIODE
1 C4355 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5% 80.6K 0.33UF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1% AGREES TO THE FOLLOWING
2 50V
CERM 1/16W 10%
MF-LF 2 6.3V
402
2402 R4354
200K
CERM-X5R
402
1 2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1%
1/16W SIZE DRAWING NUMBER REV.
MF-LF
402
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 43 106
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D D
CRITICAL
Q4410
FDC606P
7C1 =PP5V_S5_PATA SOT-6 6
5 PP5V_S0_IDE_PATA
MAKE_BASE=TRUE
4 2 VOLTAGE=5V
D
R4465
1 1
=PP5V_S0_IDE_PATA
6.2K 1 C4477 39A5

=PP3V3_S0_PATA 7D4
G
=PP3V3_S0_SB
5%
1/16W 0.1UF
10%
MF-LF
2 16V 3
26D8 7D4
2402 X5R NOSTUFF
R4425
402
C4476 NOSTUFF
10K
ODD_PWR_EN_SLOW_START_L 0.1UF R4420
1
100K
R44241
1 2 1 2 10K
R4476
1 5% 5%
10K Q4475 D 3 5%
1/16W
ODD_PWR_EN_SLOW_START_L_R
10%
16V
1/16W
MF-LF
1/16W
MF-LF CRITICAL
5%
1/16W
MF-LF
SSM6N15FE
SOT563
MF-LF
402 X5R
402
2402 4022
J4401
2 402
Per ATA Spec
R4451
1
5-1775184-1
M-ST-SM R4453
1
4.7K
51 NC 33K
R4477
330 5 G S 4 5%
1/16W
5%
1/16W
MF-LF
ODD_PWR_EN_SLOW_START
1 2 ODD_PWR_EN_SLOW_START_R MF-LF NC 2 1 NC 2402
2 402
C Q4475 D 6
5%
1/16W
MF-LF
402 1 C4475 39A7 ODD_RST_BUF_L
NC 4
6
3
5 IDE_PDD<8> 22B4 73D3 C
SSM6N15FE 0.47UF 73D3 22B4 IDE_PDD<7> 8 7 IDE_PDD<9> 22B4 73D3
SOT563
10% 22B4 IDE_PDD<6>
10 9 IDE_PDD<10> 22B4 73D3
2 6.3V
73D3
CERM-X5R 22B4 IDE_PDD<5>
12 11 IDE_PDD<11> 22B4 73D3
402 73D3
both pull up resistors 2 G S 1 73D3 22B4 IDE_PDD<4>

14 13 IDE_PDD<12> 22B4 73D3
on SB page. ODD_PWR_CORE 22B4 IDE_PDD<3>
16 15 IDE_PDD<13> 22B4 73D3
R4401
73D3
22B4 IDE_PDD<2>
18 17 IDE_PDD<14> 22B4 73D3
ODD_PWR_EN_L 0 1 2
73D3
73D3 22C4 IDE_PDD<1>

20 19 IDE_PDD<15> 22B4 73D3
ICH8 GPIO5
23A6 23A4
5% 73D3 22C4 IDE_PDD<0>

22 21 73D3 22A4 IDE_PDDREQ This signal has integrated series resistor and pull down in ICH8M
OUT
1/16W 24 23
MF-LF IDE_PDIOR_L 22B4 73D3
402 ODD_PWR_EN_L_R 39A6
26 25
73D3 22B4 IDE_PDIOW_L
ODD_PWR_RESUME IDE_PDIORDY 28 27 IDE_PDDACK_L 22B4
R4402
0
73D3 22A4
73D3 22B4
OUT
OUT IDE_IRQ14 30 29 SMC_ODD_DETECT

73D3
Indicates disk presence, to SMC
23C8
SB_GPIO40 1 2 73D3 22B4 IDE_PDA<1> 32 31 NC
5% IDE_PDA<0> 34 33 IDE_PDA<2> 22B4 73D3
1/16W NOSTUFF 73D3 22B4
MF-LF 22B4 IDE_PDCS1_L
36 35 IDE_PDCS3_L 22B4 73D3
402 C4404 1 73D3
NC38 37
CORE RAIL 5V 10PF 5% 40 39
ODD detect need less than 100ms include OS latency 50V
CERM 2
402
42 41
ODD_PWR_EN_L is OD and core well 44
46
43
45
IDE_CSEL_PD 48 47
50 49 NC
NC
52 NC
B 516S0339 B
1
R4458 R4459
1
=PP5V_S0_IDE_RESET
0 6.2K
7A7 5% 5%
1/16W 1/16W
MF-LF MF-LF
2402 2402
PER ATA SPEC PER ATA7 SPEC
1
R4460
100K
5% 39C4 =PP5V_S0_IDE_PATA
1/16W CRITICAL
MF-LF
2402 5 MC74VHC1G09
1
B SC70
4 ODD_RST_BUF_L
R4461
24.9K2ODD_PWR_EN_L_B
6
Q4420
2
U4401Y 39C5
39C7 ODD_PWR_EN_L_R
1 2
MMDT3904XF
23B6 ODD_RST_5VTOL_L A
73D3
1% SOT-363-LF
ICH8 GPIO54 3 1/16W
MF-LF
402
1
ODD_POWER_DISCHARGE
R4462
1
4.7
5%
1/16W
MF-LF
PATA CONNECTOR
A 2 402
A
BLEED CIRCUIT TO DISCHARGE ODD POWER RAIL WHEN ODD IS DISABLED. AGREES TO THE FOLLOWING
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 44 106
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SATA CONNECTOR
PLACE L4501 NEAR J4501 VALUE=3900PF IN REFERENCE SCHEM
CRITICAL
518S0390 L4501 C4503
CAPS TO BE SAME DISTANCE
D 90-OHM-100MA
1210-4SM1 SATA_A_R2D_F_P 1 2
FROM SB WITHIN EACH PAIR
73D3 22B6 SATA_A_R2D_C_P
IN
D
CRITICAL 2 3
J4501 SATA_A_R2D_F_N
0.0047UF
402 C4501
1 2 SATA_A_R2D_C_NIN
20247-019E
F-ST-SM 1 4
73D3 22B6
20 0.0047UF
PLACE NEAR ICH8 PIN
SYM_VER-1
402
1 CRITICAL
2
3
73D3
73D3
SATA_A_R2D_P
SATA_A_R2D_N C4500 L4502
90-OHM-100MA
22B6
SATA_RBIAS_N
OUT
1 2 SATA_A_D2R_F_N 1210-4SM173D3 22B6 SATA_A_D2R_N SATA_RBIAS_PN
4 OUT
2 3 MAKE_BASE=TRUE 22A6
SATA_RBIAS_P
5
6
73D3 SATA_A_D2R_C_N
SATA_A_D2R_C_P
0.0047UF
402 C4502
1 2 SATA_A_D2R_F_P SATA_A_D2R_P
OUT
R4501
73D3 73D3 22B6
OUT 1
7 1 4
8 =PP5V_S0_SATA 7A7
0.0047UF
402
SYM_VER-1 24.9
1%
9 1/16W
NC NOSTUFF NOSTUFF MF-LF
10 2402
11
1 C4520
0.1UF
C4521
10UF
1 PLACE L4502 NEAR SB
12 10% 20%
13 2 16V
X5R 2 6.3V
X5R
402 603 0
14
15
16
17 NC
18 NC
19 NC
C 21 SYSTEM (SLEEP) LED FILTER C

SATA DIFF PAIR GND VIAS
R4522
10
8C7 GND_CHASSIS_SATA
SYS_LED_ANODE_L 1 2 SYS_LED_ANODE 6B2 45A3 GV4501
HOLE-VIA-P5RP25
GV4502
HOLE-VIA-P5RP25
5%
1 C4522 1/16W
MF-LF
0.01UF 402
1 1
10% GV4503
HOLE-VIA-P5RP25 GV4504
2 16V
CERM 1 HOLE-VIA-P5RP25
IR_RX_OUT 43C8 402 PLACE R4522 AND C4522 NEAR J4501 1
GV4505
HOLE-VIA-P5RP25
GV4506
HOLE-VIA-P5RP25
1 1
(TO IR RECEIVER) R4550
100
PP5V_S3_SYSLED_F 1 2 =PP5V_S3_SYSLED 7A4 45A4 GV4507
HOLE-VIA-P5RP25
GV4508
HOLE-VIA-P5RP25
5%
1/16W 1 1
1 C4550 MF-LF
402
4.7UF
20% PLACE R4550 AND C4550 NEAR J4501
2 6.3V
CERM
603 0
B B
SATA CONNECTOR
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 45 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
USB 2.0 CONNECTORS

PP5V_S3_USB2_EXTA_F
L4602
FERR-120-OHM-1.5A
41D2
VOLTAGE=5V
1 2
D PART NUMBER ALTERNATE FOR

PART NUMBER
TABLE_ALT_HEAD
0402-LF
D
TABLE_ALT_ITEM
155S0310 155S0322 ? L4600,L4601,L4701,L4812,L4855 MURATA ALTERNATIVE
OMIT
PLACE L4600 NEAR J4600 CRITICAL
ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS J4600
USB-M71-MG3
F-RT-TH
CRITICAL
L4600 L4600 Monitor SMT for tombstone
90-OHM-100MA
5
TCM1005
SYM_VER-1 41D3 PP5V_S3_USB2_EXTA_F 1 VBUS
41A5 USB2_MUXED_EXTA_N 1 4 USB2_EXTA_F_N 2 D-
USB2_EXTA_F_P 3 D+
7C1 =PP5V_S5_USB
USB2_MUXED_EXTA_P 2 3 USB2_GND_EXTA_F 4 GND
41A5
1 C4613 1 C4612 L4604

FERR-120-OHM-1.5AMIN_LINE_WIDTH=0.6MM 6
10uF 0.1UF MIN_NECK_WIDTH=0.3MM
20%
6.3V
20%
10V
1 2 VOLTAGE=0V 1 C4602 1 C4603 514-0457
2 X5R 2 CERM
CRITICAL 0402-LF 0.01UF 0.01UF
603 402
OMIT
D4600
SC-75
10%
2 16V
CERM
402
10%
2 16V
CERM
402
CRITICAL 1
1
C4610
100UF =GND_CHASSIS_USB3
R4650
41C2 41A4 41A2 8C8
20% LAYOUT NOTE:C4602,C4603 ARE EMC BY-PASS CAPS FOR J4600

CRITICAL 2 6.3V 2
=EXTAUSB_OC_L
1
1K 2 EXTAUSB_OC_F_L
POLY
B2
8C2
5%
U4600 RCLAMP0502B =GND_CHASSIS_USB
TPS2060 41C4 41A4 41A2 8C8
C
1 C46501/16W
MF-LF
402
2 IN OUT1
7 PP5V_S3_USB2_EXTA
VOLTAGE=5V C
0.47UF
10% 8
MSOP MIN_LINE_WIDTH=0.6MM
2 6.3V
OC1*
CERM-X5R
402
3 EN1* OUT2 6 PP5V_S3_USB2_EXTB
5 VOLTAGE=5V
OC2* MIN_LINE_WIDTH=0.6MM
4 EN2*
41B2 PP5V_S3_USB2_EXTB_F
R4651
GND TPAD
1 9 L4603
FERR-120-OHM-1.5A
VOLTAGE=5V
=EXTBUSB_OC_L
1
1K 2 EXTBUSB_OC_F_L 1 2
8B2
5% OMIT 0402-LF
1 C4651
0.47UF
1/16W
MF-LF
402
CRITICAL
10%
1
C4611
100UF
2 6.3V
CERM-X5R
402 20%
2 6.3V
POLY
B2
65B6
PM_SLP_S4_LS5V
OMIT
PLACE L4601 NEAR J4601 CRITICAL
ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS J4601
USB-M71-MG3
CRITICAL F-RT-TH
L4601 L4601 Monitor SMT for tombstone 5
B 90-OHM-100MA
TCM1005
SYM_VER-1 41C3 PP5V_S3_USB2_EXTB_F 1 VBUS B
8B2 =USB2_EXTB_N 1 4 USB2_EXTB_F_N 2 D-
USB2_EXTB_F_P 3 D+
=USB2_EXTB_P 2 3 USB2_GND_EXTB_F 4 GND

8B2
6
CRITICAL
D4601
SC-75
1 C4606
0.01UF
1 C4607
0.01UF 514-0457
NOSTUFF PLACE C4675 NEAR U4675 1 10% 10%
C4675 2 16V
CERM 2 16V
CERM
0.1UF 41C4 41C2 41A2 8C8 =GND_CHASSIS_USB3 402 402
1 2 =PP3V42_G3H_SMCUSBMUX 7B1
2
20%
10V
CERM R4677
1
RCLAMP0502B
LAYOUT NOTE:C4606,C4607 ARE EMC BY-PASS CAPS FOR J4601
402 10K
5%
1/16W
MF-LF =GND_CHASSIS_USB
9
41C4 41C2 41A4 8C8

2402
SMC_RX_L
VCC
FERR-120-OHM-1.5A
L4605
46B4 45D5 44C5 44B8 6C2 1 D+A NOSTUFF D+ 3 USB2_MUXED_EXTA_P 41C5 MIN_NECK_WIDTH=0.3MM
SMC_TX_L USB2_MUXED_EXTA_N 1 2 VOLTAGE=0V
46B6 45D5 44C5 44B8 6C2 7 D-A
U4675 D- 5 41C5
0402-LF
PI3USB10LP
8C2 =USB2_EXTA_P 2 D+B TQFN
CRITICAL
8C2 =USB2_EXTA_N 6 D-B
8 OE* SEL 10 USB_DEBUGPRT_EN_L 44B8

USB EXTERNAL CONNECTORS
A GND SEL=0 CHOOSE SMC
SEL=1 CHOOSE USB
SYNC_MASTER=USB
A
4

1
0 2
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION II NOT TO REPRODUCE OR COPY IT
5% TABLE_5_ITEM

1/16W
MF-LF R4671 514-0457 2 CONN,4P USB RCPT,MIDPLANE,MG3,LF J4600,J4601 CRITICAL NORMAL
402 0 TABLE_5_ITEM

1 2 2 J4600,J4601 CRITICAL FANCY
051-7559
514-0477 CONN,4P USB RCPT,MIDPLANE,BLACK,LF
5%
1/16W
D H
MF-LF
402 APPLE INC. SCALE SHT OF
NONE 46 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
GEYSER AND DIMM0 REMOTE TEMP SENSORS

D D
L4700
600-OHM-300MA
7A4 =PP5V_S3_GEYSER 1 2 PP5V_S3_GEYSER_F
0402 VOLTAGE=5V
R4710
MIN_NECK_WIDTH=0.3MM 1 C4700
0.1UF
45D5 45C8 44C5 SMC_ONOFF_L CONN_GEYSER_ONOFF_L 1
1K 2 CONN_GEYSER_ONOFF_FLTR_L
20%
2 10V
OUT CERM
MAKE_BASE=TRUE 5% 402
1 C4710 1/16W
MF-LF PLACE C4700 NEAR J4700
0.1UF 402
20%
2
10V
CERM
402 CRITICAL
J4700
53307-1032
F-ST-SM
1 2 L4703
600-OHM-300MA
8C2 =USB2_GEYSER_P CONN_GEYSER_USB_P 3 4
0402
2 3 5 6
7 8 SMC_LID_LC 1 2 SMC_LID 6B2
8C2 =USB2_GEYSER_N CONN_GEYSER_USB_N 9 10
44B5 45C5 57A8
1 4
C PLACE L4701 NEAR J4700 TCM1005

SYM_VER-1
90-OHM-100MA
L4702 516S0588
1 C4703 C
L4701 CRITICAL 600-OHM-300MA
0.01uF
10%
CRITICAL 2 16V
D4700
SC-75
1 2 GEYSER_GND_F CERM
402
0402 MIN_LINE_WIDTH=0.6MM
1 MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V
3
2
RCLAMP0502B
B B
CONNECTOR MISC
SYNC_MASTER=USB SYNC_DATE=06/29/2006
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 47 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
BLUETOOTH
IR CYPRESS ENCORE II USB CONTROLLER
PLACE L4810 NEAR J4800
D PLACE C4810 C4811 NEAR 120-OHM-0.3A-EMI

L4810
L4810 D
PLACE C4800 AND C4801 =PP3V3_S3_BT 1 2
NEAR U4800 PIN 16 7A4
0402-LF
R4803 1 C4810 1 C4811
0 PP5V_S3_IR_R 10UF 0.1UF
7A4 =PP5V_S3_IR 1 2
20% 20%
2 10V
5% 6.3V
2 X5R CERM
1/16W
402 PP3V3_S3_BT_F
C4804 C4801 C4802
MF-LF 603 6A2
402 1 1 1
1UF
10%
0.1UF
20%
0.001UF 10%
VOLTAGE=3.3V
2 10V
X5R 2 10V
CERM 2 50V
CERM
402-1 402 402 CRITICAL
J4810
78171-0004
CRITICAL M-RT-SM
R4801 L4812 5
90-OHM-100MA
0 SB HAS INTERNAL 15K PULL-DOWNS TCM1005
16
1 2 =USB2_IR_P 8C2
SYM_VER-1
1
VDD
5% 8B2 =USB2_BT_N 1 4
USB2_BT_F_N 2
TP_IR_P00 7 P0_0 P1_0/D+ 14 USB2_IR_P_R 1/16W
MF-LF R4802 6C1
TP_IR_P01 6 P0_1 P1_1/D- 15 USB2_IR_N_R

402
1
0 2 =USB2_IR_N 6C1 USB2_BT_F_P 3 TO M13D SLOT
5 18 ENCORE_VREG_C
8C2
8C2 =USB2_BT_P 2 3 4
TP_IR_P02 P0_2/INT0 P1_2/VREG 5%
4 20
1/16W PLACE L4800 NEAR J4800
TP_IR_P03 P0_3/INT1 P1_3/SSEL MF-LF
6
R4800
100 2
TP_IR_P04 3 P0_4/INT2 P1_4/SCLK 23 1 C4800 402
40C6 IR_RX_OUT 1 IR_RX_OUT_RC 2 P0_5/TIO0 P1_5/SMOSI 24 1UF

10% 6A2 GND_BT_F 518S0521
1 25 2 10V
5%
1/16W
MF-LF 1 C4803 32
P0_6/TIO1
P0_7 OMIT
P1_6/MISO
P1_7 26
X5R
402-1 L4811
120-OHM-0.3A-EMI
VOLTAGE=0V
402
0.001UF
10% U4800 1 2
2 50V 9 P2_0 CY7C63833 21
C
C CERM
402 8 P2_1 QFN
P3_0
CRITICAL P3_1
22
0402-LF
PLACE L4811 NEAR J4800
10 27
11 28
C4803 CLOSE TO U4800 PIN 2 12 NC NC
29
17 30
19 31
VSS THRM_PAD
13
33
3G CONNECTOR
NOSTUFF
L4852
FERR-220-OHM-2A
7A7 =PP5V_S0_3G 1 2 PP5V0_S0_3G_F
0603
B NOSTUFF NOSTUFF B
1 C4850 1 C4851
0.01UF
10%
0.01UF
10% NOSTUFF
2 50V
X7R 2 50V
X7R CRITICAL
402 402
J4850
LVC-D10SFYG
F-RT-SM
43A5 8D8 =GND_CHASSIS_3GPOWER 13
11
NOSTUFF
L4853
FERR-220-OHM-2A 1
2
1 2 GND_3G_F 3
0603
NOSTUFF NOSTUFF 4
1 C4852 CRITICAL
L4855
5
0.01UF
10% 90-OHM-100MA 6
TCM1005
2 50V
X7R
SYM_VER-1 7
402 8C2 =USB2_3G_P 4 1 8
43B5 8D8 =GND_CHASSIS_3GPOWER 9
6C1 USB2_3G_F_P
6C1 USB2_3G_F_N 10
8C2 =USB2_3G_N 3 2
12
NOSTUFF
L4854 14
FERR-120-OHM-1.5A
1 2
IR CONTROLLER & BT INTERFACE
GND_CHASSIS_3G_CONN
A 0402
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 48 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups. 45C6 PP3V3_S5_AVREF_SMC
51B8 45D8 45D4 45C1 7C1 =PP3V42_G3H_SMC
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906

22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V
CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
805 402 402 402 402
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
D R4999
4.7
SMC_VCL
D
1 2 PP3V3_S5_SMC_AVCC
5%
MIN_LINE_WIDTH=0.25 MM C4907 1
MIN_NECK_WIDTH=0.20 MM 0.47UF
1/16W
N14
N15
J15
M14
M15
VOLTAGE=3.3V
C4920 1 10%
P2
P1
A1
F1
MF-LF
402 6.3V
0.1UF CERM-X5R 2
AVCC
AVCC
VCC
VCC
VCC
VCC
VCL
AVREF
AVREF
20% 402
10V
OMIT CERM 2 1 1
PM_LAN_ENABLE B12 P10 U4900 P60/KIN0* L13 SMC_PM_G2_EN 402
OMIT R4909 R4901
24C2 OUT OUT 65C6
10K 10K
44A4 OUT SMC_RSTGATE_L C13 P11 SMC_H8S2116 P61/KIN1* L14 SMC_ADAPTER_EN OUT 6C1 33C7 35C7 38C6 45B3 57C4 PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 U4900 5% 5%
BGA 1/16W 1/16W
58A3 27A5 6B2 IN ALL_SYS_PWRGD A15 P12 P62/KIN2* L15 SMC_P62 44B4 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15 SMC_H8S2116 MF-LF MF-LF
(1 OF 4) 402 402
63B5 63B4 45D5 IN RSMRST_PWRGD B14 P13 P63/KIN3* K12 SMC_P63 44B4 BGA 2 2
44B4 SMC_P14 B15 P14 P64/KIN4* K13 SMC_P64 (3 OF 4) MD1 E2 SMC_MD1

44B4 IN 6C2 46B6
24C2 OUT PM_RSMRST_L C14 P15 P65/KIN5* K14 PM_LAN_PWRGD IN 45C5 MD2 K1 SMC_KBC_MDE
46B4 45D7 6C2 IN SMC_RESET_L E3 RES*
59C7 OUT IMVP_VR_ON D12 P16 P66/IRQ6*/KIN6* J12 SMC_PROCHOT_3_3_L IN 45D1
24C3 OUT PM_PWRBTN_L C15 P17 P67/IRQ7*/KIN7* J13 SMC_P67 45C5 45C7 SMC_XTAL A2 XTAL
45C7 SMC_EXTAL B2 EXTAL NMI F4 SMC_NMI IN 6C2 46B4
SMC_P20
44B4 D13 P20 P70/AN0 N12 SMC_CPU_ISENSE IN 48C1 59C7
44B4 SMC_P21 D14 P21 P71/AN1 R13 SMC_CPU_VSENSE IN 6B2 48B1
44B4 SMC_P22 D15 P22 P72/AN2 P13 SMC_GPU_ISENSE IN 44A4
44B4 SMC_P23 E12 P23 P73/AN3 R14 SMC_GPU_VSENSE IN 44A4 ETRST* L1 SMC_TRST_L IN 6C2 46B6
66A3 45B6 6C1 OUT SMC_BATT_TRICKLE_EN_L E14 P24 P74/AN4 P14 SMC_DCIN_ISENSE IN 66C2 NO STUFF
P12
66A4 45B6 6C1 OUT SMC_BATT_CHG_EN E15 P25 P75/AN5 R15 SMC_PBUS_VSENSE IN 48D6 AVSS 1
R4902
1
R4998
1
R4903
R12
44B4 SMC_P26 E13 P26 P76/AN6 N13 SMC_BATT_ISENSE VSS 10K 10K 0
IN 66B1
5% 5% 5%
44B4 SMC_P27 P27 P77/AN7 SMC_NB_1V25_ISENSE
D1
P4
R4
F12
F13
B13
A13
A4
B4
D2
F14 P15 IN 45B3 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
LPC_AD<0> D9 P30/LAD0 P80/PME* C7 SMC_WAKE_SCI_L 2 402 2 402 2 402
46C6 22D4 6D2 BI OUT 24C8
46C6 22D4 6D2 BI LPC_AD<1> C9 P31/LAD1 P81/GA20 A7 SMC_P81 44B4
46C4 22D4 6C2 BI LPC_AD<2> A9 P32/LAD2 P82/CLKRUN* B7 PM_CLKRUN_L OUT 6C2 24C8 37A5 46B6 2
C 46C4 22D4 6C2
46B6 22D4 6C2

BI
IN
LPC_AD<3>
LPC_FRAME_L
B9
D8
P33/LAD3
P34/LFRAME*
P83/LPCPD*
P84/IRQ3*/TXD1
D6
C6
PM_SUS_STAT_L
SMC_TX_L
IN
OUT
6C2 24D5 46B4
6C2 41A8 44B8 45D5 46B6

XW4900
SM C
27C1 IN SMC_LRESET_L C8 P35/LRESET* P85/IRQ4*/RXD1 A6 SMC_RX_L IN 6C2 41A8 44B8 45D5 46B4 1
75B3 29A5 29A3 IN PCI_CLK33M_SMC A8 P36/LCLK P86/IRQ5*/SCK1/SCL1 B6 (OC) SMB_MGMT_CLK BI 47B3
46B4 24C8 6C2 BI INT_SERIRQ D7 P37/SERIRQ

P90/IRQ2* K4 SMC_ONOFF_L IN 42C8 45C8 45D5 GND_SMC_AVSS 45B6 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1 66C2
44A4 OUT SMC_GFX_THROTTLE_L A5 P40/TMIO P91/IRQ1* J2 SMC_BC_ACOK IN 6C1 45B6 57C3 57C7 66A6
45A6 OUT SMC_SYS_LED B5 P41/TMO0 P92/IRQ0* J1 SMC_BS_ALRT_L IN 6D1 45C5 57A2
47B3 BI SMB_MGMT_DATA (OC) D5 P42/SDA1 P93/IRQ12* J3 PM_SLP_S3_L IN 24D3 33C7 35C7 45A6 58B7 62B8
44B4 SMC_P43 C3 P43/TMI1/EXSCK1 P94/IRQ13* J4 PM_S4_STATE_L IN 24D3 33B7 65A6 65C4
44B4 SMC_P44 B1 P44/TMO1 P95/IRQ14* H2 PM_SLP_S5_L IN 24D3 45C3
44A4 SMC_P45 SMC_SUS_CLK

C2 P45 P96/EXCL H1 IN 45A7
44D8 SMC_P14 MAKE_BASE=TRUE
NC_SMC_P14
44B4 SMC_P46 SMB_0_S0_DATA
SMC_SYS_KBDLED
D3 P46/PWX0/PWM0 P97/IRQ15*/SDA0 G2 (OC) BI 47D6
44C8 SMC_P20 MAKE_BASE=TRUE
NC_SMC_P20
P47/PWX1/PWM1 MAKE_BASE=TRUE
44B4 OUT C1
44C8 SMC_P21 NC_SMC_P21
46B6 45D5 44C5 41A8 6C2 OUT SMC_TX_L G1 P50 44C8 SMC_P22 MAKE_BASE=TRUE
NC_SMC_P22
MAKE_BASE=TRUE
46B4 45D5 44C5 41A8 6C2 IN SMC_RX_L G4 P51 44C8 SMC_P23 NC_SMC_P23
MAKE_BASE=TRUE
47D6 BI SMB_0_S0_CLK (OC) F2 P52/SCL0 44C8 SMC_P26 NC_SMC_P26
NC_SMC_P27 OMIT
MAKE_BASE=TRUE
44B8 SMC_P46 NC_SMC_P46
NC_SMC_P44 U4900
OMIT
NC_SMC_P43 SMC_H8S2116
BGA
SMC_PA0 U4900 SMC_CASE_OPEN
(DEBUG_SW_1) 45C5
SMC_PA1
R3 PA0/KIN8*/PA2DC
SMC_H8S2116
PE0 M3
SMC_TCK
IN 45B3
NC_SMC_P62 (4 OF 4)
(DEBUG_SW_2) 45C5
PM_SYSRST_L
P3 PA1/KIN9*/PA2DD
BGA
PE1*/ETCK M2
SMC_TDI
IN 6C2 45C5 46B4
NC_SMC_P63 NC G3 NC0 NC12 F15 NC
(OC) PA2/KIN10*/PS2AC PE2*/ETDI MAKE_BASE=TRUE NC NC
27C5 24D5 OUT
USB_DEBUGPRT_EN_L
R2
(2 OF 4) M1
SMC_TDO
IN 6C2 45C5 46B4
44D5 SMC_P64 NC_SMC_P64 H3 NC1 NC13 A14
41A5 OUT
PM_EXTTS_L<0>
(OC) N3 PA3/KIN11*/PS2AD PE3*/ETDO L4
SMC_TMS
OUT 6C2 45C5 46B6
NC_SMC_P81 NC K3 NC2 NC14 C12 NC
(OC) PA4/KIN12*/PS2BC PE4*/ETMS MAKE_BASE=TRUE NC NC
15B7 8B2 BI R1 L2 IN 6C2 45C5 46B6
SMC_PF1 NC_SMC_PF1 L3 NC3 NC15 C10
B 15B7 8B2
57C8 45D5 6C1

BI
BI
PM_EXTTS_L<1>
SYS_ONEWIRE
(OC)
(OC)
N2
M4
PA5/KIN13*/PS2BD
PA6/KIN14*/PS2CC
PF0/IRQ8*/PWM2 M7 SMC_PF0 44A4
44B5
NC
NC
N4
M5
NC4
NC5
NC16
NC17
C5
A3
NC
NC
B
PF1/IRQ9*/PWM3 P6 SMC_PF1 44B4
24C3 24A5 OUT PM_BATLOW_L (OC) N1 PA7/KIN15*/PS2CD NC N7 NC6 NC18 B8 NC
SMC_LID
SMC_PB0
PF2/IRQ10*/TMOY R6
SMC_PF3
IN 6B2 42C3 45C5 57A8
44B8 SMC_SYS_KBDLED MAKE_BASE=TRUE
NC_SMC_SYS_KBDLED NC M12 NC7 NC19 E4 NC
(DEBUG_SW_3) PB0/LSMI* PF3/IRQ11*/TMOX MAKE_BASE=TRUE
45C5
SMC_RUNTIME_SCI_L
B10 N6
SMC_BATT_ISET
45C1
44A5 ALS_GAIN NC_ALS_GAIN NC M13 NC8 NC20 H4 NC
24C8 OUT
SMC_ODD_DETECT
A10 PB1/LSCI PF4/PWM4 M6
SMC_BATT_VSET
OUT 6C1 66A8
44B8 SMC_EXCARD_PWR_EN MAKE_BASE=TRUE
NC_SMC_EXCARD_PWR_EN NC L12 NC9 NC21 M9 NC
39B2 IN
ISENSE_CAL_EN
D10 PB2 PF5/PWM5 R5
SMC_SYS_ISET
OUT 44A4
44A8 SMC_FAN_0_CTL MAKE_BASE=TRUE
NC_SMC_FAN_0_CTL NC K15 NC10 NC22 N8 NC
PB3 PF6/PWM6 MAKE_BASE=TRUE
48A8 OUT
SMC_EXCARD_CP
A11 P5
SMC_SYS_VSET
OUT 66B8
44A8 SMC_FAN_2_CTL NC_SMC_FAN_2_CTL NC J14 NC11
45C3 IN
SMC_EXCARD_PWR_EN
B11 PB4 PF7/PWM7 N5 OUT 44A4
44A8 SMC_FAN_3_CTL MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
44B4 OUT
SMC_EXCARD_OC_L
C11 PB5
PG0/EXIRQ8*/TMIX P9 SMC_PG0 45C5 44A8 SMC_FAN_0_TACH MAKE_BASE=TRUE
NC_SMC_FAN_0_TACH
PB6 MAKE_BASE=TRUE
45D5 IN
SMC_GFX_OVERTEMP_L
A12
PG1/EXIRQ9*/TMIY R9 SMC_SMS_INT IN 51A8 44A8 SMC_FAN_2_TACH NC_SMC_FAN_2_TACH
45D5 IN D11 PB7
PG2/EXIRQ10*/SDA2 N9 (OC) SMB_BSA_DATA BI 47C3 44A8 6A7 SMC_FAN_3_TACH MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
44B4 OUT SMC_FAN_0_CTL G14 PC0/TIOCA0/WUE8* PG3/EXIRQ11*/SCL2 P8 (OC) SMB_BSA_CLK BI 47C3 44A8 ALS_LEFT NC_ALS_LEFT
MAKE_BASE=TRUE
50B4 6D2 OUT SMC_FAN_1_CTL G15 PC1/TIOCB0/WUE9* PG4/EXIRQ12*/EXSDAA R8 (OC) SMB_A_S3_DATA BI 47D3 44A8 ALS_RIGHT NC_ALS_RIGHT
MAKE_BASE=TRUE
44B4 OUT SMC_FAN_2_CTL G13 PC2/TIOCC0/TCLKA/WUE10* PG5/EXIRQ13*/EXSCLA M8 (OC) SMB_A_S3_CLK BI 47D3 44B5 SMC_PF0 NC_SMC_PF0
MAKE_BASE=TRUE
44B4 OUT SMC_FAN_3_CTL G12 PC3/TIOCD0/TCLKB/WUE11* PG6/EXIRQ14*/EXSDAB P7 (OC) SMB_B_S0_DATA BI 47C6 44B5 SMC_BATT_VSET NC_SMC_BATT_VSET
44B4 IN SMC_FAN_0_TACH H14 PC4/TIOCA1/WUE12* PG7/EXIRQ15*/EXSCLB R7 (OC) SMB_B_S0_CLK BI 47C6 44B5 SMC_SYS_VSET MAKE_BASE=TRUE
NC_SMC_SYS_VSET
50C4 6D2 IN SMC_FAN_1_TACH H15 PC5/TIOCB1/TCLKC/WUE13*
SMC_PROCHOT
44D8 SMC_RSTGATE_L MAKE_BASE=TRUE
NC_SMC_RSTGATE_L
PH0/EXIRQ6* MAKE_BASE=TRUE
44B4 IN SMC_FAN_2_TACH H13 PC6/TIOCA2/WUE14*
E1
SMC_THRMTRIP
OUT 45B6
44C8 SMC_GFX_THROTTLE_L NC_SMC_GFX_THROTTLE_L
PH1/EXIRQ7* F3 OUT 45B5
44A4 6A7 IN SMC_FAN_3_TACH H12 PC7/TIOCB2/TCLKD/WUE15*
PH2/FWE K2 SMC_FWE IN 45C5
51C2 IN SMS_X_AXIS M11 PD0/AN8 PH3/EXEXCL C4 ALS_GAIN OUT 44B4

MAKE_BASE=TRUE
51C2 IN SMS_Y_AXIS P11 PD1/AN9 PH4 D4 SMC_PH4 44A4 44C5 SMC_GPU_ISENSE SMC_GPU1_ISENSE 60B2 60C7
MAKE_BASE=TRUE
51C2 IN SMS_Z_AXIS R11 PD2/AN10 PH5 B3 SMS_ONOFF_L OUT 51C7 44C5 SMC_GPU_VSENSE SMC_GPU1_VSENSE 48B1
SMC_ANALOG_ID SMC_P45 MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN
45C6 IN
SMC_NB_CORE_ISENSE
N11
P10
PD3/AN11
PD4/AN12
44C8
SMC_PH4 MAKE_BASE=TRUE
SMC_ENRGYSTR_LDO_PGOOD
66D3
45C5 66C1
SMC
61C5 IN 44A5
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
A 62C2
44A4
IN
IN
SMC_NB_1V8_ISENSE
ALS_LEFT
R10
N10
PD5/AN13
PD6/AN14
If SMS interrupt is not used, pull up to SMC rail.
SYNC_MASTER=T9_MLB

A
44A4 IN ALS_RIGHT M10 PD7/AN15
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 49 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
SMC Reset Button / Brownout Detect

51B8 45D4 45C1 44D4 7C1 =PP3V42_G3H_SMC THESE NEED TO BE PULLED TO THE PROPER RAIL: SMC 1.05V to 3.3V Level Shifting
SMS_INT_L
SMC_TPM_RESET_L =PP3V3_S0_SMC_LS
C5000
0.1UF
1 CRITICAL
2 R5000
1 7D4
PP3V3_S0
20% VDD 1K
5% SMS_INT_L 7D7 6B2 PP1V05_S0 7D4 6A2
10V
CERM 2 U5000 1/16W
MF-LF
402
RN5VD30A-F
SOT23-5
2402 44A8 SMC_GFX_OVERTEMP_L R50301 2 10K 1
R5078
D
6B2 SMC_MANUAL_RST_L
NOSTUFF NC
5
4
CD
NC
OUT 1 46B4
44C3 6C2 SMC_RESET_L
OUT 470
5%
1/16W
D
1 R5001C5001 1 GND R5070
1 MF-LF
2 402
0 3 =PP3V42_G3H_SMC 3.3K
5% 0.01UF 10%
51B8 45D8 45C1 44D4 7C1 5%
1/16W 44C5
1/16W 16V MF-LF
SMC_PROCHOT_3_3_L
MF-LF CERM 2 2402
2402 402 RSMRST_PWRGD R50941 2 100K
63B5 63B4 44D8
SMC_ONOFF_L R50531 2 10K 3

Q5077
R50281
45C8 44C5 42C8
Silk: "SMC RST" SMC_EXCARD_OC_L 2 10K 5 BC847BV-X-F

44B8
SMC_TX_L R50801 2 10K CPU_PROCHOT_BUF SOT563

46B6 44C5 44B8 41A8 6C2
SMC_RX_L R50811 2 100K 4

R50821
46B4 44C5 44B8 41A8 6C2
SYS_ONEWIRE 2 2.0K
57C8 44B8 6C1
SMC_BS_ALRT_L R50831 2 470K R5071 6

Q5077
R50841 3.3K
57A2 44C5 6D1
Debug Power Button SMC Crystal Circuit

46B6 44B5 6C2 SMC_TMS
SMC_TDO R50851
2
2
10K
10K
70C3 59C8 45B5 9C5
CPU_PROCHOT_L 5%
1 2
CPU_PROCHOT_L_R
2 BC847BV-X-F
SOT563
SMC_TDI R50861 2 10K 1/16W
MF-LF 1
SMC_ONOFF_L C5020
46B4 44B5 6C2
46B4 44B5 6C2 SMC_TCK R50871 2 10K 402
15PF R50481
45D5 44C5 42C8
OUT
NOSTUFF SMC_XTAL SMC_FWE 2 10K
1 2
R50731
44A5
1
R5010 44C3
SMC_LID 2 100K
SMC_ENRGYSTR_LDO_PGOODR50951
57A8 44B5 42C3 6B2
CRITICAL
0 Silk: "PWR BTN" Y5020
5% 2 10K =PP3V42_G3H_SMC
7C1 44D4 45D4 45D8 51B8
5% 50V 66C1 44A2
PM_LAN_PWRGD R50911 10K
2
1/10W CERM 2
20.00MHZ 402
R50981
44C5
MF-LF
2603 5X3.2-SM SMC_PA0 2 10K
C5021 44B8
SMC_PA1 R50991 2 10K

R50901 R5076
1
15PF 44B8
1
SMC_EXTAL SMC_PB0 2 10K
44C3
1 2 44B8
SMC_P67 R50891 2 10K 10K

5%
Is this the best part to use? 5%
50V
44C5
44B5 SMC_PG0 R50791 2 10K 1/16W

MF-LF
CERM 2402
C
402
C
SMC AVREF
NOSTUFF
Supply SMC_PF3
SMC_CPU_RESET_3_3_L
44B5
R5072
0
1 2
5%
1/16W
R50061 2 100K PM_SLP_S5_L 24D3 44C5
MF-LF
402
VR5065 44A8 SMC_ANALOG_ID R50491 2 10K
R50241 2 10K SMC_EXCARD_CP 44B8
=PP3V42_G3H_SMCVREF ISL60002-33
SOT23-3 PP3V3_S5_AVREF_SMC
R5054
R 50541 R50471
7C1 44D4
MIN_LINE_WIDTH=0.4 MM SMC_BATT_TRICKLE_EN_L SMC_CASE_OPEN
1 VIN
CRITICAL
VOUT 2 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
66A3 44C8 6C1 2 10K 2 10K 44B5
GND
3 1 C5067 66A4 44C8 6C1 SMC_BATT_CHG_EN R50551 2 10K R50961 2 10K SMC_ADAPTER_EN 6C1 33C7 35C7 38C6 44D5 57C4
0.01UF
10%
2 16V
CERM 66A6 57C7 57C3 44C5 6C1 SMC_BC_ACOK R50881 2 470K R50971 2 10K SMC_NB_1V25_ISENSE 44C5
1 C5065C5066 1
0.47UF 10uF
402
10% 20%
2 6.3V
CERM-X5R
6.3V
X5R 2
402 603
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 MM66C2
44C1 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1 SMC 3.3V to 1.05V Level Shifting
VOLTAGE=0V
CPU_PROCHOT_L 9C5 45C3 59C8 70C3 PM_THRMTRIP_L 9C6 15A6 22C2 70B3
TABLE_ALT_HEAD

PART NUMBER
Q5001 D 6 Q5001 D 3
B 353S1278 353S1381 ? VR5065 TI REF3133

TABLE_ALT_ITEM
SSM6N15FE
SOT563
SSM6N15FE
SOT563 B
2 G S 1 5 G S 4
SMC_PROCHOT 44A5 SMC_THRMTRIP

44A5
SYSTEM (SLEEP) LED CURRENT DRIVER

40B6 7A4 =PP5V_S3_SYSLED TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
1OMIT
3.3V TO PBUS LEVEL SHIFTING R5051
1
R5050
TABLE_5_ITEM
114S0071 1 31.6, 1%, 1/16W, MF-LF, 402 R5050 NORMAL

357 1 C5050 31.6 TABLE_5_ITEM
1%
1/16W 0.001UF 1%
1/16W
114S0086 1 44.2, 1%, 1/16W, MF-LF, 402 R5050 FANCY
=PPVIN_S5_IMVP
R5075
470K PBUS_SMC_VSENSE_EN_L
MF-LF
2402
10%
2 50V
CERM
MF-LF
2402
7A1 1 2 48D7 SYS_LED_ISET 402 SYS_LED_ILIM
1%
1/16W
ENABLE VSENSE IN S0 ONLY 1 4
MF-LF
402 Q5050
MMDT3906XF 2 5 Q5050
MMDT3906XF
Q5002 D 6 SOT-363 SOT-363
SSM6N15FE
R5011 SMC SUPPORT
3
SOT563 6
24D3 SUS_CLK_SB 0
1 2 44C5 SMC_SUS_CLK R5052 RC FILTERED AT SATA CONN
OUT
3.74K2 SYNC_MASTER=GPU SYNC_DATE=07/17/2006
A 5%
1/16W
MF-LF
402
2 G S 1 SYS_LED_EN1
1%
SYS_LED_BIAS
40C5 6B2 SYS_LED_ANODE
OUT
A
62B8 58B7 44C5 35C7 33C7 24D3 IN PM_SLP_S3_L 1/16W
MF-LF
402 0.0094A NORMAL
R5011 CLOSE TO SB Q5002 D 3 0.007A FANCY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SSM6N15FE AGREES TO THE FOLLOWING
SOT563 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5 G S 4
SMC_SYS_LED
44C8
IN
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 50 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
LPC+ Connector FWH_INIT_L Generation

7C4 =PP3V3_S0_LPCPLUS
C LPCPLUS LPCPLUS C
CRITICAL 1
R5192 1
R5191
LPCPLUS 330 1.3K
5% 5%
=PP3V42_G3H_LPCPLUS J5100 1/16W 1/16W
7B1 6D2
F-ST-5047 MF-LF MF-LF
7A7 6D2 =PP5V_S0_LPCPLUS SM1 2 402 2 402
1 2 6C2 FWH_INIT_L
3 4 PCI_CLK33M_LPCPLUS IN 6C2 29B3 75C3
44C8 22D4 6D2 BI LPC_AD<0> 5 6 LPCPLUS

3
44C8 22D4 6D2 BI LPC_AD<1> 7 8 LPC_AD<2> BI 6C2 22D4 44C8 Q5190
BC847BV-X-F 5 CPU_INIT_LS3V3
9 10 LPC_AD<3> BI 6C2 22D4 44C8 SOT563
LPC_FRAME_L 11 12 LPCPLUS
44C8 22D4 6C2 IN 4 LPCPLUS
PM_CLKRUN_L INT_SERIRQ 6 R5190
44C5 37A5 24C8 6C2 OUT
BOOT_LPC_SPI_L
13
15
14
16 PM_SUS_STAT_L
BI 6C2 24C8 44C8
Q5190
BC847BV-X-F 2 CPU_INIT_R_L 1
330 2 CPU_INIT_L
23B5 6C2 OUT IN 6C2 24D5 44C5 IN 9D6 22C4 70B3
SMC_TMS 17 18 SMC_TDI SOT563 5%

45C5 44B5 6C2 OUT OUT 6C2 44B5 45C5
1/16W
DEBUG_RESET_L 19 20 SMC_TCK 1 MF-LF
27D1 6C2 IN OUT 6C2 44B5 45C5
402
44C1 6C2 OUT SMC_TRST_L 21 22 SMC_RESET_L OUT 6C2 44C3 45D7
SMC_TDO 23 24 SMC_NMI PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

45C5 44B5 6C2 IN OUT 6C2 44C1
44D1 6C2 OUT SMC_MD1 25 26 SMC_RX_L OUT 6C2 41A8 44B8 44C5 45D5
45D5 44C5 44B8 41A8 6C2 IN SMC_TX_L 27 28

29 30 LINDACARD_GPIO OUT 6C2 24A7 24D5
516S0416
B B
LPC+ Debug Connector

A SYNC_MASTER=WFERRY SYNC_DATE=06/01/2006
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 51 106
8 7 6 5 4 3 2 1
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ICH8-M SMBus Connections SMC "0" SMBus Connections SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
7C4 =PP3V3_S0_SMBUS_SB 7C4 =PP3V3_S0_SMBUS_SMC_0_S0 7A4 =PP3V3_S3_SMBUS_SMC_A_S3
ICH8-M R52001
4.7K
1
R5201
4.7K
Clock Chip SMC R52501
4.7K
1
R5251 HEAT PIPE/FIN-STACK
4.7K
SMC R52701
100K
1
R5271
100K
U2300 5% 5% SLG8LP537V: U2900 U4900 5% 5% U5500 U4900 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0xD2 Read: 0xD3) (MASTER) MF-LF MF-LF (MASTER) MF-LF MF-LF
402 2 2 402 402 2 2 402 402 2 2 402
D 73A3 24D5 SMB_CLK SMBUS_SB_SCL

MAKE_BASE=TRUE
=SMBUS_CK505_SCL 28B6 44B8 SMB_0_S0_CLK 76C3 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
THRM_HEATPIPE_SMB_CLK 49D4 44A5 SMB_A_S3_CLK 76C3 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE D
73A3 24D5 SMB_DATA SMBUS_SB_SDA =SMBUS_CK505_SDA 28B6 44B5 SMB_0_S0_DATA 76C3 SMBUS_SMC_0_S0_SDA THRM_HEATPIPE_SMB_DATA 49D4 44A5 SMB_A_S3_DATA 76C3 SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
SO-DIMM "A"
J3100
(Write: 0xA0 Read: 0xA1)
=I2C_SODIMMA_SCL 30A6 SMC "B" SMBus Connections SMC "Battery A" SMBus Connections
=I2C_SODIMMA_SDA 30A6
7C4 =PP3V3_S0_SMBUS_SMC_B_S0
7B1 =PP3V42_G3H_SMBUS_SMC_BSA
SO-DIMM "B" SMC R52601 1

R5261 CPU Temp
J3200
(Write: 0xA4 Read: 0xA5)
U4900
4.7K
5%
1/16W
4.7K
5%
1/16W
EMC1043-5: U5520 SMC R52801
1K
1
R5281
1K
Battery
(MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99) U4900 5% 5% J6950
402 2 2 402 1/16W 1/16W
=I2C_SODIMMB_SCL (MASTER) MF-LF MF-LF (Write: 0x16 Read: 0x17)
31A6 402 2 2 402
44A5 SMB_B_S0_CLK 76C3 6B2 SMBUS_SMC_B_S0_SCL THRM_CPU_SMB_CLK 49B4
MAKE_BASE=TRUE
=I2C_SODIMMB_SDA 31A6 44A5 SMB_BSA_CLK 76C3 SMBUS_SMC_BSA_SCL =SMBUS_BATT_SCL 57A2
44A5 SMB_B_S0_DATA 76C3 6B2 SMBUS_SMC_B_S0_SDA THRM_CPU_SMB_DATA 49B4 MAKE_BASE=TRUE
MAKE_BASE=TRUE
44A5 SMB_BSA_DATA 76C3 SMBUS_SMC_BSA_SDA =SMBUS_BATT_SDA 57A2
MAKE_BASE=TRUE
AIRPORT
C J3400
SMC "MANAGEMENT" SMBUS CONNECTIONS C
=SMB_AIRPORT_CLK 33B3
=SMB_AIRPORT_DATA 33B3
51B6 7A4 =PP3V3_S3_SMBUS_SMC_MGMT
SMC R52321
10K
1
R5233
10K
SMS
U4900 5% 5% U5930
SMC MGMT Bus 1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
44C5 SMB_MGMT_CLK 76C3 SMBUS_SMC_MGMT_SCL =I2C_SMS_SCL 51A6

MAKE_BASE=TRUE
44C8 SMB_MGMT_DATA 76C3 SMBUS_SMC_MGMT_SDA =I2C_SMS_SDA 51A6
MAKE_BASE=TRUE
B B
ICH8-M ME SMBus Connections
7D1 =PP3V3_S5_SMBUS_SB_ME
SMBUS CONNECTIONS
A ICH8-M R52301 1
R5231 SYNC_MASTER=WFERRY SYNC_DATE=06/01/2006
U2300
10K
5%
1/16W
10K
5%
1/16W NOTICE OF PROPRIETARY PROPERTY
A
(MASTER?) MF-LF MF-LF
402 2 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
73A3 24D5 SMB_ME_CLK SMBUS_SB_ME_SCL AGREES TO THE FOLLOWING
MAKE_BASE=TRUE
73A3 24D5 SMB_ME_DATA SMBUS_SB_ME_SDA
MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 52 106
8 7 6 5 4 3 2 1
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PROCESSOR DCIN VOLTAGE SENSE CPU CURRENT SENSE

C5300
470PF
1 2
10%
50V
=PPVIN_S5_CPU_IMVP 3 PBUS_S0_SMC_VSENSE R5307 R5305 CERM
D
2
S
59D8 59D4 59C2 7B1
402
SSM3J15FV IMVP6_DROOP
1
0 2
30.1K2
IMVP6_CPU_ISENSE_P
1
D
SOT-723
Q5350
59B6 59A4
5%
1/16W
1%
1/16W
R5300
1M D
MF-LF MF-LF 1 2
R5350
1
G
402 NOSTUFF 402
1 27.4K 1 C5304 1%
1/16W
1%
1/16W 0.1UF
20%
MF-LF
402
MF-LF
2402 2 10V
CERM
402
C5301
0.1UF
PBUS_SMC_VSENSE_EN_L 1 2 =PP3V3_S0_CPUPOWER
45A5 7C4
DRIVEN LOW IN S0 SMC_PBUS_VSENSE 20%

10V
44C5
CERM
402
CRITICAL
R5351
1
5.49K
1 C5350 U5300
HPA00141AIDCKR
1% 0.22UF
10%
CPU_ISENSE_R_P 1 +
5
SC70-5 R5302
1/16W
MF-LF 2 6.3V V+ 4.53K
CPU_ISENSE_OUT_R SMC_CPU_ISENSE
2402
CERM-X5R
402
GND_SMC_AVSS
R5308
0
R5306
30.1K
4 1 2
1%
44C5 59C7
IMVP6_VO 1 2 IMVP6_CPU_ISENSE_N
1 2 CPU_ISENSE_R_N 3 V- 1/16W
C5302
44C1 45B6 48A1 48B1 48C1 60B2 61C5 62C2 59B6 59A4
- MF-LF 1
66B1 66C2
5% 1% 2 402
PLACE C5350 NEAR SMC
1/16W
MF-LF
NOSTUFF 1/16W
MF-LF
0.22UF
20%
402 1 C5355 402 2 6.3V
X5R
402
0.1UF
20% GND_SMC_AVSS
2 10V
CERM
402
1 C5303
1
R5303 44C1 45B6 48A1 48B1 48C6 60B2 61C5 62C2
66B1 66C2
470PF 1M
10%
2 50V
CERM
1%
1/16W
MF-LF
PLACE RC FILTER CLOSE TO SMC
402 2402
C C
CPU VOLTAGE SENSE

R5312
4.53K
48B5 11D7 10D7 10B5 7D7 =PPVCORE_S0_CPU 1 2 SMC_CPU_VSENSE 6B2 44C5
1%
1/16W
MF-LF
402 1 C5312
0.22UF
20% C5312 CLOSE TO SMC
2 6.3V
X5R
402
Current Sense Calibration Circuit GND_SMC_AVSS 44C1 45B6 48A1 48C1 48C6 60B2 61C5 62C2 66B1
66C2
Switches in fixed load on power supplies to calibrate current sense circuits

B B
GPU VOLTAGE SENSE
=PPVCORE_S0_CPU R5381 SMC_GPU1_VSENSE
=PPVCORE_S0_NB_GFX 14.53K
48B3 11D7 10D7 10B5 7D7
21C5 17D5 17B7 7B7 2 44A2

1
R5343
1.00
1%
1/16W
MF-LF
CRITICAL 1% 402
=PP5V_S0_ISENSECAL
7A7
Q5300 1/4W
MF-LF 1 C5376
SI3446DV 21206 0.22UF
TSOP-LF 1 CPUVCORE_ISENSE_CAL
20%
2 6.3V
C5376 CLOSE TO SMC
CRITICAL 2 MIN_LINE_WIDTH=0.50 mm X5R
402
U5302
5 SN74AHCT1G125DCKRE4 R5342 5
ISENSE_CAL_EN
2 4 ISENSE_CAL_EN_5V1
1K 2 ISENSE_CAL_EN_5V_R3 6
44B8
IN
SC70-5 5%
GND_SMC_AVSS 44C1 45B6 48B1 48C1 48C6 60B2 61C5 62C2 66B1
66C2
3 1 1/16W 4
MF-LF
402
CPU Current & Voltage Sense

A SYNC_MASTER=GPU

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 53 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
HEAT-PIPE/FIN-STACK TEMPERATURE ZONE

R5501
33
PP3V3_S0_THRM_HEATPIPE_F 1 2 =PP3V3_S0_THRM_SNR 7C4 49C2
PLACE C5501 NEXT 5%

TO U5500 VDD 1 C5501 C5502 1 1/16W
MF-LF
0.1UF 1UF 402
D
10%
16V
2 X5R
402
10%
6.3V
2 CERM
402
D
CRITICAL 1. ROUTE DXP AND DXN DIFFERENTIALLY
CRITICAL
J5550 2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
6 PLACE C5501 NEAR U5500 VDD
78171-0004 3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
M-RT-SM VDD
6A1 THRM_HEATPIPE_P
5 U5500
EMC1043-5
1 PLACE C5510 1 C5510 1 DP1
MSOP
THRM_HEATPIPE_SMB_CLK
CONNECTOR DRIVES TWO 0.0022UF SMCLK 8
(WRITE: 0X98 READ: 0X99)
47D3
IO
2 NEXT TO U5500 10% 2 DN1
TEMP DIODE JUNCTIONS SMDATA 7 47D3 THRM_HEATPIPE_SMB_DATA
3 2 50V
CERM
IO
4 402 3 DP2 ADDR= 1001 100B

4 DN2
6A1 THRM_HEATPIPE_N GND
6
5
518S0521
1. ROUTE DXP AND DXN DIFFERENTIALLY
2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
6A1 THRM_FINSTACK_P
1 C5511 PLACE C5511

0.0022UF
10% NEXT TO U5500
2 50V
CERM
402 6A1 THRM_FINSTACK_N
C LAYOUT NOTE: LAYOUT NOTE:

R5524
33
C
PP3V3_S0_THRM_CPU_F 1 2 =PP3V3_S0_THRM_SNR 7C4 49D2
ADD GND GUARD TRACE ROUTE CPU_THERMD_P AND
5%
FOR CPU_THERMD_P AND
CPU_THERMD_N
CPU_THERMD_N ON SAME
LAYER.
1 C5522
0.1UF
1 C5523
1UF
1/16W
MF-LF
402
10% 10%
2 16V 2 6.3V
10 MIL TRACE
10 MIL SPACING
CPU TEMPERATURE ZONE X5R
402
CERM
402
OUT
9C6 CPU_THERMD_P
CRITICAL
1 C5520
0.0022UF
6
VDD
PLACE C5522 NEAR U5520 VDD
1. ROUTE DXP AND DXN DIFFERENTIALLY
(TO CPU INTERNAL THERMAL DIODE) 10%
2 50V 2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
U5520
CERM
402 EMC1043-5
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD MSOP
1 DP1
THRM_CPU_SMB_CLK
SMCLK 8
(Write: 0x98 Read: 0x99)
47C3
9C6 CPU_THERMD_N 2 DN1
IO
IN
SMDATA 7 47C3 THRM_CPU_SMB_DATA IO
6A1 THRM_DIMM_DX_F_P 1 2 THRM_DIMM_DX_P 3 DP2 ADDR= 1001 100B
3 R5522 THRM_DIMM_DX_N 4 DN2
GND
Q5520
CRITICAL
1
10
1%
1/16W
1 C5521
0.0022UF 5
BC846BM3T5G MF-LF
402 10%
SOT732-3 NOSTUFF 2 50V
CERM
PLACE UNDER J3101
2 1 C5524
0.0022UF
402
10% PLACE C5524 NEXT TO Q5520

2 50V
CERM
402
B 1 2
B
6A1 THRM_DIMM_DX_F_N R5523 1. ROUTE DXP AND DXN DIFFERENTIALLY
10
1%
2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
1/16W
MF-LF
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
402
TEMPERATURE SENSE
A SYNC_MASTER=GPU
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 55 106
8 7 6 5 4 3 2 1
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D D
7A7 6D2 =PP5V_S0_FAN_RT

=PP3V3_S0_FAN_RT
C C
7C4 6D2
CRITICAL
R5660 1 J5601
78171-0004
47K
5%
M-RT-SM
NC 5
R5665 1/16W
MF-LF
402 2
5V DC
147K2 FAN_RT_TACH
1
44A8 6D2 SMC_FAN_1_TACH 6D2 2 TACH
5% 3
1/16W
MF-LF 4 MOTOR CONTROL
402 GND
NC 6
R5661 1
100K
5% Q5660 518S0521
1
1/16W
MF-LF SSM3K15FV
G
402 2 SOD-VESM
FAN_RT_PWM
D
6D2
SMC_FAN_1_CTL
3
2
44A8 6D2
B B
Fan
SYNC_MASTER=ENET
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 56 106
8 7 6 5 4 3 2 1
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PAGE NOTES
INPUT
=PP3V3_S3_SMS - 3.3V POWER FOR SMS (STAYS ALIVE IN SLEEP)
SMS_ONOFF_L - CONNECT TO SMC TO BE ABLE TO PUT SMS INTO LOW-POWER MODE
OUTPUT
SMS_ACC_*_AXIS - ACCELEROMETER OUTPUT TO SCU
PAGE HISTORY
D 5/19/2005
7/26/2005
7/26/2005
- FIRST REVISION OF PAGE
- REMOVED BOM TABLE AND UPDATED SYMBOL TO KXM52-2050
- CONNECTED PD PIN TO SMC’S SMS_ONOFF_L
D
7/26/2005 -
Desired Orientation
(Placed on board bottom side)
Package Top
1
+Y
7A4 =PP3V3_S3_SMS +X
NC
C5920
0.1UF
1 +Z (up)
10%
CRITICAL 16V
3 12 X5R 2
VDD VMUX 402
U5920
KXPA42050
DFN
SMS_ACC_SELFTEST 9 SELF OUTPUTX 5 SMS_X_AXIS 44A8
TEST
44A5 SMS_ONOFF_L 8 PS OUTPUTY 7 SMS_Y_AXIS 44A8
10 S1 OUTPUTZ 6 SMS_Z_AXIS 44A8
C R5921
1
10K
11 S0
NC1
NC2
1
2
NC
NC
C
5% 13
1/16W NC13 NC
MF-LF
2402
THRML
NC14 14 NC 1 C5904 1 C5905 1 C5906
0.033UF 0.033UF 0.033UF
GND PAD 10% 10% 10%
4 15 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402
SMC_ACC_SELFTEST-->is a test signal
0 -->Normal operation
1 -->Self test
Desired Orientation
(Placed on board bottom side)
Package Top
B +Z (UP)
B
+Y
+X 1
=PP3V42_G3H_SMC 47C3 7A4 =PP3V3_S3_SMBUS_SMC_MGMT

45D8 45D4 45C1 44D4 7C1
NOSTUFF
NOSTUFF
C5931
1 C5932
9
1
VDD VDDIO 0.022UF 0.1UF
10%
R5930
1
=I2C_SMS_SCL 6 SCK U5930 11 NC
10%
16V 2
16V
X5R
10K
5%
47B1
BMA150 NC
2 CERM-X5R
402
402
1/16W 7 SDO LGA 12 NC
MF-LF
2 402 47B1 =I2C_SMS_SDA 8 SDI
CRITICAL
NOSTUFF
1 NC
44B5 SMC_SMS_INT 4 INT
RESERVED
10 NC
NOSTUFF 5 CSB
R5931
1
GND
10K STUFF R5930 TO USE U5920
3
5%
1/16W
MF-LF
2 402 STUFF R5931 TO USE U5930
SMS
SYNC_MASTER=SMC SYNC_DATE=08/23/2005
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 59 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
7D1 =PP3V3_S5_ROM
R61001 1
R6101 C6100 1
3.3K 3.3K 0.1UF 8 CRITICAL
5% 5% 10%
1/16W 1/16W 16V 2 VDD
MF-LF MF-LF X5R PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100
402 2 2 402 402 U6100 PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300
R6190 close to SB
R6190 16MBIT R6193 R6193 close to SB
15 SOI 15 2
73A3 23C5 IN SPI_SCLK_R 1 2 73A3 SPI_A_SCLK_R 6 SCK SI 5 73A3 SPI_A_SI_R 1 SPI_SI_R IN 23C5 73A3
5%
1/16W R6191 SST25VF016B
R6114
5%
1/16W
MF-LF 15 OMIT MF-LF
73A3 23C5 IN SPI_CE_R_L<0> 402 1 2 73A3 SPI_CE_L<0> 1 CE* 15 402
SO 2 73A3 SPI_A_SO_R 1 2 SPI_SO OUT 23C5 73A3
5% SPI_A_WP_L 3 WP*
R6191 close to 1/16W
SB SPI_A_HOLD_L
5%
MF-LF 7 HOLD* 1/16W R6114 close to u6100
C 402
VSS
MF-LF
402 C
4
PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300
PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300
B B
SPI ROMs
A SYNC_MASTER=WFERRY
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 61 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S1538
L6202 MIN_LINE_WIDTH=0.40MM
D
FERR-220-OHM
1 2
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG 53A3
D
0402
MIN_LINE_WIDTH=0.30MM L6201
VOLTAGE=3.3V FERR-220-OHM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
7C4 =PP3V3_S0_AUDIO CODEC_DVDD AVDD_ADC_DAC
56B5 55D8 53A7
1 2 53C8
0402
OMIT OMIT
CRITICAL CRITICAL CRITICAL
C6200 1 1 C6201 1 C6203 C6204 1 1 C6206 C6205 1 1 C6207
1UF 0.001UF 0.001UF 150UF 0.001UF 150UF 0.001UF
10% 10% 10% 20% 10% 20% 20%
6.3V 2 50V 2 50V 2 50V 2 50V
CERM 2 CERM CERM 6.3V 2
POLY CERM 6.3V 2
POLY CERM
402 402 402 CASE-B2 402 CASE-B2 402
=GND_AUDIO_CODEC
25
38
8B4 53A7 53B7 54A8 54B8 54C8 55B3 56A4 56A8 56B1 56B4
1
9
56B5 56B8 56C4
DVDD
DVDD_IO
AVDD1
AVDD2
8A5 6C1
IN ACZ_BITCLK R6206
8A5 6C1 ACZ_SYNC 39
IN
6 BCLK SPDIFO 48 AUD_SPDIF_O 1 2 AUD_SPDIF_OUT 55D3
CODEC_DVDD 8A5 6D1
IN
ACZ_SDATAOUT
53D6 NO STUFF 10 SYNC SPDIFI/EAPD/MIDI-I/DMIC-R 47 5%
1
R6270 R6204 5 SDATA_OUT CRITICAL
1/16W
MF-LF AUD_SPDIF_I 55B3
39
100K 8A5 6D1
OUT ACZ_SDATAIN<0> 1 2 CODEC_SDATA_IN 8 SDATA_IN U6200 SENSE_A 13
402
AUD_SENSE_A 56A8 56C8
5%
1/16W 5% ALC885Q-VB3-GR SENSE_B 34 AUD_SENSE_B 56C8
MF-LF 1/16W QFN
MF-LF
2 402 402 REV B3
54A8 AUD_GPIO_0 2 GPIO0/DMIC-CLK PORT-A-L 39 AUD_BI_PORT_A_L 56C4
AUD_GPIO_1 3 GPIO1/DMIC-L PORT-A-R 41 AUD_BI_PORT_A_R 56C4
1
R6271 PORT-F-L 16 NO_TEST NC_AUD_BI_PORT_F_L
AUD_BI_PORT_C_L 23 PORT-C-L
10K
56B1
PORT-F-R 17 NO_TEST NC_AUD_BI_PORT_F_R
5% 56A1 AUD_BI_PORT_C_R 24 PORT-C-R
1/16W PORT-F-VREFO 30 NO_TEST NC_AUD_VREF_PORT_F
MF-LF AUD_VREF_PORT_A
C 2 402 54B8
54C8
AUD_BI_PORT_D_L
AUD_BI_PORT_D_R
35
36
PORT-D-L
PORT-D-R
PORT-A-VREFO/DCVOL
PORT-E-L
33
14 NO_TEST NC_AUD_BI_PORT_E_L
56C2
C
PORT-E-R 15 NO_TEST NC_AUD_BI_PORT_E_R
NC_BAL_IN_L NO_TEST18 CD-L PORT-E-VREFO 31 NO_TEST NC_AUD_VREF_PORT_E
NC_BAL_IN_COM NO_TEST19 CD-GND PORT-B-VREFO 28 AUD_VREF_PORT_B 56B4
NC_BAL_IN_R NO_TEST20 CD-R PORT-B-L 21 AUD_BI_PORT_B_L 56A4
PORT-B-R 22 AUD_BI_PORT_B_R 56A4
PORT-C-VREFO 29 NO_TEST NC_AUD_VREF_PORT_C

BEEP 12 BEEP PORT-B-VREFO2 32 NO_TEST NC_AUD_VREF_PORT_D
PORT-G-L 43 NO_TEST NC_AUD_BI_PORT_G_L
8A5 6C1
IN
ACZ_RST_L 11 RESET* PORT-G-R 44 AUD_BI_PORT_G_R 54A8
PORT-H-L 45 NO_TEST NC_AUD_BI_PORT_H_L

CRITICAL PORT-H-R 46 NO_TEST NC_AUD_BI_PORT_H_R
R6203
1
1 C6208
THRM_PAD
100K 0.1UF VREF 27 AUD_CODEC_VREF
5%
40 AUD_CODEC_JDREF
1
R6209
AVSS1
AVSS2
1/16W 10% JDREF
DVSS
16V 100K
MF-LF 2 X5R
2 402 NC 37 NC_VRP 5%
402
NO_TEST 1
R6205 1/16W
MF-LF
20.0K
C6212 2 402
49
4
7
26
42
1% 1
1/16W
MF-LF 0.001UF
10%
NO STUFF 2 402 CRITICAL 50V
2 CERM
R6201
1 C6210 1
402
3.3UF
0 10%
5% 16V 2
1/16W TANT
MF-LF SMA-LF
2 402
B 56B1 56A8 56A4 55B3 54C8 54B8 54A8 53D3 53A7 8B4
56C4 56B8 56B5 56B4
=GND_AUDIO_CODEC
B
VOLTAGE=0V
AUDIO 4.5V REGULATOR

APPLE P/N 353S1576
MIN_NECK_WIDTH=0.20 MM L6200
FERR-220-OHM
U6201
VOLTAGE=5V LREG_TPS79501DRB
SON
56C4 7A7 6D1 =PP5V_S0_AUDIO 1 2 AUD_4V5_REG_IN 1 IN1 OUT1 3 PP4V5_AUDIO_ANALOG 53D3
0402 2 IN2 OUT2 4

8 EN NR/FB 5 4V5_REG_FB
R6202 1
R6210 1 C6224
1K GND THRM_PAD NC 80.6K 15PF
56B5 55D8 53D7 7C4 =PP3V3_S0_AUDIO 1 2 AUD_REG_SHDN_L 1% 5%
50V
1/16W 2 CERM
6
7
5% MF-LF
1/16W 402
MF-LF 2 402
402
CRITICAL
C6221 1 1 C6223 PLACE R6210, R6211, AND C6224 CLOSE TO U6201
1 C6220 10UF 0.001UF VOUT=1.2246V*[1+(R6210/R6211)]=4.58V 1
R6211
0.1UF
20%
6.3V 2
10%
2 50V 1%
29.4K AUDIO: CODEC
10% X5R CERM
16V 603 402 1/16W
2 X5R MF-LF
A 402 2 402 SYNC_MASTER=M70AUDIO

A
56B1 56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 8B4 =GND_AUDIO_CODEC
56C4 56B8 56B5 56B4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
NO STUFF AGREES TO THE FOLLOWING
1
5% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W
MF-LF
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 62 106
8 7 6 5 4 3 2 1
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SATELLITE & SUB TWEETER AMPLIFIER APN:353S1595
SATELLITE 169 HZ < FC < 282 HZ

SUB 80 HZ < FC < 132 HZ
D GAIN 12DB D
MIN_NECK_WIDTH=0.20 MM R6660 MIN_NECK_WIDTH=0.20 MM
0
54C4 SPKRAMP_R_P_OUT 2 1 SPKRCONN_R_P_OUT OUT 6B1 55C2
VOLTAGE=5V 5%
1/16W
MIN_LINE_WIDTH=0.60 MM MF-LF
402
54C8 54B8 7A7 6D1 =PP5V_S0_AUDIO_AMP
MIN_NECK_WIDTH=0.20 MM R6661 MIN_NECK_WIDTH=0.20 MM
0
54C4 SPKRAMP_R_N_OUT 2 1 SPKRCONN_R_N_OUT OUT 6B1 55C2
5%
PP5V_S0_AUDIO_F 54B8 54C8 1/16W
VOLTAGE=5V MF-LF
402
R6600 MIN_LINE_WIDTH=0.30 MM
0 MIN_NECK_WIDTH=0.20 MM
5% OMIT
RIGHT SATELLITE
1/16W CRITICAL
MF-LF C6607 1 C6602
402
1uF
1UF
1 1
C6601
10%
6.3V
1 10
10%
47UF
CERM 2 VDD PVDD 6.3V
20%
CRITICAL 402 CERM 2 2 6.3V
POLY
L6610 C6610 U6610 402 CASE-B3-SM
FERR-1000-OHM 0.047UF AUD_SPKRAMP_INR MAX9705
TDFN1
AUD_BI_PORT_D_R 1 2 AUD_SPKRAMP_INR_L 1 2 2 IN+ 8 SPKRAMP_R_P_OUT
53C7 IN OUT+ 54D3
0402
10%
MAX9705_R_N 3 IN- OUT- 9 SPKRAMP_R_N_OUT 54C3
16V CRITICAL SYNC 6
X7R 5 SHDN* MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
C 54B8 54A6 AUD_SPKRAMP_SHUTDOWN_L
402
CRITICAL GND PGND PAD
THRML
R6601
1
100
5%
SPKRAMP_L_P_OUT
R6670
2
0 1
SPKRCONN_L_P_OUT
C
C6611 1 4 7 11 1/16W
MF-LF
54B4
5%
OUT 6B1 55C2
0.047UF 1/16W
10% 2 402 MF-LF
16V 402
X7R 2
402 SPKRAMP_SYNC1 54A4
=GND_AUDIO_CODEC
55B3 54B8 54A8 53D3 53B7 53A7 8B4
56C4 56B8 56B5 56B4 56B1 56A8 56A4 SPKRAMP_THERMPLANE 54A4 54B4 MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
54B8 54A8 54A5 8A4 =GND_AUDIO_AMP MIN_NECK_WIDTH=0.20 MM R6671 MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT 2
0 1 SPKRCONN_L_N_OUT
54D8 54B8 7A7 6D1 =PP5V_S0_AUDIO_AMP 54B4 OUT 6B1 55C2
5%
54C4 54B8 PP5V_S0_AUDIO_F OMIT 1/16W
CRITICAL MF-LF
402
C6604 1 1
C6603
1UF 47UF
C6608 1 1 10 10%
6.3V
20%
LEFT SATELLITE
CRITICAL 1uF VDD PVDD CERM 2
402
2 6.3V
POLY
10% CASE-B3-SM
L6620 C6620 6.3V
CERM 2
U6620
FERR-1000-OHM 0.047UF 402 MAX9705
AUD_BI_PORT_D_L AUD_SPKRAMP_INL_L AUD_SPKRAMP_INL TDFN1
53C7 IN
1 2 1 2 2 IN+ OUT+ 8 SPKRAMP_L_P_OUT 54C3
0402
10%
MAX9705_L_N 3 IN- OUT- 9 SPKRAMP_L_N_OUT 54C3
16V
X7R CRITICAL SYNC 6 SPKRAMP_SYNC2 54A4
402 5 SHDN*
54C8 54A6 AUD_SPKRAMP_SHUTDOWN_L THRML
CRITICAL GND PGND PAD
C6621 1 4 7 11
0.047UF
10% MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
16V
X7R 2
402 MIN_NECK_WIDTH=0.20 MM R6680 MIN_NECK_WIDTH=0.20 MM
0
=GND_AUDIO_CODEC SPKRAMP_THERMPLANE SPKRAMP_SUB_P_OUT 2 1 SPKRCONN_SUB_P_OUT
B B
55B3 54C8 54A8 53D3 53B7 53A7 8B4 54A4 54C4 54A4 OUT 6A1 55C2
56C4 56B8 56B5 56B4 56B1 56A8 56A4
5%
54C8 54A8 54A5 8A4 =GND_AUDIO_AMP 1/16W
MF-LF
402
54D8 54C8 7A7 6D1 =PP5V_S0_AUDIO_AMP

54C8 54C4 PP5V_S0_AUDIO_F OMIT
CRITICAL MIN_NECK_WIDTH=0.20 MM R6681 MIN_NECK_WIDTH=0.20 MM
0
C6606 1 1
C6605 54A4 SPKRAMP_SUB_N_OUT 2 1 SPKRCONN_SUB_N_OUT OUT 6A1 55C2
1UF 120UF 5%
C6609 1 1 10 10%
6.3V 20% 1/16W
MF-LF
CRITICAL 1uF VDD PVDD CERM 2 2 6.3V
POLY 402
10% 402 CASE-B2
L6630 C6630 6.3V
CERM 2
U6630
FERR-1000-OHM 0.1UF 402 MAX9705
53B2 IN
AUD_BI_PORT_G_R 1 2 AUD_SPKRAMP_INSUB_L 1 2 AUD_SPKRAMP_INSUB 2 IN+
TDFN1
OUT+ 8 SPKRAMP_SUB_P_OUT 54B3 SUB-TWEETER
0402
10%
MAX9705_SUB_N 3 IN- OUT- 9 SPKRAMP_SUB_N_OUT 54B3
L6611 16V
X5R CRITICAL SYNC 6 SPKRAMP_SYNC1 54C4
FERR-1000-OHM 402 5 SHDN*
53C7 IN AUD_GPIO_0 1 2 THRML

GND PGND PAD
1
R6602
0402
4 7 11 100
5%
R6610 1 AUD_SPKRAMP_SHUTDOWN_L 54B8 54C8 CRITICAL 1/16W
MF-LF
10K
5%
C6631 1 2 402
1/16W 0.1UF
MF-LF 10%
402 2 16V
X5R 2 SPKRAMP_SYNC2 54B4
402
=GND_AUDIO_CODEC SPKRAMP_THERMPLANE
AUDI0: SPEAKER AMP
55B3 54C8 54B8 53D3 53B7 53A7 8B4 54A4 54B4 54C4
56C4 56B8 56B5 56B4 56B1 56A8 56A4
54C8 54B8 54A5 8A4 =GND_AUDIO_AMP
A SYNC_MASTER=M70AUDIO SYNC_DATE=03/12/2007
A
XW6600
SM
54C8 54B8 54A8 8A4 =GND_AUDIO_AMP 1 2 SPKRAMP_THERMPLANE 54A4 54B4 54C4
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 66 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
MIC CONNECTOR
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX APN:518S0392 CRITICAL
J6701
48227-0301
L6790 M-RT-SM1
4
FERR-220-OHM
D 53D7 53A7 7C4
56B5
=PP3V3_S0_AUDIO 1
0402
2
AUD_SPDIF_OUT
IN 53C2
55B1 6B1 MIC_LO_CONN 1
D
L6700 L6701 55B1 6B1 MIC_HI_CONN 2
FERR-120-OHM-1.5A FERR-120-OHM-1.5A 56A6 55A1 6B1 MIC_SHLD_CONN 3
AUD_CONNJ1_SLEEVE 1 2 AUD_CONNJ1_SLEEVE_F 1 2
55B8 PP3V3_S0_AUDIO_SPDIF 0402-LF 0402-LF 5
L6702
OMIT
AUD_CONNJ1_TIPDET
FERR-1000-OHM
1 2 AUD_CONNJ1_TIPDET_F SPEAKER CONNECTOR CRITICAL
J6702
78171-0002
CRITICAL
J6700 0402
APN:518S0519
M-RT-SM
3
AUDIO-OUT-M71-MG3 L6703 L6704
F-RT-TH
2 FERR-1000-OHM FERR-1000-OHM SPKRCONN_L_P_OUT 1
AUD_CONNJ1_RING_F 54C1 6B1 IN
3 1 2 1 2 AUD_PORTA_R BI 56C1 54C1 6B1 IN SPKRCONN_L_N_OUT 2
4 0402 0402
4
5 AUD_CONNJ1_RING L6705 L6706
1 FERR-1000-OHM FERR-1000-OHM CRITICAL
J6703
VCC
7 AUD_CONNJ1_TIP 1 2 AUD_CONNJ1_TIP_F 1 2 AUD_PORTA_L BI 56C1 78171-0004
6 0402 0402 M-RT-SM
GND 5
VIN 8
9 L6707
SHLD_PIN
10
FERR-1000-OHM R6700 54B1 6A1 IN SPKRCONN_SUB_P_OUT 1
SHLD_PIN AUD_CONNJ1_SLEEVEDET 1 2 AUD_CONNJ1_SLEEVEDET_F 1
10K 2 AUD_J1_SLEEVEDET_R SPKRCONN_SUB_N_OUT 2
OUT 56B6 56B8 54B1 6A1 IN
0402 5% SPKRCONN_R_P_OUT 3
APN:514-0459 NO STUFF 2
CRITICAL 1/16W
MF-LF
54D1 6B1 IN
SPKRCONN_R_N_OUT 4
DZ6700
DZ6704 402
54C1 6B1 IN
1 C6700 5.6V-15A CRITICAL 2
6.8V-100PF
402 R6701 APN:518S0521 6
1UF
C 10%
2 6.3V
CERM
0405 1 3
DZ6702
6.8V-100PF CRITICAL
1
CRITICAL
2
1
4.7
5%
2 AUD_J1_TIPDET_R OUT 56C8 C
402 402 2 1/16W
55A8 GND_AUDIO_SPDIF_DGND 1 3 DZ6703 DZ6705 MF-LF
XW6705
R6791 2 4
NO STUFF 1
6.8V-100PF 6.8V-100PF
402
SM
1
0 2 DZ6701 402 402
1 1 C6705 =GND_CHASSIS_AUDIO_JACK 1 2 CHASSIS_AUDIO_JACK_ISOL
5.6V-15A 100PF
8D8 55A3 55A8 55C8
5% 0405 1 5%
1/16W 2 4
MF-LF 2 50V
CERM
402 402
55C1 55A8 55A3 CHASSIS_AUDIO_JACK_ISOL
XW6700
SM
AUD_J1_COM 1 2
XW6701
SM
AUD_J2_COM 1 2 =GND_AUDIO_CODEC 8B4 53A7 53B7 53D3 54A8 54B8 54C8 56A4 56A8 56B1 56B4
56B5 56B8 56C4
AUD_J2_OPT_OUT
R6749
10 AUD_SPDIF_I
MIC EMI FILTER
1 2 OUT 53C2
5%
55D8 PP3V3_S0_AUDIO_SPDIF 1/16W
MF-LF
L6750 L6751 L6770 L6771
402 FERR-120-OHM-1.5A FERR-120-OHM-1.5A FERR-1000-OHM FERR-1000-OHM
MIC_LO MIC_LO_CONN_F MIC_LO_CONN
AUD_CONNJ2_SLEEVE 1 2 AUD_CONNJ2_SLEEVE_F 1 2 56A6 6B1 OUT
1 2 1 2 6B1 55D3
OMIT 0402-LF 0402-LF 0402 0402

CRITICAL L6752
J6750 FERR-1000-OHM
B AUDIO-IN-MG3-M71
F-RT-TH
1
0402
2 AUD_CONNJ2_TIPDET_F B
2 L6772 L6773
L6753 L6754 FERR-1000-OHM FERR-1000-OHM
4 AUD_CONNJ2_TIP FERR-1000-OHM FERR-1000-OHM MIC_HI 1 2
MIC_HI_CONN_F 1 2
MIC_HI_CONN
3 AUD_CONNJ2_TIPDET AUD_CONNJ2_RING_F 56A6 6B1 OUT 6B1 55D3
1 2 1 2 AUD_PORTC_R BI 56A2 0402 0402
5 AUD_CONNJ2_RING 0402 0402
1 CRITICAL
L6755 L6756 2
VCC
8
FERR-1000-OHM FERR-1000-OHM DZ6770
GND
7 6.8V-100PF
6
1 2 AUD_CONNJ2_TIP_F 1 2 AUD_PORTC_L BI 56B2 402
VOUT 0402 0402 CRITICAL
9 2 MIC_SHLD_CONN
SHLD_PIN
SHLD_PIN
10 L6757
1
DZ6771
FERR-1000-OHM R6750 6.8V-100PF 6B1 55D3 56A6
10K
402 1
R6740
APN:514-0458 AUD_CONNJ2_SLEEVEDET 1 2 AUD_CONNJ2_SLEEVEDET_F 1 2
1
0
5%
0402 5% 1/16W
1/16W MF-LF
MF-LF
1 3 402 2 402
NO STUFF
1 C6750 1 C6751 2 CRITICAL 2
R6751
1UF 10uF DZ6751 DZ6753 CRITICAL
4.7
10%
2 6.3V
20%
6.3V
2 X5R
5.6V-15A
0405 6.8V-100PF DZ6755 1 2 AUD_J2_TIPDET_R OUT 56A8
CHASSIS_AUDIO_JACK_ISOL
CERM
402 603 2 4 402 6.8V-100PF 5%
55C8 55C1 55A8
CRITICAL 2 2 402 1/16W

GND_AUDIO_SPDIF_DGND NO STUFF 1 3 CRITICAL MF-LF
55C8
DZ6750 DZ6752 1
DZ6754
1
402
6.8V-100PF
C6756
AUDIO: JACK
5.6V-15A 402 6.8V-100PF 1 TABLE_5_HEAD
0405 402 100PF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
1 1 5%
2 4 TABLE_5_ITEM
2 50V 514-0459 1 J6700 CRITICAL NORMAL
A
CERM CONN, 3.5MM COMBO AUDIO OUT, RA MG3, LF
SYNC_MASTER=M70AUDIO SYNC_DATE=03/12/2007
55C8 55C1 55A3 CHASSIS_AUDIO_JACK_ISOL
402
514-0458 1 CONN, 3.5MM COMBO AUDIO IN, RA, MG3, LF J6750 CRITICAL NORMAL
TABLE_5_ITEM
TABLE_5_ITEM
A
514-0479 1 CONN, 3.5MM COMBO AUDIO OUT, RA, BLACK, LF J6700 CRITICAL FANCY
TABLE_5_ITEM
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

514-0478 1 CONN, 3.5MM COMBO AUDIO IN, RA, BLACK, LF J6750 CRITICAL FANCY AGREES TO THE FOLLOWING
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 67 106
8 7 6 5 4 3 2 1
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CODEC OUTPUT SIGNAL PATHS

FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT
HP OUT 0X0F (15) 0X05 (5) 0X15 (21,PORTA) VREF_A(100%) 0X15 (21,PORTA)
SAT SPKR 0X26 (38) 0X25 (37) 0X14 (20,PORTD) GPIO 0 N/A
D SUB SPKR
SPDIF OUT
0X0E (14)
N/A
0X04 (4)
0X06 (6)
0X16 (22,PORTG)
0X1E (30,SPDIF OUT)
GPIO 0
N/A
N/A
0X1B (27,PORTE)
D
CODEC INPUT SIGNAL PATHS

FUNCTION MIXER VOLUME MUTE CONTROL CONVERTER PIN COMPLEX VREF DET ASSIGNMENT
LINE IN 0X23 (35) 0X08 (8) 0X08 (8) 0X08 (8) 0X1A (26,PORTC) N/A 0X1A (26,PORTC) HP/LO DE-POP SWITCH
MIC IN 0X24 (36) 0X07 (7) 0X07 (7) 0X07 (7) 0X18 (24,PORTB) VREF_B (80%) N/A
SPDIF IN N/A N/A N/A 0X0A (10) 0X1F (31,SPDIF IN) N/A N/A APN:353S1459 PORT A HP/LO
53A7 7A7 6D1 =PP5V_S0_AUDIO
OMIT
CRITICAL
C6830
100UF
1 2 AUD_PORTA_L OUT 55C3
1 C6836 MAX9890BETA+ 20%

1UF VCC 6.3V
1
R6834
U6801
POLY
53C2 IN AUD_BI_PORT_A_R 10%
B2
2 6.3V OMIT 27.4K
PORT A DETECT PORT E DETECT(SPDIF DELEGATE) CERM
402 TDFN CRITICAL 1%
OUT AUD_SENSE_B MAX9890_OUTL C6831 1/16W

53C2
INRCRITICALOUTL 100UF
MF-LF
402 2
OUT AUD_SENSE_A AUD_BI_PORT_A_L MAX9890_OUTR AUD_PORTA_R
1 2
56A8 53C2 53C2 IN INL OUTR OUT 55C3
20%
56B8 56B3 56A8 PP3V3_S0_AUDIO_F SHDN* AUD_VREF_PORT_A IN 6.3V
53C2
AUD_OUTJACK_INSERT_L 1 1
R6806 R6805 POLY
C
B2
C 1
R6801
1%
39.2K
1/16W
39.2K
1%
1/16W
CEXT
THM
MAX9890_CEXT
1
R6839
R6835
27.4K
1
270K Q6800 D 6 MF-LF

2 402
MF-LF
2 402
GND PAD 1 C6835 10K 1%
5%
1/16W SSM6N15FE AUD_PORTA_DET_L NC AUD_PORTE_DET_L NC 0.1UF 5%
1/16W
1/16W
MF-LF
MF-LF SOT563 10% MF-LF 402
16V 2
2 402 2 X5R 2 402
Q6801 D 3 Q6801 D 6 402
G S 1 SSM6N15FE SSM6N15FE =GND_AUDIO_CODEC

R6802 2
SOT563 SOT563
56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 53A7 8B4
56B8 56B5 56B4 56B1
47K
55C3 IN AUD_J1_TIPDET_R 1 2 AUD_J1_DET_RC
5%
1
1/16W 5 G S 4 2 G S 1
MF-LF
402
C6801
0.1UF
10% 16V
2 X5R 402
56C4 56B8 56B5
54B8 54A8 53D3 53B7 53A7 8B4 =GND_AUDIO_CODEC
PLACE L6800/C6800 CLOSE TO Q6800
56B4 56B1 56A8 56A4 55B3 54C8 L6800
R6803 FERR-1000-OHM
PP3V3_S0_AUDIO_F 1
100K 2 AUD_J1_SLEEVEDET_INV =PP3V3_S0_AUDIO 1 2 PP3V3_S0_AUDIO_F
56C8 56B3 56A8 55D8 53D7 53A7 7C4 56A8 56B8 56C8
5% 0402
1 1/16W
R6861 MF-LF
270K 402 1 C6800
5% Q6800 D 3 56B8 55C3 AUD_J1_SLEEVEDET_R
0.1UF
1/16W
MF-LF SSM6N15FE 10%
16V
SOT563
2 402 2 X5R
56B6 55C3 IN AUD_J1_SLEEVEDET_R 56A8 56A4 55B3 54C8 54B8 54A8 53D3 53B7 53A7 8B4 =GND_AUDIO_CODEC 402
56C4 56B8 56B4 56B1
5 G S 4
MIC INPUT CIRCUITRY PORT C LI
CRITICAL
1 C6802 R6850 R6855 C6832
B 0.01UF
10%
16V
1
6.81K
2 VREF_PORT_B_R 1
2.2K
2 AUD_VREF_PORT_B 53C2
2
3.3UF
1 AUD_BI_PORT_C_L
B
2 CERM 55B3 IN AUD_PORTC_L OUT 53C7
1/16W 1% 1/16W 5%
402 MF-LF 402 MF-LF 402
56C4 56B8 56B5 1 10%
54B8 54A8 53D3 53B7 53A7 8B4 =GND_AUDIO_CODEC CRITICAL R6836 16V
56B4 56B1 56A8 56A4 55B3 54C8
1 TANT
C6853 27.4K SMA-LF
1%
10UF 1/16W
20%
6.3V MF-LF
2 X5R 402 2
603 =GND_AUDIO_CODEC 8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A4 56A8 56B4
56B5 56B8 56C4
1
=GND_AUDIO_CODEC 8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A4 56A8 56B1
R6837
27.4K
Line-in (PORT C) DETECT 56B5 56B8 56C4
1% CRITICAL
R6851 C6850
0.1uF
1/16W
MF-LF
402
C6833
56C8 53C2 AUD_SENSE_A
MIC_HI
330
MIC_IN
2 3.3UF
55B3 6B1 IN 1 2 1 2 AUD_BI_PORT_B_L 53C2
2 1
MAKE_BASE=TRUE 55B3 IN AUD_PORTC_R AUD_BI_PORT_C_R OUT 53C7
1/16W 5%
R6813 1
CRITICAL
MF-LF 402 10% 16V
X5R 402
10%
56C8 56B8 56B3 PP3V3_S0_AUDIO_F 10K 1
R6852 CRITICAL AUD_BI_PORT_B_R 53C2 16V
5% C6851 1
100K
CRITICAL TANT
1/16W 680PF 1 SMA-LF
MF-LF 10% 5% C6852 NO STUFF
402 2 1/16W
1
R6811
50V
CERM 2 MF-LF 100PF
5% PLACE C6852 NEAR U6200
270K
5%
AUD_INJACK_INSERT_L NC 402 2 402 XW6800
SM
50V
CERM 2
402
1/16W
MF-LF
2 402
Q6802 55B3 6B1 IN MIC_LO 1 2 =GND_AUDIO_CODEC 8B4 53A7 53B7 53D3 54A8 54B8 54C8 55B3 56A8 56B1 56B4
56B5 56B8 56C4
SSM3K15FV D 3 NO STUFF
SOD-VESM R6853
R6812 MIC_SHLD_CONN 0
1 2
55D3 55A1 6B1 IN
47K
55A3 IN AUD_J2_TIPDET_R 1 2 AUD_J2_DET_RC 5%
1/16W
AUDIO: JACK TRANSLATORS
5% MF-LF
A A
1
1/16W 1 G S 2 402 SYNC_MASTER=M70AUDIO SYNC_DATE=03/12/2007
MF-LF C6811
402
0.1UF NO STUFF
10% 16V R6854 NOTICE OF PROPRIETARY PROPERTY
2 X5R 402 0
56C4 56B8
1 2 =GND_CHASSIS_AUDIO_MIC 8D8 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
54B8 54A8 53D3 53B7 53A7 8B4 =GND_AUDIO_CODEC PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
56B5 56B4 56B1 56A4 55B3 54C8 5% AGREES TO THE FOLLOWING
1/16W
MF-LF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402
NO STUFF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R6856
051-7559
1 2
5%
1/16W
D H
MF-LF
402 APPLE INC. SCALE SHT OF
NONE 68 106
8 7 6 5 4 3 2 1
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D
DC-JACK INTERFACE R6905
47
5%
CRITICAL
D6901
HN2D01JEF
SOT665
D
1/8W
MF-LF
805 5
1 2 PPDCIN_G3H_R 1 =PPDCIN_G3H 7B3
518S0526 BATT_POS_F
1 2 PPVBATT_G3H_R 3 4
CRITICAL
INRUSH LIMITER
66B2 57B2
CRITICAL
CRITICAL R6940 Q6950
J6900 F6900 47
5% NC
2
AO4409
87438-0563 6AMP-24V 1/8W
MF-LF
SOI
M-RT-SM VOLTAGE=18.5V
1206-1 PP18V5_DCIN
805 MIN_LINE_WIDTH=0.6 MM 8 =PP18V5_G3H_INRUSH7B3
1 PP18V5_DCIN_F 1 2 MIN_NECK_WIDTH=0.20 MM 3 D4
S3 7 VOLTAGE=18.5V
VOLTAGE=18.5V 2 D3 MIN_LINE_WIDTH=0.6 MM
2
3
MIN_LINE_WIDTH=2 MM 1
MIN_NECK_WIDTH=0.20 MM C6902
0.01uF R6902 ONEWIRE_PWR_EN_L
1
1
S2
D2
6 MIN_NECK_WIDTH=0.20 MM
4 10% 1K
1 2 R6904 S1 D1 5
Q6910 47K 2
ACIN DETECTION
2 25V GATE
CRITICAL 5 X7R
402
5%
1/16W
MF-LF
SSM6N15FE R6911
D 3 100K
5%
2 1/16W R6913
1
1 C6917 4
D6900
SC-75 1 NC 6C1
SMC_BC_ACOK
1
402
2 SMC_BC_ACOK_ONEWIRE_R
SOT563
5%
1/16W
MF-LF
402 S 66A5 7B1
=PP3V42_G3H_ACIN 470K
5% 0.22UF
20%
MF-LF 1/16W
2 25V
44C5 66B8 66A8
C6907 C6918
45B6
3
=GND_DCIN_CHGND 66A6 57C3 1 402 1 MF-LF X5R
8C8 1 2402 603
0.001UF ONEWIRE_PWR_EN_L_DIV
G
R6908 1 0.1UF
2 ADAPTER_SENSE 10%
2 50V
5 G S 4 D R6906
1
102K
10%
2 25V
44D5
33C7 6C1SMC_ADAPTER_EN
CERM
402 Q6940 3
102K
1% 1% X5R
402
38C6 35C7
45B3
ACIN_ENABLE_L_DIV
RCLAMP2402B NTK3142P 1/16W
MF-LF
1/16W
MF-LF CRITICAL MIN_LINE_WIDTH=0.2 MM
SOT723-3
2402 2 402 U6950 MIN_NECK_WIDTH=0.2 MM
SYS_ONEWIRE
6 SYS_ONEWIRE_BILAT
1 CRITICAL R6914
1
4 S
3 D
45D5 44B8 6C1 TC7SZ08AFEF
U6900 5 SOT665 330K
D
2 2
PP18V5_DCIN_ONEWIRE ACIN_1V20_REF 4 TLV7211 A 5%
Q6920 - SC70 4 1/16W
ACIN_ENABLE_GATE
V+ MF-LF
Q6920 Y
G
G 5
SSM6N15FE 2402
C 2
1 1
C
OVP
B
SOT563 SSM6N15FE1 R6932
SOT563
1
R6901 1
R6933 ACIN_DIV 3
+ V- 3
24.3K 1% 1%
1K 5%
100K 5 ACIN_ENABLE_L
R6903
NC
1/16W
MF-LF
1
10K 1 C6930
1/16W
MF-LF
1/16W
MF-LF R6910
1M
6
2 402 5% 2 402 2 402
1/16W 0.1UF 5%
ONEWIRE_EN MF-LF
2 402
10%
2 25V
5
1 ONEWIRE_DCIN_DIV R6907 1R6909
1 1/16W
MF-LF
402
D 6 Q6910
X5R 10.7K 51.1K 66A6
SSM6N15FE
Q6999 ONEWIRE_OV
402
4
V+ 1%
1/16W
1%
1/16W
1 2 SMC_BC_ACOK 45B6
6C1
SOT563
SSM3K15FV 1
R6931
44C5
57C7
3 D MF-LF MF-LF 66A6 6C1
SOD-VESM 3 ONEWIRE_ESD 100K 2402 2 402
CRITICALV- 5%
U6990 2 1/16W
MF-LF
2 G S 1
1
R6900
100K
1 C6903 LM397
SOT23-5
2 402
5% 0.001UF G 1
1/16W 10% 2 S
MF-LF 2 50V
CERM
TABLE_ALT_HEAD
2 402 402 PART NUMBER ALTERNATE FOR

PART NUMBER
TABLE_ALT_ITEM
376S0466 376S0543 ? Q6950 AOS MOSFET

TABLE_ALT_ITEM
353S1717 353S1297 ? U6990 TI & NATIONAL
B
BATTERY INTERFACE B
L6901
FERR-50-OHM
SM-LF
6D1 BATT_POS 1 2 BATT_POS_F

57D5 66B2
L6902
L6909 120-OHM-0.3A-EMI
2 1 0402-LF
600-OHM-300MA
0402 4 3
6D1 SMBUS_BATT_SCL_F 1 2 =SMBUS_BATT_SCL 47C1
6 5
7B1 =PP3V42_G3H_LIDSWITCH 1 2
NC 8 7 NC
10
VOID
9 SMBUS_BATT_SDA_F
L6903
6D1
120-OHM-0.3A-EMI
12 11 6D1 BATT_NEG 0402-LF
L6907 14 13
1 2 =SMBUS_BATT_SDA
600-OHM-300MA 16 15 47C1
0402
PP3V42_G3H_LIDSWITCH_F 18 17 SMC_BS_ALRT_L_F
1 2 GND_SMC_LID_F 20 19 L6904
120-OHM-0.3A-EMI
0402-LF
CRITICAL 1 2 SMC_BS_ALRT_L
L6908 J6950
6D1 44C5 45C5
600-OHM-300MA
0402 127216FA020
F-ST-SM
1 C6911
0.001UF
1 C6905
0.001UF
1 C6909
0.001UF
1 C6915
47pF
1 C6906
47pF L6905 DC-In & Battery Connectors
FERR-50-OHM SYNC_MASTER=POWER SYNC_DATE=07/13/2005
A
1 2 10% 10% 10% 5% 5%
A
45C5 44B5 42C3 6B2 SMC_LID SMC_LID_F
2 50V
CERM
50V
2 CERM 2 50V
CERM 2 50V
CERM 2 50V
CERM
SM-LF
402 402 402 402 402 NOTICE OF PROPRIETARY PROPERTY
1 2
1 C6920 1 C6921 57A6 8D8 =GND_BATT_CHGND THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0.01uF 0.01uF AGREES TO THE FOLLOWING
10% 10% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2 16V
CERM 2 16V
CERM
=GND_BATT_CHGND MLB TOP VIEW III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
8D8 57A6
LID HALL EFFECT SENSOR

PIN 1
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 69 106
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S0 FETS & POWER SEQUENCING & PGOOD

D D
CRITICAL
Q7000
FDM6296
MICROFET3X33
2
=PP5V_S0_FET 7A8 58C8 1.05V S0 RUN/SS CONTROL
65B5 58C6 58B3 7C1 =PP5V_S5_FET
5
D S
1
5V S0 FET R7030 R7031
100K 330
TABLE_ALT_HEAD
G C7003 MOSFET FDM6296 5%
1/16W
5%
1/16W
0.0022UF MF-LF MF-LF
PART NUMBER
BOM OPTION REF DES COMMENTS: 4
10% CHANNEL N-TYPE 58C4 58C3 58B8 58B3 58A3
=PP3V3_S0_FET
7D6 2
402
1 1V05S0_RUNSS_BUF
2
402
1 1V05S0_RUNSS 61B5
50V
RDS(ON) 15 mOhm @4.5V
TABLE_ALT_ITEM
376S0448 376S0445 ? Q7000 CERM

402
P5VS0_EN 1 2
LOADING 4.348 A Q7007
D 6
SSM6N15FE 1 C7030
CRITICAL SOT563 0.01UF
Q7001
FDC655BN
10%
2 16V
CERM
65C4 65A5 7D1 =PP3V3_S5_FET
1
D
SOT6 =PP3V3_S0_FET 7D6 58A3 58B3 58B8 58C3 58D3 2 G S 1 402
2 58C2 58B2 RUNSS_GATE_D_L
5
6
S
G 3
4
3.3V S0 FET
C7004 MOSFET FDC655BN
0.0022UF
10%
50V
CHANNEL N-TYPE 1.25V S0 RUN/SS CONTROL
CERM
402 RDS(ON) 33 mOhm @4.5V R7041 R7040
P3V3S0_EN 1 2 100K 330
LOADING 1.810 A C
C 5%
1/16W
MF-LF
5%
1/16W
MF-LF
7D6 =PP3V3_S0_FET
2
402
1 1V25S0_RUNSS_BUF
2
402
1 1V25S0_RUNSS 64B6
CRITICAL 58D3 58C4 58B8 58B3 58A3
Q7004
FDC655BN =PP1V8_S0_FET D 3
7B4 =PP1V8_S3_FET
1
D
SOT6 7B8 58B8
Q7006 1 C7040
2 SSM6N15FE
SOT563 0.0012UF
5
6 G 3 1.8V S0 FET 5 G S 4
10%
2 50V
CERM
402
=PP5V_S5_FET S 4
58D4 7A8 =PP5V_S0_FET 2 1 65B5 58D5 58B3 7C1
MOSFET FDC655BN 58C2 58B2 RUNSS_GATE_D_L
1 C7005
R7001 1
R7002 C7000
1UF
0.0022UF CHANNEL N-TYPE
23
30.9K 4.87K 10%
6.3V RDS(ON) 33 mOhm @4.5V
1.5V S0 RUN/SS CONTROL
1% 1% 2 10%
50V
CERM
1/16W 1/16W CERM VDD 402
MF-LF
402
MF-LF
2 402
402
U7000 P1V8S0_EN 1 2 LOADING 0.260 A
ISL6130IRZA
QFN
62A3 PGOOD_1V8S3 20
12
S0PWRGD_5V_DIV
UVLO_A GATE_A 2
5
R7050
10K
R7051
330
UVLO_B GATE_B
5% 5%
58D3 58C4 58C3 58B3 58A3 7D6 =PP3V3_S0_FET
2 1 S0PWRGD_3V3_DIV
17 UVLO_C GATE_C 6 1/16W
MF-LF
1/16W
MF-LF
S0PWRGD_1V8_DIV
14 7 RUNSS_GATE_D
R7003 R7004
1 UVLO_D GATE_D
2
402
7D6 =PP3V3_S0_FET 1 1V5S0_RUNSS_BUF
2
402
1 1V5S0_RUNSS 6D7 61B5
28.7K 7.5K CRITICAL 58D3 58C4 58C3 58B8 58A3
1% 1% DLY_ON_A 21 TP_DLY_ON_A
1/16W 1/16W 8 TP_DLY_ON_B 65B5 58D5 58C6 7C1 =PP5V_S5_FET D 3
MF-LF
402
MF-LF
2 402 S0SEQ_BEGIN 1 ENABLE_1
DLY_ON_B
16 TP_DLY_ON_C 1
R7061 Q7007 1 C7050
DLY_ON_C SSM6N15FE 0.001UF
DLY_ON_D 15 TP_DLY_ON_D 470K
5%
SOT563 10%
2 50V
CERM
B 58C4 7B8 =PP1V8_S0_FET
2 1 NC 19 NC DLY_OFF_A 18 DLY_OFF_A
13 DLY_OFF_B
1/16W
MF-LF
2402 5 G S 4
402
B
NC DLY_OFF_B
RUNSS_GATE_D_L
R7005 R7006
58C2
1 DLY_OFF_C 3 DLY_OFF_C
NC 11 ENABLE_2*
22.1K
1%
13.7K NC 22 DLY_OFF_D 4 DLY_OFF_D
1% NOSTUFF NOSTUFF D 6
1/16W
MF-LF
402
1/16W
MF-LF
SYSRST*
RESET0* 24
1
NOSTUFF 1
C7024 C7021 1 C7022 1 C7023 Q7006
2 402 RESET1* 9 0.01UF 0.01UF
10%
0.01UF
10%
0.022UF
10%
SSM6N15FE
SOT563
THML 10%
16V 2 16V
CERM 2 16V
CERM 2 16V
CERM-X5R
GND PAD 2 CERM 402 402 402
402 2 G S 1
PM_SLP_S3_L 1 2
25
10
62B8 45A6 44C5 35C7 33C7 24D3
R7007
47
~26MS
5%
1/16W
MF-LF
402 DEASSERTED 160MS
AFTER UVLO_D VALID
=PP3V3_S0_FET 7D6 58B3 58B8 58C3 58C4 58D3
R7012
1
1 C7001
0.1UF
100K 10%
5% 2 16V
X5R
1/16W 402
6
MF-LF
PGOOD_SEQUENCER 2 402 VDD
1 CRITICAL 5 =PP1V25_S0_FET
PGOOD_1V05S0 RESET* U7002 SENSE 7C7
61A6
TPS3808-1.25V S0 FETS & Power Sequencing
61A3 PGOOD_1V5S0 ALL_SYS_PWRGD_AND 3 MR* SOT23-6 CT 4 ALL_SYSPWRGD_DLY
A MAKEBASE=TRUE
U7002.3 has int 90K pull-up
GND 1 C7002
0.001UF
SYNC_MASTER=DSIMON-WF SYNC_DATE=05/31/2006
A
2
10% NOTICE OF PROPRIETARY PROPERTY
2 50V
CERM
402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
ALL_SYS_PWRGD 6B2 27A5 44D8 II NOT TO REPRODUCE OR COPY IT
D 051-7559
LATEST ISSUE: 2007/01/02
H
NONE 70 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
7A7 =PP5V_S0_CPU_IMVP 59D8 59C2 48D7 7B1 =PPVIN_S5_CPU_IMVP

5
CRITICAL CRITICAL
1 2 PP5V_S0_IMVP6_VDD
1 C7109
33UF
1 C7117
33UF
1 C7118
1 C7126 MIN_NECK_WIDTH=0.2 MM CRITICAL 20% 20%
1UF
10%
R7112 1UF VOLTAGE=5V
C7135 DPRSLPVR DPRSTP* PSI* Operation Mode
Q7100 2 16V
POLY 2 16V
POLY
25V
X5R
10 10%
6.3V
1
10UF 4 CASED2E-SM CASED2E-SM 2 603
5% CERM 20% 0 1 1 2-Phase CCM RJK0305DPB
D
1/16W 2
D
MF-LF
402
402
2
6.3V
X5R
603
LFPAK
PWM FREQ. = 300 kHz
59C2 48D7 7B1 =PPVIN_S5_CPU_IMVP 1 2 PPVIN_S5_IMVP6_VIN 0 1 0 1-Phase CCM
MAX CURRENT = 44A
59D4 MIN_LINE_WIDTH=0.25 MM
R7120 1 C7196 MIN_NECK_WIDTH=0.2 MM
1 0 1 1-Phase DCM 1 2 3
10 0.01UF
10% (IMVP6_PHASE1) 1 2
=PPVORE_S0_CPU_REG 7D8
5%
1/16W
MF-LF 2
16V
CERM 1 0 0 1-Phase DCM CRITICAL
24C3 15A6
70B3 IN
PM_DPRSLPVR 402 402 5 5 L7100
MIN_LINE_WIDTH=0.25 MM CRITICAL CRITICAL 0.36UH-30A-0.80MOHM
MIN_NECK_WIDTH=0.2 MM 1 2 IMVP6_BOOT1_RC MPC1055-SM
7C4 =PP3V3_S0_IMVP1 2 PP3V3_S0_IMVP6_3V3
4
Q7101 4
Q7104 MPC1055LR36
DCR=0.8mOhm
R7124 RJK0301DPB RJK0301DPB
R7121 1 C7130 0
5%
LFPAK LFPAK 1 2
10 0.1uF NO STUFF
5%
1/16W
10%
16V
1/16W
MF-LF
402
R7151
10K
MF-LF 2 X5R 1%
402 402 1 2 IMVP6_BOOT2_RC 1/16W
GND_IMVP6_SGND MF-LF
59B7 59A4 20 22 31 1 2 3 1 2 3 402
NO STUFF NO STUFF R7125 C7127 1
C7115 1 2
R7127 R7126
VIN VDD PVCC
0 1 0.1UF
0.1UF 1 2 1 2
4.02K 470K 70A3 10B7 CPU_VID<6> 43 VID6 59A8 36
BOOT1 IMVP6_BOOT1 5%
10%
10%
1%
1/16W 402 CRITICAL
10B7 CPU_VID<5>
42 VID5 CRITICAL59A6 26 IMVP6_BOOT2
1/16W
MF-LF
16V NO STUFF NO STUFF R7100 C7103 R7104
MF-LF
402
70A3
10B7 CPU_VID<4>
41 VID4 U7100BOOT2 402 2
16V
X5R
2 X5R
402 1 C7100 1 C7190 10K
1%
0.22uF 1
5%
1 2 1 2 70A3
QFN 402 0.0022UF 0.0022UF 1/16W 10% 1/16W
10B7 CPU_VID<3> IMVP6_UGATE1
40 VID3 35 10% 10% MF-LF 6.3V MF-LF
ISL9504BCRZ
UGATE1
59A8
CERM-X5R
1
R7145 70A3
10B7 CPU_VID<2>
39 VID2
34 2
50V
CERM
2 50V
CERM
402
402
402
NO STUFF 499 70A3 PHASE1
59A8 IMVP6_PHASE1 402 402
10B7 CPU_VID<1>
38 VID1
C7110 ERT-J0EV474J 1%
1/16W
70A3
10B7 CPU_VID<0>
0.01uF 37 VID0 LGATE1
32 IMVP6_LGATE1
MF-LF 70A3 59A8
10% IMVP6_NTC_R 2 402 (GND)
16V PGND1
33
CERM 70B3 22C4 15B6 9B2 CPU_DPRSTP_L 46 DPRSTP*
402 IN
70B3 IMVP_DPRSLPVR 45 DPRSLPVR ISEN1
24 IMVP6_ISEN1 (IMVP6_ISEN1)
C
59A8
C
1 2
IN IMVP6_PSI_L
27B2
2 PSI*
NO STUFF 3 IMON 59A6 27 IMVP6_UGATE2
R7106 44C5
48C1 OUT
1
SMC_CPU_ISENSE 2 IMVP6_PMON UGATE2
=PPVIN_S5_CPU_IMVP 59D8
0 NO STUFF IMVP6_PHASE2
59D4
59A6 28
7B1
5%
1/16W R7146 48 3V3 PHASE2
CRITICAL CRITICAL
48D7
4.53K C7199
70C3 45C3 45B5 9C5
CPU_PROCHOT_L 402
1
MF-LF
2
1% 27A7
1/16W OUT
VR_PWRGD_CK505_L 47 CLK_EN*
44 VR_ON
59A6 30
LGATE2 IMVP6_LGATE2 5 1 C7101
33UF
1 C7108
33UF
1
1UF
1
R7101
FROM SMC MF-LF IMVP_VR_ON 29 (GND) 10%
25V 3.65K
402 IN
PGND2 20% 20% 1%
27B5 15B6 VR_PWRGOOD_DELAY 1 PGOOD 2 16V 2 16V 2 X5R 1/16W
1 2 OUT POLY POLY 603 MF-LF
IMVP6_VR_TT 5 VR_TT* CASED2E-SM CASED2E-SM 2 402
R7108 59A6 23
ISEN2 IMVP6_ISEN2 4
C7105 IMVP6_NTC 6 NTC
147K
0.015uF 1%
1/16W VSUM
19 IMVP6_VSUM CRITICAL
Q7102
59A4
10% MF-LF 59A4 IMVP6_SOFT 7 SOFT
16V
X7R
402 OCSET 8 59A4 IMVP6_OCSET
402 1 2 59A4 6D7 IMVP6_RBIAS 4 RBIAS VO
59A4 48C5
18 IMVP6_VO NO STUFF RJK0305DPB
1 1 2 3 LFPAK
DROOP
59A4 48D5 16 IMVP6_DROOP C7116 (IMVP6_PHASE2) 1 2
59A4 IMVP6_VDIFF 13 VDIFF 0.001UF CRITICAL
17 2
IMVP6_DFB 1 2 10%
1 C7106 1 2 IMVP6_FB2 12 FB2
DFB
59A4
50V 5
CRITICAL 5
CRITICAL L7101
0.001UF 59A4
CERM 0.36UH-30A-0.80MOHM
1
R7118 R7117 C7129
10%
50V
CERM
NO STUFF IMVP6_FB
59A4
59A4 6D7 IMVP6_COMP

11 FB
10 COMP
VSEN
14
15 1K 4.32K
1
180pF
402
Q7103 Q7105 MPC1055-SM
MPC1055LR36
1
R7109
2 402 R7113 RTN 1%
1/16W
1%
1/16W 5%
1
R7116 RJK0301DPB RJK0301DPB DCR=0.8mOhm
1K 59A4 IMVP6_VW 9 VW MF-LF MF-LF 2 50V 13.7K 4 LFPAK 4 LFPAK
IMVP6_VSEN
1K 1%
2 402
402 1%
IMVP6_VDIFF_RC CERM
IMVP6_RTN
1% 1/16W 1 2 1/16W 1 2 1 2 1 2
1/16W MF-LF 402 MF-LF
MF-LF 402 25 NC
2 402
2 402
1
R7111 C7131 (IMVP6_VO) R7105 C7104 R7107
255 GND TPAD 0.068UF 10K
1%
0.22uF 1
5%
1% 10% 10%
1/16W 21 49 1 2 3 1 2 3 1/16W 1/16W
MF-LF
2 402
10V
CERM
402
1
R7130 MF-LF
402
6.3V
CERM-X5R
MF-LF
402
1 2
59A4 59A4
3.92K 402
(IMVP6_FB) 1%
GND_IMVP6_SGND
B
59A4
59C8
(IMVP6_VW) NO STUFF C7134 1 C7128 1

R7115
1/16W
MF-LF
2 402
NO STUFF
C7102 1
NO STUFF
C7192
NO STUFF
1 2 B
1 C7114 C7132 1
0.033UF 0.22UF 11K
IMVP6_VO_R 1
0.0022UF 0.0022UF
1
R7143 R7152
470PF 0.01UF 10% 10% 1% 10% 10% 3.65K 10K
10% 16V 6.3V 1 1%
50V 10% X5R CERM-X5R 1/16W 50V 2 50V 1% 1/16W
CERM 16V 2 402 2 402 MF-LF 2 CERM 1/16W MF-LF
2 402 CERM 2 402 CRITICAL CERM 402 MF-LF 402
C7113 402 R7131 402 2 402
1
220PF 1 C7107 1
R7110 1 2 10KOHM-5%
IMVP6_COMP_RC 5% 0.001UF 6.81K (IMVP6_ISEN2)
25V 10% 1% 0603-LF
2 CERM 50V 1/16W
402 CERM
1
R7114
2 402 MF-LF
2 402
C7133 2
ERT-J1VR103J (IMVP6_VSUM)
0.018UF
97.6K 10%
1% 16V (IMVP6_VO)
1/16W X7R
MF-LF 402
2 402 (IMVP6_COMP)
1 2 R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.
2 C7121 R7123
1 1
R7122
OMIT 0 0
TABLE_ALT_HEAD
0.22uF PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
XW7100
SM
10%
6.3V
5%
1/16W
5%
1/16W
PART NUMBER
CERM-X5R MF-LF MF-LF TABLE_ALT_ITEM
1 402 2 402 2 402 128S0093 128S0092 ? C7101,C7108 KEMET T520V336M016ATE0457650

CPU_VCCSENSE_P 10A6 59A4 70A3 MIN_LINE_WIDTH MIN_NECK_WIDTH TABLE_ALT_ITEM
128S0093 128S0092 ?
CPU_VCCSENSE_N 10A6 59A4 70A3
59B6
IMVP6_OCSET 0.25 MM 0.20 MM
C7109,C7117 KEMET T520V336M016ATE0457650
59C6
IMVP6_VSUM 0.25 MM 0.20 MM
IMVP6 CPU VCORE REGULATOR

59C8 59B7
GND_IMVP6_SGND 0.50 MM 0.20 MM
IMVP6_VO 0.25 MM 0.20 MM
IMVP6 CPU VCore Regulator
59B6 48C5
59B6 48D5
IMVP6_DROOP 0.25 MM 0.20 MM
IMVP6_DFB 0.25 MM 0.20 MM
A SYNC_MASTER=POWER SYNC_DATE=07/13/2005
A
59B6
59C7
IMVP6_SOFT 0.25 MM 0.20 MM
59B7 6D7
IMVP6_RBIAS 0.25 MM 0.20 MM NOTICE OF PROPRIETARY PROPERTY
MIN_LINE_WIDTH MIN_NECK_WIDTH MIN_LINE_WIDTH MIN_NECK_WIDTH 59B7
IMVP6_VDIFF 0.25 MM 0.20 MM
59C6
IMVP6_PHASE1 1.5 MM 0.25 MM 59C6
IMVP6_PHASE2 0.25 MM 0.25 MM 59B7
IMVP6_FB2 0.25 MM 0.20 MM
59C6
IMVP6_BOOT1 0.25 MM 0.25 MM 59C6
IMVP6_BOOT2 0.25 MM 0.25 MM 59B7
IMVP6_FB 0.25 MM 0.20 MM
59C6
IMVP6_UGATE1 1.5 MM 0.25 MM 59C6
IMVP6_UGATE2 0.25 MM 0.25 MM 59B7 6D7
IMVP6_COMP 0.25 MM 0.20 MM
59C6
IMVP6_LGATE1 1.5 MM 0.25 MM 59C6
IMVP6_LGATE2 0.25 MM 0.25 MM 59B7
IMVP6_VW 0.25 MM 0.25 MM
59C6
IMVP6_ISEN1 0.25 MM 0.25 MM 59C6
IMVP6_ISEN2 0.25 MM 0.25 MM 59A5 10A6
CPU_VCCSENSE_P 0.25 MM 0.25 MM
70A3
70A3 59A5 10A6
CPU_VCCSENSE_N 0.25 MM 0.25 MM SIZE DRAWING NUMBER REV.
59B6
IMVP6_RTN
IMVP6_VSEN
0.25 MM 0.25 MM
D 051-7559 H
LATEST ISSUE: 2007/01/23 59B5

0.25 MM 0.25 MM
APPLE INC. SCALE
NONE
SHT
71
OF
106
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D
RENDER VCORE POWER SUPPLY D
60C5 60A7 60A5 GND_GCORE_SGND 2 1 60A7 GCORE_VDD1 2

=PP5V_S0_NB_GFX_IMVP
7A7
R7217
150K R7202
1%
1/16W
C7221
1UF
10
5%
MF-LF 10% 1/16W
402 6.3V MF-LF TABLE_ALT_HEAD
CERM 402 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
1 2 GCORE_RBIAS PART NUMBER
60A5
402 1
60A7 GCORE_PVCC 2
TABLE_ALT_ITEM
128S0093 128S0092 ?
2 1 60A5 GCORE_SOFT
C7202 R7203 C7217 KEMET T520V336M016ATE0457650
C7215 NO STUFF 1
2.2UF 1
TABLE_ALT_ITEM
104S0023 104S0018 ? R7205 CYNTEC RL-1632-3A-R002-FNH
0.015UF R7218 20% 5%

6.3V 1/16W
=PP3V3_S0_NB_GFX_IMVP 7C4 10% 4.53K 2 CERM1
MF-LF
402
16V
X7R
1%
1/16W
603
60A7 GCORE_VIN 1 2
=PPVIN_S5_NB_GFX_IMVP 7B1
402 MF-LF
NO STUFF NO STUFF 1 402
R7221
1
R7222
1 R7220 SMC_GPU1_ISENSE1 2 GCORE_PMON 1 C7200 R7200
C7218 1 CRITICAL
60B2 44A2
30K 0.01UF 10 5 1
10K 10K 5% 1 2 10% 5% 1UF C7217
16
22
1% 1% 2 25V 1/16W
33UF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF R7225
100K R7224 VDD PVCC
X7R
402 MF-LF
402
CRITICAL 2
10%
25V 20%
2402 2402 2 402
5% 10K
GND_GCORE_SGND 60A5 60A7 60D7
Q7200 X5R
603 2 16V
POLY
1/16W
MF-LF
5%
1/16W U7200
CRITICAL
4 RJK0305DPB
LFPAK
CASED2E-SM
402 MF-LF
402 1 RBIAS QFN
VIN 14 R7201 C7201
0.1UF
ISL6263B
0
1 2
2 SOFT
18 GCORE_UGATE 1/16W
5% 10%
16V CRITICAL PWM FREQ. = 333 kHz
UGATE
60A7
MF-LF
402
X5R
402 1 2 3
L7200
0.82UH-16.5A MAX CURRENT = 7.7A
C 28 IMON BOOT 17 GCORE_BOOT 1
60A7 2
2 GCORE_BOOT_RC 1
IHLP2525EZ-SM
1 2
CRITICAL =PPVCORE_S0_NB_GFX_IMVP C
1 2
NC 31 PGOOD PHASE
60A7 19 GCORE_PHASE 1 2 7B8
R7223
10K
15B3
21B6
GFX_VID<0>
GFX_VID<1>
23
24
VID0
R7205 GPU_ISENSE_VCC 1 2 =PP3V3_S0_PDCISENS
VID1
5%
15B3
0.002 7C4 61C5 66C3
1/16W
MF-LF
21B6
15B3 GFX_VID<2> 25 VID2
5
1%
1/4W
C72231 R7226
402
21B6
15B3 GFX_VID<3> 26 VID3 MF-LF 0.1UF
10% 100
21B6 1206 1%
1 C7214 1 C7213 15A3 GFX_VID<4> 27 VID4 CRITICAL GPU_ISENSE_R1_N
16V
X5R 1/16W
MF-LF
Q7201
2
8B1 GFX_VR_EN 29
402 402
0.001UF 0.001UF VR_ON
10%
2 50V
CERM
10%
2 50V
CERM
GCORE_AF_EN 30
GCORE_FDE 32
AF_EN LGATE
60A7 21 GCORE_LGATE 4 RJK0303DPB
LFPAK
1
R7206
2.21K
Placement Note:
402 402 FDE 7 PLACE C7221 NEAR U7201 PIN 7
1% 2
60A5 GCORE_VSEN 8 VSEN 1/16W
MF-LF 1 R1- V+ 4 PLACE RC CLOSE TO SMC
60A5 GCORE_RTN 9 RTN 402
2 V- 6 GPU_ISENSE1 2 SMC_GPU1_ISENSE 44A2 60C7
60A5 GCORE_VW 4 VW 1 2 3 GPU_ISENSE_R1_P 8 R1+

R2 CRITICAL R7227 C7222 1
2 1 VSUM
60A7 13 GCORE_VSUM GCORE_VSUM_R 3
+ U7201 4.53K 0.22UF
5 INA326EA-250 20%
1 C7211 1
R7214 VO 12 MSOP 1%
1/16W 2 X5R
6.3V
C7212
0.001UF 0.001UF 6.98K
1% GCORE_COMP 5 COMP 3 GCORE_OCSET 1 2
1 2
GPU_ISENSE_R2 MF-LF
402 402
OCSET 1
R7207 C7203 GND_SMC_AVSS 44C1
60A5 60A5
10% 1/16W
10% R7204
45B6 48A1 48B1 48C1 48C6 61C5 62C2 66B1 66C2
50V 11 GCORE_DFB
50V
CERM
2 CERM
402
MF-LF
2402 6 FB
DFB
60A7
R7208 1 C7204
47PF 750 200K
1% 470PF
1
402 4.99K
1% 5% 1%
1/16W
1/16W 10%
MF-LF 50V
2 50V
7 VDIFF 2 CERM
1/16W CERM MF-LF 2 402
MF-LF 402 402 402
DROOP 10 402
C7210 R7213 C7209
GCORE_VDIFF
GCORE_DROOP
PGND VSS THRM_PAD 2 1
220PF 1 150K 10%
680PF OMIT
5% CRITICAL
20
15
33
1%
25V
CERM
402
1/16W
2 MF-LF
50V
CERM
402
R7210
499 C7205 1 C7219 1 C7220
402
1% 0.001UF 10UF 330UF
B 60A5 1 2
2 GCORE_FB_RC 1
60A5 1 2 60A7
1/16W
MF-LF
402
10%
50V
CERM
402
20%
6.3V
2 X5R
603
20%
2.5V
2 POLY
B
GCORE_FB CASE-D2E-LF
60A5
XW7200 1 2 1 2
1
R7216 1R7215 R7211 C7208 SM
0
5% 0 1.1K 0.001UF
10%
R7209
C7207 1K
1/16W
MF-LF
5%
1/16W
1%
1/16W 50V
CERM
330PF
10% 1%
2402 MF-LF MF-LF 402 50V 1/16W
2402 402 CERM MF-LF
2 1 402 402
60A5 1 2 GCORE_VDIFF_RC
2 1
R7212
2.21K
1%
1 C7206
1/16W 10%
0.1UF
MF-LF
402 2 16V
X5R
1 2 60D7 60C5 60A7 GND_GCORE_SGND 402
MIN_LINE_WIDTH MIN_NECK_WIDTH MIN_LINE_WIDTH MIN_NECK_WIDTH

60C5
GCORE_PHASE 1 MM 0.25 MM I103 60B5
GCORE_OCSET 0.3 MM 0.25 MM I115
60C5
GCORE_BOOT 0.3 MM 0.25 MM I104 60B6
GCORE_VW 0.3 MM 0.25 MM I116
60C5
GCORE_UGATE 1 MM 0.25 MM I105 60B6
GCORE_RTN 0.3 MM 0.25 MM I117
GCORE_LGATE 1 MM 0.25 MM GCORE_VSEN 0.3 MM 0.25 MM
I106 I118
Render VCore Supplies
60C5 60C6
60C5
GCORE_BOOT_RC 0.3 MM 0.25 MM I107 60D6
GCORE_RBIAS 0.3 MM 0.25 MM I119
GND_GCORE_SGND 0.6 MM 0.25 MM GCORE_SOFT 0.3 MM 0.25 MM
A
60D7 60C5 60A5 I108 60C6 I120
GCORE_VDD GCORE_COMP SYNC_MASTER=GPU SYNC_DATE=06/29/2006
60D5
60D5
GCORE_PVCC
0.3 MM
0.3 MM
0.25 MM
0.25 MM
I109
I110
60B6
60B6
GCORE_FB
0.3 MM
0.3 MM
0.25 MM
0.25 MM
I121
I122 NOTICE OF PROPRIETARY PROPERTY
A
60C5
GCORE_VIN 0.3 MM 0.25 MM I111 60B6
GCORE_VDIFF 0.3 MM 0.25 MM I123
60B5
GCORE_DROOP 0.3 MM 0.25 MM I112 60B6
GCORE_FB_RC 0.3 MM 0.25 MM I124
60B5
GCORE_VSUM 0.3 MM 0.25 MM I113 60B6
GCORE_VDIFF_RC 0.3 MM 0.25 MM I125
60B5
GCORE_DFB 0.3 MM 0.25 MM I114
D 051-7559
H
NONE 72 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
D D
1.5V/1.05V POWER SUPPLY

=PP1V05_S0_REG_RNB_ISENSE_VCC 1 2 =PP3V3_S0_PDCISENS
7D8 7C4 60C2 66C3
1 C7390 C73031 R7390

Placement Note: 22UF
20%
0.1UF
10%
16V
100
1%
State PM_SLP_S3_L PP1V5_S0 PP1V05_S0
1/16W
PLACE C7390,C7391 2 6.3V
CERM
X5R MF-LF
S0 HIGH 1.5V
402 2 402
1.05V
NEAR NB
805
Placement Note:
PLACE C7303 NEAR U7301 PIN 7
NB_ISENSE_R1_N
2 7
1 R1- V+ 4 PLACE RC CLOSE TO SMC
S3/S5/G3Hot LOW 0.0V 0.00V
CRITICAL V- 6 NB_ISENSE 1 2 SMC_NB_CORE_ISENSE 44A8
1
R7302
1
R7392 8 R1+ CRITICAL
0.002 2.21K R2
U7301 R7305 C7306 1
C 1%
1/4W
MF-LF
1%
1/16W
MF-LF
402
3
+ 5
MSOP
4.53K
INA326EA-250
1%
1/16W
0.22UF
20%
2 6.3V
C
2 NB_ISENSE_R2 MF-LF X5R
2 1206
NB_ISENSE_R1_P 1
R7391 C7399 1
402 402
GND_SMC_AVSS 44C1 45B6 48A1 48B1 48C1 48C6 60B2
62C2 66B1 66C2
R7361
3.3
200K
1% 470PF 5%
1/16W
1/16W 10% MF-LF
1 C7351 2
MF-LF
402
50V
2 CERM
402
402
1 2
=PP5V_S5_1V51V05S0 Routing Note:
10UF
20%
1V51V05S0_V5FILT 7C1
The discharge path (VO2) should have
2 6.3V
X5R Routing Note:
1
C7305 1 C7301
10UF
Placement Note: a dedicated trace to the output cap;
603
The discharge path (VO1) should have 1UF
10% 20% R7361,C7305 close to U7300 pin 15. separate from the output voltage
2 10V 2 6.3V C7301 close to U7600 pin 16. sensing trace,
a dedicated trace to the output cap; X5R X5R
402-1 603
separate from the output voltage 61A3 GND_1V51V05S0_SGND
sensing trace,
=PPVIN_S5_1V05S0 7A1 7A1 =PPVIN_S5_1V5S0

CRITICAL CRITICAL CRITICAL
C73411 C7340 CRITICAL
5
5
Q7360 1 C7381 1 C7380 PWM FREQ. = 360 kHz
PWM FREQ. = 300 kHz 1
1UF 33UF Q7320 D FDM6296
1UF 33UF
20%
SI7110DN C7324 R7324 R7364 C7364 10%
25V MAX CURRENT = 4A
15
16
10% 20% 16V
MAX CURRENT = 8A 2
25V
X5R 16V
2 POLY PWRPK-1212-8
D
0.1UF 0 0 0.1UF
MICROFET3X3 2 X5R
603 2 POLY
CASED2E-SM
603 CASED2E-SM 10% 5% 5% 10%
=PP1V05_S0_REG G 4 16V 1/16W V5FILT V5IN 1/16W 16V 4 G CRITICAL =PP1V5_S0_REG
7D8 6B2
CRITICAL X5R
402 MF-LF MF-LF X5R
402 L7360 7C8 62C5
VOLTAGE=1.05V
MIN_LINE_WIDTH=1.5 mm L7320
1.0UH-13A-5.6M-OHM
S
2
402
1 1V05S0_VBST_RC
1 2 1V05S0_VBST 22
1 VO1
CRITICAL
SYM(1 OF 2) VO2 6
9 1V5S0_VBST 1
402
2 1V5S0_VBST_RC2 1
S
1.0UH-13A-5.6M-OHM
VOLTAGE=1.5V
SM-IHLP-1 3 2 1 MIN_LINE_WIDTH=1 mm 1V05S0_VH 21
U7300 DR_VH2
VBST1
DR_VH1
VBST2
101V5S0_VH MIN_LINE_WIDTH=1 mm 1 2 3 SM-IHLP-1
1 2 MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
mm
1V05S0_LL 20 TPS51124 LL2
LL1
111V5S0_LL MIN_LINE_WIDTH=1 mm 1 2
B <Rc> CRITICAL
MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
mm
1V05S0_VL 19 DR_VL1 QFN DR_VL2
121V5S0_VL MIN_LINE_WIDTH=1 mm
CRITICAL 1
NO STUFF B
NO STUFF 1 Q7321
5
NO STUFF MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 5
C7392 <Ra> 1
C7329 R7327 C7369
1 1V05S0_TRIP 17 141V5S0_TRIP CRITICAL 1
C7350 R7367
1 7.68K SI7108DNS R7326 1V05S0_VFB 2
TRIP1
VFB1
TRIP2
VFB2 5 1V5S0_VFB Q7361 330UF
1
10UF 20.0K 100PF
100PF 1%
1/16W PWRPK-1212-8 D 274K
1% 24 PGOOD1 PGOOD2 7
D
SI7110DN 10%
3 2 2.0V 20% 2 1% 5%
5%
50V MF-LF 1 1/16W PWRPK-1212-8 TANT
D2T 2 6.3V
X5R
1/16W
MF-LF 2 50V
CERM
2 2 402 MF-LF
CERM
402
OMIT
CRITICAL
C7352
G 4 2 402 1
R7325 58D1 23 EN1
1V05S0_RUNSS TONSEL 4 NC 4 G 603 402 402
2 330UF S
1V05S0_LL_RC
1%
6.65K 8 EN2
6D7 1V5S0_RUNSS
1 C7389 1
R7365
NO STUFF
58B1
220PF 3.74K
S
<Rd> 20%
2.5V
POLY 3 2 1 1
C7325
1/16W
MF-LF
2 402
GND PGND THRM_PAD 5%
25V 1%
1/16W 1 2 3 <Rb>
NO STUFF 1 R7328
CASE-D2E-LF
0.1UF
1 C7398 2 CERM
402 MF-LF 1
R7368
18
13
25
1 220PF 2 402 20.5K
C7328
0.001UF
20.0K
1%
1/16W
2
10%
16V
X5R 2
5%
25V
CERM
1%
1/16W
10% MF-LF 402 402 1 MF-LF
2
2 50V 2 402
2 402
CERM
402 XW7300
SM
61B6 GND_1V51V05S0_SGND
Vout = 0.758V * (1 + Rc / Rd) Routing Note:
Vout = 0.758V * (1 + Ra / Rb)
put 6 vias under the thermal
TABLE_ALT_HEAD
pad (pin 25)

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
128S0093 128S0092 ? C7380,C7340 KEMET T520V336M016ATE0457650

58A5 PGOOD_1V05S0 PGOOD_1V5S0
Note: pu on PGOOD page 58A5
TABLE_ALT_ITEM
"note: pu on pgood page"

1.5V / 1.05V Supplies
SYNC_MASTER=POWER
A
TABLE_ALT_HEAD

PART NUMBER I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_ALT_ITEM

376S0448 376S0445 ? Q7360
D 051-7559
H
NONE 73 106
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D
1.8V/0.9V POWER SUPPLY D
State PM_SLP_S4_LPM_SLP_S3_LPP1V8_S3 PP0V9_S0

S0 HIGH HIGH 1.8V 0.9V
S3 HIGH LOW 1.8V 0.0V
S5/G3Hot LOW LOW 0.0V 0.0V
Vout = 0.75V * (1 + Ra / Rb)
<Rb> NO STUFF
1 2
1 2 1V8S3_VDDQSET
R7522
20.0K <Ra> C7503 Placement Note:
MEM_ISENSE_VCC 1 2 =PP3V3_S3_PDCISENS 7A4 62A2
1%
1/16W R7521 5%100PF Routing Note:
PLACE C7543 NEAR NB C75041 R7561
MF-LF 28K 0.1UF 100
5%
C 402 1%
1/16W
MF-LF
50V
CERM
402
CONNECT VDDQSNS TO C7542 PIN1
using separate trace. =PP1V8_S3_REG_R 7B5
10%
16V
X5R 2
1/16W
MF-LF
402 C
402 402 Placement Note:
1 2 7 PLACE C7504 NEAR U7501 PIN 7
2
MEM_ISENSE_R1_N 1 R1- V+ 4 PLACE RC CLOSE TO SMC
1 2 MEMVTT_VREF =PP1V5_S0_REG 7C8 61B1
V- 6 MEM_ISENSE1 2 SMC_NB_1V8_ISENSE 44A8
1 C7501 8 R1+ CRITICAL C7505
C7540
0.033UF 10UF
1
R7560
2.94K
3
+
R2
U7501 R7503
4.53K
1
0.22UF
20% 1%
5 INA326EA-2501%
1/16W 20%
10%
16V 2 6.3V
X5R CRITICAL 1/16W
MF-LF
MSOP
MEM_ISENSE_R2
MF-LF
402 2 6.3V
X5R
X5R
402
603 GND_1V8S3_VTTGND 1
R7502 62A6
2 402 402
GND_SMC_AVSS
1 2 1V8S3_V5FILT
1 =PP5V_S5_1V8S30V9S0 0.002
2 1%
1/4W MEM_ISENSE_R1_P
1
R7563
200K
1 C7564 44C1 45B6 48A1 48B1 48C1 48C6 60B2 61C5 66B1 66C2
R7507 1 C7502 MF-LF 1% 470PF

C7500 4.7 10UF 21206 1/16W
MF-LF
10%
2 50V
1UF 5%
1/16W 20% 2 402 CERM
402
10% MF-LF 2 6.3V
10V 402 X5R
X5R 603
402-1
7D8
=PP0V9_S0_REG
1V8S3_VBST
1 2
=PPVIN_S5_1V8S30V9S0
1V8S3_VBST_RC
R7500
23
24
14
22
15
7A1
1
R7510 CRITICAL 1 C7531
9
2
8.25K 0
5% 5 CRITICAL 1 C7530
1%
1/16W
VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS 1/16W
MF-LF Q7520 33UF
1UF
10%
402 SI7110DN 25V 20%
MF-LF
2 402 Routing Note: C7509 D
PWRPK-1212-8 2 16V
POLY
2 X5R
603
CONNECT VTTSNS TO C7507 PIN1 1 0.1uF
10%
CASED2E-SM
using separate trace. 16V
X5R
4 G CRITICAL
L7520 PWM FREQ. = 400 kHz
B 58B7 45A6 44C5 35C7 33C7 24D3
65C2
PM_SLP_S3_L
1V8S3_RUNSS
10
11
S3
S5
PGOOD 13 2 402
S
1.0UH-13A-5.6M-OHM
SM-IHLP-1
MAX CURRENT = 10.75A B
MIN_LINE_WIDTH=1 mm
CRITICAL DRVH 21 1V8S3_DRVH MIN_NECK_WIDTH=0.25 mm 1 2 3 VOLTAGE=1.8V
U7500
SYM (1 OF 2) LL 20 1V8S3_LL MIN_LINE_WIDTH=1 mm
1 2
MIN_NECK_WIDTH=0.25 mm =PP1V8_S3_REG 7B6
6 COMP TPS51116 5 OMIT

OMIT
QFN 19 1V8S3_DRVL
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm CRITICAL CRITICAL
1V8S3_CS 16 CS
DRVL
C7542
1 C7543
Routing Note:
MODE 4 D CRITICAL 1
330UF
1 C7541
10UF 20%
330UF
Connect CS_GND to NC0 7 NC Q7521 20%
2.5V 20%
6.3V
2 2.5V
POLY
Q7521 PIN1,2.3
12 NC
4 G SI7108DNS 2 POLY
CASE-D2E-LF 2 X5R
CASE-C2
using Kevin connection. NC1 PWRPK-1212-8 603
S
1 C7507
10UF
1 C7508
10UF
THRM_PAD CS_GND GND PGND VTTGND 1 2 3
25
17
18
20% 20%
2 6.3V
X5R 2 6.3V
X5R
603 603
62C5 GND_1V8S3_VTTGND 1 2
XW7501
SM
GND_1V8S3_SGND 1 2 PGOOD_1V8S3 58B6
Routing Note: Placement Note: XW7500

SM TABLE_ALT_HEAD
R7599
100K
put 6 vias under the thermal pad PLACE XW7500,XW7501 NEAR C7542 PIN 2 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 5%
PART NUMBER 1/16W
MF-LF
TABLE_ALT_ITEM 402
1.8V/0.9V Supplies
128S0093 128S0092 ? C7530 KEMET T520V336M016ATE0457650 1 2 =PP3V3_S3_PDCISENS
TABLE_ALT_ITEM
SYNC_MASTER=POWER
A
D 051-7559
H
NONE 75 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
D 5V/3.3V POWER SUPPLY D
State SMC_PM_G2_EN PP3V3_G3H PP5V_S5 PP3V3_S5

G3H LOW 3.3V 0.0V 0.0V
S0/S3/S5 HIGH 3.3V 5.0V 3.3V
Vout = 1V * (1 + Ra / Rb) Vout = 1V * (1 + Rc / Rd)

CRITICAL
<Ra> CRITICAL<Rb> CRITICAL
<Rd>CRITICAL<Rc>
R7667
20K
R7668
4.99K
R7628
8.66K
R7627
20K
0.1% 0.1% 0.1% 0.1%
1/16W 1/16W 1/16W 1/16W
MF MF MF MF
402 402 402 402
1 2 1 2 63B6 63B4 63A4 GND_5V3V3S5_SGND 1 2 1 2
Routing Note: NO STUFF R7610 C7600 NO STUFF Routing Note:

C The discharge path (VO1) should have
C7667 0
5%
1
0.001UF
10% C7627 The discharge path (VO2) should have C
a dedicated trace to the output cap; 100PF
5%
1/16W
MF-LF 50V
CERM
100PF
5%
a dedicated trace to the output cap;
separate from the output voltage 50V 402 2 402 50V separate from the output voltage
sensing trace, CERM 1 25V3V3S5_VREF CERM sensing trace,
402 402
2 1 5V3V3S5_V5FILT 63A4
2 1
5VS5_VFB 3V3S5_VFB
5V3V3S5_TONSEL
1
2
3
5
4
6
7
8
C7622
VO1
COMP1
VFB1
VREF2
VFB2
COMP2
VO2
1
=PPVIN_S5_5VS5
GND
22PF
Routing Note:
put 6 vias under the thermal pad
5%
2 50V
=PPVIN_S5_3V3S5
CRITICAL 1 CRITICAL CRITICAL CERM 7A1
1
C7682 C7680
1 C7681 (pin 33)
33 PWPD
U7600
402
CRITICAL
33UF 33UF
1UF
10% RSMRST_PWRGD
32 SKIPSEL
TPS51120 EN5 9 NC RSMRST_PWRGD 44D8 45D5 63B5
1 C7641
1UF
1
C7640
2 25V
63B4 45D5 44D8
20% 2 20% LLP
2 X5R 31 10 NC 10% 33UF
16V
POLY
CASED2E-SM
16V
POLY
CASED2E-SM
603 C7660 R7660 TONSEL
SYM (2 OF 3)
EN3
R7620 C7620 2 25V
X5R 2 20%
16V
5 0.1UF
10% 0 30 PGOOD1 PGOOD2 11 0 0.1UF
10%
603 POLY
16V 5% 5% 16V 5 CASED2E-SM
X5R 1/16W 6D7 29 12 1/16W X5R
CRITICAL 402 MF-LF 65C5 EN1 EN2 MF-LF 65C5
402 D
402 402 CRITICAL
Q7660 D
2 1 5VS5_VBST_RC
1 2 28 VBST1
5VS5_VBST VBST2 13 3V3S5_VBST 1 2 3V3S5_VBST_RC2 1
Q7620
SI7110DN MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=1 mm
PWRPK-1212-8 G 4 MIN_NECK_WIDTH=0.25 27 DRVH1
5VS5_DRVH
mm DRVH2 143V3S5_DRVH
MIN_NECK_WIDTH=0.25 mm 4 G FDM6296
MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=1 mm
MICROFET3X3
PWM FREQ. = 280 kHz

S MIN_NECK_WIDTH=0.25
MIN_LINE_WIDTH=1 mm
mm 26 LL1
5VS5_LL LL2 153V3S5_LL MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=1 mm
S
1 2 3
PWM FREQ. = 430 kHz
3 2 1 25 DRVL1
5VS5_DRVL DRVL2 163V3S5_DRVL MIN_NECK_WIDTH=0.25 mm
MAX CURRENT = 5A
MAX CURRENT = 7.5A 1 2 1 2
V5FILT
PGND1
21 VREG5
VREG3
PGND2
B CRITICAL CRITICAL B
VIN
23 CS1
18 CS2
L7660
3.3UH
5 5VS5_RUNSS 3V3S5_RUNSS 5
L7620
=PP5V_S5_REG NO STUFF1 4.7UH =PP3V3_S5_REG
24
22
20
19
17
5VS5_VREG
7C3 7D3
IHLP
OMIT OMIT
C7671
5VS5_CS
3V3S5_CS
VOLTAGE=5V 1 IHLP VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm CRITICAL CRITICAL
CRITICAL
D
C7670 0.01UF
D
CRITICAL
OMIT OMIT
CRITICAL CRITICAL
1 C7690
2.2UF
1
C7691 1
C7692 Q7661 4
220PF
5%
10%
2 16V 4 Q7621 1
C7652 1
C7651 1 C7650
150UF 150UF G
25V
CERM
2 CERM
402
G
150UF 150UF 10UF
10% 20% 20% SI7110DN SI7110DN
2 16V
X5R 2 6.3V 2 6.3V S 402 S 20% 20% 20%
603 POLY
CASE-B2
POLY
CASE-B2
PWRPK-1212-8 GND_5V3V3S5_SGND 63A4 63B6 63C4
PWRPK-1212-8 2 6.3V
POLY 2 6.3V
POLY 2 6.3V
X5R
GND_5V3V3S5_SGND 603
3 2 1 63C4 63B4 63A4
1 2 3 CASE-B2 CASE-B2
NO STUFF1 R7605 1 1
R7603 NO STUFF
R7670 7.87K 5.90K
1
R7671
100K
100K
5%
1%
1/16W
1%
1/16W 5%
1/16W MF-LF MF-LF 1/16W
MF-LF 2 402 2 2 402 MF-LF
402 2 402
5V3V3S5_V5FILT 63C4
7A1
63B6
=PPVIN_S5_5VS5
R7601
4.7
5V3V3S5_VREG3
5%
1/16W
TABLE_ALT_HEAD
MF-LF
PART NUMBER
BOM OPTION REF DES COMMENTS: 402
1 2
5V/3.3V Supplies
TABLE_ALT_ITEM

TABLE_ALT_ITEM
1 C7602
1UF 1 C7604 1 C7605 1 C7603 Placement Note:
128S0093 128S0092 ? C7640 KEMET T520V336M016ATE0457650
10% 10UF 1UF 10UF R7601,C7605 close to U7600 pin 20.
A 376S0448 376S0445 ? Q7620
TABLE_ALT_ITEM
KEMET T520V336M016ATE0457650
2 25V
X5R
603 2
20%
6.3V
X5R
10%
2 10V
X5R
20%
2 6.3V
X5R
C7602 close
C7604 close
to U7600
to U7600
pin 22.
pin 21.
SYNC_MASTER=POWER SYNC_DATE=07/13/2005
A
TABLE_ALT_ITEM
603 402-1 603
152S0693 152S0133 ? L7620 MAGLAYER IHLP2525CZ-2SM C7603 CLOSE TO U7600 PIN 19.
R7605,R7603 close to U7600. PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 2 GND_5V3V3S5_SGND 63B4 63B6 63C4 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
XW7601
SM
D 051-7559 H
LATEST ISSUE: 2006/12/22 APPLE INC. SCALE

NONE
SHT
76
OF
106
8 7 6 5 4 3 2 1
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D 3.425V G3H SUPPLY D
Supply needs to guarantee 3.31V delivered to SMC VRef generator
7B1 =PPVIN_G3H_P3V42G3H P3V42G3H5_BOOST

3 6 C77911 CRITICAL
VIN
CRITICAL
BOOST
10%
0.22uF L7790
33uH
PWM FREQ. = 1 MHz @16.5V
U7790 6.3V
CERM-X5R
402
2
CDPH4D19F-SM MAX CURRENT = 0.2A
LT3470
1 SHDN*TSOT23-8 SW 5 PP3V42G3H_SW
1 2 =PP3V42_G3H_REG 7C3
NC 2 NC
BIAS 7
<Ra>
1 C7792 R7791
1
FB 8
22pF348K 1%
GND 5% 1/16W
4 2 50V
CERM MF-LF 1 C7793
402 2402
P3V42G3H_FB 22UF
CRITICAL
<Rb> 20%
2 6.3V
C7790
1
R7792 CERM
805
C
1
10UF
10%
200K
1%
1/16W
C
2 25V MF-LF
X5R
1206-1 2402
Vout = 1.25V * (1 + Ra / Rb)
1.25V S0 REGULATOR
7C1 =PP3V3_S5_1V25S0
Continuous
NO STUFF
C7720 1
R7727
11
10
1
47UF
R7722
3
1
0 SVIN PVIN
20%
4V
1M
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
402
U7720
LTC3412A
CERM-X5R 2
0805 B
402 2 2
P1V25S0_RT 15 RT QFN
1V25S0_RUNSS 1 PGOOD 12
58C1 RUN/SS
Connect RUNSS off-page to control CRITICAL
If unconnected, powers up with PVIN. P1V25S0_ITH 13 ITH 4 CRITICAL
NOTE: Be aware of pull-up on this signal. P1V25S0_MODE16 SYNC/MODE 5 L7720
2.2UH-3.25A
R7721 1 SW 8 =PP1V25_S0_REG 7C8
Burst
8.25K 1
R7728 14 VFB 9 P1V25S0_SW
1%
1/16W 0 THERM
MIN_LINE_WIDTH=0.6 mm IHLP1616BZ-SM
Vout = 1.2516V
MF-LF
402 2
5%
1/16W
MF-LF
SGND PGND PAD <Ra> 1
C7728 3.0A max output
1000PF
2
R7723
6
7
17
(Switcher limit)
1
P1V25S0_ITH_RC 2 402 10%
47.0K 25V
C7725
1
R7726 1%
2 X7R
C7729
402
C7723 C7724 C7730
1 1
1/16W
1 1
470PF 309K MF-LF 47UF
1
1000PF 100PF 10% 1% 402 2 20% 47UF
10% 5% 50V 1/16W 4V 20%
MF-LF
25V
2 X7R
50V
CERM 2
CERM
402
2
2 402 XW7700
SM
CERM-X5R
0805
2 4V
2 CERM-X5R
402 402 0805
GND_P1V2S3_SGND 1 2
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 mm P1V25S0_VFB
<Rb>
R7724 1
60.4K
1%
1/16W
MF-LF
402 2
3.42V/1.25V Switcher
P1V25S0_VFB_DIV
SYNC_MASTER=ENETSYNC_DATE=12/06/2005
A <Rc> A
R7725 1
23.2K
1% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF-LF AGREES TO THE FOLLOWING
402 2
Vout = 0.8V * (1 + Ra / (Rb + Rc)) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
D 051-7559 H

NONE
SHT
77
OF
106
8 7 6 5 4 3 2 1
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S3 FETS & S3/S5 CONTROL

D
5V/3.3V S5 RUN/SS CONTROL 1.8V S3 RUN/SS CONTROL

5VS5_RUNSS 6D7 63B5
65A4 7A6 =PP3V3_S3_FET
D 3
Q7859 65A5 58C5 7D1 =PP3V3_S5_FET 1

R7875
R7857
470K SSM6N15FE 10K
1%
SOT563 1/16W
5% CRITICAL
C 1/16W
MF-LF
402
5 G S 4 5 U7870
74LVC1G07
MF-LF
2 402 C
7B1
=PP3V42_G3H_PWRCTL
1 2 SMC_PM_G2_EN_L SC70
65A6 44C5 33B7 24D3
IN
PM_S4_STATE_L
2 4 1V8S3_RUNSS 62B8
NC Open drain output

Q7860 3V3S5_RUNSS
SSM6N15FE
SOT563
D 3 63B4 1 3
NC
D 6
SMC_PM_G2_EN
Q7859
44D5
IN
5 G S 4 SSM6N15FE
SOT563
1
R7856
100K
2 G S 1
5%
1/16W
MF-LF
2 402
CRITICAL
Q7865
FDC638P
SM-LF =PP5V_S3_FET
7A5
6
B
58D5 58C6 58B3 7C1
=PP5V_S5_FET4 5
2
1
5V S3 FET B
MOSFET FDC638P
R7805 C7801
0.0022uF CHANNEL P-TYPE
100K 3
5%
1/16W
MF-LF
10%
50V RDS(ON) 48 mOhm @4.5V
402 CERM
7C1
=PP5V_S5_PWRCTL
1 2 PM_SLP_S4_LS5V 1 2 P5VS3_EN_L
402
1 2 LOADING 0.051 A
R7806
10K
5%
1/16W CRITICAL
Q7860
D 6
MF-LF
402 Q7866
FDC638P =PP3V3_S3_FET
SSM6N15FE
SOT563
SM-LF 7A6 65C3
65C4 44C5 33B7 24D3

IN
PM_S4_STATE_L
2 G S 1 =PP3V3_S5_FET
65C4 58C5 7D1
4
6
5
2
3.3V S3 FET
1
MOSFET FDC638P
R78071
100K CHANNEL P-TYPE
5%
1/16W R7808 3
C7802
0.01UF RDS(ON) 65 mOhm @2.5V
MF-LF
402
10K
2 5% 10%
1/16W
MF-LF
16V
CERM LOADING 0.098 A
1
402
2 P3V3S3_EN_L
402
1 2 S3 FET & S3/S5 Control
SYNC_MASTER=DSIMON-WF
A
D 051-7559
H
NONE 78 106
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PBUS SUPPLY / BATTERY CHARGER LDO_FDBK

4
LDO_OUT 1
D U7950
VCCCRITICAL
3
D
MAX8719 CRITICAL
1 IN TDFN OUT 8 2
Q7900
AO4409 SMC_ENRGYSTR_LDO_EN6 SHDN*
R7952
221K D7950
Placement Note: 44A2 PGOOD 5 0.1%-50PPM
SOI 1/16W
MF-LF
BAT54CW-X-F
PLACE NEAR R7997 1 402-1 SOT-323
=PP18V5_G3H_CHGR 8 MIN_LINE_WIDTH=0.6 MM 1 C7952 R7954 7 I.C. FB 3 1 2
7B1
7
D4
S3
3 MIN_NECK_WIDTH=0.25 MMPPVDCIN_G3H_PRE 1UF 100K NC THRML
CRITICAL
D3 2 10% 5% GND 1
3 6
S2
2 25V
1/16W
MF-LF
PAD R7953
CRITICAL D2 1 X5R 22.6K 1 C7951
9
5 D1 S1 603 2 402
D NO STUFF 0.1% 1UF
Q7940 GATE 1
R7903 3 4
1/16W
MF
2 402
10%
25V
2 X5R
FDN360P_NL G 1 66B5 CHGR_VDD 4 100K
5% VIN+ VIN- 603
SOT-23 1/16W
S MF-LF
1 2 1 2 CHGR_VDDP 2 402 CRITICAL
2 PLACE RC CLOSE TO SMC
R7900 =PP3V3_S0_PDCISENS
5 V+ U7970 OUT 1 DCIN_ISENSE 1 2 SMC_DCIN_ISENSE 44C5 SMC_ENRGYSTR_LDO_PGOOD
C7901 R7901 C7911 4.7 1 C7912 MIN_LINE_WIDTH=0.2 MM
61C5 60C2 7C4
INA193 44A2
45C5
0.001UF 56.2K 5% 1UF SOT23-5
10%
50V 1%
1/16W
1UF
10%
1/16W
MF-LF 10% 1 C7970 R7970
4.53K
1 C7971
CERM 10V 402 10V
MF-LF 2 X5R 1CRITICAL 1% 0.22UF
1
402
2 CHGR_VCOMP_RC
1
402
2
X5R
402-1 402-1 C7904 1 R7997 1UF
10% GND 1/16W
MF-LF
20%
6.3V
1
CRITICAL 0.1UF R7905 0.02 2 6.3V 402 2 X5R
D7900
CHGR_FB
10% CERM 2
18 0.5% 402
R7967 25V
13
402
26
B0530WXF X5R 2 5% 1W
GND_SMC_AVSS
3.01K SOD-123 402 1/16W
MF-LF
MF 44C1 45B6 48A1 48B1 48C1 48C6 60B2 61C5 62C2 66B1
1% 2 0612
2
1/16W 402 MIN_LINE_WIDTH=0.6 MM
MF-LF VDD VDDP 1 2
C7900 402 MIN_NECK_WIDTH=0.25PP18V5_S5_CHGR_SW_R
MM
0.033uF CHGR_FB_R 1 2 5 FB SGATE 18 CHGR_SGATE
CRITICAL NO STUFF
10% R7902 CRITICAL CRITICAL
16V
X5R
402 8 ACLIM
CHGR_ACLIM U7900 CSIP 19 100K
5% 1
C7905 1 C7906 1 C7907
1 C7950
QFN CSIN 20 CHGR_CSIN 1UF 1UF
1 2 3 ICOMP
CHGR_ICOMP
1/16W
MF-LF
402
22UF
20%
22UF 20% 10% 10%
25V 25V
C 1 C7940
4 VCOMP
CHGR_VCOMP BGATE 17 CHGR_BGATE 1 2 5 2 25V
POLY 2 25V
POLY 2 X5R
603
2 X5R
603 C
ISL6257HRZ
0.1UF NC 9 VADJ DCIN 25 CHGR_DCIN CASE-D2-LF CASE-D2-LF
10% 2 CELLS CRITICAL
2 25V
X5R BOOT 14 CHGR_BOOT 1 2 CHGR_BOOT_RC
Q7901 CRITICAL =PPBUSB_G3H 7B3
402 21 CSOP
CHGR_CSOP UGATE 15 CHGR_UGATE R7910
2.2
4 RJK0305DPB 1 2 =PPBUSA_G3H 7B3
22 CSON PHASE 16 CHGR_PHASE LFPAK
1
R7940 1 C7902 1 C7967 7
CHGR_CHLIM
5%
1/16W C7903 1
88.7K 1UF 470PF CHLIM
LGATE 12 CHGR_LGATE
MF-LF
402 0.1UF CRITICAL
R7908 F7900
1% 10% 10% 10% 0.01 7AMP
1/16W 2 10V
X5R
50V 6 VREF EN 1 25V
NC 0.5% 1206
MF-LF 402-1 2 CERM
402
X5R
402 2 1W
3
2 402 1 2 3 MIN_LINE_WIDTH=0.6 MM MF MIN_LINE_WIDTH=0.6 MM
THRML_PAD
23 ACPRN DCPRN 24 NC MIN_NECK_WIDTH=0.25 MM
0612
27 28 NC PPVBAT_G3H_CHGR_REG PPVBAT_G3H_CHGR_OUT
1
CHGR_ACSET 1 2
CHGR_VREF
ACSET DCSET
CHGR_ACPRN
6B1 66B5
CRITICAL CRITICAL CRITICAL CRITICAL
PGND
1 L7900 C7910
D7922 5 1
GND
Q7902 1
C7908 1
C7909
CHGR_EN
MMBD914XXG
1
R7906 4.7UH 33UF 100UF
1UF
SOT23 2.2 RJK0305DPB FDA1254-3SM 20%
10%
25V
29
11
20%
10
LFPAK 2 X5R
3 5% 2 16V 2 16V 603
1/16W POLY ELEC
CHGR_ACSET_RC MF-LF 4 CASED2E-SM 6.3X5.5SM1
2 402 NO STUFF
1
R7941 1
R7944
1 C7917 NO STUFF
C7916 1
1 C7941 10%
0.1UF 0.001UF 1 2 CHGR_PHASE_RC
10K 100K 0.1UF Placement Note:
2 25V 10%
R7981
1%
1/16W
MF-LF
1%
1/16W
MF-LF
10%
2 25V
X5R
402
50V
CERM 2
1 2 3 49.9
1 C7981 3 4 PLACE NEAR R7908
X5R 402 1% 0.0022UF
2 402 2 402 402 1/10W 10% VIN+ VIN-
2 50V
66B8
66A8 GND_CHGR_SGND 1 2 MF-LF CERM
603 402 CRITICAL
R7968
XW7900 U7975 PLACE RC CLOSE TO SMC
V+INA193
SM 5
2.37K 7C4 =PP3V3_S0_PBATTISENS OUT 1 BATT_ISENSE1 2 SMC_BATT_ISENSE 44C5
1%
1/16W
SOT23-5
=PP3V42_G3H_ACIN MF-LF
C7975 R7971
SMC_SYS_ISET_L
1 2 402 1
4.53K
CHGR_VREF_VF
PWM FREQ. = 300 kHz
66A8 66A5 57C4 7B1
CHGR_ACLIM_R 1 2
1UF 1% 1 C7972
R7969
B B
1/16W
10K
10%
6.3V
GND MF-LF
402
0.22UF
2 CERM 20%
5%
1/16W 1 2 1
R7951 402
2 6.3V
2 X5R
CRITICAL
MF-LF
402 R7960 100K Q7920 R7920 402
2
15.0K 27
Q7960 D 6
Q7960
SSM6N15FE
D 3 1%
1/16W
1%
1/16W
MF-LF
AO4409 SOI
5%
3W
GND_SMC_AVSS 60B2 61C5 62C2
44C1 45B6 48A1
48B1 48C1 48C6
SSM6N15FE
SOT563 SOT563
MF-LF
402 R7961
1
1 C7927 2 402
MF
2525-1 MIN_LINE_WIDTH=0.6 MM
66C2
V-
8 PPVBATT_G3H_PRE MIN_NECK_WIDTH=0.2 MM
20.0K
1
V+
0.022UF 1 2 BATT_POS_F
U7901
1% PPVBAT_G3H_CHGR_OUT 3 D4 57B2 57D5
CHGR_VDD 66C2 6B1 S3 7

6
10%
CRITICAL
1/16W 66C6
NO STUFF 2 D3
MF-LF 2 16V S2
CERM-X5R 1 C7920 1 C7921 1 C7922 1R79301 C7918 1 6 8
5
ACIN_ENABLE_GATE
2 G S 1 2 402 D2
TLV341
402 3 D4
SOT563
SMC_SYS_ISET 5 G S 4 1 0.01uF 0.1UF 0.01UF 470K S1 D1 5 S3 7

44B5
10% 10% 10% 0.22UF 2 D3
R7950 S2
4
1% 6
2 16V 2 16V
16V 10% GATE
CERM X5R 2 CERM 1/16W 1 D2
100K MF-LF 2 10V S1 5
66B5 66A8 GND_CHGR_SGND 1% 402 402 402
2 402
CERM
402 4 D1
1/16W
NOSTUFF MF-LF BATT_FET_GATE GATE CRITICAL
R7964 2
2.43K
1%
402
1
R7931
NO STUFF 1
R7922
4 Q7921
AO4409
1/16W
MF-LF 330K
1 C7924 39.2K SOI
D 6 0.01uF
CHGR_CHLIM_R 1
402
2 Q7950 5%
1/16W 10%
2 16V
1%
1/16W
66B8 66A5 57C4 7B1
=PP3V42_G3H_ACIN
1 2 R7909 SSM6N15FE MF-LF
2 402
CERM
402
MF-LF
1 2 100K SOT563
SMC_BATT_ISET_L
BYPASS_R_GATEMIN_NECK_WIDTH=0.2 MM
R7979 R7962 1%
1/16W
10K BATT_ENABLE_L
5%
1/16W Q7961 D 3
15.0K
1%
1
MF-LF
402
2
C7980 1 2 G S 1 Q7950 MIN_LINE_WIDTH=0.2 MM
1
R7923
MF-LF
402 D 6 SSM6N15FE 1/16W
MF-LF
402
0.1UF
10%
SSM6N15FE D 3 MIN_NECK_WIDTH=0.2 MM
35.7K
SOT563 SOT563
Q7961
SSM6N15FE
1
R7963
44.2K
1 C7928
16V
X5R
402
2 D 6
Q7922
1%
1/16W
MF-LF
SOT563 1% 0.01UF
10%
SSM6N15FE 2 402
1/16W 16V
SOT563 BYPASS_R_DRV
44B5 6C1 SMC_BATT_ISET
5 G S 4 MF-LF
2 402
2 CERM
402 5 G S 4 Q7924 D 3
2 G S 1
R7965
100K
2 G S 1 SSM6N15FE
SOT563
6 D Q7924 PBUS Supply/Battery Charger
GND_CHGR_SGND 1% SSM6N15FE
A
66B8 66B5
SOT563
TABLE_ALT_HEAD
66B8
66A8
57C4 7B1 =PP3V42_G3H_ACIN
1
1/16W
MF-LF
402
2 P3V42_G3H_ACIN_R 5 G S 4
SYNC_MASTER=SMC
A
PART NUMBER
1 S G 2
TABLE_ALT_ITEM
Q7922 D 3 44C8 6C1 SMC_BATT_CHG_EN

SSM6N15FE 45B6
SMC_BATT_TRICKLE_EN_L 6C1 44C8 45B6
SOT563 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_BC_ACOK
TABLE_ALT_ITEM
376S0466 376S0543 ? AOS

Q7900,Q7920,Q7921 MOSFET 57C7 57C3 45B6 44C5 6C1 1 2 BATT_RC
R7925
10K 1 C7923 II NOT TO REPRODUCE OR COPY IT
1% 0.1UF 5 G S 4
1/16W 10%
MF-LF 16V SIZE DRAWING NUMBER REV.
402 X5R
051-7559
2
402
D H

NONE
SHT
79
OF
106
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7A7
=PP5V_S0_LCD
PP5V_INV
R9000
1 MIN_LINE_WIDTH=0.30 MM
FERR-120-OHM-1.5A
L9003
100K
1%
VOLTAGE=5V
=PPBUS_S5_INV 1 PPBUS_ALL_INV_CONN
1/16W 3 2 6B1
Q9005 7B1
INVERTER CONNECTOR D
MF-LF 0402-LF VOLTAGE=12.6V
2 402
R9001 D NTK3142P MIN_LINE_WIDTH=0.30 MM
D INV_PWREN_F_L
1
100K 2 INV_PWREN_L 1 G
SOT723-3
R9003
0
Q9006 1%
1/16W
1 2
SSM3K15FV D 3 MF-LF
402
S 5%
1/16W
CRITICAL
SOD-VESM MF-LF
402 J9000
2 78171-0004
M-RT-SM
L9000
120-OHM-0.3A-EMI
5
1 G S 2 C9014
0.0022UF 1 2 6B1 PP5V_INV_F 1
LVDS_BKLT_EN
14D5
IN 1 2 0402-LF VOLTAGE=5V
6B1 INV_GND 2
3
10% MIN_NECK_WIDTH=0.20 MM
50V 6B1 INV_BKLIGHT_PWM_L
4
CERM
402
120-OHM-0.3A-EMI
L9001
6
1 2
=PP3V3_S0_LCD 0402-LF 518S0521
R9004
67B7 67B5 7C4
2
1 C9001 1 C9002 C9000
1/16W
MF-LF
CRITICAL 1
402
100PF 1000PF 1000PF
5%
0
5% 10% 10%
5 TC7SZ08AFEF 2 50V 25V
2 X7R 2 25V
PLT_RST_L 2 SOT665 CERM X7R
1
27D4 23A6 A 402 402 402
4 BKLIGHT_CTL
1
U9053Y
14D5 LVDS_BKLT_CTL B
3
C90591 THIS GND CONECTS TO CHASSIS GND
0.1UF
10% INVT_CHGND 8D8
16V 2
X5R
402
C C
7D1 =PP3V3_S5_LCD CRITICAL
R9002 Q9003
LCD + CAMERA CONNECTOR
1
100K FDC606P
SOT-6
5% 6
1/16W
MF-LF 5 PP3V3_LCDVDD_SW
2 402
R9023 4 2 VOLTAGE=3.3V C9009
D
10K
1 MIN_NECK_WIDTH=0.20 MM 0.001UF
1
LCDVDD_PWREN_L 2 1 C9011 1 C9012 1 2
G
Q9004 5%
1/16W
MF-LF
0.1UF
10%
10UF
20% 10% CRITICAL
J9001
SSM3K15FV 2 16V 2 6.3V 50V
SOD-VESM
D 3 402
LCDVDD_PWREN_L_R
3 X5R
402
X5R
603
CERM
402 S-050162B
F-RT-SM
25
C9013
0.0033UF 67A6
67A4 67A2 8C8 =GND_CHASSIS_LVDS 23
1 2
1 G S 2 =PP3V3_S0_LCD FERR-120-OHM-1.5A
L9004
10% 7C4 67B5 67B7
67C6 1
50V
14D5
IN
LVDS_VDD_EN CERM
402
1 2 PP3V3_LCDVDD_SW_F 2
VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MIN_NECK_WIDTH=0.20
MM
R9008
1 R9009 1 0402-LF MM 3
1
R9014 10K 10K 5% 120-OHM-0.3A-EMI
L9008 PP3V3_S0_LCD_F (LVDS DDC POWER)
VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20
MM MM
4
100K 5%
1/16W
1/16W
MF-LF
5
1%
1/16W MF-LF 2402 67C6 67B7 67B5 7C4 =PP3V3_S0_LCD 1 2 6
2402
B
MF-LF
2 402
14D5 LVDS_DDC_CLK
0402-LF
CRITICAL
71D3 14C5
71D3 14C5
IO
IO
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
7
8 B
14D5 LVDS_DDC_DATA L9006
90-OHM-200MA
71D3 14C5
IO LVDS_A_DATA_N<1> 9
LVDS_A_DATA_P<1> 10
67C6 67B5 7C4 =PP3V3_S0_LCD SM
SYM_VER-1
71D3 14C5
71D3 14C5
IO
LVDS_A_DATA_N<2> 11
71D3 14C5 LVDS_A_CLK_N1 4 IO
12
NOSTUFF NOSTUFF CRITICAL IO 71D3 14C5
IO LVDS_A_DATA_P<2>
R9015
1
R9016 1 L9007
90-OHM-200MA
LVDS_A_CLK_F_N 13
10K 5%
10K 5%
SM
SYM_VER-1
71D3 14C5
IO LVDS_A_CLK_P2 3 LVDS_A_CLK_F_P 14
1/16W
MF-LF
1/16W
MF-LF 8C2 =USB2_CAMERA_P 1 4
15 LCD I/F
IO 16
2 402 2402
USB2_CAMERA_CONN_P 17
LVDS_CTRL_CLK 8C2
IO
=USB2_CAMERA_N 2 3 USB2_CAMERA_CONN_N 18 CAMERA I/F
14D5 12B1
19
L9005
FERR-120-OHM-1.5A 20
21
LVDS_CTRL_DATA =PP5V_S3_CAMERA
1 2 PP5V_S3_CAMERA_F 67A4 MIC_LO_LVDS_CONN
14D5 12B1 7A4
MIC_HI_LVDS_CONN 22
NOSTUFF 0402-LF VOLTAGE=5V 67A4
L9010
FERR-1000-OHM
MIN_LINE_WIDTH=0.30 MM 24
=GND_CHASSIS_LVDS 26
OUT MIC_LO_LVDS 1 2 MIC_LO_LVDS_CONN C9010 1 67B2 67A6 67A4 8C8
0402NOSTUFF C90161 C90151 0.001UF

10% Plexi: 516S0212
L9011
FERR-1000-OHM
0.001UF
10%
50V
0.001UF
10%
50V
50V
CERM
402
2 *Enclosure: 518S0364
CERM 2 CERM 2
MIC_HI_LVDS 1 2 MIC_HI_LVDS_CONN 402 402
OUT
L9012
0402NOSTUFF
67A2
INVERTER,LVDS,TMDS
SYNC_MASTER=GPU SYNC_DATE=06/23/2006
A LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED
MIC_SHIELD_LVDS1
FERR-1000-OHM
2 =GND_CHASSIS_LVDS C90081 A
OUT 8C8 67A2 67A6 67B2
0.001UF NOTICE OF PROPRIETARY PROPERTY
R9013
2.37K
0402 NOSTUFF NOSTUFF
CRITICAL 2 CRITICAL 2
10%
50V
CERM 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
71C3 14D5 LVDS_IBG 1 2 DZ9000 DZ9001 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1% 8V-100PF 8V-100PF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 402-1 402-1
MF-LF II NOT TO REPRODUCE OR COPY IT
402
1 1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
=GND_CHASSIS_LVDS SIZE DRAWING NUMBER REV.
051-7559
67B2 67A4 67A2 8C8
D H
NONE 90 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
L9206 L9201
FERR-120-OHM-1.5A FERR-120-OHM-1.5A R9207 R9237
PP3V3_S0_ANALOG_TMDS_F =PP1V8_S0_TMDS1 PP1V8_S0_TMDS_F TMDS_TX_P<0> 149.92 TMDS_TX<0> 149.92 TMDS_TX_N<0>
69C8
68D8 68C8
68B1 7C4 =PP3V3_S0_TMDS
1 2 68D6 7B7
2 69B2 68B2 68B2 69B2
68B7 68B2
0402-LF VOLTAGE=3.3V 0402-LF VOLTAGE=1.8V
69C2 69B7
MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM 1% 1%
MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM 1/16W 1/16W
MF-LF MF-LF
1 C9236 1 C9237 1C9238 1C9239 1 C9240 C9207
1 1 C9208 1C9209 1 C9210 1C9211 1 C9212 1 C9213 402 1 C9222 402
0.1UF 0.001UF 0.1UF 0.001UF 0.1UF 0.001UF 0.001UF
0.001UF 0.001UF 0.1UF 0.1UF 10UF 10% 10% 10% 10% 10% 10% 10UF 10%
10% 10% 10% 10% 20% 2 16V 2 50V 2 16V 2 50V 2 16V 2 50V 20% 2 50V
2 50V
CERM
50V
2 CERM 2 16V
X5R
16V
2 X5R 6.3V
2 X5R X5R
402
CERM
402
X5R
402
CERM
402
X5R
402
CERM
402 2 6.3V
X5R
CERM
402
402 402 402 402 603 603
D ONE 0.1UF AND 1000PF FOR EACH PIN ONE 0.1UF AND 1000PF FOR EACH PIN R9208 R9238 D
TMDS_TX_P<1> 49.9 TMDS_TX<1> 149.92 TMDS_TX_N<1>
L9203
FERR-120-OHM-1.5A
L9200
FERR-120-OHM-1.5A
69B2 68B2 1
1%
2
1%
68B2 69B2
1/16W 1/16W
MF-LF MF-LF
PP3V3_S0_ANALOG_SDVO_F =PP1V8_S0_TMDS 1 PP1V8_S0_ANALOG_SDVO_F
69C8
68D8 68C8
1 2
VOLTAGE=3.3V
68C4 68D6 7B7
2
VOLTAGE=1.8V
68C4 402 1 C9223 402
68B7 68B2
69C2 69B7 0402-LF MIN_LINE_WIDTH=0.3MM 0402-LF MIN_LINE_WIDTH=0.5MM 0.001UF
MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM 10%
2 50V
CERM
1 C9230 C9231
1 C9214
1 1 C9200 1 C9201 1 C9202 C9203
1 1 C9204 402
0.001UF
10%
0.1UF
10%
0.1UF
10%
0.001UF
10%
0.001UF
10%
0.1UF
10%
0.1UF
10%
10UF
20%
2 50V
CERM 2 16V
X5R 2 16V
X5R 2 50V
CERM 2 50V
CERM 2 16V
X5R 2 16V
X5R 2 6.3V
X5R
402 402 402 402 402 402 402 603
R9209
49.92 TMDS_TX<2> 149.92
R9239
69B2 68B2 TMDS_TX_P<2>
1 TMDS_TX_N<2> 68B2 69B2
1% 1%
ONE 0.1UF AND 1000PF FOR EACH PIN 1/16W
MF-LF
1/16W
MF-LF
L9204
FERR-120-OHM-1.5A
402 1 C9224 402
0.001UF
69C8 10%
68D8 68C8
1 2 PP3V3_S0_PVCC1_TMDS_F 68C4 2 50V
CERM
68B7 68B2
69C2 69B7 0402-LF VOLTAGE=3.3V 402
1 C9232 C9233
1 C9206
1
0.001UF
10%
0.1UF
10%
0.1UF
10% 49.92
R9210 R9240
49.92 TMDS_TX_CLK_N
2 50V
CERM 2 16V
X5R 2 16V
X5R 69A2 68B2 TMDS_TX_CLK_P
1 TMDS_TX_CLK
1 68B2 69A2
402 402 402 1% 1%
1/16W 1/16W
MF-LF MF-LF
402 1 C9225 402
0.001UF
10%
C L9205
2 50V
CERM
402 C
FERR-120-OHM-1.5A MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP
69C2 69B7
=PP3V3_S0_TMDS
1 2 PP3V3_S0_PVCC2_TMDS_F 68C4
68B2 68B1 7C4
68D8 68C8 68B7
69C8 0402-LF VOLTAGE=3.3V PLACE THE CAP NEAR THE NB SIDE
MIN_NECK_WIDTH=0.25MM 71D3 14B3
IN
PEG_R2D_C_P<0>
1 C9234 C9235
1
PEG_R2D_C_N<0> PP3V3_S0_ANALOG_SDVO_F
0.001UF 0.1UF 71D3 14C3
IN 68D6
10% 10% PP1V8_S0_ANALOG_SDVO_F
2 50V 2 16V
68D3
CERM
402
X5R
402 71D3 14B3
IN
PEG_R2D_C_P<1> PP3V3_S0_PVCC2_TMDS_F
68C6
71D3 14C3
IN
PEG_R2D_C_N<1> 68C6 PP3V3_S0_PVCC1_TMDS_F
71D3 14B3
IN
PEG_R2D_C_P<2>
71D3 14C3
IN
PEG_R2D_C_N<2>
71D3 14B3
IN PEG_R2D_C_P<3> 68D6 68B1 PP3V3_S0_ANALOG_TMDS_F =PP3V3_S0_TMDS
PEG_R2D_C_N<3> 68D3 PP1V8_S0_TMDS_F 7C4 68B1 68B7 68C8 68D8 69B7 69C2 69C8
71D3 14B3
IN 1 C92211 C9205
0.1UF 10UF
10
28
34
15
21
11
26
36
42
48
10% 20%
1
DVI_HOTPLUG_DET 2 16V
X5R 2 6.3V
X5R
402 603
VCC0
VCC1
VCC2
AVCC0
AVCC1
PVCC1
PVCC2
SVCC0
SVCC1
SPVCC
OVCC
1 C92411 C92421 C92431 C92441 C9245 1 C92461 C92471 C9248
1 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
PP3V3_S0_ANALOG_TMDS_F 68B4 68D6
R9250 10% 10% 10% 10% 10% 10% 10% 10%
100K 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R CRITICAL
5% "Place R9250 near U2300.F12" 402 402 402 402 402 402 402 402 TMDS_SDR_P37 SDR_P U9200 17 TMDS_TX_P<0>
1/16W TX0_P 69B2 68D3
OUT
MF-LF
2402 TMDS_SDR_N38 SDR_N SIL1362ACLU TX0_N 16 69B2 68D1 TMDS_TX_N<0>
OUT
1
R9204
LQFP TMDS_TX_P<1>
TMDS_SDG_P40 SDG_P TX1_P 20 69B2 68D3
OUT 249
1%
TMDS_SDG_N41 19 TMDS_TX_N<1>
B
SDG_N TX1_N 1/16W
B
69B2 68D1
OUT
MF-LF
TMDS_SDB_P43 SDB_P
SDVO RCVR DIFF SIG
TX2_P 23 69B2 68C3 TMDS_TX_P<2>
OUT 2402
TMDS_SDB_N44 SDB_N CORE DATA TX2_N 22 69B2 68C1 TMDS_TX_N<2>
OUT
=PP3V3_S0_TMDS 7C4 68B2 68B7 68C8 68D8 69B7
C9219 TMDS_SDC_P46 TXC_P 14 69A2 68C3 TMDS_TX_CLK_P

OUT
69C2 69C8
0.1UF
10% 16V
C9220 TMDS_SDC_N47
SDC_P
TXC_N 13 69A2 68C1 TMDS_TX_CLK_N
OUT
69C8 69C2 69B7 68D8 68C8 68B2 68B1 7C4 =PP3V3_S0_TMDS 1

PEG_D2R_P<1>
X5R 402
2
0.1UF
10% 16V
X5R 402 TMDS_INT_P 32
SDC_N
EXT_SWING 25 TMDS_EXT_SWING R9205
1
10K
1
R9206
10K
14C3
71D3 OUT
SDI_P
1 2 5% 5%
1 71D3 14D3
1 OUT
PEG_D2R_N<1> TMDS_INT_N 33 SDI_N 1/16W 1/16W
R9201 R9202 MF-LF MF-LF
2.94K 2.94K TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH TMDS_EXT_RES
35 EXT_RES
I2C MASTER 2402 2402
1% 1% INTER SCLDDC 8 TMDS_I2C_SCL
PLACE R9200,U9201 CLOSE TO 1/16W 1/16W
TMDS_I2C_SDA
MF-LF MF-LF SDADDC 9
MINI DVI CONN J9401 402 2 402 2 27D1 TMDS_RST_L 2 RESET*
CRITICAL
SDVO_CTRLCLK 5
TMDS_I2C_SCL AND TMDS_I2C_SDA DON’T NEED TO CONNECT
SDSCL CONFIG/ TEXT MODE
U9201 IO 15A3
30
5 15A3 SDVO_CTRLDATA 4 SDSDA PRGRM
TEST
R9200 5.5V TOL INPUT
74LVC1G17DRL
SOT-553
IO
ADDRESS=0X70
NC 6 A1
TMDS_HTPLG 1
10K 2TMDS_HTPLG_R 2 4 TMDS_HTPLG_BUF IF HIGH, ADDRESS=0X72
69C6
IN 29 HTPLG
5% 3.3V ACTIVE OUTPUT
AGND0
AGND1
AGND2
PGND2
SGND0
SGND1
SPGND
1/16W NC
GND0
GND1
1 1
MF-LF
1 R9211 R9212
R9200 INSURES ESD DIODE R9213
402 1 3
9.09K 9.09K
270K 1% 1% DVI_HOTPLUG_DET 23A6 68B8
R9203
1
7
31
12
18
24
27
39
45
3
CURRENT IS SMALL 5% 1/16W 1/16W
1/16W
MF-LF
MF-LF
402
MF-LF
402
1K
5%
402 2 2 1/16W
2 MF-LF
2402
EXTERNAL TMDS
SYNC_MASTER=GRAPHIC
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 92 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
NB VIDEO ALIASES
14A5 =CRT_TVO_IREF CRT_TVO_IREF 14B5 =CRT_BLUE CRT_BLUE 69B8 71C3
MAKE_BASE=TRUE
14C5 =TV_A_DAC TV_A_DAC MAKE_BASE=TRUE
69B8 71C3
14B5 =TV_B_DAC TV_B_DAC MAKE_BASE=TRUE

14B5 =CRT_GREEN CRT_GREEN 69A8 71C3
=TV_C_DAC TV_C_DAC
Video Connectors EXTERNAL VIDEO (VGA) INTERFACE
14B5 69A8 71C3
MAKE_BASE=TRUE
14B5 =CRT_RED CRT_RED 69A8 71C3
MAKE_BASE=TRUE
14B5 =CRT_HSYNC_R CRT_HSYNC_R 69C3 71C3
D 14A5 =CRT_VSYNC_R CRT_VSYNC_R MAKE_BASE=TRUE

69C3 71C3
MAKE_BASE=TRUE D
Isolation required for DVI power switch
TMDS(MINI DVI) INTERFACE
A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF CRITICAL D9401
1SS418 L9444
AND GROUND F9404SOD-723 600-OHM-300MA
0.5AMP-13.2V
R9469
1.21K 7A7
=PP5V_S0_TMDS 1 2 PP5V_S0_TMDS_FUSE
2 1 1 2 PP5V_S0_DVIPORT 69B4
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR
VOLTAGE=5V VOLTAGE=5V 0402 VOLTAGE=5V
71C3 69D7 CRT_TVO_IREF 1 2 MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20 MM SM-LF MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
1%
1/16W
MF-LF
1 C9404
0.1UF
=PP3V3_S0_TMDS 7C4 68B1 68B2 68B7 68C8 68D8 69B7 69C8
402 20%
2 10V
CERM
1 C9460
402 0.1UF
20%
2 10V
CERM
=GND_CHASSIS_TMDS_UPPER 8C8 69A4 CRITICAL 402
=PP3V3_S0_NB
TABLE_ALT_HEAD
7C4 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: U9404
8 SN74LVC2G125DCU
PART NUMBER
R9460
39
US
R9470
CRT_HSYNC_LS 1 39
VCC
TABLE_ALT_ITEM
740S0044 740S0028 ? F9404

CRT_HSYNC_R1 2 CRT_HSYNC_LS_R
5 A 3 2 VGA_HSYNC
71C3 69D5
125 Y 69B4
1
R9466 R9467
1
PP5V_S0_DVIPORT_D
5%
1/16W GND
5%
1/16W NOSTUFF
2.2K
5%
2.2K
5%
MF-LF
402 4
7 MF-LF
402 1 C9442
1/16W
MF-LF
1/16W
MF-LF 33PF
5%
2402 2 402 2 50V
DVI power DIODE on page 95 (D9500) CERM
402
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR
TV_DCONSEL<0> R9462 1 1
R9463
C C
14B5
2.2K 2.2K CRITICAL

5% 5% 8 U9404
14B5 TV_DCONSEL<1> 1/16W
MF-LF
1/16W
MF-LF R9461
39 VCC
SN74LVC2G125DCU
US
R9471
39
4022 2402 CRT_VSYNC_R 1 2 CRT_VSYNC_LS_R
2 A 6 CRT_VSYNC_LS 1 2 VGA_VSYNC
71C3 69D5
5%
125 Y
5%
69B4
1/16W GND 1/16W NOSTUFF

68A8 TMDS_HTPLG MF-LF
402 4
1 MF-LF
402 1 C9443
33PF
5%
=PP3V3_S0_TMDS 2 50V
69C2 69B7 68D8 68C8 68B7 68B2 68B1 7C4
1 C9410 CERM
402
10%
0.001UF
R94211 R94221 2 50V
CERM
TABLE_ALT_HEAD
2.2K 2.2K 402 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
5%
1/16W
5%
1/16W 5
Q9401 GPU_CRT_DDC_CLK
PART NUMBER
SSM6N15FE
TABLE_ALT_ITEM
MF-LF MF-LF 155S0370 155S0348 ? L9404 MURATA ALTERNATIVE

4022 4022
OMIT
G
SOT563
Q9401 1 C9411 CRITICAL
100PF
CRT_DDC_CLK
2
SSM6N15FE 5% L9405
S
14B5
2 50V
G
IO
3 SOT563 90-OHM-100MA
4 CERM 1210-4SM1
402 TMDS_TX_P<2> 68B2 68C3
CRT_DDC_DATA GPU_CRT_DDC_DATA OMIT 2 3

S
14B5
IO
6 CRITICAL
NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT 1
J9401 TMDS_TX_N<2> 68B2 68C1
1 C9412 MINI-DVI-M42-BLK 1 4
100PF
SYM_VER-1
PLACE R9450 R9451 CLOSE TO GMCH F-RT-TH OMIT CRITICAL

5%
69D7
71C3
TV_A_DAC
CRT_BLUE
2 50V
CERM
402 PP5V_S0_DVIPORT 17
25 1
9
TMDS_TX_CONN_P<2>
L9407
90-OHM-100MA
71C3 69D5 69D4 1210-4SM1 TMDS_TX_P<1>
26 2 TMDS_TX_CONN_N<2> 68B2 68D3
2 3
18 10
B R9450
1
75
1
R9451
75 69C8 69C2
68B2 68B1 7C4 =PP3V3_S0_TMDS
NC
NC
27
19
3
11
TMDS_TX_CONN_P<1>
1 4
TMDS_TX_N<1> 68B2 68D1
B
1% 1% 68D8 68C8 68B7
28 4 TMDS_TX_CONN_N<1>
EXT_COMPVID_B
SYM_VER-1
1/16W 1/16W
MF-LF MF-LF
VGA_B 20 12 OMIT
2402 2402 C9439
1
VGA_HSYNC 29 5 TMDS_TX_CONN_P<0> CRITICAL
14B5 =TV_A_RTN 0.1UF
10%
69C1
13 L9406
90-OHM-100MA
2 16V
X5R TMDS_TX_CONN_N<0> 1210-4SM1
=CRT_BLUE_L
402
30 6 TMDS_TX_P<0>
FL9400
14B5 68B2 68D3
VGA_G 22 14 2 3
CRITICAL
16
1
210MHZ
MEA2010P-SM 8 69C1 VGA_VSYNC
31 7 TMDS_TX_CONN_CLK_P
VCC 15 TMDS_TX_N<0> 68B2 68D1
2 4 1 4
S1A DA TMDS_TX_CONN_CLK_N
PLACE R9452 R9453 CLOSE TO GMCH 3 S2A
U9401 2 7 32 8 SYM_VER-1
CRITICAL
VGA_R 24 16
SOP
EXT_Y_G L9404
TS3V330
69D7 TV_B_DAC 5 S1B DB 7 3 6

71C3
CRT_GREEN 6 300-OHM-100MA
S2B 1210-4SM
33
34
35
36
69D5
71C3 TMDS_TX_CLK_P 68B2 68C3
4 5
11 9 514-0376 2 3
1
R9452 1R9453 10
S1C
S2C
DC
75 75 12
TMDS_TX_CLK_N 68B2 68C1
1%
1/16W
MF-LF
1%
1/16W
MF-LF
14 S1D
DD
CRITICAL =GND_CHASSIS_TMDS_UPPER 8A6 =GND_CHASSIS_TMDS_DOWN
1 4
13 1 69C4 8C8 SYM_VER-1
2 402 2 402 S2D IN

EN_L 15 NOSTUFF
14B5 =TV_B_RTN
GND 1 C9421
14B5
=CRT_GREEN_L 8 EXT_C_R 0.1UF
10%
16V
2 X5R
402
MINI-DVI CONNECTOR
SYNC_MASTER=EUGENESYNC_DATE=05/21/05
A PLACE R9454 R9455 CLOSE TO GMCH
TABLE_5_HEAD

A
69D7 TV_C_DAC
71C3 TABLE_5_ITEM
CRT_RED 155S0371 3 TDK AND MURATA L9405,L9406,L9407 CRITICAL K36 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
69D5 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
71C3 AGREES TO THE FOLLOWING
1
R9454 1R9455 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
75
1%
75
1%
1/16W 1/16W SB_CRT_TVOUT_MUX_L 24D2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF-LF MF-LF
2402 2402
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION SIZE DRAWING NUMBER REV.
14B5 =CRT_RED_L
14B5 =TV_C_RTN
514-0480 1 CONN,REC,MINI-DVI,32P,RA,TABS,MG3 J9401 CRITICAL NORMAL
TABLE_5_ITEM
TABLE_5_ITEM
APPLE INC.
D 051-7559 H
514-0481 1 CONN,REC,MINI-DVI,32P,RA,TABS,BLK J9401 CRITICAL FANCY SCALE SHT OF

NONE 94 106
8 7 6 5 4 3 2 1
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FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
FSB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
FSB_COMMON FSB_55S FSB_COMMON FSB_ADS_L 9D6 13C3
FSB_DSTB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_COMMON FSB_55S FSB_COMMON FSB_BNR_L 9D6 13C3
FSB_COMMON FSB_55S FSB_COMMON FSB_BPRI_L 9D6 13C3

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
FSB_COMMON FSB_55S FSB_COMMON FSB_BREQ0_L 9D6 13B3

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
FSB_COMMON FSB_55S FSB_COMMON FSB_DBSY_L 9D6 13B3
FSB_ADDR * =3:1_SPACING ? FSB_DATA * =3:1_SPACING ? FSB_COMMON FSB_55S FSB_COMMON FSB_DEFER_L 9D6 13B3
FSB_COMMON FSB_55S FSB_COMMON FSB_DPWR_L 9B2 13B3

FSB_ADDR2ADDR * =2:1_SPACING ? FSB_DATA2DATA * =2:1_SPACING ?
FSB_DRDY_L
D FSB_ADSTB * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM
FSB_DSTB * =3:1_SPACING ?
FSB_COMMON
FSB_COMMON
FSB_55S
FSB_55S
FSB_COMMON
FSB_COMMON FSB_HIT_L
9D6 13B3
9C6 13B3 D
FSB_COMMON FSB_55S FSB_COMMON FSB_HITM_L 9C6 13B3

FSB_ADDR2ADSTB * =3:1_SPACING ? FSB_DATA2DSTB * =3:1_SPACING ?
FSB_COMMON FSB_55S FSB_COMMON FSB_LOCK_L 9D6 13B3
TABLE_SPACING_RULE_HEAD
FSB_COMMON FSB_55S FSB_COMMON FSB_RS_L<2..0> 9D6 13A3
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_COMMON FSB_55S FSB_COMMON FSB_TRDY_L 9D6 13B3
FSB_CPURST_L FSB_55S FSB_COMMON FSB_CPURST_L 9D6 12B5 13A5

FSB_COMMON * =2:1_SPACING ?
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_D_L<15..0> 9C4 13C5 13D5
TABLE_SPACING_ASSIGNMENT_HEAD
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DINV_L<0> 9C4 13B3

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<0> 9C4 13B3
FSB_ADDR FSB_ADDR * FSB_ADDR2ADDR FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<0> 9C4 13B3

FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_D_L<31..16> 9B4 9C4 13C5
FSB_DATA_GROUP1 FSB_55S FSB_DATA FSB_DINV_L<1> 9B4 13B3

FSB_DATA FSB_DATA * FSB_DATA2DATA
FSB_DSTB1 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<1> 9B4 13B3
FSB_DATA FSB_DSTB * FSB_DATA2DSTB FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<1> 9B4 13B3
All FSB signals with impedance requirements are 55-ohm single-ended. FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_D_L<47..32> 9C2 13B5 13C5
Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs. FSB_DATA_GROUP2 FSB_55S FSB_DATA FSB_DINV_L<2> 9C2 13B3
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs. FSB_DSTB2 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<2> 9C2 13A3
DSTB complementary pairs are spaced 1:1 and routed as differential pairs. FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<2> 9C2 13B3
Design Guide recommends each strobe/signal group is routed on the same layer. FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_D_L<63..48> 9B2 9C2 13B5
Design Guide recommends FSB signals be routed only on internal layers. FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_DINV_L<3> 9B2 13B3
FSB_DSTB3 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<3> 9B2 13A3

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1. FSB_DSTB_L_N<3>
FSB_DSTB_55S FSB_DSTB 9B2 13B3
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_A_L<16..3> 9D8 13C3 13D3
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3 FSB_REQ_L<4..0>
FSB_ADDR_GROUP0 FSB_55S FSB_ADDR
C CPU Signal Constraints C
9C8 9D8 13A3
FSB_ADSTB0 FSB_55S FSB_ADSTB FSB_ADSTB_L<0> 9D8 13C3
FSB_ADDR_GROUP1 FSB_55S FSB_ADDR FSB_A_L<35..17> 9C8 13C3
PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_ADSTB1 FSB_55S FSB_ADSTB FSB_ADSTB_L<1> 9C8 13C3
CPU_27P4S * Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL CPU_IERR_L CPU_55S CPU_IERR_L 9D6
CPU_FERR_L CPU_55S CPU_FERR_L 9C8 22C2

CPU_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
CPU_PROCHOT_L CPU_55S CPU_2TO1 CPU_PROCHOT_L 9C5 45B5 45C3 59C8
NOTE: 7 mil gap is for VCCSense pair, which CPU_PWRGD CPU_55S CPU_PWRGD 9B2 12B1 22C4
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT Intel says to route with 7 mil spacing without CPU_FROM_SB CPU_55S CPU_INTR 9B8 22C4
specifying a target differential impedance. CPU_FROM_SB CPU_55S CPU_NMI 9B8 22C4

CPU_2TO1 * =2:1_SPACING ?
CPU_FROM_SB CPU_55S CPU_A20M_L 9C8 22C4
CPU_COMP * 25 MIL ? CPU_FROM_SB CPU_55S CPU_DPSLP_L 9B2 22C4

CPU_FROM_SB CPU_55S CPU_IGNNE_L 9C8 22C4

CPU_GTLREF * 25 MIL ?
DG recommends at least 25 mils, >50 mils preferred CPU_INIT_L CPU_55S CPU_INIT_L 9D6 22C4 46B2
CPU_ITP * =2:1_SPACING ? CPU_FROM_SB CPU_55S CPU_SMI_L 9B8 22C4

CPU_FROM_SB CPU_55S CPU_STPCLK_L 9B8 22C4

CPU_VCCSENSE * 25 MIL ?
PM_THRMTRIP_L CPU_55S CPU_2TO1 PM_THRMTRIP_L 9C6 15A6 22C2 45B3
FSB_CPUSLP_L CPU_55S FSB_CPUSLP_L 9A2 13A5

Most CPU signals with impedance requirements are 55-ohm single-ended. PM_DPRSLPVR
PM_DPRSLPVR CPU_55S CPU_2TO1 15A6 24C3 59D8
Some signals require 27.4-ohm single-ended impedance. IMVP_DPRSLPVR
(See above) CPU_55S CPU_2TO1 59C7
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 CPU_BSEL0 CPU_55S CPU_2TO1 CPU_BSEL<0> 9B4 29C6
(See above) CPU_55S CPU_2TO1 NB_BSEL<0> 15C6 29C8
CPU_BSEL1 CPU_55S CPU_2TO1 CPU_BSEL<1> 9A4 29B6
(See above) CPU_55S CPU_2TO1 NB_BSEL<1> 15C6 29B8
CPU_BSEL2 CPU_55S CPU_2TO1 CPU_BSEL<2> 9A4 29A6
(See above) CPU_55S CPU_2TO1 NB_BSEL<2> 15B6 29B8
B CPU_DPRSTP_L CPU_55S CPU_2TO1 CPU_DPRSTP_L 9B2 15B6 22C4 59C7

B
CPU_GTLREF CPU_55S CPU_GTLREF CPU_GTLREF 9B4
CPU_COMP CPU_55S CPU_COMP CPU_COMP<3> 9B3
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 9B3
CPU_COMP CPU_55S CPU_COMP CPU_COMP<1> 9B3
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 9B3
XDP_TDI CPU_55S CPU_ITP XDP_TDI 9B7 9C6 12B3
XDP_TDO CPU_55S CPU_ITP XDP_TDO 9A7 9C6 12B5
XDP_TMS CPU_55S CPU_ITP XDP_TMS 9B7 9C6 12B2
XDP_TCK CPU_55S CPU_ITP XDP_TCK 9A7 9C6 12B2 12B3
XDP_TRST_L CPU_55S CPU_ITP XDP_TRST_L 9A7 9C6 12B3
XDP_BPM_L CPU_55S CPU_ITP XDP_BPM_L<4..0> 9C6 12B2 12B3
XDP_BPM_L5 CPU_55S CPU_ITP XDP_BPM_L<5> 9C5 12B2
CLK_FSB_100D CLK_FSB XDP_CLK_P 75C3
CLK_FSB_100D CLK_FSB XDP_CLK_N 75C3
(FSB_CPURST_L) CPU_55S CPU_ITP ITP_CPURST_L

CPU_55S CPU_2TO1 CPU_VID<6..0> 10B7 59C7
CPU_55S CPU_2TO1 IMVP6_VID<6..0>

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 10A6 59A4 59A5
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N 10A6 59A4 59A5
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P

CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N
CPU/FSB Constraints
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 100 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
PCI-Express / DMI Bus Constraints
ALLOW ROUTE
NET_TYPE
PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
PEG_R2D PCIE_100D PCIE PEG_D2R_N<1> 14D3 68B6
DMI_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_100D PCIE PEG_D2R_P<1> 14C3 68B6
PCIE_100D PCIE PEG_R2D_C_P<3..0> 14B3 68B6 68C6

PCIE_100D PCIE PEG_R2D_C_N<3..0> 14B3 14C3 68B6 68C6

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PCIE * 20 MIL ?
DMI * 20 MIL ?
D SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5 DMI_N2S DMI_100D DMI DMI_N2S_P<3..0> 15B3 23D2
D
DMI_100D DMI DMI_N2S_N<3..0>
Video Signal Constraints
15B3 23D2
DMI_S2N DMI_100D DMI DMI_S2N_P<3..0> 15B3 23D2
ALLOW ROUTE
DMI_100D DMI DMI_S2N_N<3..0> 15B3 15C3 23D2

LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK_P 14C5 67B3

LVDS_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK_N 14C5 67B3
CRT_50S * Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_P<2..0> 14C5 67B2
LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_N<2..0> 14C5 67B2

CRT_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
LVDS_A_DATA3 LVDS_100D LVDS LVDS_A_DATA_P<3>
LVDS_A_DATA3 LVDS_100D LVDS LVDS_A_DATA_N<3>
LVDS * 20 MIL ?
CRT * 25 MIL ? DG Says 40 mil spacing minimum

CRT_2CRT * 20 MIL ?
CRT_SYNC * 25 MIL ? DG Says 30 mil spacing minimum LVDS_IBG LVDS LVDS_IBG 14D5 67A8
CRT_SYNC2SYNC * 20 MIL ? CRT_TVO_IREF CRT CRT_TVO_IREF 69D7 69D8

CRT_RED CRT_50S CRT CRT_RED 69A8 69D5

TVDAC * 25 MIL ? DG Says 40 mil spacing minimum CRT_GREEN
CRT_GREEN CRT_50S CRT 69A8 69D5
TVDAC_2TVDAC * 20 MIL ? CRT_BLUE CRT_50S CRT CRT_BLUE 69B8 69D5
CRT_SYNC CRT_55S CRT_SYNC CRT_HSYNC_R 69C3 69D5

CRT_SYNC CRT_55S CRT_SYNC CRT_VSYNC_R 69C3 69D5

TV_A_DAC CRT_50S TVDAC TV_A_DAC 69B8 69D7
CRT CRT * CRT_2CRT TV_B_DAC CRT_50S TVDAC TV_B_DAC

C C
69A8 69D7
TV_C_DAC CRT_50S TVDAC TV_C_DAC 69A8 69D7

CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC
TVDAC TVDAC * TVDAC_2TVDAC
LVDS signals are 100-ohm +/- 20% differential impedence.

CRT & TVDAC signal single-ended impedence varies by location:
- 37.5-ohm +/- 15% from GMCH to first termination resistor.
- 50-ohm +/- 15% from first to second termination resistor.
- 55-ohm +/- 15% from second termination resistor to connector.
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.
B B
NB Constraints
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 101 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
DDR2 Memory Bus Constraints Memory Net Properties
ALLOW ROUTE
NET_TYPE
MEM_45S * Y =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD
MEM_A_CLK MEM_70D MEM_CLK MEM_CLK_P<2..0> 15D3 30A4 30D4
MEM_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_70D MEM_CLK MEM_CLK_N<2..0> 15D3 30A4 30D4
MEM_70D * Y =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_A_CNTL MEM_45S MEM_CTRL MEM_CKE<1..0> 15D3 30C4 30C6 32D6
MEM_A_CNTL MEM_45S MEM_CTRL MEM_CS_L<1..0> 15D3 30B4 30B6 32D6

MEM_85D * Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
MEM_A_CNTL MEM_45S MEM_CTRL MEM_ODT<1..0> 15C3 30B4 30B6 32D6
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
MEM_A_CMD MEM_55S MEM_CMD MEM_A_A<14..0> 15C6 16B5 16C5 30B4 30B6 30C4 30C6 32C6
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_A_BS<2..0>
D MEM_CLK2MEM * =4:1_SPACING ?
MEM_CLK MEM_CLK *
MEM_CLK2MEM
MEM_A_CMD
MEM_A_CMD
MEM_55S
MEM_55S
MEM_CMD
MEM_CMD MEM_A_RAS_L
16D5 30B4 30B6 30C6 32C6
16B5 30B4 32B6 D

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_CMD MEM_55S MEM_CMD MEM_A_CAS_L 16D5 30B6 32B6

MEM_CTRL2CTRL * =2:1_SPACING ? MEM_CLK MEM_CTRL * MEM_CLK2MEM
MEM_A_CMD MEM_55S MEM_CMD MEM_A_WE_L 16B5 30B6 32B6
MEM_CTRL2MEM * =3:1_SPACING ? MEM_CLK MEM_CMD * MEM_CLK2MEM

MEM_A_DQ_BYTE0 MEM_55S MEM_DATA MEM_A_DQ<7..0> 16D8 30D4 30D6
MEM_CMD2CMD * =1.5:1_SPACING ? MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_A_DQ_BYTE1 MEM_55S MEM_DATA MEM_A_DQ<15..8> 16C8 30D4 30D6
MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DQ<23..16> 16C8 30C4 30C6

MEM_CMD2MEM * =3:1_SPACING ? MEM_CLK MEM_DQS * MEM_CLK2MEM
MEM_A_DQ_BYTE3 MEM_55S MEM_DATA MEM_A_DQ<31..24> 16C8 30C4 30C6 30D4 30D6
MEM_DATA2DATA * =1.5:1_SPACING ? TABLE_SPACING_ASSIGNMENT_HEAD

MEM_A_DQ_BYTE4 MEM_55S MEM_DATA MEM_A_DQ<39..32> 16B8 16C8 30B4 30B6
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DQ<47..40> 16B8 30A4 30A6 30B4 30B6
MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQ_BYTE6 MEM_55S MEM_DATA MEM_A_DQ<55..48> 16B8 30A4 30A6

MEM_CMD MEM_CLK * MEM_CMD2MEM

MEM_DQS2MEM * =3:1_SPACING ? TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQ_BYTE7 MEM_55S MEM_DATA MEM_A_DQ<63..56> 16A8 16B8 30A4 30A6
MEM_CMD MEM_CTRL * MEM_CMD2MEM

MEM_2OTHER * 25 MIL ? TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DM0 MEM_55S MEM_DATA MEM_A_DM<0> 16D5 30D4
MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DM1 MEM_55S MEM_DATA MEM_A_DM<1> 16D5 30D4

MEM_A_DM2 MEM_55S MEM_DATA MEM_A_DM<2> 16C5 30C6

MEM_CMD MEM_DATA * MEM_CMD2MEM
MEM_A_DM3 MEM_55S MEM_DATA MEM_A_DM<3> 16C5 30C4
MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DM4 MEM_55S MEM_DATA MEM_A_DM<4> 16C5 30B4
MEM_A_DM5 MEM_55S MEM_DATA MEM_A_DM<5> 16C5 30B6

MEM_A_DM6 MEM_55S MEM_DATA MEM_A_DM<6> 16C5 30A6

MEM_A_DM7 MEM_55S MEM_DATA MEM_A_DM<7> 16C5 30A4
MEM_CTRL MEM_CLK * MEM_CTRL2MEM

MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS_P<0> 16C5 30D6
MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_85D MEM_DQS MEM_A_DQS_N<0> 16C5 30D6

MEM_A_DQS1 MEM_85D MEM_DQS MEM_A_DQS_P<1> 16C5 30D6

MEM_CTRL MEM_CMD * MEM_CTRL2MEM
MEM_85D MEM_DQS MEM_A_DQS_N<1> 16C5 30D6
MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS_P<2> 16C5 30C4
MEM_85D MEM_DQS MEM_A_DQS_N<2>

C C
16C5 30C4
MEM_CTRL MEM_DQS * MEM_CTRL2MEM

MEM_A_DQS3 MEM_85D MEM_DQS MEM_A_DQS_P<3> 16C5 30C6
MEM_85D MEM_DQS MEM_A_DQS_N<3> 16C5 30C6
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQS4 MEM_85D MEM_DQS MEM_A_DQS_P<4> 16C5 30B6
MEM_85D MEM_DQS MEM_A_DQS_N<4> 16C5 30B6

MEM_DATA MEM_CLK * MEM_DATA2MEM
MEM_A_DQS5 MEM_85D MEM_DQS MEM_A_DQS_P<5> 16C5 30B4
MEM_DATA MEM_CTRL * MEM_DATA2MEM MEM_85D MEM_DQS MEM_A_DQS_N<5> 16C5 30B4

MEM_A_DQS6 MEM_85D MEM_DQS MEM_A_DQS_P<6> 16C5 30A4

MEM_DATA MEM_CMD * MEM_DATA2MEM
MEM_85D MEM_DQS MEM_A_DQS_N<6> 16C5 30A4
MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_A_DQS7 MEM_85D MEM_DQS MEM_A_DQS_P<7> 16C5 30A6

MEM_85D MEM_DQS MEM_A_DQS_N<7> 16C5 30A6

MEM_DATA MEM_DQS * MEM_DATA2MEM
MEM_B_CLK MEM_70D MEM_CLK MEM_CLK_P<5..3> 15D3 31A4 31D4
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
MEM_70D MEM_CLK MEM_CLK_N<5..3> 15D3 31A4 31D4

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CNTL MEM_45S MEM_CTRL MEM_CKE<4..3> 15D3 31C4 31C6 32D5 32D6

MEM_CLK * * MEM_2OTHER MEM_DQS MEM_CLK * MEM_DQS2MEM
MEM_B_CNTL MEM_45S MEM_CTRL MEM_CS_L<3..2> 15C3 15D3 31B4 31B6 32D6
MEM_CTRL * * MEM_2OTHER MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_B_CNTL MEM_45S MEM_CTRL MEM_ODT<3..2> 15C3 31B4 31B6 32D6
MEM_CMD * * MEM_2OTHER MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_B_CMD MEM_55S MEM_CMD MEM_B_A<14..0> 15C6 16B1 16C1 31B4 31B6 31C4 31C6 32A5 32B5
MEM_B_CMD MEM_55S MEM_CMD MEM_B_BS<2..0> 16D1 31B4 31B6 31C6 32A6

MEM_DATA * * MEM_2OTHER MEM_DQS MEM_DATA * MEM_DQS2MEM
MEM_B_CMD MEM_55S MEM_CMD MEM_B_RAS_L 16B1 31B4 32A6
MEM_DQS * * MEM_2OTHER MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_B_CMD MEM_55S MEM_CMD MEM_B_CAS_L 16D1 31B6 32A6
MEM_B_CMD MEM_55S MEM_CMD MEM_B_WE_L 16B1 31B6 32A6

Need to support MEM_*-style wildcards!
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DQ<7..0> 16D4 31D4 31D6
MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DQ<15..8> 16C4 31D4 31D6
MEM_B_DQ_BYTE2 MEM_55S MEM_DATA MEM_B_DQ<23..16> 16C4 31C4 31C6
MEM_B_DQ_BYTE3 MEM_55S MEM_DATA MEM_B_DQ<31..24> 16C4 31C4 31C6
B MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_55S
MEM_55S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
16B4 16C4 31B4 31B6
16B4 31A4 31A6 31B4 31B6

B
MEM_B_DQ_BYTE6 MEM_55S MEM_DATA MEM_B_DQ<55..48> 16B4 31A4 31A6
MEM_B_DQ_BYTE7 MEM_55S MEM_DATA MEM_B_DQ<63..56> 16A4 16B4 31A4 31A6
MEM_B_DM0 MEM_55S MEM_DATA MEM_B_DM<0> 16D1 31D4
MEM_B_DM1 MEM_55S MEM_DATA MEM_B_DM<1> 16D1 31D4
MEM_B_DM2 MEM_55S MEM_DATA MEM_B_DM<2> 16C1 31C4
MEM_B_DM3 MEM_55S MEM_DATA MEM_B_DM<3> 16C1 31C6
MEM_B_DM4 MEM_55S MEM_DATA MEM_B_DM<4> 16C1 31B4
MEM_B_DM5 MEM_55S MEM_DATA MEM_B_DM<5> 16C1 31A6
MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS_P<0> 16C1 31D6
MEM_85D MEM_DQS MEM_B_DQS_N<0> 16C1 31D6
MEM_B_DQS1 MEM_85D MEM_DQS MEM_B_DQS_P<1> 16C1 31D6
MEM_85D MEM_DQS MEM_B_DQS_N<1> 16C1 31D6
MEM_B_DQS2 MEM_85D MEM_DQS MEM_B_DQS_P<2> 16C1 31C6
MEM_85D MEM_DQS MEM_B_DQS_N<2> 16C1 31C6
MEM_B_DQS3 MEM_85D MEM_DQS MEM_B_DQS_P<3> 16C1 31C4
MEM_85D MEM_DQS MEM_B_DQS_N<3> 16C1 31C4
MEM_B_DQS4 MEM_85D MEM_DQS MEM_B_DQS_P<4> 16C1 31B6
MEM_85D MEM_DQS MEM_B_DQS_N<4> 16C1 31B6
MEM_B_DQS5 MEM_85D MEM_DQS MEM_B_DQS_P<5>

Memory Constraints
16C1 31A4
MEM_85D MEM_DQS MEM_B_DQS_N<5> 16C1 31B4
MEM_B_DQS6 MEM_85D MEM_DQS MEM_B_DQS_P<6>

A
16C1 31A6
SYNC_MASTER=WFERRY SYNC_DATE=06/08/2006
MEM_B_DQS7
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
16C1 31A6
16C1 31A4 NOTICE OF PROPRIETARY PROPERTY

A
MEM_85D MEM_DQS MEM_B_DQS_N<7> 16C1 31A4
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 102 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
Disk Interface Constraints
ALLOW ROUTE
NET_TYPE
IDE_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
IDE_PDD IDE_55S IDE IDE_PDD<15..0> 22B4 22C4 39C3 39C5
SATA_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD IDE_PDA IDE_55S IDE IDE_PDA<2..0> 22B4 39B3 39B5
IDE_PDCS IDE_55S IDE IDE_PDCS1_L 22B4 39B5

SATA_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
IDE_PDCS IDE_55S IDE IDE_PDCS3_L 22B4 39B3
IDE_CNTL IDE_55S IDE IDE_PDIOW_L 22B4 39B5
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT IDE_PDIOR_L IDE_55S IDE IDE_PDIOR_L 22B4 39C3
IDE_CNTL IDE_55S IDE IDE_PDDACK_L 22B4 39B3

IDE * =1.8:1_SPACING ?
IDE_PDDREQ
D SATA * 20 MIL ?
IDE_CNTL
IDE_PDIORDY
IDE_55S
IDE_55S
IDE
IDE IDE_PDIORDY
22A4 39C3
22A4 39B5 D
IDE_IRQ14 IDE_55S IDE IDE_IRQ14 22B4 39B5
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9 IDE_RST_L IDE_55S IDE ODD_RST_5VTOL_L 23B6 39A8
HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD

SATA_A_R2D SATA_100D
SATA_100D
SATA
SATA
SATA_A_R2D_C_P
SATA_A_R2D_C_N
22B6 40D4
22B6 40D4
PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D SATA SATA_A_R2D_P 40D7
SATA_100D SATA SATA_A_R2D_N 40D7

HDA_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
SATA_A_D2R SATA_100D SATA SATA_A_D2R_P 22B6 40C4
SATA_100D SATA SATA_A_D2R_N 22B6 40D4
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SATA_100D SATA SATA_A_D2R_C_P 40C7

SATA_100D SATA SATA_A_D2R_C_N 40D7

HDA * =1.8:1_SPACING ?
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
USB_60S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

USB_90D * Y =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

USB * 20 MIL ?
USB_2CLK * 25 MIL ? DG says minimum spacing 50 mils to clocks

C SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2
C
HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 8A6 22C8
Internal Interface Constraints HDA_55S HDA HDA_BIT_CLK_R 22C6
ALLOW ROUTE
HDA_SYNC HDA_55S HDA HDA_SYNC 8A6 22C8

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
HDA_55S HDA HDA_SYNC_R 22C6
SMB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_RST_L HDA_55S HDA HDA_RST_L 8A6 22C8
HDA_55S HDA HDA_RST_L_R 22C6

SPI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
HDA_SDIN0 HDA_55S HDA HDA_SDIN0 8A6 22C8
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_SDOUT HDA_55S HDA HDA_SDOUT 8A6 22B8
HDA_55S HDA HDA_SDOUT_R 22B6

SMB * =3:1_SPACING ?
USB_EXTA USB_90D USB USB_EXTA_P 8C1 23C2

SPI * =1.8:1_SPACING ?
USB_90D USB USB_EXTA_N 8C1 23C2
USB_90D USB USB_EXTA_MUXED_P

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17
USB_90D USB USB_EXTA_MUXED_N
USB_MINI USB_90D USB USB_MINI_P 8C1 23C2
USB_90D USB USB_MINI_N 8C1 23C2
USB_3G USB_90D USB USB_3G_P

USB_90D USB USB_3G_N
USB_CAMERA USB_90D USB USB_CAMERA_P 8C1 23C2
USB_90D USB USB_CAMERA_N 8C1 23C2
USB_BT USB_90D USB USB_BT_P 8C1 8C2 23C2
USB_90D USB USB_BT_N 8B1 8B2 23C2
USB_TPAD USB_90D USB USB_TPAD_P 8C1 23C2
B USB_IR
USB_90D
USB_90D
USB
USB
USB_TPAD_N
USB_IR_P
8C1 23C2
8C1 8C2 23C2

B
USB_90D USB USB_IR_N 8C1 8C2 23C2
USB_EXTB USB_90D USB USB_EXTB_P 8B1 23C2
USB_90D USB USB_EXTB_N 8B1 23C2
USB_EXCARD USB_90D USB USB_EXCARD_P 8B1 23C2
USB_90D USB USB_EXCARD_N 8B1 23C2
USB_EXTC USB_90D USB USB_EXTC_P 8B1 23C2
USB_90D USB USB_EXTC_N 8B1 23C2
USB_RBIAS USB_60S USB_RBIAS 23B3
SMB_SB_SCL SMB_55S SMB SMB_CLK 24D5 47D8
SMB_SB_SDA SMB_55S SMB SMB_DATA 24D5 47D8
SMB_SB_ME_SCL SMB_55S SMB SMB_ME_CLK 24D5 47A8
SMB_SB_ME_SDA SMB_55S SMB SMB_ME_DATA 24D5 47A8
SPI_SCLK SPI_55S SPI SPI_SCLK_R 23C5 52C7
SPI_55S SPI SPI_A_SCLK_R 52C5
SPI_SI SPI_55S SPI SPI_SI_R 23C5 52C3
SPI_55S SPI SPI_A_SI_R 52C4
SPI_SO SPI_55S SPI SPI_SO 23C5 52C3
SPI_55S SPI SPI_A_SO_R 52C4
SPI_CE_L0 SPI_55S SPI SPI_CE_R_L<0> 23C5 52C7
SPI_55S SPI SPI_CE_L<0> 52C6
SPI_CE_L1 SPI_55S SPI SPI_CE_R_L<1>

SB Constraints (1 of 2)
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 103 106
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
PCI Bus Constraints
ALLOW ROUTE
NET_TYPE
PCI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
PCI_AD PCI_55S PCI PCI_AD<18..0> 23A8 23B8 37B5 37C5
PCI_AD19 PCI_55S PCI PCI_AD<19> 23A8 37B6
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCI_AD20 PCI_55S PCI PCI_AD<20> 23A8 37B5
PCI_AD PCI_55S PCI PCI_AD<31..21> 23A8 37B5

PCI * =2:1_SPACING ?
PCI_AD PCI_55S PCI PCI_PAR 23A6 37B5
PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0> 23B6 37B5

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19 PCI_IRDY_L
PCI_CNTL PCI_55S PCI 23A4 23A6 37A5
Platform LAN (Nineveh) Constraints PCI_CNTL PCI_55S PCI PCI_DEVSEL_L 23A4 23A6 37A5
D
D PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP

PCI_CNTL
PCI_LOCK_L
PCI_55S
PCI_55S
PCI
PCI
PCI_PERR_L
PCI_LOCK_L
23A4 23A6 37A5
23A4 23A6
PCI_CNTL PCI_55S PCI PCI_SERR_L 23A4 23A6 37A5

LAN_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
PCI_CNTL PCI_55S PCI PCI_STOP_L 23A4 23A6 37A5
ENET_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCI_CNTL PCI_55S PCI PCI_TRDY_L 23A4 23A6 37A5
PCI_CNTL PCI_55S PCI PCI_FRAME_L 23A4 23A6 37A5

GLAN_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
PCI_FW_REQ_L PCI_55S PCI PCI_FW_REQ_L 23A4 23B6 37A5
PCI_FW_GNT_L PCI_55S PCI PCI_FW_GNT_L 23B5 37A5
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 23A4 23B6
PCI_GNT1_L PCI_55S PCI PCI_GNT1_L

ENET_CLK * =2.5:1_SPACING ?
PCI_REQ2_L PCI_55S PCI PCI_REQ2_L 23A4 23B6
ENET_GLAN * 20 MILS ? PCI_GNT2_L PCI_55S PCI PCI_GNT2_L

INT_PIRQA_L PCI_55S PCI INT_PIRQA_L 23A4 23A8

ENET_LAN * =1.5:1_SPACING ?
INT_PIRQB_L PCI_55S PCI INT_PIRQB_L 23A4 23A8
ENET_MDI * 25 MILS ? DG says 30 mils min separation. INT_PIRQC_L PCI_55S PCI INT_PIRQC_L 23A4 23A8
INT_PIRQD_L PCI_55S PCI INT_PIRQD_L 23A4 23A8 37A5
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 INT_PIRQE_L PCI_55S PCI INT_PIRQE_L 23A4 23A6
INT_PIRQF_L PCI_55S PCI INT_PIRQF_L

Controller Link (AMT) Constraints
23A4 23A6
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
CLINK_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

CLINK_12MIL * Y 12 MILS 5 MILS 300 MILS =STANDARD =STANDARD
C CLINK * =1.8:1_SPACING ?
C
CLINK_VREF * 12 MILS ?
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
PCIE_E_R2D PCIE_100D PCIE PCIE_E_R2D_C_P 33B5 33B6
PCIE_100D PCIE PCIE_E_R2D_C_N 33B5 33B6
PCIE_E_D2R PCIE_100D PCIE PCIE_E_D2R_P 33B5
PCIE_100D PCIE PCIE_E_D2R_N 33B5 33C5
GLAN_COMP GLAN_COMP 22C6
ENET_LAN LAN_55S ENET_LAN LAN_RSTSYNC

ENET_LAN LAN_55S ENET_LAN LAN_R2D<2..0>
LAN_D2R<2..0>
B
ENET_LAN
ENET_GLAN_CLK
LAN_55S
LAN_55S
ENET_LAN
ENET_CLK ENET_GLAN_CLK_R B
LAN_55S ENET_CLK ENET_GLAN_CLK
ENET_MDI0 ENET_100D ENET_MDI ENET_MDI_P<0> 34B8 36B7
ENET_100D ENET_MDI ENET_MDI_N<0> 34B8 36B7
ENET_MDI1 ENET_100D ENET_MDI ENET_MDI_P<1> 34B8 36C7
ENET_100D ENET_MDI ENET_MDI_N<1> 34B8 36C7
ENET_MDI2 ENET_100D ENET_MDI ENET_MDI_P<2> 34B8 36B7
ENET_MDI3 ENET_100D ENET_MDI ENET_MDI_P<3> 34B8 36C7
CLINK_NB CLINK_55S CLINK CLINK_NB_CLK 15A3 24C3
CLINK_NB CLINK_55S CLINK CLINK_NB_DATA 15A3 24C3
CLINK_NB_RESET_L CLINK_55S CLINK CLINK_NB_RESET_L 15A3 24C3
CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_CLK 24C3
CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_DATA 24C3
CLINK_WLAN_RESET_L CLINK_55S CLINK CLINK_WLAN_RESET_L 24D5
NB_CLINK_VREF CLINK_12MIL CLINK_VREF NB_CLINK_VREF 15A4
SB_CLINK_VREF0 CLINK_12MIL CLINK_VREF SB_CLINK_VREF0 24C3
SB_CLINK_VREF1 CLINK_12MIL CLINK_VREF SB_CLINK_VREF1 24C3
SB Constraints (2 of 2)
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 104 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
Clock Signal Constraints Clock Net Properties
ALLOW ROUTE
NET_TYPE
CLK_FSB_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
CK505_CPU CLK_FSB_100D CLK_FSB CK505_CPU0_P 6C7 28C4 29D6
CLK_PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CK505_CPU CLK_FSB_100D CLK_FSB CK505_CPU0_N 6C7 28C4 29D6
CK505_NB CLK_FSB_100D CLK_FSB CK505_CPU1_P 6C7 28C4 29D6

CLK_MED_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
CK505_NB CLK_FSB_100D CLK_FSB CK505_CPU1_N 6C7 28C4 29D6
CLK_SLOW_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CK505_ITP CLK_FSB_100D CLK_FSB CK505_CPU2_ITP_SRC10_P 6C7 28C4 29D6
CK505_ITP CLK_FSB_100D CLK_FSB CK505_CPU2_ITP_SRC10_N 6C7 28C4 29D6

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CK505_PCIF0 CLK_MED_55S CLK_MED CK505_PCIF0_CLK 28B8 29B6
D CLK_FSB * 25 MIL ?
CK505_PCIF1
CK505_PCI1
CLK_MED_55S
CLK_MED_55S
CLK_MED
CLK_MED
CK505_PCIF1_CLK
CK505_PCI1_CLK
6C7 28B6 29B6
28B6 29B6
D
CLK_PCIE * 20 MIL ? CK505_PCI2 CLK_MED_55S CLK_MED CK505_PCI2_CLK 8C4 28B6
CK505_PCI3 CLK_MED_55S CLK_MED CK505_PCI3_CLK 28B6 29A6

CLK_MED * 20 MIL ?
CK505_PCI4 CLK_MED_55S CLK_MED CK505_PCI4_CLK 8C4 28B6
CLK_SLOW * 10 MIL ? CK505_PCI5 CLK_MED_55S CLK_MED CK505_PCI5_FCTSEL1 28B6 29B2
(CPU_BSEL0) CLK_MED_55S CLK_MED CK505_USB48_FSA 28A4 29D8

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6 CK505_CLK14P3M_TIMER
(CPU_BSEL2) CLK_MED_55S CLK_MED 28A4 29D8
CK505_DOT96 CLK_PCIE_100D CLK_PCIE CK505_DOT96_27M_P 6C7 28A4 29B6
CLK_PCIE_100D CLK_PCIE CK505_DOT96_27M_N 6C7 28A4 29B6
CK505_LVDS CLK_PCIE_100D CLK_PCIE CK505_LVDS_P 6C7 28B4 29C6
CLK_PCIE_100D CLK_PCIE CK505_LVDS_N 6C7 28B4 29C6
CK505_SRC1 CLK_PCIE_100D CLK_PCIE CK505_SRC1_P

CLK_PCIE_100D CLK_PCIE CK505_SRC1_N
CK505_SRC2 CLK_PCIE_100D CLK_PCIE CK505_SRC2_P 6C7 28B4 29C6
CLK_PCIE_100D CLK_PCIE CK505_SRC2_N 6C7 28B4 29C6

CLK_PCIE_100D CLK_PCIE CK505_SRC6_N 6C7 28B4 29B6

C CK505_SRC8 CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
CK505_SRC8_P
CK505_SRC8_N
6B7 28A4 29B6
6B7 28A4 29B6

C
(CK505_CPU) CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 9B6 29D3
(CK505_CPU) CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 9B6 29D3
(CK505_NB) CLK_FSB_100D CLK_FSB FSB_CLK_NB_P 13B3 29D3
(CK505_NB) CLK_FSB_100D CLK_FSB FSB_CLK_NB_N 13B3 29D3
(CK505_ITP) CLK_FSB_100D CLK_FSB XDP_CLK_P 70A3
(CK505_ITP) CLK_FSB_100D CLK_FSB XDP_CLK_N 70A3
(CK505_PCIF0) CLK_MED_55S CLK_MED PCI_CLK33M_LPCPLUS 6C2 29B3 46C4
(CK505_PCIF1) CLK_MED_55S CLK_MED PCI_CLK33M_SB 23A6 29A5 29B3
(CK505_PCI1) CLK_MED_55S CLK_MED PCI_CLK33M_FW 29A5 29B3 37A5
(CK505_PCI2) CLK_MED_55S CLK_MED PCI_CLK33M_TPM

(CK505_PCI3) CLK_MED_55S CLK_MED PCI_CLK33M_SMC 29A3 29A5 44C8
CK505 PCI4 is project-specific

CK505 PCI5 is project-specific
(CPU_BSEL0) CLK_MED_55S CLK_MED SB_CLK48M_USBCTLR 24D3 29A5 29D6
(CPU_BSEL2) CLK_MED_55S CLK_MED SB_CLK14P3M_TIMER 24D3 29A5 29D6
(CPU_BSEL0) CLK_MED_55S CLK_MED CK505_FSA 29C8 29D6
(CPU_BSEL2) CLK_MED_55S CLK_MED CK505_FSC 29A8 29D6
(CK505_DOT96) CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_P 8B1 29B3
(CK505_DOT96) CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_N 8B1 29B3
(CK505_LVDS) CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_P 8B1 29C3
(CK505_LVDS) CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_N 8A1 29C3
B (CK505_SRC1)
(CK505_SRC1)
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
PEG_CLK100M_P
PEG_CLK100M_N
B
(CK505_SRC2) CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_P 23C2 29C3
(CK505_SRC2) CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_N 23D2 29C3
(CK505_SRC3) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_P

(CK505_SRC3) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_N
(CK505_SRC4) CLK_PCIE_100D CLK_PCIE SB_CLK100M_SATA_P 22B6 29C3
(CK505_SRC4) CLK_PCIE_100D CLK_PCIE SB_CLK100M_SATA_N 22B6 29C3
(CK505_SRC5) CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_P 15C3 29C3
(CK505_SRC5) CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_N 15C3 29C3
(CK505_SRC6) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 29C3 33C5
(CK505_SRC6) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 29B3 33C5
CK505 SRC7 is project-specific
CK505 SRC8 is project-specific
Clock Constraints
A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 105 106
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
FireWire Interface Constraints FireWire Net Properties
ALLOW ROUTE
NET_TYPE
FW_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
FW_D_CTL FW_55S FW FW_LINK<7..0>
FW_110D * Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF FW_D_CTL FW_55S FW FW_CTL<1..0>
FW_LCLK CLK_MED_55S CLK_MED CLKFW_LINK_LCLK
CLK_MED_55S CLK_MED CLKFW_PHY_LCLK

FW_PCLK CLK_MED_55S CLK_MED CLKFW_LINK_PCLK
FW * =2:1_SPACING ? CLK_MED_55S CLK_MED CLKFW_PHY_PCLK
FW_LKON FW_55S FW FW_LKON

FW_TP * =3:1_SPACING ?
FW_LKON_R
D FW_LPS
FW_55S
FW_55S
FW
FW FW_LPS D
FW_LREQ FW_55S FW FW_LREQ
FW_PINT FW_55S FW FW_PINT
FWPHY_CLK98P304M_XI CLK_MED_55S CLK_MED CLK98P304M_FW_XI_R
CLK_MED_55S CLK_MED CLK98P304M_FW_XI
FW_0_TPA FW_110D FW_TP FW_0_TPA_P
FW_0_TPA FW_110D FW_TP FW_0_TPA_N
FW_0_TPB FW_110D FW_TP FW_0_TPB_P
FW_110D FW_TP FW_0_TPB_N
FW_1_TPA FW_110D FW_TP FW_1_TPA_P
FW_1_TPA FW_110D FW_TP FW_1_TPA_N
FW_1_TPB FW_110D FW_TP FW_1_TPB_P
FW_110D FW_TP FW_1_TPB_N
Port 2 Not Used
SMC SMBus Net Properties

NET_TYPE
SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 47D2
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 47D2
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL

C C
6B2 47C5
SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 6B2 47C5
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 47D5
SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 47D5
SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 47C2
SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 47C2
SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 47B2
SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 47B2
B B
FireWire & SMC Constraints

A
APPLE INC.
D 051-7559 H
SCALE SHT OF
NONE 106 106
8 7 6 5 4 3 2 1
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Apple Macbook A1181 13 - 7559 820-2279 K36A MLB 051RevH (02-15-2008) Schematics

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Apple Macbook A1181 13 - 7559 820-2279 K36A MLB 051RevH (02-15-2008) Schematics

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8 7 6 5 4 3 2 1

K36A MLB SCHEMATIC

H 581757 PRODUCTION RELEASED 04/15/08

REFERENCED FROM K36

DIMENSIONS ARE IN MILLIMETERS

METRIC APPLE INC.

J9001 U6100/50 J5601

DMI CLnk 0 SPI

E-NET CLnk 1 PCI AZALIA DIMM’s Clk Gen

K36 POWER SYSTEM ARCHITECTURE SMC PWRGD

SMC_BATT_ISENSE PGOOD1 PGOOD2 VR_PWRGD_CK505 VRMPWRGD

BOARD STACK-UP AND CONSTRUCTION

BOM OPTION REMOVED BOM OPTION REMOVED

L7 POWER 0.031 ---

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

0.076 128S0147 4 HF VERSION OF 128S0057 C4610,C4611,C6830,C6831 CRITICAL K36

B 337S3587 1 IC,PDC,Q7ZF,QS,NON-DTS,M0,2.1/0.8G,3M,479FCBGA U1000 CRITICAL GOOD_NON_DTS

128S0164 3 HF VERSION OF 128S0073 C2130,C2716,C7543 CRITICAL K36

337S3561 1 IC,PDC,Q7ZF,QS,C0,2.4/0.8G,3M,479FCBGA U1000 CRITICAL BEST_FUSED

128S0169 3 HF VERSION OF 128S0111 C7220,C7352,C7542 CRITICAL K36

PART NUMBER ALTERNATE FOR

128S0150 6 HF VERSION OF 128S0115 C6204,C6205,C7651,C7652,C7691,C7692 CRITICAL K36

337S3600 337S3576 ? U1000 THERMTRIP SCREENED

L11-L12 0.07 128S0135 2 HF VERSION OF 128S0129 C6601,C6603 CRITICAL K36

337S3604 337S3561 ? U1000 THERMTRIP SCREENED

L12 SIGNAL(BOTTOM)0.047 0.1

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

338S0516 1 IC,CRESTLINE,GM965,667 U1400 CRITICAL K36

TOTAL 1.276 ---

338S0434 1 IC,ICH8,BGA U2300 CRITICAL K36

516-0162 2 IN-LINE SODIMM CONNECTOR J3101,J3201 CRITICAL K36

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

NOTICE OF PROPRIETARY PROPERTY

AGREES TO THE FOLLOWING

826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM EEE:0PH CRITICAL GOOD H

826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM EEE:0PK CRITICAL BEST NONE

Functional Test Points

5VS5_RUNSS I15 TRUE FAN_RT_PWM 50B3 I3 TRUE SMBUS_BATT_SCL_F 57A5

44A8 50B4 I177 TRUE BATT_POS 57B5 D

LPC+ Debug Connector I9

FUNC_TEST I11 TRUE =PP5V_S0_AUDIO 7A7 53A7 56C4

=PP3V42_G3H_LPCPLUS TRUE GND_AUDIO_AMP

CLOCK NO_TESTS I19 TRUE

I22 TRUE ACZ_SDATAIN<0>

TRUE CK505_CPU0_N TRUE LPC_FRAME_L I23

I116 TRUE CK505_CPU2_ITP_SRC10_P 28C4 29D6 75D3

CK505_LVDS_P FWH_INIT_L SYS_ONEWIRE

I81 TRUE PCI_CLK33M_LPCPLUS 29B3 46C4 75C3

TRUE CK505_PCIF1_CLK TRUE LPC_AD<2>

TRUE CK505_SRC2_P TRUE SMC_TDI I46

TRUE CK505_SRC4_N TRUE SMC_NMI I225

I189 TRUE CK505_SRC5_P 28B4 29C6 75C3

28B4 29C6 75C3 Other Func Test Points DC-JACK FUNC_TEST

I58 TRUE 66B5 66C2

I59 TRUE INV_GND 67D2

NO_TEST SLEEP LED FUNC_TEST

TRUE FW_B_TPB_N_SPN I220

I205 TRUE FW_C_TPA_P_SPN 8D1

TRUE FW_C_TPB_N_SPN ALL_SYS_PWRGD

TRUE PP1V05_S0_R TRUE SPKRCONN_L_N_OUT

TRUE PP1V5_S0 TRUE SPKRCONN_R_N_OUT

I211 TRUE LVDS_B_DATA_N0_SPN 8D5 I167 TRUE PP1V2_ENET_S0 7B5

I212 TRUE LVDS_B_DATA_N1_SPN 8D5 I168 TRUE PP1V8_S3 7B4