Proceedings of ESSDERC, Grenoble, France, 2005

A Closed-Form Charge-Based Expression for

Drain Current in Symmetric and Asymmetric
Double Gate MOSFET
A. S. Roy (1) , J.-M. Sallese (1) and C. C. Enz (1,2)
(1) Ecole Polytechnique Fédérale de Lausanne (EPFL)
Laboratoire d’Electronique Général (LEG), CH-1015 Lausanne, Switzerland
(2) Swiss Center for Electronics and Microtechnology (CSEM), CH-2007 Neuchâtel, Switzerland.
anandasankar.roy@epfl.ch, Jean-Michel.Sallese@epfl.ch, christian.enz@csem.ch
Abstract:
Although both exact [6] and design oriented approxi-
mate [3] closed-form analytical solution of the drain cur-
VGf
rent for the symmetric double gate (DG) MOST exist,
a closed-form expression for asymmetric DG MOST is
FRONT GATE
still lacking. This work presents an analytic closed-form
y
charge-based expression for the drain current for asym- VS VD
SOURCE tsi DRAIN
metric DG MOST. The expression presented in this work x L
tox
is valid from weak to strong inversion and retains the BACK GATE
asymptotic behavior.
VGb
1. Introduction
Figure 1: Schematic diagram of a DG MOSFET. ∆f (b)
Double gate (DG) MOST has several intrinsic advantages are the work function difference between the front(back)
over bulk MOST [1, 2, 5]. A good compact model for gate electrode and intrinsic silicon..
DG MOSFET is a prerequisite to actually exploit those
advantages in integrated circuits. To date, a simple phys-
ical compact model is still lacking even for the ‘classi- constant in the Poisson equation and is invariant over ver-
cal’ asymmetric DG MOST because of it’s relatively com- tical position. It is related to the normalized band bending
ψ as
plex electrostatics. Ref [6] has presented an exact so-  2  2
lution for symmetric DG MOST but it does not yield a 1 LD dψ
C=e − ψ
. (2)
closed form solution for the drain current for the asym- 2 tsi dξ
metric case, which is essential in order to have a com- The total inversion charge qi is qi = qf + qb . When the
pact model. In this work we handle the electrostatics in a device operates in weak inversion (WI) qf and qb have
piece-wise way and by suitable interpolation we present a different signs and are approximately equal in magnitude
semi-empirical analytic closed form charge-based expres- (this is because the field inside the silicon film is constant).
sion for the drain current for both symmetrical and asym- In strong inversion (SI), qf and qb have the same sign and
metrical DG MOST. only in SI qf and qb carry the physical significance of in-
version charge.
2. Model Derivation We know that the drain current is given by [3]
 vd  qd
In our work we normalize the voltages by the thermal volt- dvch
I = Ispec qi dvch = Ispec qi dqi , (3)
age UT = kT /q, charges by Cox · UT (Cox = εox /tox vs qs dqi
being the oxide capacitance per unit area) and the distance
W µC ox T U2
x by tsi , with ξ = x/tsi . In appendix it is shown that an where Ispec = L and qs (qd ) is the normalized
analysis of Poisson equation (for undoped silicon) leads to inversion charge at source (drain). The only information

we need in order to formulate a charge-based expression
∗
(b) −vch = qf (b) + ln qf (b) + 2a C −ln(2a ), (1) of the current is dv
2 2 2
vgf dqi as a function of charge qi . When
ch

two gates are tied at the same potential, dv

dqi has the same
ch

where qf (b) is the normalized charge stored per unit area dv

charge dependence as dqgi in equilibrium (see eq. 1). To
in the front (back) gate. a is a technology dependent
 pa- exploit this property we will assume that both gates are
rameter given by a = εεox si tox
LD , where LD =
UT εsi
qni tied to the same potential VG . Note that this is not a lim-
∗
is the Debye length. vgf (b) is the normalized form of itation of the model because any gate voltage asymmetry
VGf (b) − ∆f (b) (see Fig. 1 for the definitions) and vch is can be resolved by defining VG as the common mode volt-
the normalized channel potential [3]. C is the integration age between VGf and VGb and by including the differential

0-7803-9205-1/05/$20.00 ©2005 IEEE 149 Paper 1.D.4

Proceedings of ESSDERC, Grenoble, France, 2005

voltage in ∆f and ∆b . Now we will derive dv dqi in three

ch
inverted surface and two inverted surfaces takes place, we
different operating regions. consider that at this point the front surface will be strongly
In WI the total inversion charge Qi can be written as inverted and contribute to most of the charge. These ob-
 tsi servations allow us to write
Ψ
Qi = qni e UT dx, (4) Qi ≈ Cox (VG − ∆f − Ψp ), (12)
0

where Ψ is the band bending, ni is the carrier concentra-
tion and q is the electron charge. Using E = − dV
dx and
assuming the field is constant along the silicon thickness
(because there is vanishingly small charge stored in the
silicon film) we obtain
where Ψp is the pinch-off value of the surface potential.
To obtain the value of VG at this point, we notice that at
the back surface (which is now at the edge of inversion)
continuity of displacement vector is still applicable and
by the definition of inversion Ψb = Ψp . This implies

UT qni UΨf −Etsi

Csi (Ψp − Ψp ) = 0 = Cox (VG − ∆b − Ψp ). (13)
Qi = e T 1 − e UT , (5)
E Eliminating VG gives
∆b −∆f Qtran = Cox (∆b − ∆f ). (14)
where E = εsi
tsi +2( εox )tox
and Ψf is the band bending at
the front surface. In normalized form we have In normalized form qtran = δb − δf = δ.
dqi dψf When both surfaces are strongly inverted, the integration
= qi . (6) constant has negligible effect because qf and qb are much
dvg dvg
greater than the integration constant (which corresponds
As inversion charge is very small in WI, we can approx- to the minimum band-bending). We can write
imate our system as a capacitive divider and write down ∗
vgf (b) = qf (b) + 2 ln(qf (b) ) (15)
ψf as
Adding these two equations we get
Csi + Cox ∗ Csi
ψf = v + v∗ , (7) 2vg − (δf + δb ) = qf + qb + 2 ln(qf qb ). (16)
2Csi + Cox gf 2Csi + Cox gb
where Csi = εsi /tsi is the silicon capaciance per unit Asymptotically we can assume that qf ≈ qb . Therefore in
area. As both gates are tied to the same potential we have SI, we have
∗ ∗ dvg 1 2
δvgf = δvgb = δvg , which implies = + . (17)
dqi 2 qi
dvg 1 dv
= . (8) Now we will combine all the expressions of dqgi (eqn. (8),
dqi qi (11) and (17)) in such a way that in symmetric case it re-
duces to the derivation presented in [2]. We have chosen
Now we will consider the case when only the front gate is
the following interpolation function between the different
inverted. In order to analyze this situation we will make
asymptotic forms
two assumptions: (i) charge sheet approximation at the
front gate (ii) continuity of displacement vector at the back  
gate. Now, when only the first gate is inverted, the integra- dvg 1 1 1 qin
= + −
tion constant C in the Poisson equation (1) can be well ap- dqi 1+F 2 1+F qin n
+ λqtran
proximated by C ≈ − 21 ( LtsiD )2 · ( dψ 2 (18)
dξ ) ( C is independent 2qi + 2 CCox (qtran + 2)
si

of position and considering the situation at the back gate + Csi

.
qi2 + 2 C (qtran + 2)qi
where band bending is so small that it’s contribution to C ox

can be neglected). Approximation (i) allow us to write In our implementation we have chosen n = 4 and λ = 21 .
dψ This choice provides a reasonably simple expression of the
 ψb − ψf . (9) current and a good accuracy. The expression of the current
dξ
becomes ID = Ispec (i0 (qs ) − i0 (qd )), where
Using approximation (ii) we can write
  √ 2
∗
Cox (vgb − ψb )  Csi (ψb − ψf ). qi2 1 1 1 −1 2q
(10) i0 (qi ) = − √ · − · qtran · tan ( 2 i )
2
4 2 2 2 1+F qtran
Using the above two equations we can eliminate ψb , and  
Csi
∗
from the definitions of qf (b) = vgf (b) − ψf (b) and the fact
+ ln qi2 + 2 (qtran + 2)qi .
Cox
that qi = qf + qb , we express both qf and C in terms of qi
(19)
and substitute them back in (1). We can now differentiate
the expression to obtain This analysis provides the current if the charges at the
source and drain are known. These charges can be found
dvg 1 2qi + 2 CCox
si
·δ by solving a coupled non-linear equations at both ends [3].
= + 2 , (11)
dqi 1+F C
qi + 2 Cox
si
· δ · qi But the equations can be decoupled if one integrates the
dv
expression of dqgi . This requires the evaluation of charge
where F = CsiC+Csi
ox
and δ = δb − δf , δf (b) being the qi at vg = 0 ( the integration constant) in terms of techno-
normalized value of ∆f (b) . To find out the total inver- logical parameters, which can be easily done by using (7)
sion charge Qtran when the transition between only one and the value of E in WI.
150
Proceedings of ESSDERC, Grenoble, France, 2005
4
10 250 4000
This work
Numerical simulation This work
3500 Numerical simulation
2
10
200
Normalized current ( log scale)

Normalized current ( lin scale)

3000
0
10

Normalized current
150 2500

−2
10 2000
100 t =10,15,25,30 nm
si
−4
10 1500 tox=2 nm
t =20 nm Vg= 2 V
si
t =2 nm 1000
ox 50 Vs= 0 V
−6 V = 50 mV
10 d ∆ =−∆ =0.5 V
Vs=0 V b f
∆b=−∆f= 0.5, 0.25, 0 V 500
−8
10 0
0 0.5 1 1.5 2 0
Gate voltage ( V) 0 0.5 1 1.5 2
Drain Voltage (V)

Figure 2: Plot of ID vs VG in linear region of operation.

∆f and ∆b are the work-function difference in front and Figure 4: Plot of ID vs VD for VG = 2 V, ∆b = −∆f =
back gate respectively. The current is higher for higher 0.5 V and tsi = 10, 15, 25, 30 nm. The current is higher
asymmetry (∆b − ∆f ). for thicker silicon film.

1.4
4000
This work This work
Numerical simulation Numerical simulation
3500 1.2

3000 1
Normalized current

2500
0.8
gm/ID

2000
0.6
tsi=20 nm t =20 nm
1500 si
tox=2 nm
tox=2 nm
0.4 ∆b=−∆f= 0.5, 0.25, 0 V
1000 Vgs= 2 V
∆b=∆f= 0.5, 0.25, 0 V
0.2
500

0 0 −5 0 5
0 0.5 1 1.5 2 10 10 10
Drain Voltage (V) Normalized current

Figure 3: Plot of ID vs VD for VG = 2 V and ∆b = Figure 5: Plot of gm UT /ID vs ID /Ispec in saturation for
−∆f = 0.5, 0.25 and 0 V . As in Fig. 2, the current is ∆b = −∆f = 0.5, 0.25 and 0 V . The ratio is higher for
higher for higher asymmetry (∆b − ∆f ). lower asymmetry (∆b − ∆f ).

3. Results and Discussions ID is plotted versus VD in Fig. 3 for different values of

the effective gate voltage asymmetry. In saturation, con-
In order to validate the semi-empirical expression we com- trary to the linear region, the current starts to depend on
pare the analytic expression with exact numerical integra- the work-function asymmetry even at high gate voltages.
tion [5, 6]. This is because the presence of a channel potential makes
Fig. 2 shows the plots of ID vs VG (in lin and log scales) some portion of the channel moderately or weakly in-
for different values of the work-function asymmetry. The verted. These plots also exhibit a very good concordance.
plots show that by increasing the asymmetry, it is possible The effect of the silicon film thickness is illustrated for a
to have more current in weak and moderate inversion. This given value of effective gate voltage asymmetry in Fig. 4.
is an expected behavior because higher asymmetry implies The plots show ID versus VD in saturation for different
higher value of charge at low inversion level, hence higher silicon film thicknesses and for a given value of the work-
current. But at higher gate voltages the effect of asym- function asymmetry. These plots show that the current in-
metry decreases. This can be explained by noticing that at creases with tsi . A higher value of tsi reduces the thresh-
higher gate voltage charge have a linear variation with gate old of the system by giving a higher value of inversion
voltage as indicated by (17). The plots show very good charge in weak inversion. These plots confirm the scala-
agrement in both lin and log scale. The excellent match bility of our model.
in log scale shows that the transition between strong and Fig. 5 shows the plots of gm /ID versus ID in saturation
week inversion is very well captured by the single ana- for different values of the work-function asymmetry. As
lytical expression. However, a very small discrepancy is discussed in [4], this special quantity is of great inter-
observed around VG = ∆b − ∆f in linear scale. This est for analog IC design. Accuracy between numerical
is because of the interpolative nature of the model in this simulations and our analytical approach confirms that the
region. model is also accurate for small-signal analysis. In addi-
151
Proceedings of ESSDERC, Grenoble, France, 2005
4
10 120 Now, we will use the above equations to obtain a charge
This work
Numerical simulation -based model. At the front (back) interface we have

ε dψ 
Normalized Inversion charge ( log scale)

εox ∗

Normalized Inversion charge (lin scale)

2
10 100

v − ψf (b) =
si  . (23)
0
10 80 tox gf (b) tsi dξ  f (b)
∗
−2
10 60
We now define a dimensionless quantity qf (b) = vgf (b) −
ψf (b) . From (23) we have
−4
 2  2   2
dψ 
10 40
2 εsi tox
qf (b) = . (24)
dξ f (b)
tsi=20 nm
−6
10 t =2 nm
ox 20
εox tsi
∆b=−∆f= 0.5, 0.25, 0 V

From (22) we can write

−8
10
0 0.5 1 1.5 2
0  
Gate voltage ( V)
qf2 (b)
ψf (b) = ln +C . (25)
2( εεox
si 2 tox 2
) ( LD )
Figure 6: Plot of normalized inversion charge vs VG in sat-
In non-equilibrium (20) changes to
uration for ∆b = −∆f = 0.5, 0.25 and 0 V . The charge
 2
is higher for higher asymmetry (∆b − ∆f ). d2 ψ tsi
= eψ−vch . (26)
dξ 2 LD
tion, these results show that the highest gm /ID is obtained Now if we ignore SCE ( dvdξch = 0) and replace ψ − vch =
for symmetric operation. nothing changes but all ψ becomes ψ. Using the defi-
ψ,
Finally, in order to obtain the terminal charge one needs
to solve a coupled nonlinear equation at drain and source nition qf (b) = vgf (b) − ψf (b) = vgf (b) − ψ f (b) − vch , we
∗ ∗

end. Fig. 6 shows the plots for normalized inversion obtain (1) from (25).
charge versus VG for both coupled (exact) [5] and de-
coupled (approximate, discussed at the end of previous 6. Acknowledgments
section) solutions.
The work presented in this paper was supported by the
Swiss National Science Foundation under grant number
4. Conclusion 200021-107971/1.
In this work we have presented, for the first time, an ana-
lytical closed form charge-based expression for the drain References:
current of asymmetric DG MOST. Both charge and cur-
rent are obtained through a coherent picture using only [1] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini,
the physical parameters of the device and show a good and T. Elewa. Double-gate silicon-on-insulator tran-
match with exact numerical solution over a wide range of sistor with volume inversion: A new device with
bias and geometry. In addition, due to its special approach greatly enhanced performance. IEEE Electron Device
dv Lett., 8:410–412, 1987.
based on a novel interpolation technique in the dqgi do-
[2] K. Kim and J. G. Fossum. Double-gate CMOS:
main, this model can also be extended to small-signal dc
Symmetrical- versus asymmetrical-gate devices.
parameters analysis, which is mandatory for efficient cir-
IEEE Trans. Electron Devices, 48(2):294299, Feb
cuit design.
2001.
[3] J-M. Sallese, François Krummenacher, Fabien
5. Appendix Prégaldiny, Christophe Lallement, A. Roy, and
C. Enz. A design oriented charge-based current
In case of a undoped channel the Poison equation in equi-
model for symmetric DG MOSFET and its correla-
librium can be written as (in normalized form)
tion with the EKV formalism. Solid-State Electronics,
 2 49(3):485–489, March 2005.
d2 ψ tsi
= eψ . (20) [4] M. Sylveira, D. Flandre, and P.G. A. Gespers. A
dξ 2 LD
gm/ID based methodology for the design of CMOS
We can integrate the equation leading to analog circuits and its application to the synthesis of a
 2  2  2 silicon-on-insulator micropower OTA. IEEE Journal
1 dψ 1 dψr tsi  ψ  of Solid-State Circuits, 31(9):1314–1319, Sep. 1996.
− = e − eψr , (21)
2 dξ 2 dξ LD [5] Y. Taur. Analytic solutions of charge and capacitance
in symmetric and asymmetric double-gate MOSFET.
where ψr is the potential at any reference point. From this
L2
IEEE Trans. Electron Devices, 48(12):2861 – 2869,
we notice that eψ − 21 t2D dψ
dξ is invariant over the vertical Dec. 2001.
si
position. We will take it to be the constant of the integra- [6] Y. Taur, Xiaoping Liang, Wei Wang, and Huaxin Lu.
tion C. Eq. (21) becomes A continuous, analytic drain-current model for DG
 2  2 MOSFETs. IEEE Electron Dev. Let., 25(2):399–401,
dψ tsi   Feb. 2004.
=2 · eψ − C . (22)
dξ LD
152