POWER SYSTEM ANALYSIS (UEE509)

By
Course Coordinator- Dr. Manbir Kaur
Associate Professor, Electrical and
Instrumentation Engineering Department

Course Instructor- Dr. Amit Kumar

Assistant Professor, Electrical and
Instrumentation Engineering Department
 Lecture-2
Bus Admittance Matrix assembly
with Direct Method
 Objectives
• To learn assembly of bus admittance matrix

3
 Formulation of Bus Admittance
matrix
• Direct method
• Singular Transformation Technique
• Inverse of bus impedance matrix

4
 Direct Method
For ‘𝑛’ node network , apply Kirchhoff's current law at 𝑖𝑡ℎ
node such that
𝐼𝑖 = 𝑉𝑖 − 𝑉𝑔 𝑦𝑖𝑔 + 𝑉𝑖 − 𝑉1 𝑦𝑖1 +
𝑉𝑖 − 𝑉2 𝑦𝑖2 +…+ 𝑉𝑖 − 𝑉𝑗 𝑦𝑖𝑗 + ⋯ + 𝑉𝑖 − 𝑉𝑖−1 𝑦𝑖,𝑖−1 + ⋯ +
𝑉𝑖 − 𝑉𝑖+1 𝑦𝑖,𝑖+1 +
…+ 𝑉𝑖 − 𝑉𝑖𝑛 𝑦𝑖𝑛
Rearranging in terms of coefficients of voltage as:
𝐼𝑖 = −𝑦𝑖𝑔 𝑉𝑔 − 𝑦𝑖1 𝑉1 − 𝑦𝑖2 𝑉2 −𝑦𝑖3 𝑉3 − ⋯ − 𝑦𝑖,𝑖−1 𝑉𝑖−1 +
𝑦𝑖𝑔 + 𝑦𝑖1 + 𝑦𝑖2 + ⋯ + 𝑦𝑖𝑗 + 𝑦𝑖,𝑖−1 + 𝑦𝑖,𝑖+1 + ⋯ + 𝑦𝑖𝑛 𝑉𝑖 −
𝑦𝑖,𝑖+1 𝑉𝑖+1 − ⋯ − 𝑦𝑖𝑗 𝑉𝑗 − ⋯ − 𝑦𝑖𝑛 𝑉𝑛
(Assume node 𝑔 as ground node held at zero potential such
that 𝑉𝑔 = 0)

5
Direct Method cont…
• For 𝑖 ≠ 𝑗 (off-diagonal element)
𝑌𝑖𝑗 = −𝑦𝑖𝑗 ; 𝑖 = 1,2 … 𝑛, j = 1,2 … 𝑛
= Negative of the admittance of element connected between node
𝑖 𝑎𝑛𝑑 𝑗
𝐼
𝑌𝑖𝑗 𝑖 ≠ 𝑗 = 𝑖 ; ∀𝑉𝑖 = 0 𝑒𝑥𝑐𝑒𝑝𝑡 𝑉𝑗 . It is called short circuit transfer
𝑉𝑗
admittance.
• For 𝑖 = 𝑗 (diagonal element)
𝐼𝑖
𝑌𝑖𝑖 𝑖 = 𝑗 = ; ; ∀𝑉 = 0, 𝑒𝑥𝑐𝑒𝑝𝑡 𝑉𝑖 .
𝑉𝑖
𝑛

= 𝑦𝑖0 + ෍ 𝑦𝑖𝑗 ; 𝑖 = 1,2 … 𝑛

𝑗=1
= Sum of admittances of all elements connected at node 𝑖.
𝑦𝑖0 is representing shunt admittance (Admittance of element
connected between 𝑖 𝑡ℎ 𝑛𝑜𝑑𝑒 with respect to ground.
It is called short circuit self admittance.

6
 Properties of 𝑌𝐵𝑈𝑆
• It is a square matrix of dimensions (𝑛 × 𝑛)
• It is a symmetric matrix . (𝑌𝑖𝑗 = 𝑌𝑗𝑖 )
• 𝑌𝑖𝑗 𝑖 ≠ 𝑗 = 0 ,
if 𝑖 𝑡ℎ bus is not connecetd to 𝑗𝑡ℎ bus.
• It is a sparse matrix (connectivity of network is
about 20-25%)
• It may be a singular matrix (determinant is
zero)
7
IEEE 5 Bus System

8
𝐼3𝐿 = − 𝐼4𝐿 = −

𝐼5𝐿 = −

9
Assume 𝐼1 , 𝐼2 , 𝐼3 , 𝐼4 and 𝐼5 are currents injected at respective buses
and are taken as positive.
Applying KCL at respective buses
𝐼1 = 𝐼12 + 𝐼13
𝐼2 = −𝐼12 + 𝐼23 + 𝐼24 + 𝐼25
𝐼3𝐿 = 𝐼13 − 𝐼34 + 𝐼23 𝑎𝑛𝑑 𝐼3𝐿 = −𝐼3
𝐼4𝐿 = 𝐼34 + 𝐼24 − 𝐼45 𝑎𝑛𝑑 𝐼4𝐿 = −𝐼4
𝐼5𝐿 = 𝐼25 + 𝐼45 𝑎𝑛𝑑 𝐼5𝐿 = −𝐼5
Rewriting in voltage/admittance form
𝐼1 = 𝑦12 (𝑉1 − 𝑉2 ) + 𝑦13 (𝑉1 − 𝑉3 )
𝐼1 = (𝑦12 +𝑦13 )𝑉1 − 𝑦12 𝑉2 − 𝑦13 𝑉3
Similarly
𝐼2 = −𝐼12 + 𝐼23 + 𝐼24 + 𝐼25
𝐼2 = −𝑦12 𝑉1 − 𝑉2 + 𝑦23 𝑉2 − 𝑉3 + 𝑦24 𝑉2 − 𝑉4 + 𝑦25 (𝑉2 − 𝑉5 )
𝐼2 = −𝑦12 𝑉1 + (𝑦12 + 𝑦23 + 𝑦24 + 𝑦25 ) 𝑉2 − 𝑦23 𝑉3 − 𝑦24 𝑉4 − 𝑦25 𝑉5

10
 Bus admittance matrix example cont…
Similarly
−𝐼3 = 𝐼13 − 𝐼34 + 𝐼23
𝐼3 = −𝑦13 𝑉1 − 𝑉3 + 𝑦34 𝑉3 − 𝑉4 − 𝑦23 (𝑉2 − 𝑉3 )
𝐼3 = −𝑦13 𝑉1 − 𝑦23 𝑉2 + 𝑦13 + 𝑦23 + 𝑦34 𝑉3 − 𝑦34 𝑉4
Similarly −𝐼4 = 𝐼34 + 𝐼24 − 𝐼45
𝐼4 = −𝑦34 𝑉3 − 𝑉4 − 𝑦24 𝑉2 − 𝑉4 + 𝑦45 𝑉4 − 𝑉5
𝐼4 = −𝑦24 𝑉2 − 𝑦34 𝑉3 + 𝑦24 + 𝑦34 + 𝑦45 𝑉4 − 𝑦45 𝑉5
Similarly −𝐼5 = 𝐼25 + 𝐼45
𝐼5 = −𝑦25 𝑉2 − 𝑉5 − 𝑦45 𝑉4 − 𝑉5
𝐼5 = −𝑦25 𝑉2 − 𝑦45 𝑉4 + (𝑦25 +𝑦45 )𝑉5

11
 Ybus cont…

Writing in matrix form

𝐼1 𝑦12 + 𝑦13 −𝑦12 −𝑦13 0 0 𝑉1
𝐼2 −𝑦12 𝑦12 +𝑦23 +𝑦24 +𝑦25 −𝑦23 −𝑦24 −𝑦25 𝑉2
𝐼3 = −𝑦13 −𝑦23 𝑦13 + 𝑦23 + 𝑦34 −𝑦34 0 𝑉3
𝐼4 0 −𝑦24 −𝑦34 𝑦24 + 𝑦34 + 𝑦45 −𝑦45 𝑉4
𝐼5 0 −𝑦25 0 −𝑦45 𝑦25 + 𝑦45 𝑉5

Therefore

BUS ADMITTANCE MATRIX WILL BE 𝒀𝑩𝑼𝑺 =

𝒚𝟏𝟐 + 𝒚𝟏𝟑 −𝒚𝟏𝟐 −𝒚𝟏𝟑 𝟎 𝟎

−𝒚𝟏𝟐 𝒚𝟏𝟐 +𝒚𝟐𝟑 +𝒚𝟐𝟒 +𝒚𝟐𝟓 −𝒚𝟐𝟑 −𝒚𝟐𝟒 −𝒚𝟐𝟓
−𝒚𝟏𝟑 −𝒚𝟐𝟑 𝒚𝟏𝟑 + 𝒚𝟐𝟑 + 𝒚𝟑𝟒 −𝒚𝟑𝟒 𝟎
𝟎 −𝒚𝟐𝟒 −𝒚𝟑𝟒 𝒚𝟐𝟒 + 𝒚𝟑𝟒 + 𝒚𝟒𝟓 −𝒚𝟒𝟓
𝟎 −𝒚𝟐𝟓 𝟎 −𝒚𝟒𝟓 𝒚𝟐𝟓 + 𝒚𝟒𝟓

12
 IEEE 5 Bus Line Data
p–q Line impedance Zpq Line charging 𝒚𝒑𝒒 /2
R per unit X per unit
1 - 2 (A) 0.02 0.06 X per unit
1 –3 (B) 0.08 0.24 0.0 + j0.025
2 - 3 (C) 0.06 0.25 0.0 + j0.020
2 - 4 (D) 0.06 0.18 0.0 + j0.020
2 - 5 (E) 0.04 0.12 0.0 + j0.015
3 - 4 (F) 0.01 0.03 0.0 + j0.010
4 - 5 (G) 0.08 0.24 0.0 + j0.025

(All values are in per unit with Base MVA =100, Base
Voltage =11kV) 13
 Example : Assemble Bus admittance
matrix of five bus system
Element From To Bus Series Impedance Shunt Mutual
Bus Admittance Reactance
R X Y(sh)/2
(Per unit) (per unit) (Per unit)
A 1 Ref 0.04 0.12 -- --
B 1 2 0.02 0.06 -- --
C 2 Ref 0.04 0.12 -- --
D 2 3 0.06 0.25 j0.02 j0.25 with
E 2 4 0.06 0.18 j0,.02 element E

F 2 5 0.04 0.12 j0.015

G 1 3 0.08 0.24 j0.025
H 3 4 0.01 0.03 j0.010
K 4 5 0.08 0.24 j0.025

14
𝜋-representation of Transmission Link

15
Example: Assemble Bus admittance matrix for IEEE 5 bus system.
Procedure:
Step 1: Calculate primitive admittance 𝑦𝑖𝑗 of each element
Step 2: Calculate diagonal elements
𝑌𝑖𝑖 = σ5𝑗=1 𝑦𝑖𝑗 ; 𝑖=1,2,3,4,5
𝑌11 = 𝑦10 + 𝑦12 + 𝑦13 + 𝑦𝐺(𝑆ℎ)
𝑌22 = 𝑦20 + 𝑦21 + 𝑦23 + 𝑦24 + 𝑦25 + 𝑦𝐷(𝑆ℎ) +𝑦𝐸(𝑆ℎ) +𝑦𝐹(𝑆ℎ)
𝑌33 = 𝑦31 + 𝑦32 + 𝑦34 + 𝑦𝐷(𝑆ℎ) + 𝑦𝐻(𝑆ℎ)
𝑌44 = 𝑦42 + 𝑦43 + 𝑦45 + 𝑦𝐸(𝑆ℎ) +𝑦𝐻(𝑆ℎ) +𝑦𝑘(𝑆ℎ)
𝑌55 = 𝑦52 + 𝑦54 + 𝑦𝐹(𝑆ℎ) + 𝑦𝑘(𝑆ℎ)
Step 3: Calculate off-diagonal elements
𝑌𝑖𝑗 = −𝑦𝑖𝑗 ; 𝑖=1,2,3,4,5; 𝑗=1,2,3,4,5
𝑌12 = −𝑦12 , 𝑌13 = −𝑦13 , 𝑌14 = 0, 𝑌15 = 0, 𝑌23 = −𝑦23 , 𝑌24 = −𝑦24 , 𝑌25 , =
− 𝑦25 , 𝑌34 = −𝑦34 , 𝑌35 = 0, 𝑌45 = −𝑦45
Step 4: Due to symmetry
𝑌21 = 𝑌12 , 𝑌31 = 𝑌13 , 𝑌41 = 𝑌14 , 𝑌51 = 𝑌15 , 𝑌32 = 𝑌23 , 𝑌42 = 𝑌24 , 𝑌52 =
𝑌25 , 𝑌43 = 𝑌34 , 𝑌53 = 𝑌35 , 𝑌54 = 𝑌45
Step 5: All shunt elements 𝑦𝑖𝑗0 𝑎𝑟𝑒 added to the node admittance to which it is
connected. (Only diagonal elements are affected)
16
Formulation of Bus admittance Matrix
• For (diagonal elements)
𝑛

𝑌𝑖𝑖 𝑖 = 𝑗 = 𝑦𝑖0 + ෍ 𝑦𝑖𝑗 ; 𝑖 = 1,2 … 𝑛 ;

𝑗=1
= Sum of admittances of all elements connected at node 𝑖.

• For (off-diagonal element)

𝑌𝑖𝑗 (𝑖 ≠ 𝑗) = −𝑦𝑖𝑗 ; 𝑖 = 1,2 … 𝑛, j = 1,2 … 𝑛
= Negative of the admittance of element connected
between node 𝑖 𝑎𝑛𝑑 𝑗

17
 Algorithm for 𝒀𝑩𝑼𝑺
Step 1: Read number of buses (NB) and number of elements (NE)
Step 2: Initialise 𝑌𝑖𝑗0 = 0 𝑖 = 1,2 … 𝑁𝐵; 𝑗 = 1,2 … 𝑁𝐵
Step 3: Set line element counter count NE =1
Step 4: Read the sending and receiving end node 𝑖 and 𝑗 for an element .
Step 5: Read admittance y between buses 𝑖 and 𝑗 .
Step 6: For 𝑖 ≠ 0 𝑎𝑛𝑑 𝑗 =0, implement 𝑌𝑖𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑖𝑜𝑙𝑑 + 𝑦
For 𝑖 = 0 𝑎𝑛𝑑 𝑗 ≠ 0 implement 𝑌𝑗𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑗𝑜𝑙𝑑 + 𝑦
For 𝑖 ≠ 0 𝑎𝑛𝑑 𝑗 ≠ 0, implement
𝑌𝑖𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑖𝑜𝑙𝑑 + 𝑦
𝑌𝑗𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑗𝑜𝑙𝑑 + 𝑦
𝑌𝑖𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑗𝑜𝑙𝑑 − 𝑦
Step 7: Check if count ≥ NE, if yes, then go to step 8 ,
else count=count+1 and go to step 4.
Step 8: Write bus admittance matrix 𝑌𝑖𝑗 and stop.

18
 With shunt admittances
Step 1: Read number of buses (NB) and number of elements (NE)
Step 2: Initialise 𝑌𝑖𝑗0 = 0 𝑖 = 1,2 … 𝑁𝐵; 𝑗 = 1,2 … 𝑁𝐵
Step 3: Set line element counter count NE=1
Step 4: Read the sending and receiving end node 𝑖 and 𝑗 for an
element .
Step 5: Read admittance y between bused 𝑖 and 𝑗 and shunt
admittance 𝑦𝑠ℎ
Step 6: For 𝑖 ≠ 0 𝑎𝑛𝑑 𝑗 =0, implement 𝑌𝑖𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑖𝑜𝑙𝑑 + 𝑦 + 𝑦𝑠ℎ
For 𝑖 = 0 𝑎𝑛𝑑 𝑗 ≠ 0 implement 𝑌𝑗𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑗𝑜𝑙𝑑 + 𝑦 + 𝑦𝑠ℎ
For 𝑖 ≠ 0 𝑎𝑛𝑑 𝑗 ≠ 0, implement
𝑌𝑖𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑖𝑜𝑙𝑑 + 𝑦 + 𝑦𝑠ℎ
𝑌𝑗𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑗𝑜𝑙𝑑 + 𝑦 + 𝑦𝑠ℎ
𝑌𝑖𝑗𝑛𝑒𝑤 = 𝑌𝑗𝑖𝑛𝑒𝑤 = 𝑌𝑖𝑗𝑜𝑙𝑑 − 𝑦
Step 7: Check if count ≥ NE, if yes, then go to step 8 ,
else count=count+1 and go to step 4.
Step 8: Write bus admittance matrix 𝑌𝑖𝑗 and stop.
19
Thank you