Electronic Circuits Chapter 3: Multistage Amplifier and Differential Amplifier

Dr.
Dung Trinh HCMUT / 2017
Electronic Circuits
Chapter 3: Multistage Amplifier and
Differential Amplifier
Dr. Dung Trinh
1
Dr. Dung Trinh HCMUT / 2017
Content
Introduction
Cascade Configuration
Cascode Configuration
Darlington Configuration
2
Introduction
In most applications, a single
transistor amplifier will not be
able to meet the combined
specifications of a given
amplification factor, input
resistance, and output resistance. A generalized three-stage amplifier
BJT
Name Comments
1st stage 2nd stage
Voltage Amp CE CE High Voltage Gain
Cascode CE CB High bandwidth
Op-Amp CE CC High Zin low Zout
Current buffer CB CC Higher Zout than CB/CG
Current buffer CB CE
Not common CB CB
Not common CC CE
Differential Amp CC CB High voltage gain and BW.
Darlington CC CC High current gain
3
A two-stage common-emitter amplifier in a cascade

configuration with npn and pnp transistors
4
❖ Two stage common-emitter amplifier in a cascade configuration:
small signal equivalent circuit.
❖ Input resistance: 𝑹𝒊𝒏 = 𝑹𝟏 ∥ 𝑹𝟐 ∥ 𝒓𝝅𝟏
❖ Small signal voltage gain:

𝑹𝟏 ∥ 𝑹𝟐
𝑨𝒗 = 𝒈𝒎𝟐 𝑹𝟐 ∥ 𝑹𝑳 𝒈𝒎𝟏 𝑹𝑪𝟏 ∥ 𝒓𝝅𝟐
𝑹𝟏 ∥ 𝑹𝟐 + 𝑹𝒔
5
Example 1: Determine the small-signal voltage gain of the following multi-transistor
circuit:
 1 = 173
ICQ1 = 2.54 mA
2 = 157
ICQ2 = 1.18 mA
VC1 = -0.82 V
VECQ1 = 1.10 V
VCEQ2 = 1.79 V
GV = 4790
6
circuit:
7
circuit:
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Example 2: Consider the circuit shown in the following figure. The transistor parameters
are 𝑘𝑛1 = 0.5mA/𝑉 2, 𝑘𝑛2 = 0.2mA/𝑉 2and 𝑉𝑇𝑁1 = 𝑉𝑇𝑁2 = 1.2𝑉. The Q point is: 𝐼𝐷1 =
0.2𝑚𝐴, 𝐼𝐷2 = 0.5𝑚𝐴.
Determine the small-signal voltage gain of a multistage cascade circuit.
Gv = -6.14
9
Exercise 1: Consider the circuit shown in the following figure. The transistor parameters
are  = 125, 𝑉𝐵𝐸 (𝑜𝑛) = 0.7𝑉
a. Determine the small-signal voltage gain of the multistage cascade circuit.
b. Determine the input resistance and output resistance.
Gv = -17.7
Rin = 4.76 k
Ro = 43.7 
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❖ In cascode configuration, a Common-
Emitter (or Common-Source) amplifier
drives a Common-Base (or Common-
Gate) amplifier.
❖ The input capacitance of CE amplifier is

small because the voltage gain of Q1 is
small (near unity) which means the
Miller capacitance is minimized.
❖ The CE stage increases the input

impedance of the CB stage.
Cascode Amplifier
❖ The voltage gain is achieve in the
Common-Base stage.
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The ac equivalent circuit
Cascode Amplifier
The small-signal equivalent circuit

12
Example 2: Consider the circuit shown in the

following figure. The transistor parameters are 𝑘𝑛1 =
0.8mA/𝑉 2 , 𝑘𝑛2 = 0.8mA/𝑉 2 and 𝑉𝑇𝑁1 = 𝑉𝑇𝑁2 =
1.2𝑉. The Q point is: 𝐼𝐷1 = 0.4𝑚𝐴, 𝐼𝐷2 = 0.4𝑚𝐴.
Determine the small-signal voltage gain of the
cascode circuit.
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PSPICE Simulation: Use PSPICE to run simulation for the following CE-CB (cascode) amplifier.
The Beta DC of Q1,Q2 are 162 and 161 respectively. The mid-band gain of the amplifier from
PSPICE is 120. Validate the DC and AC analysis of the amplifier using circuit analysis? Note that
Beta AC gain of Q1, Q2 are 177 and 176 respectively.
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PSPICE Simulation: It is clear that the high-frequency (HF) 3dB cut-off frequency of the
Cascode amplifier is much higher than that of the circuit in Example 1 (CE-CE Amplifier).
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Darlington Pair
❖ In some applications, it would be desirable to have a bipolar
transistor with a much larger current gain than can normally be
obtained.
❖ A Darlington configuration provides increased current gain.
❖ The effective 𝛽 of the Darlington pair is:
𝜷𝑫𝑷 = 𝜷𝟏 𝜷𝟐 + 𝜷𝟏 + 𝜷𝟐
❖ Darlington pairs are often fabricated on a

single chip to achieve matched Q1 and Q2
characteristics. Then:
𝜷𝑫𝑷 = 𝜷𝟐 + 𝟐𝜷
A Darlington pair configuration
16
Darlington Pair
❖ The effective small-signal input resistance
of the Darlington pair is:
𝑟𝑖𝑛(𝐷𝑃) = 𝛽1 𝑟𝑒1 + 𝑟𝑖𝑛 𝑏𝑎𝑠𝑒 2 ≃ 𝛽1 𝑟𝑒1 + 𝛽2 𝑟𝑒2
where:
25𝑚𝑉 25𝑚𝑉
𝑟𝑒1 = 𝑟𝑒2 =
𝐼𝐶1 𝐼𝐶2
Small-signal equivalent circuit

❖ Note that: 𝐼𝐸2 ≃ 𝛽2 𝐼𝐸1 . Then: 𝑟𝑒1 ≃ 𝛽2 𝑟𝑒2
❖ And: 𝑟𝑖𝑛(𝐷𝑃) ≃ 𝛽1 𝑟𝑒1 + 𝛽2 𝑟𝑒2 = 2𝑟𝑒2
17
Darlington Pair
PSPICE Simulation: Use PSPICE to run simulation for the following CE-CC amplifier. The Beta
DC gain of Q1,Q2 and Q3 are 168, 187 and 108 respectively. The mid-band gain of the
amplifier from PSPICE is 26. Validate the DC and AC analysis of the amplifier using circuit
analysis? Note that Beta AC gain of Q1, Q2 and Q3 are 184, 197 and 126 respectively.
18
❖ The input stage of every op amp is a differential amplifier.
❖ Less sensitive to noise and interference.
❖ Enable to bias amplifier and connect to other stage without the use of
coupling capacitors.
19
Differential Amplifier – DC Analysis

❖ Assume Q1 and Q2 are matched.
𝐼𝑄
𝐼𝐸1 = 𝐼𝐸2 =
2
𝐼𝑄+
𝑣𝐶1 = 𝑣𝐶2 = 𝑉 − 𝑅𝐶
2
20
Diffrential Amp – Small Signal Operation

❖ If 𝑣𝑖𝑑 ≠ 0:
𝐼𝐶𝑄
𝑣𝐶1 = 𝑉+ − + Δ𝐼 𝑅𝐶
2
𝐼𝐶𝑄
𝑣𝐶2 = 𝑉 + − − Δ𝐼 𝑅𝐶
2
𝑣𝐶1 − 𝑣𝐶2 = 2Δ𝐼𝑅𝐶
21

❖ If 𝑣𝑖𝑑 ≠ 0:
❖ Since the two transistors are biased at the

same quiescent current:
𝒓𝝅𝟏 = 𝒓𝝅𝟐 = 𝒓𝝅 𝒈𝒎𝟏 = 𝒈𝒎𝟐 = 𝒈𝒎
❖ At node Ve:
𝑽𝝅𝟏 𝑽𝝅𝟐 𝑽𝒆
+ 𝒈𝒎 𝑽𝝅𝟏 + 𝒈𝒎 𝑽𝝅𝟐 + =
𝒓𝝅 𝒓𝝅 𝑹𝒐
𝟏+𝜷 𝟏+𝜷 𝑽𝒆
or: 𝑽𝝅𝟏 + 𝑽𝝅𝟐 =
𝒓𝝅 𝒓𝝅 𝑹𝒐
❖ From the circuit we see that:
𝑽𝝅𝟏 𝑽𝒃𝟏 − 𝑽𝒆 𝑽𝝅𝟐 𝑽𝒃𝟐 − 𝑽𝒆
= and =
𝒓𝝅 𝑹 𝑩 + 𝒓𝝅 𝒓𝝅 𝑹𝑩 + 𝒓𝝅
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❖ If 𝑣𝑖𝑑 ≠ 0:
❖ Finally we have:
𝟏+𝜷 𝑽𝒆
𝑽𝒃𝟏 + 𝑽𝒃𝟐 − 𝟐𝑽𝒆 =
𝒓𝝅 + 𝑹 𝑩 𝑹𝒐
𝑽𝒃𝟏 + 𝑽𝒃𝟐
or: 𝑽𝒆 =
𝒓 + 𝑹𝑩
𝟐+ 𝝅
𝟏 + 𝜷 𝑹𝒐
𝑣𝑑 𝑣𝑑
❖ One-sided output: 𝑣𝑏1 = 𝑣𝑐𝑚 + 𝑣𝑏2 = 𝑣𝑐𝑚 − 𝑉𝑜 = 𝑉𝑐1 − 𝑉𝑐2
2 2
𝜷𝑹𝑪 −𝜷𝑹𝑪
𝑨𝒅 = 𝑨𝒄𝒎 =
𝟐 𝒓 𝝅 + 𝑹𝑩 𝒓𝝅 + 𝑹𝑩 + 𝟐 𝟏 + 𝜷 𝑹𝒐
𝜷𝑹𝑪
❖ Two-sided output: 𝑨𝒅 = 𝑨𝒄𝒎 = 𝟎
𝒓𝝅 + 𝑹𝑩
23

❖ Two-sided output: Effect of RC mismatch
𝑉𝑜 = 𝑉𝑐1 − 𝑉𝑐2
= −𝑔𝑚 𝑉𝜋2 𝑅𝐶2 + 𝑔𝑚 𝑉𝜋1 𝑅𝐶1
𝑨𝒅 = 𝒈𝒎 𝑹𝑪
𝟏 𝚫𝑹𝑪
𝑨𝒄𝒎 = 𝒈𝒎 𝟐𝚫𝑹𝑪 ≈
𝟐 𝟏 + 𝜷 𝑹𝒐 𝑹𝒐
𝟏+ 𝒓𝝅
❖ The Common Mode Rejection Ratio (CMRR) is:
𝑨𝒅 𝒈𝒎 𝑹𝒐
𝑪𝑴𝑹𝑹 = =
𝑨𝒄𝒎 𝚫𝑹𝑪 Τ𝑹𝑪
24
Operational Amplifiers
❖ Practical transistor amplifiers consist of a number of stages connected in cascade.
❖ In addition to providing gain, the first (or input) stage is usually required to:
▪ Provide a high input resistance.
▪ In a differential amplifier the input stage must also provide large CMRR.
▪ The middle stages of an amplifier cascade is to provide the bulk of the voltage gain.
▪ The middle stages convert the signal from differential mode to single-ended mode.
▪ The middle stages also shift the DC level of the signal in order to allow the output
signal to swing both positive and negative .
▪ The last (or output) stage of an amplifier is to provide a low output resistance.
❖ In order to illustrate the circuit structure an method of analysis, two examples: a CMOS
Op-Amp and a bipolar Op-Amp will be investigated.
25
A Bipolar OpAmp
Current Source
Conversion from
differential to single-
ended
Shifting DC level
Emitter Follower (CC)

Amplifier: Voltage
Buffer
26
A Bipolar OpAmp – DC Analysis

Example 2:
a. Perform DC Analysis of
the bipolar Op-Amp.
b. Determine the small-
signal voltage gain, input
resistance and output
resistance of the circuit.
Rid = 20.2k
Ro = 152
GV = 8513
27
Q&A
28

Electronic Circuits Chapter 3: Multistage Amplifier and Differential Amplifier

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Dr.

Dung Trinh HCMUT / 2017

Dr. Dung Trinh

A two-stage common-emitter amplifier in a cascade

❖ Input resistance: 𝑹𝒊𝒏 = 𝑹𝟏 ∥ 𝑹𝟐 ∥ 𝒓𝝅𝟏

❖ Small signal voltage gain:

❖ The input capacitance of CE amplifier is

❖ The CE stage increases the input

The ac equivalent circuit

The small-signal equivalent circuit

Example 2: Consider the circuit shown in the

❖ The effective 𝛽 of the Darlington pair is:

❖ Darlington pairs are often fabricated on a

Small-signal equivalent circuit

❖ And: 𝑟𝑖𝑛(𝐷𝑃) ≃ 𝛽1 𝑟𝑒1 + 𝛽2 𝑟𝑒2 = 2𝑟𝑒2

Differential Amplifier – DC Analysis

Diffrential Amp – Small Signal Operation

𝑣𝐶1 − 𝑣𝐶2 = 2Δ𝐼𝑅𝐶

Diffrential Amp – Small Signal Operation

❖ Since the two transistors are biased at the

𝒓𝝅𝟏 = 𝒓𝝅𝟐 = 𝒓𝝅 𝒈𝒎𝟏 = 𝒈𝒎𝟐 = 𝒈𝒎

Diffrential Amp – Small Signal Operation

Diffrential Amp – Small Signal Operation

= −𝑔𝑚 𝑉𝜋2 𝑅𝐶2 + 𝑔𝑚 𝑉𝜋1 𝑅𝐶1

Emitter Follower (CC)

A Bipolar OpAmp – DC Analysis

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