Compal La-B301p Zswaa r10 - Pre-Mp - 20140210a

A B C D E
1 1
Compal Confidential
ZSWAA/ZCWAA Schematics Document
Intel Haswell ULT/Broadwell U with DDR3L
2 2
AMD GPU Jet Pro/Topaz XT S3 (Single Rank)
LA-B301P REV 1.0 Schematic

3 3
Intel Processor (Haswell ULT/Broadwell U)

2014-02-10 Rev 1.0
4 4
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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ZSWAA/ZCWAA LA-B301P
Date: Monday, February 10, 2014 Sheet 1 of 52
A B C D E
A B C D E
External Graphics
AMD GPU Jet Pro S3/Topaz XT S3
PCI-Express 4X Gen3 8GT/s Intel Haswell ULT/Broadwell U Memory BUS(DDR3L) 204pin DDR3-SO-DIMM X2
Single Rank
Dual Channel BANK 0, 1, 2 page 16,17
VRAM (gDDR3) 900MHz @ 1.35V eDP 1X 5.4GT/s
1 1
page 18~25 1.35V DDR3L 1333/1600 MT/s
Haswell ULT/
LVDS Conn. LVDS Translator
Broadwell U
Colay eDP RTD2132N-CGT Processor USB30 2x
page 27 5V 5GT/s USB3.0 x2 Right
page 26 USB20 port 0,1
USB20 2x USB30 port 1,2
page 34
5V 480MHz
OPI
HDMI Conn. Touch Screen

USB20 1x
page 28 5V 480MHz USB20 port 5
page 27
Lynx Point - LP/

2
USB20 1x Int. Camera 2
Wildcat Point - LP 5V 480MHz USB20 port 7

page 27
NGFF Slot 1 PCIe Gen1 1x PCH SATA HDD/SSD

SATA Gen3 port 0
WLAN PCIe port 4 1.5V 5GT/s
5V 6GHz(600MB/s)
SATA port 0
page 31
USB20 port 4
USB20 1x
page 32 5V 480MHz
SATA Gen3 port 1 SATA ODD
SATA port 1
5V 6GHz(600MB/s) page 31
1168pin BGA DP 2X 5.4GT/s DP to CRT Translator

page 05~15 ITE IT6513FN CRT Conn.
page 30
3
page 29 3
LPC BUS HD Audio

3.3V 33 MHz 3.3V 24MHz
Sub Boards
LS-B301P
LED/B RTC CKT. SPI ROM KB9012QF A4 HDA Codec
page 37 page 7 (8MB) page 36
page 8 ALC233-VB1-CG
(w/o S&M) page 35
LS-B302P DC/DC Interface CKT.
Power Button/B
page 37
page 38
Int.KBD TPM
page 37 page 33
Power Circuit DC/DC SPK Conn
page 35
LS-B303P
LAN+USB/B page 39~48
4
Audio Combo Jack 4
page 33
Power On/Off CKT.
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page 37
LS-B304P
CardReader/TP/LID B Security Classification Compal Secret Data Compal Electronics, Inc.
page 37 Issued Date 2013/09/25 Deciphered Date 2016/09/25 Title
Block Diagram
1.0
A B C D E
A B C D E
EC_ON
PU350
B+ DESIGN CURRENT 10.81A
Ipeak=8A, Imax=5.6A, Iocp=9A +5VALW
SY8208CQNC
SUSP#
U3
DESIGN CURRENT 4.98A +5VS
TPS22966DPUR
+5VS
U7
DESIGN CURRENT 1.1A +5VS_ODD
AP2151DWG-7
1 1
ODD_EN
U16
DESIGN CURRENT 1A +HDMI_5V_OUT
TPS22967DSGR
USB_EN#0
UR1
DESIGN CURRENT 2A +USB_VCCB
SY6288D20AAC
USB_EN#2
UR3
DESIGN CURRENT 2A +USB_VCCC
SY6288D20AAC
EC_ON
PU300 DESIGN CURRENT 0.025A +3VL
SY8206BQNC Ipeak=5A, Imax=3.5A, Iocp=6A DESIGN CURRENT 2.73A +3VALW
SUSP#
U3
DESIGN CURRENT 6A +3VS
TPS22966DPUR
LCD_ENVDD
2
U1 2
DESIGN CURRENT 2A +LCD_VDD

SY6288C20AAC
PXS_PWREN
QV3
DESIGN CURRENT 1.555A +3VGS
AO3413
PCH_PWR_EN#
Q10
DESIGN CURRENT 253mA +3VALW_PCH
AO3413
WOWL_EN
U8
DESIGN CURRENT 0.37A +3V_WLAN
TPS22967DSGR
SUSP#
PUM00
Ipeak=0.5A, Imax=0.35A, Iocp=5.7A DESIGN CURRENT 0.468A +1.5VS
APL5930KAI-TRG
3
PXS_PWREN 3
PU1800
Ipeak=1A, Imax=0.7A, Iocp=2.5A DESIGN CURRENT 0.35A +1.8VGS
SY8032ABC
PXS_PWREN
PUF00
Ipeak=3A, Imax=2.1A, Iocp=4A DESIGN CURRENT 1.93A +0.95VGS
SY8033BDBC
SYSON: Enable 1.35V

DDR_VTT_PG_CTRL: Enable 0.675VS
PUW00 DESIGN CURRENT 10.2A
Ipeak=10A, Imax=7A, Iocp=12A +1.35V
RT8207MZQW PXS_PWREN#
QV5
DESIGN CURRENT 6.5A +1.35VGS
AO4354
DESIGN CURRENT 1.5A +0.675VS

SUSP#
PUH00
Ipeak=5A, Imax=3.5A, Iocp=6A DESIGN CURRENT 5.66A +1.05VS_VTT
SY8206DQNC
4 4
VR_ON
PUZ00
DESIGN CURRENT 32A
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+CPU_CORE
TPS51624RSM
PXS_PWREN
PUV00 Security Classification Compal Secret Data Compal Electronics, Inc.
DESIGN CURRENT 24A +VGA_CORE 2013/09/25 2016/09/25 Title
RT8880BGQW
Issued Date Deciphered Date Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D E
A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails BTO Option Table
+5VS Function SKU Processor GPU VRAM Internal Panel HDMI Wake On Wireless
+RTCVCC B+ +5VL +5VALW +1.35V
+3VS
+3VL +3VALW Description UMA DIS HASWELL BROADWELL JET TOPAZ X76 LVDS eDP HDMI WOWL NON-WOWL
+1.5VS
+1.5VALW
power +CPU_CORE
plane Explain UMA DIS HASWELL BROADWELL JET TOPAZ X76 LVDS eDP HDMI WOWL NON-WOWL
+VGA_CORE
1 1
+3VGS
BTO UMA@ VGA@ HASWELL@ BROADWELL@ JET@ TOPAZ@ X76@ LVDS@ IEDP@ HDMI@ ISCT@ NOISCT@
+1.8VGS
+1.35VGS
+0.95VGS
Function CPU (R1 PN)
+1.05VS_VTT
State
Description I3-4005U I5-4200U I3-4010U 2990U I5-4210U I3-4015U
Explain SA000072Q70 SA00006SM80 SA00006SXA0 SA00007LM00 SA00007LO00 SA00007LN00
BTO 4005UR1@ 4200UR1@ 4010UR1@ 2990UR1@ 4210UR1@ 4015UR1@
S0
O O O O O O
Function CPU (R3 PN)
S1
O O O O O O
Description I3-4005U I5-4200U I3-4010U
S3
O O O O O X
2 Explain SA000072Q60 SA00006SM90 SA00006SX90 2
S5 S4/AC
O O O O X X
BTO 4005UR3@ 4200UR3@ 4010UR3@
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery Function ODD XDP FIX Short pad ESD
don't exist X X X X X X
Description ZPODD Non-ZPODD XDP FIX Short pad ESD
Explain Zero Power ODD Non-Zero Power ODD XDP FIX 0 ohm short pad ESD
PCH SM Bus Address
BTO ZPODD@ NONZP@ XDP@ FIX@ Rshort@ ESD@ @ESD@
Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b Function EMI CAM_EMI CRT_EMI TPM_EMI TOUCH_EMI
Description EMI CAM_EMI CRT_EMI TPM_EMI TOUCH_EMI

3 3
Explain EMI CAM_EMI CRT_EMI TPM_EMI TOUCH_EMI
BTO EMI@ @EMI@ CAM_EMI@ @CAM_EMI@ CRT_EMI@ @CRT_EMI@ TPM_EMI@ @TPM_EMI@ TOUCH_EMI@ @TOUCH_EMI@
EC SM Bus1 Address EC SM Bus2 Address
Power Device HEX Address Power Device HEX Address

SIGNAL
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b STATE SLP_S3# SLP_S4# SLP_S5#
+3VL Smart Charger 12 H 0001 0010 b +3VGS AMD GPU 9E H 1001 1010 b
Full ON HIGH HIGH HIGH
S1(Power On Suspend) HIGH HIGH HIGH

Power Device HEX Address
S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH

4 Platform SKU CPU PCH VGA 4
S5 (Soft OFF) LOW LOW LOW
AMD GPU G3 LOW LOW LOW
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Intel UMA Haswell-M Lynx Point - LP Jet Pro S3
SharkBay ULT DIS ULT Processor Topaz XT S3 Security Classification Compal Secret Data Compal Electronics, Inc.
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date Notes List
Custom 1.0
A B C D E
5 4 3 2 1
HASWELL_MCP_E
UC1A @
CRT@ C76 1 2 0.1U_0402_16V7K H_DP1_N0 C54 C45

<29> H_DP1_C_N0 DDI1_TXN0 EDP_TXN0 H_EDP_TXN0 <26>
CRT@ C80 1 2 0.1U_0402_16V7K H_DP1_P0 C55 B46
<29> H_DP1_C_P0 DDI1_TXP0 EDP_TXP0 H_EDP_TXP0 <26>
CRT@ C77 1 2 0.1U_0402_16V7K H_DP1_N1 B58 A47
DP to CRT <29>
<29>
H_DP1_C_N1
H_DP1_C_P1
CRT@ C74 1 2 0.1U_0402_16V7K H_DP1_P1 C58 DDI1_TXN1
DDI1_TXP1
EDP_TXN1
EDP_TXP1
B47
H_EDP_TXN1
H_EDP_TXP1
<26>
<26>
B55
A55 DDI1_TXN2 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
<28> H_HDMI_TX2- DDI2_TXN0
C50 A45 H_EDP_AUXN <26>
<28> H_HDMI_TX2+ DDI2_TXP0 EDP_AUXN
C53 B45 H_EDP_AUXP <26>
<28> H_HDMI_TX1- DDI2_TXN1 EDP_AUXP
B54
HDMI <28>
<28>
H_HDMI_TX1+
H_HDMI_TX0-
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43
<28> H_HDMI_TX0+ DDI2_TXP2 EDP_DISP_UTIL
A53 Trace width=20 mils,Spacing=25mil,Max length=100mils
<28> H_HDMI_TXC- DDI2_TXN3
B53
<28> H_HDMI_TXC+ DDI2_TXP3
1 OF 19 Rev1p2
HASWELL_MCP_E
UC1B @
T20 @ D61
T97 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY# @ T154
<36> H_PECI PECI PRDY K62 XDP_PREQ#
2 1 R68 R10 JTAG
PREQ E60 XDP_TCK
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#
<36> H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI
C @ESD@ PROC_TDI F62 XDP_TDO C
1 2 H_CPUPW RGD PROC_TDO
CH6 180P_0402_50V8J R25 1 2 10K_0402_5% H_CPUPW RGD C61
PROCPWRGD PWR
+1.35V J60 BPM#0 @ T155
BPM#0 H60 BPM#1 @ T156
BPM#1 H61 BPM#2 @ T148
BPM#2 H62 BPM#3 @ T149
R24 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 BPM#4 @ T150
SM_RCOMP0 BPM#4
1
R23 1 2 121_0402_1% SM_RCOMP1 AV60 DDR3 H63 BPM#5 @ T151

R184 R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 BPM#6 @ T152
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 BPM#7 @ T153
470_0402_5% <16,17> DIMM_DRAMRST# SM_DRAMRST BPM#7
AV61
<16> DDR_PG_CTRL SM_PG_CNTL1
2
DDR3 Compensation Signals

2 OF 19 Rev1p2
DIMM_DRAMRST# PU/PD for JTAG signals
+1.05VS_VTT
B B
XDP_TMS R86 1 @ 2 51_0402_5%
XDP_TDI R87 1 XDP@ 2 51_0402_5%
XDP_PREQ# R88 1 @ 2 51_0402_5%
XDP_TDO R89 1 XDP@ 2 51_0402_5%
XDP_TCK R90 1 XDP@ 2 51_0402_5%
XDP_TRST# R91 1 @ 2 51_0402_5%
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(1/11) DDI,MSIC,XDP
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
UC1C @
HASWELL_MCP_E
UC1D @
DDR_A_D0 AH63 AU37

DDR_A_D1 AH62 SA_DQ0 SA_CLK#0 AV37 SA_CLK_DDR#0 <16>
DDR_A_D2 AK63 SA_DQ1 SA_CLK0 AW36 SA_CLK_DDR0 <16> DDR_B_D0 AY31 AM38
DDR_A_D3 AK62 SA_DQ2 SA_CLK#1 AY36 SA_CLK_DDR#1 <16> DDR_B_D1 AW31 SB_DQ0 SB_CK#0 AN38 SB_CLK_DDR#0 <17>
AH61 SA_DQ3 SA_CLK1 SA_CLK_DDR1 <16> AY29 SB_DQ1 SB_CK0 AK38 SB_CLK_DDR0 <17>
DDR_A_D4 DDR_B_D2
AH60 SA_DQ4 AU43 AW29 SB_DQ2 SB_CK#1 AL38 SB_CLK_DDR#1 <17>
DDR_A_D5 DDR_B_D3
D DDR_A_D6 AK61 SA_DQ5 SA_CKE0 AW43 DDRA_CKE0_DIMMA <16> DDR_B_D4 AV31 SB_DQ3 SB_CK1 SB_CLK_DDR1 <17> D
DDR_A_D7 AK60 SA_DQ6 SA_CKE1 AY42 DDRA_CKE1_DIMMA <16> DDR_B_D5 AU31 SB_DQ4 AY49
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D6 AV29 SB_DQ5 SB_CKE0 AU50 DDRB_CKE0_DIMMB <17>
AM62 SA_DQ8 SA_CKE3 AU29 SB_DQ6 SB_CKE1 AW49 DDRB_CKE1_DIMMB <17>
DDR_A_D9 DDR_B_D7
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
AP62 SA_DQ10 SA_CS#0 AR32 DDRA_CS0_DIMMA# <16> AW27 SB_DQ8 SB_CKE3
DDR_A_D11 DDR_B_D9
DDR_A_D12 AM61 SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# <16> DDR_B_D10 AY25 SB_DQ9 AM32
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D11 AW25 SB_DQ10 SB_CS#0 AK32 DDRB_CS0_DIMMB# <17>
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D12 AV27 SB_DQ11 SB_CS#1 DDRB_CS1_DIMMB# <17>
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D16 AP58 SA_DQ15 SA_RAS AW34 DDR_A_RAS# <16> DDR_B_D14 AV25 SB_DQ13 SB_ODT0
DDR_A_D17 AR58 SA_DQ16 SA_WE AU34 DDR_A_WE# <16> DDR_B_D15 AU25 SB_DQ14 AM35
DDR_A_D18 AM57 SA_DQ17 SA_CAS DDR_A_CAS# <16> DDR_B_D16 AM29 SB_DQ15 SB_RAS AK35 DDR_B_RAS# <17>
AK57 SA_DQ18 AU35 AK29 SB_DQ16 SB_WE AM33 DDR_B_WE# <17>
DDR_A_D19 DDR_B_D17
DDR_A_D20 AL58 SA_DQ19 SA_BA0 AV35 DDR_A_BS0 <16> DDR_B_D18 AL28 SB_DQ17 SB_CAS DDR_B_CAS# <17>
AK58 SA_DQ20 SA_BA1 AY41 DDR_A_BS1 <16> AK28 SB_DQ18 AL35
DDR_A_D21 DDR_B_D19
DDR_A_D22 AR57 SA_DQ21 SA_BA2 DDR_A_BS2 <16> DDR_B_D20 AR29 SB_DQ19 SB_BA0 AM36 DDR_B_BS0 <17>
DDR_A_D23 AN57 SA_DQ22 AU36 DDR_A_MA0 DDR_B_D21 AN29 SB_DQ20 SB_BA1 AU49 DDR_B_BS1 <17>
DDR_A_D24 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D22 AR28 SB_DQ21 SB_BA2 DDR_B_BS2 <17>
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D23 AP28 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39DDR_A_MA7 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41DDR_A_MA11 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
C DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13 C
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D40 AY54 SA_DQ39 AJ61 DDR_A_DQS#0 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D41 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D39 AU21 SB_DQ38 SB_MA15
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D40 AY19 SB_DQ39 AW30 DDR_B_DQS#0
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 <16> DDR_A_D[0..63] AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 DDR_B_D42
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 <16> DDR_A_MA[0..15] DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22DDR_B_DQS#4
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 <16> DDR_A_DQS#[0..7] DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D49 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 <16> DDR_A_DQS[0..7] AR21 SB_DQ47 SB_DQSN7
DDR_A_D50 DDR_B_D48
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_B_DQS0
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57DDR_A_DQS4 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53DDR_A_DQS5 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
AK49 SA_DQ58 SM_VREF_CA AR51 SM_DIMM_VREFCA <16> AR20 SB_DQ56 SB_DQSP7
DDR_A_D59 DDR_B_D57
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 SA_DIMM_VREFDQ <16> DDR_B_D58 AK18 SB_DQ57
AK48 SA_DQ60 SM_VREF_DQ1 SB_DIMM_VREFDQ <17> AL18 SB_DQ58
DDR_A_D61 DDR_B_D59
DDR_A_D62 AM51 SA_DQ61 DDR_B_D60 AK20 SB_DQ59
DDR_A_D63 AK51 SA_DQ62 DDR_B_D61 AM20 SB_DQ60 <17> DDR_B_D[0..63]
SA_DQ63 DDR_B_D62 AR18 SB_DQ61
AP18 SB_DQ62 <17> DDR_B_MA[0..15]
DDR_B_D63
SB_DQ63
<17> DDR_B_DQS#[0..7]
<17> DDR_B_DQS[0..7]
B B
3 OF 19 Rev1p2
4 OF 19 Rev1p2
A A
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2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(2/11) DDRIII
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
UC1E @
2 1 PCH_RTCX1 AW5
CH2 15P_0402_50V8J PCH_RTCX2 AY5 RTCX1
SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_C_DTX_N0 <31>
1
PCH_INTVRMEN AV7 RTC H5
10M_0402_5%
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_C_DTX_P0 <31>
YH1 PCH_SRTCRST# AV6 B15 HDD/SSD
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0 <31>
PCH_RTCRST# AU7 A15
RH2
32.768KHZ_12.5P_1TJF125DP1A000D RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <31>
1
D J8 SATA_PRX_C_DTX_N1 <31> D
2
2 1 SATA_RN1/PERN6_L2 H8
CMOS Setting, near DDR Door SATA_RP1/PERP6_L2 A17
SATA_PRX_C_DTX_P1 <31>
JCMOS @ CH3 15P_0402_50V8J
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 <31> ODD
+RTCVCC RH23 1 2 PCH_RTCRST# 1 2 <36> PCH_RTCRST# B17
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <31>
20K_0402_5%
CH4 1 2 HDA_BIT_CLK AW8 J6
1U_0402_6.3V6K HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
<35> AZ_SDIN0_HD HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
iME Setting. T6 @ AU12 AUDIO SATA
JME @ HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
RH24 1 2PCH_SRTCRST# 1 2 T7 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
20K_0402_5% T8 @ AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
CH5 1 2 T9 @ AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17
I2S1_SCLK SATA_TP3/PETP6_L0
1U_0402_6.3V6K ODD_DETECT# PU at Page10
V1 EC_SMI# <36>
SATA0GP/GPIO34 U1
SATA1GP/GPIO35 ODD_DETECT# <10,31> +1.05VS_ASATA3PLL
V6 @ T159
SATA2GP/GPIO36 AC1 @
INTVRMEN SATA3GP/GPIO37
T165
*H Integrated VRM enable
L Integrated VRM disable +RTCVCC 51_0402_5% 1 @ 2 R98
T95 @ PCH_JTAG_RST#
PCH_JTAG_TCK
AU62
AE62 PCH_TRST A12
T21 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 @ T13
T19 @ PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 @ T14
PCH_TDO RSVD within 500 mils
PCH_INTVRMEN R73 1 2 330K_0402_5% T15 @ PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
T10 @ AL11 PCH_TMS SATA_RCOMP U3
T11 @ AC4 RSVD SATALED
SM_INTRUDER# R72 1 2 1M_0402_5% T22 @ PCH_TCK_JTAGX AE63 RSVD
T12 @ AV2 JTAGX
C RSVD C
5 OF 19 Rev1p2
HDA for AUDIO

RP14
<35> AZ_RST_HD# 1 8 HDA_RST#
<35> AZ_BITCLK_HD 2 7 HDA_BIT_CLK
<35> AZ_SDOUT_HD 3 6 HDA_SDOUT
<35> AZ_SYNC_HD 4 5 HDA_SYNC
33_0804_8P4R_5%
<36> PWRME_CTRL 1 Rshort@ 2

R163 0_0402_5%
ME Debug
FAN Control Circuit
B +5VS B
RTC schematic for non-chargeable @
JFAN
1A +FAN2 1
+RTCBATT 1 Rshort@ 2 +5VS_FAN 2 1
+RTCVCC 1 2 R32 0_0603_5% @ 3 2
+3VL 2 3
1
D16 RB751V40_SC76-2 C43
1 2 +RTCBATT_R 2 1 C60 4
D17 @ RB751V40_SC76-2 R277 1K_0402_5% 10U_0805_6.3V6M 1000P_0402_50V7K 5 GND
1
2
@ U4 1 GND
1
C502 1 8 CVILU_CI4403M1HRT-NH
0.1U_0402_16V4Z 2 EN GND 7
+
2 +FAN2 3 VIN GND 6 R29 10K_0402_5%

4 VOUT GND 5 2 1
<36> DFAN1 VSET GND +3VS
JRTC 10mil
1
P2793BB0_SO8 FAN_SPEED1
FAN_SPEED1 <36>
R437 SUYIN_060003HA002G202ZL C71 1
+RTC_R 2 1 @ 10U_0805_6.3V6M C75
2
1K_0402_5% 0.01U_0402_25V7K
@
2
Main source SA00005CA00
-
2nd source SA00005JO00

2
0812 -> Add R277 for RTC reserve charge
A Change D16,D17 P/N from A
SCS0340L010 to SCS00003500
for X code.
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(3/11) RTC,SATA,XDP
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
PCH_X1 UC1F @
2 1 PCH_X2
1M_0402_5% R48
C43 A25 PCH_X1

Y2 C42 CLKOUT_PCIE_N0 XTAL24_IN B25 PCH_X2
1 3 T158 @ U2 CLKOUT_PCIE_P0 XTAL24_OUT
2 4 PCIECLKRQ0/GPIO18 K21 @ T16
24MHZ_12PF_X3G024000DC1H B41 RSVD M21 @ T17
1 1 <37> CLK_CR# CLKOUT_PCIE_N1 RSVD
D A41 C26 XCLK_BIASREF R78 1 2 3.01K_0402_1% +1.05VS_AXCK_LCPLL D
<37> CLK_CR CLKOUT_PCIE_P1 DIFFCLK_BIASREF
C2 C3 <37> CLKREQ_CR# CLKREQ_CR# Y5
12P_0402_50V8J 12P_0402_50V8J PCIECLKRQ1/GPIO19 C35 R140 1 2 10K_0402_5%
2 2 C41 CLOCK TESTLOW_C35 C34 R141 1 2 10K_0402_5%
<33> CLK_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
PCIE LAN B42 AK8 R142 1 2 10K_0402_5%
<33> CLK_LAN CLKOUT_PCIE_P2 TESTLOW_AK8
<33> CLKREQ_LAN# CLKREQ_LAN# AD1 SIGNALS AL8 R148 1 2 10K_0402_5%
PCIECLKRQ2/GPIO20 TESTLOW_AL8
B38 AN15 CLKOUT_LPC0 R390 2 EMI@ 1 22_0402_5%
<32> CLK_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_EC <36>
C37 AP15 CLKOUT_LPC1_R R391 2 1 22_0402_5%
<32> CLK_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLKOUT_LPC1 <33>
WLAN <10,32> CLKREQ_WLAN# CLKREQ_W LAN# N1 TPM@EMI@
PCIECLKRQ3/GPIO21 B35 CLK_BCLK_ITP# @ T18
A39 CLKOUT_ITPXDP_N A35 CLK_BCLK_ITP @ T130
+3VS <18> CLK_PCIE_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P +3VS
B39 CLK_PCI_EC
<18> CLK_PCIE_VGA CLKOUT_PCIE_P4
<19> CLK_REQ_VGA# CLK_REQ_VGA# U5
PCIECLKRQ4/GPIO22
1
B37 1 CH10
1 2 CLKREQ_CR# A37 CLKOUT_PCIE_N5 @EMI@
RH90 10K_0402_5% T160 @ T2 CLKOUT_PCIE_P5 CH11 @EMI@ 10P_0402_50V8J
PCIECLKRQ5/GPIO23 10P_0402_50V8J 2
1 2 CLKREQ_LAN# 2
RH92 10K_0402_5% 6 OF 19 Rev1p2
CLKREQ_WLAN# pull high on page 10

HASWELL_MCP_E
UC1G @
+3VS AU14 AN2

<33,36> LPC_AD0 LAD0 SMBALERT/GPIO11 SMB_ALERT# <10>
AW12 AP2 PCH_SMBCLK
<33,36> LPC_AD1 LAD1 SMBCLK
AY12 LPC AH1 PCH_SMBDATA
<33,36> LPC_AD2 LAD2 SMBDATA PCH_SMBDATA <10>
2
C AW11 AL2 C
<33,36> LPC_AD3 LAD3 SML0ALERT/GPIO60 LAN_EN <10,33>
RH89 AV12 SMBUS AN1
<33,36> LPC_FRAME# LFRAME SML0CLK SML0CLK <10>
10K_0402_5% AK1
SML0DATA SML0DATA <10>
UMA@ AU4 @ T170
SML1ALERT/PCHHOT/GPIO73 AU3 PCH_SMLCLK1
1
SML1CLK/GPIO75 AH3
SML1DATA/GPIO74 PCH_SMLDATA1 <10>
CLK_REQ_VGA# PCH_SPICLK AA3
PCH_SPICS0# Y7 SPI_CLK AF2 @ T23
Y4 SPI_CS0 CL_CLK AD2 @ T24
SPI_CS1 CL_DATA
2
AC2 SPI C-LINK AF4 @ T25

RH91 PCH_SPIDI AA2 SPI_CS2 CL_RST
PCH_SPIDO1 AA4 SPI_MOSI +3VALW _PCH
10K_0402_5% SPI_MISO
VGA@ PCH_SPIDO2 Y6
PCH_SPIDO3 AF1 SPI_IO2 RP8
1
SPI_IO3 1 8 2.2K_0804_8P4R_5%
<9> SUSW ARN#
PCH_SMLCLK1 2 7
3 6
<11> USB_CHG_OC#
PCH_SMBCLK 4 5
7 OF 19 Rev1p2
PCH_SMBDATA pull high on page 10
+3VS
+3VS
2
B B
R116 R119
4.7K_0402_5% 4.7K_0402_5%
2
+3VALW _PCH Q7A
2N7002DW -T/R7_SOT363-6
1
PCH_SMBDATA 6 1 PM_SMBDATA <16,17,37>
5
RH5 2 1 1K_0402_5% PCH_SPIDO2 +3VALW _PCH
RH16 2 1 1K_0402_5% PCH_SPIDO3 PCH_SMBCLK 3 4

SPI ROM for BIOS & ME & Win8 (8MByte ) CH9 0.1U_0402_10V7K
PM_SMBCLK <16,17,37>
1 2 Q7B
UH3 2N7002DW -T/R7_SOT363-6
RH61 1 FIX@ 2 15_0402_5% PCH_SPICS0# 1 8
<36> EC_CS0# CS# VCC
PCH_SPIDO1 RH68 1 2 15_0402_5% PCH_SPI0_DO1 2 7 PCH_SPI0_DO3 RH65 1 2 15_0402_5% PCH_SPIDO3
PCH_SPIDO2 RH69 1 2 15_0402_5% PCH_SPI0_DO2 3 SO HOLD# 6 PCH_SPI0_CLK RH66 1 Rshort@ 2 0_0402_5% PCH_SPICLK
4 WP# SCLK 5 PCH_SPI0_DI RH67 1 2 15_0402_5% PCH_SPIDI
GND SI +3VS
RH72 1 FIX@ 2 15_0402_5%
<36> EC_SDIO
S IC FL 64M W 25Q64FVSSIQ SOIC 8P SPI ROM
5
RH74 1 FIX@ 2 15_0402_5% PU 2.2K at EC side (+3VS)
EC_SCK <36>
RH78 1 FIX@ 2 15_0402_5% PCH_SMLDATA1 3 4
EC_SDI <36> EC_SMB_DA2 <19,36>
2
QH4B
Please place UH3 close to U1 CPU, 2N7002DW -T/R7_SOT363-6
6 1
Please place RH66, RH67, RH68 near UH3 PCH_SMLCLK1
EC_SMB_CK2 <19,36>
QH4A
A A
2N7002DW -T/R7_SOT363-6
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(4/11) CLK,SPI,SMBUS
Custom 1.0
5 4 3 2 1
5 4 3 2 1
DH2
PCH_PW ROK 2 +3VALW _PCH
+3VS
1 PCH_RSMRST#
EC_SW I# RH171 2 1
1
3 1K_0402_5%
<36,42> POK
R227 DSWODVREN - On Die DSW VR Enable
10K_0402_5% BAS40-04_SOT23-3 * LHEnable(DEFAULT)
Disable
+RTCVCC
2
SYS_RESET#
HASWELL_MCP_E
UC1H @
D R124 1 2 330K_0402_5% D
@ESD@ R206 SYSTEM POWER MANAGEMENT

1 2 PLT_RST# SUSW ARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSW ODVREN
CH7 180P_0402_50V8J SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#
SYS_PW ROK AG2 SYS_RESET DPWROK AJ5 EC_SW I#
SYS_PWROK WAKE EC_SW I# <33,36>
<36> PCH_PW ROK PCH_PW ROK AY7
10K_0402_5% 2 1 R117 PCH_RSMRST# AB5 PCH_PWROK 1 2
APWROK +3VS
PLT_RST# AG7 V5 CLKRUN# R157 8.2K_0402_5%
<18,36> PLT_RST# PLTRST CLKRUN/GPIO32 AG4 @ T104
2 1 PCH_RSMRST# SUS_STAT/GPIO61 AE6
SUSCLK/GPIO62 CLK_EC <32>
C169 0.1U_0402_16V7K AP5 PM_SLP_S5#
SLP_S5/GPIO63 PM_SLP_S5# <36>
@ <36> PCH_RSMRST# PCH_RSMRST# AW6 @ T27
2 1 PCH_PW ROK SUSW ARN# AV4 RSMRST @ T28 @ T29
<8> SUSW ARN# SUSWARN/SUSPWRDNACK/GPIO30
C170 0.1U_0402_16V7K <36> PBTN_OUT# AL7 AJ6 PM_SLP_S4#
PWRBTN SLP_S4 PM_SLP_S4# <36>
@ PCH_ACIN AJ8 AT4 PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# <36>
+3VALW _PCH R156 1 2 8.2K_0402_5% PCH_BATLOW # AN4 AL5 @ T30
+3VALW_PCH T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
SLP_WLAN/GPIO29 SLP_LAN +3VALW _PCH
10K_0402_5%
1
R245
100K_0402_5% not support Deep S4,S5 can NC
Note for PCH_ACIN: Deep Sx need use 8 OF 19 Rev1p2
D21 EC GPIO for ACPRESENT function
2
<36,41> ACIN 1 2 PCH_ACIN

DDPB_CTRLDATA: Port B Detected
RB751V40_SC76-2
DDPC_CTRLDATA: Port C Detected
C C
Change D21 P/N from 1: Port B or C is detected

SCS0340L010 to SCS00003500 * 0: Port B or C is not detected
for X code. (Have internal PD)
HASWELL_MCP_E
UC1I @
+3VS
RH17 1 LVDS@ 2 0_0402_5%
<26> PCH_PW M_TL
RH18 1 IEDP@ 2 0_0402_5% PCH_PW M B8 B9
<27> PCH_PW M_EDP EDP_BKLCTL DDPB_CTRLCLK
RH19 1 Rshort@ 2 0_0402_5% EC_ENBKL_R_CPU A9 C9 R271 1 2 2.2K_0402_5%
EC_ENBKL_R C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9
EDP_VDDEN DDPC_CTRLCLK UMA_HDMI_CLK <28>
EC_ENBKL_R D11
<26,36> EC_ENBKL_R DDPC_CTRLDATA UMA_HDMI_DATA <28>
<27> LCD_ENVDD
1
R418 U6
<18,48> DGPU_PW RGD PIRQA/GPIO77
100K_0402_5% P4 C5
<10,20,45,48> PXS_PW REN PIRQB/GPIO78 DDPB_AUXN H_DDI1_AUXN <29>
N4 DISPLAY B6
<10,18> DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN
1 2 N2 B5
<10,37> TP_INTR# H_DDI1_AUXP <29>
2
RH7 HASW ELL@ 0_0402_5% T26 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6

PME GPIO DDPC_AUXP
1 2 U7
RH8 0_0402_5% T157 @ L1 GPIO55
BROADW ELL@ PCH_GPIO54 L3 GPIO52 C8
GPIO54 DDPB_HPD H_DP_HPD <29>
PCH_GPIO51 R5 A8 HDMI_HPD <10,28>
B PCH_GPIO53 L4 GPIO51 DDPC_HPD D6 H_EDP_HPD B
GPIO53 EDP_HPD H_EDP_HPD <26,27>
H_EDP_HPD
9 OF 19 Rev1p2
1
R417
R403 100K_0402_5%
PCH_PW ROK R65 1 Rshort@ 2 0_0402_5% SYS_PW ROK 0_0402_5%
2 @ 1
2
1
+3VS
R208
10K_0402_5%
5
VCC
2
PLT_RST# 1
IN1 4
OUT PLT_RST_BUF# <32,33,37>
2
GND
IN2
1
R416
100K_0402_5%
3
U30
MC74VHC1G08DFT2G_SC70-5
2
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(5/11) PM,GPIO,DDI
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VS Note: need check all GPIO PU need or not after BIOS post
RP23 1 8
2 7 TP_INTR# <37,9>
3 6 SERIRQ
4 5 ODD_EN
10K_0804_8P4R_5%
HASWELL_MCP_E
UC1J @
D D
T162 @ P1 D60 H_THERMTRIP#

RP27 1 8 T167 @ AU2 BMBUSY/GPIO76 THERMTRIP V4 KB_RST#
GPIO8 RCIN/GPIO82 KB_RST# <36>
2 7 ODD_DA# AM7 T4 SERIRQ SERIRQ <33,36>
3 6 EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 1 2 R146
DGPU_HOLD_RST# <18,9> <36> EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
4 5 CLKREQ_W LAN# <32,8> ODD_EN Y1 MISC AF20 @ T106 49.9_0402_1%
<38> ODD_EN GPIO16 RSVD
10K_0804_8P4R_5% ODD_DA# T3 AB21
<31> ODD_DA# GPIO17 RSVD
PCH_GPIO24 AD5
PCH_GPIO27 AN5 GPIO24
ESD@ PCH_GPIO28 AD7 GPIO27
1 2 ODD_DA# PCH_GPIO26 AN3 GPIO28
CH8 180P_0402_50V8J GPIO26 R6 PCH_GPIO83 +1.05VS_VTT
PASSW ORD_CLEAR# AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
T166 @ AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85 HASW ELL@
GPIO57 GSPI0_MISO/GPIO85
1
JPW PCH_GPIO58 AL4 L8 PCH_GPIO86 RH9 0_0402_5%
+3VALW _PCH @ PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT#_GPIO87 1 2 DGPU_PRSNT# R144
AK4 GPIO59 GSPI1_CS/GPIO87 L5 PCH_GPIO88 1K_0402_5%
2
PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89
RP34 1 8 BROADW ELL@ U4 GPIO47 GSPI1_MISO/GPIO89 K2 @ T135
SML0DATA <8>
2
2 7 DGPU_PRSNT# 1 2 DGPU_PRSNT#_GPIO49 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 @ T134
LAN_EN <33,8> GPIO49 UART0_RXD/GPIO91
3 6 RH10 0_0402_5% T139 @ P3 K3 PCH_GPIO92 H_THERMTRIP#
SMB_ALERT# <8> GPIO50 UART0_TXD/GPIO92
4 5 PCH_GPIO71 Y2 J2 PCH_GPIO93
SML0CLK <8> HSIOPC/GPIO71 UART0_RTS/GPIO93
RP35 10K_0804_8P4R_5% T168 @ AT3 LPIO G1 @ T114
8 1 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4
PCH_SMBDATA <8> GPIO14 UART1_RXD/GPIO0 HDMI_HPD <28,9>
7 2 T169 @ AM4 G2 @ T111
PCH_SMLDATA1 <8> GPIO25 UART1_TXD/GPIO1
6 3 PCH_GPIO45 AG5 J3 @ T133
USB_OC#2 <11,33,36> GPIO45 UART1_RST/GPIO2
5 4 PCH_GPIO46 AG3 J4 PCH_GPIO3
USB_OC#0 <11,34,36> GPIO46 UART1_CTS/GPIO3 F2 @ T132
C 2.2K_0804_8P4R_5% HASW ELL@ PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5 C
RH4 1 2 0_0402_5% AM2 GPIO9 I2C0_SCL/GPIO5 G4 PM_I2CSDA1
<36> EC_SCI# GPIO10 I2C1_SDA/GPIO6 PM_I2CSDA1 <37>
P2 F1 PM_I2CSCL1
DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PM_I2CSCL1 <37>
C4 E3 PCH_GPIO64
BROADW ELL@ T136 @ L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
RH6 1 2 0_0402_5% N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
PCH_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
<35> PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
+3VS RP28 1 8 PCH_GPIO27 C3 PCH_GPIO68
2 7 PASSW ORD_CLEAR# SDIO_D2/GPIO68 E2 ZP_DETECT
3 6 SDIO_D3/GPIO69
ODD_DETECT# <31,7>
4 5 PXS_PW REN <20,45,48,9> 10 OF 19 Rev1p2
10K_0804_8P4R_5%
+3VS
PM_I2CSDA1 R274 1 @ 2 1K_0402_5%
+3VS PM_I2CSCL1 R272 1 @ 2 1K_0402_5%

1
R306
10K_0402_5%
UMA@ +3VS Need to check the resistors value
2
GPIO87/GPIO49
1
DGPU_PRSNT# +3VS
DGPU_PRSNT# R215
2
10K_0402_5% ZPODD@ R269 1 @ 2 1K_0402_1% PCH_SPKR

B R219 B
10K_0402_5%
PowerXpress 0
GPIO69
2
VGA@ ZP_DETECT
UMA 1
1
ZPODD SKU 1 SPKR / GPIO81 : NO REBOOT
1
R216
10K_0402_5% NONZP@
None ZPODD SKU 0 1: ENABLED
0: DISABLED (Have internal PD)
*
2
GPIO88
TOUCH SKU 0 +3VALW _PCH PCH_GPIO86 R273 1 @ 2 1K_0402_5%
PCH_GPIO66 R270 1 @ 2 1K_0402_1%
None TOUCH SKU 1
R247 1 2 10K_0402_5% EC_LID_OUT#
GPIO15 : TLS Confidentiality GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
1: Intel ME TLS with confidentiality 1: ENABLED 1: ENABLED (Have internal PU)

0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) * 0: DISABLED
A
* (Have internal PD)
* A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(6/11) GPIO,LPIO
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
UC1K @
PCIE_GTX_C_CRX_N0 F10 AN8

PERN5_L0 USB2N0 USB20_N0 <34>
PCIE_GTX_C_CRX_P0 E10 AM8 USB-Right1
PERP5_L0 USB2P0 USB20_P0 <34>
PCIE_CTX_C_GRX_N0 C78 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_N0 C23 AR7
PETN5_L0 USB2N1 USB20_N1 <34>
PCIE_CTX_C_GRX_P0 C79 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_P0 C22 AT7 USB-Right2
PETP5_L0 USB2P1 USB20_P1 <34>
PCIE_GTX_C_CRX_N[0..3] <18>
PCIE_GTX_C_CRX_N1 F8 AR8
PCIE_GTX_C_CRX_P[0..3] <18> PERN5_L1 USB2N2 USB20_N2 <33>
PCIE_GTX_C_CRX_P1 E8 AP8 USB-Left1
PCIE_CTX_C_GRX_N[0..3] <18>
D PCIE_CTX_C_GRX_N1 C82 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_N1 B23 AR10 D
PCIE_CTX_C_GRX_P[0..3] <18> PETN5_L1 USB2N3
PCIE_CTX_C_GRX_P1 C83 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_P1 A23 AT10
PETP5_L1 USB2P3
PCIE_GTX_C_CRX_N2 H10 AM15
PERN5_L2 USB2N4 USB20_N4 <32>
PCIE_GTX_C_CRX_P2 G10 AL15 WiMAX / BT
PCIE_CTX_C_GRX_N2 C86 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_N2 B21 AM13
PCIE_CTX_C_GRX_P2 C87 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_P2 C21 AN13 Touch Screen
PCIE_GTX_C_CRX_N3 E6 AP11
PCIE_GTX_C_CRX_P3 F6 PERN5_L3 USB2N6 AN11
PERP5_L3 USB2P6
PCIE_CTX_C_GRX_N3 C90 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_N3 B22 AR13
PCIE_CTX_C_GRX_P3 C91 1 2 VGA@ .1U_0402_16V7K PEG_HTX_GRX_P3 A21 AP13 Camera
<33> PCIE_PRX_C_LANTX_N3 G11

F11 PERN3 G20
<33> PCIE_PRX_C_LANTX_P3 PERP3 USB3RN1
PCIE LAN H20
C155 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_N3 C29 USB3.0 P1 USB3RP1
<33> PCIE_PTX_C_LANRX_N3 PETN3
C160 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_P3 B30 PCIe USB C33
<33> PCIE_PTX_C_LANRX_P3 PETP3 USB3TN1 B34
F13 USB3TP1
<32> PCIE_PRX_W LANTX_N4 PERN4
<32> PCIE_PRX_W LANTX_P4 G13 E18
PERP4 USB3RN2 U3RXDN2 <34>
WLAN NGFF type F18
USB3.0 P2 USB3RP2 U3RXDP2 <34>
C156 1 2 0.1U_0402_16V7K PCIE_PTX_W LANRX_N4 B29
<32> PCIE_PTX_C_W LANRX_N4 PETN4
C157 1 2 0.1U_0402_16V7K PCIE_PTX_W LANRX_P4 A29 B33
<32> PCIE_PTX_C_W LANRX_P4 PETP4 USB3TN2 U3TXDN2 <34>
A33
G17 USB3TP2 U3TXDP2 <34>
F17 PERN1/USB3RN3
C PERP1/USB3RP3 C
C30 USB3.0 P3 / PCIE P1
C31 PETN1/USB3TN3 AJ10 USBRBIAS R154 1 2 22.6_0402_1%
PETP1/USB3TP3 USBRBIAS CAD note:
AJ11
F15 USBRBIAS AN10 @ T35 Route single-end 50-ohms and max 450-mils length.
<37> PCIE_PRX_C_CRTX_N2 PERN2/USB3RN4 RSVD
<37> PCIE_PRX_C_CRTX_P2 G15 AM10 @ T36 Avoid routing next to clock pins or under stitching capacitors.
PERP2/USB3RP4 USB3.0 P4 / PCIE P2 RSVD
PCIE Card Reader Recommended minimum spacing to other signal traces is 15 mils
C163 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_N2 B31
<37> PCIE_PTX_C_CRRX_N2 PETN2/USB3TN4
C161 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_P2 A31
<37> PCIE_PTX_C_CRRX_P2 PETP2/USB3TP4 AL3 USB_OC#0_R R167 1 @ 2 0_0402_5% USB-Right
OC0/GPIO40 USB_OC#0 <10,34,36>
AT1
+1.05VS_AUSB3PLL OC1/GPIO41 USB_CHG_OC# <8>
AH2 USB_OC#2_R R168 1 @ 2 0_0402_5% USB-Left
OC2/GPIO42 USB_OC#2 <10,33,36>
T33 @ E15 AV3 1 2 +3VALW _PCH
T34 @ E13 RSVD OC3/GPIO43 R234 10K_0402_5%
R232 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
B27 PCIE_RCOMP
PCIE_IREF
11 OF 19 Rev1p2
B B
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(7/11) PCIE,USB
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
UC1L @
T37 @ L59
+1.35V T38 @ J58 RSVD VCC
RSVD VCC
AH26 VCC
AJ31 VDDQ VCC
AJ33 VDDQ VCC
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
D D
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
AY44 VDDQ VCC E35
+CPU_CORE AY50 VDDQ VCC E37
VDDQ VCC E39
F59 VCC E41
T39 @ N58 VCC VCC E43
T40 @ AC58 RSVD VCC E45
RSVD VCC E47
VCC_SENSE_R E63 VCC E49
T41 @ AB23 VCC_SENSE VCC E51
T107 @ +VCCIO_OUT A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
T42 @ AD23 E57
AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
N63 VIDALERT VCC F40
<47> VR_SVID_CLK VIDSCLK VCC
VIDSOUT L63 F44
+3VS VCCST_PG_EC_R B59 VIDSOUT HSW ULT POWER VCC F48
+1.05VS_VTT F60 VCCST_PWRGD VCC F52
<47> VR_ON VR_EN VCC
<47> VGATE C59 F56
VR_READY VCC
1
+3VALW _PCH C167 G23

VCC
1
R422 1 2 0.1U_0402_16V7K D63 G25
100K_0402_5% U18 R309 @ T131 @ CPU_PW R_DEBUG H59 VSS VCC G27
1 5 P62 PWR_DEBUG VCC G29
@
NC VCC
10K_0402_5% Reserved Only VSS VCC
R166 T45 @ P60 G31
2
C 2 0_0402_5% T46 @ P61 RSVD_TP VCC G33 C

<36> VCCST_PG_EC
2
A 4 VCCST_PG_EC_R 1 @ 2 T47 @ N59 RSVD_TP VCC G35
Y VCCST_PWRGD <36,44> RSVD_TP VCC
3 2 T48 @ N61 G37
GND T98 @ T59 RSVD_TP VCC G39
74AUP1G07GW _TSSOP5 C168 T142 @ AD60 RSVD VCC G41
T143 @ AD59 RSVD VCC G43
0.1U_0402_16V7K RSVD VCC
1 T144 @ AA59 G45
@ RSVD VCC
T141 @ AE60 G47
T140 @ AC59 RSVD VCC G49
T147 @ AG58 RSVD VCC G51
+1.05VS_VTT T145 @ U59 RSVD VCC G53
T146 @ V59 RSVD VCC G55
SVID ALERT RSVD VCC
VCC
G57
AC22 H23
+CPU_CORE AE22 VCCST VCC J23
+1.05VS_VTT AE23 VCCST VCC K23
VCCST VCC K57
Place the PU VCC
AB57 L22
resistors close to CPU VCC VCC
1
AD57 M23
R171 AG57 VCC VCC M57
C24 VCC VCC P57
75_0402_1% VCC VCC
C28 U57
R172 C32 VCC VCC W57
2
43_0402_1% VCC VCC

2 1 H_CPU_SVIDALRT# 12 OF 19 Rev1p2
<47> VR_SVID_ALRT#
+1.35V +1.35V
B B
SVID DATA VDDQ DECOUPLING
+1.05VS_VTT
Place the PU
resistors close to CPU
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
C8
C9
C10
C11
R173 @ @ @
CC53
CC54
22U_0603_6.3V6M
22U_0603_6.3V6M
C12
C13
C14
C15
C19
C17
130_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2
2
2 Rshort@ 1 VIDSOUT
<47> VR_SVID_DAT
R174 0_0402_5%
+CPU_CORE
1
R177
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2
VCC_SENSE_R 2 Rshort@ 1 R178

VCC_SENSE <47>
0_0402_5% 2.2UF/6.3V/0402 * 4
A A
<14> VSS_SENSE_R 2 Rshort@ 1 R235

VSS_SENSE <47>
www.vinafix.vn
0_0402_5%
1
R233 Security Classification Compal Secret Data Compal Electronics, Inc.

100_0402_1% 2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(8/11) Power
2
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT HASWELL_MCP_E
UC1M @
K9 +3VALW _PCH +RTCVCC

L10 VCCHSIO
M9 VCCHSIO C73 1 2 1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
N8 VCCHSIO mPHY AH11
P9 VCC1_05 RTC VCCSUS3_3 AG10
1 1 1@
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VCC1_05 VCCRTC +RTCVCC
+1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2 1 1
VCCUSB3PLL DCPRTC
C21
C20
C70
+1.05VS_ASATA3PLL B11 C54 0.1U_0402_16V7K @
VCCSATA3PLL +3VALW _PCH
C52
C51
C50
2 2 2
T99 @ Y20 SPI Y8 C58 2 1 0.1U_0402_16V7K 2 2 2
AA21 RSVD OPI VCCSPI @
D +1.05VS_APLLOPI D
W21 VCCAPLL
Near K9 Near L10 Near M9
VCCAPLL AG14
VCCASW +1.05VS_VTT
AG13
+3VALW _PCH VCCASW
+1.05VS_VTT
HDA --> 3.3V or 1.5V T105 @ J13 USB3
+1.05VS_VTT +1.05VS_AUSB3PLL I2C --> 1.8V DCPSUS3 J11 C81 1 2 10U_0603_6.3V6M
Near B18 VCC1_05 H11 C84 1 2 1U_0402_6.3V6K
C42 1 2 1U_0402_6.3V6K 2 1 C38 AH14 AXALIA/HDA VCC1_05 H15 C40 1 2 1U_0402_6.3V6K
L1 1 2 C64 1 2 22U_0603_6.3V6M 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 C41
2.2UH_LQM2MPN2R2NG0L_30% VCC1_05 AF22 1U_0402_6.3V6K
Idc 1.2A Rdc 0.11ohm +/-30% T116 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 2
DCPSUS2 CORE DCPSUSBYP AG20
+1.05VS_ASATA3PLL +3VALW _PCH DCPSUSBYP AE9
VCCASW +1.05VS_VTT
C39 AF9 C53 1 2 22U_0805_6.3V6M C69
Near B11 Near AC9 2 1 22U_0603_6.3V6M AC9 VCCASW AG8 C37 1 2 1U_0402_6.3V6K 1 2 0.47U_0402_16V4Z
VCCSUS3_3 VCCASW +3VALW _PCH
C46 1 2 1U_0402_6.3V6K C59 @ AA9 AD10
L2 1 2 C65 1 2 22U_0603_6.3V6M Near AH10 2 1 0.1U_0402_16V7K AH10 VCCSUS3_3 DCPSUS1 AD8 @ T108
2.2UH_LQM2MPN2R2NG0L_30% C61 V8 VCCDSW3_3 GPIO/LCC DCPSUS1 Near AG19
Idc 1.2A Rdc 0.11ohm +/-30% Near V8 2 1 22U_0603_6.3V6M W9 VCC3_3
VCC3_3 J15
+1.05VS_APLLOPI VCCTS1_5 +1.5VS
R210 @ +3VS
THERMAL SENSOR K14 +3VS
0_0805_5% VCC3_3 K16 C55 1 2 0.1U_0402_16V7K
1 2 Near AA21 VCC3_3
C47 1 2 1U_0402_6.3V6K
L3 1 2 C66 1 2 22U_0603_6.3V6M +1.05VS_AXCK_DCB J18
2.2UH_LQM2MPN2R2NG0L_30% K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
Idc 1.2A Rdc 0.11ohm +/-30% A20 T9 C44 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
+1.05VS_VTT J17
C C57 R21 VCCCLK C
Near J17 2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER
+1.05VS_VTT +1.05VS_AXCK_DCB C56 T100 @ K18 VCCCLK SUS OSCILLATOR AB8 @ T137
Near R21 2 1 1U_0402_6.3V6K T101 @ M20 RSVD DCPSUS4
Near J18 V21 RSVD
C48 1 2 1U_0402_6.3V6K AE20 RSVD AC20 @ T103
+3VALW _PCH VCCSUS3_3 RSVD
L4 1 2 C67 1 2 22U_0603_6.3V6M AE21 AG16 +1.05VS_VTT
2.2UH_LQM2MPN2R2NG0L_30% VCCSUS3_3 USB2 VCC1_05 AG17
Idc 1.2A Rdc 0.11ohm +/-30% VCC1_05 C45 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
Near A20 13 OF 19 Rev1p2
C49 1 2 1U_0402_6.3V6K
L5 1 2 C68 1 2 22U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%
+3VALW to +3VALW_PCH
B +3VALW +3VALW _PCH B
@
2 1
PJ2 2 1 JUMP_43X39
Q10
@ AO3413_SOT23
S
3 1
CH111
CH112
CH113
G
1 1
2
@ @ @
0.1U_0402_25V6
0.1U_0402_10V7K
0.01U_0402_25V7K
2 2
PCH_PW R_EN# 2 @ 1
<38> PCH_PW R_EN#
RH3 47K_0402_5%
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(9/11) Power
Custom 1.0
5 4 3 2 1
5 4 3 2 1
@ @ @
HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R <12>
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH44 VSS VSS AN45 AV24 VSS VSS D12
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 Rev1p2 VSS
14 OF 19 Rev1p2
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(10/11) GND
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E HASWELL_MCP_E
UC1Q @ UC1R @
DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3 T51 @ AT2 N23 @ T64

DC_TEST_AY3_AW 3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 @ T58 T52 @ AU44 RSVD RSVD R23 @ T65
T49 @ AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 T53 @ AV44 RSVD RSVD T23 @ T66
DC_TEST_AY61_AW 61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T59 T54 @ D15 RSVD RSVD U10 @ T67
DC_TEST_AY62_AW 62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 RSVD RSVD
T50 @ B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 @ T60
D D
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 @ T61 T55 @ F22 AL1 @ T68
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 @ T62 T56 @ H22 RSVD RSVD AM11 @ T69
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW 2 T57 @ J21 RSVD RSVD AP7 @ T70
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW 3 RSVD RSVD AU10 @ T71
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW 61 RSVD AU15 @ T72
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW 62 RSVD AW14 @ T73
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T63 RSVD AY14 @ T74
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63 RSVD
18 OF 19 Rev1p2
UC1S @ HASWELL_MCP_E
T110 @ CFG0 AC60 AV63 @ T75

T109 @ CFG1 AC62 CFG0 RSVD_TP AU63 @ T76
T112 @ CFG2
CFG3
AC63
AA63
CFG1
CFG2
RSVD_TP CFG Straps for Processor
CFG4 AA60 CFG3 C63 @ T77
T113 @ CFG5 Y62 CFG4 RSVD_TP C62 @ T78
C T117 @ CFG6 Y61 CFG5 RSVD_TP B43 @ T79 C
T115 @ CFG7 Y60 CFG6 RSVD CFG3
T119 @ CFG8 V62 CFG7 A51 @ T80
CFG8 RSVD_TP
1
T118 @ CFG9 V61 B51 @ T81
T121 @ CFG10 V60 CFG9 RSVD_TP R224
T120 @ CFG11 U60 CFG10 L60 @ T82 1K_0402_1%
T124 @ CFG12 T63 CFG11 RESERVED RSVD_TP @
T122 @ CFG13 T62 CFG12 N60 @ T83
2
T125 @ CFG14 T61 CFG13 RSVD
T123 @ CFG15 T60 CFG14 W23 @ T84
CFG15 RSVD Y22 @ T85
T128 @ CFG16 AA62 RSVD AY15 OPI_COMP
T127 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T129 @ CFG17 AA61 CFG18 AV62 @ T86
U62 CFG17 RSVD D58
T126 @ CFG19
CFG19 RSVD
@ T87 Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
VSS 1: DISABLED
T90 @ A5 CFG3
RSVD P20 @ T88
RSVD 0: ENABLED; SET DFX ENABLED BIT
T91 @ E1 R20 @ T89
T92 @ D1 RSVD RSVD IN DEBUG INTERFACE MSR
T93 @ J20 RSVD
T94 @ H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF
1
19 OF 19 Rev1p2
R225
1K_0402_5%
B B
2
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1%
2 1 TD_IREF Display Port Presence Strap
R226 8.2K_0402_5%
1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
A A
www.vinafix.vn
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date HSW MCP(11/11) RSVD
Custom 1.0
5 4 3 2 1
A B C D E
+1.35V
+1.35V +1.35V +1.35V
JDIMM1
1
+V_DDR_REFA 1 2
VREF_DQ VSS
DDR3 SO-DIMM A +5VS
0.1U_0402_16V7K
3 4 DDR_A_D9
VSS DQ4
C34
R54 DDR_A_D13 5 6 DDR_A_D12
R293
2_0402_1%
1.8K_0402_1% DDR_A_D8 7
9
DQ0
DQ1
DQ5
VSS
8
10 DDR_A_DQS#1
Reverse Type @
1
R187 1 2 SA_ODT0
H=4.0mm
2
1 2 11 VSS DQS0# 12 DDR_A_DQS1 66.5_0402_1%
<6> SA_DIMM_VREFDQ DM0 DQS0 2
1 13 14
2
@ DDR_A_D14 15 VSS VSS 16 DDR_A_D15
1 DQ2 DQ6 +1.35V
0.1U_0402_16V7K
C106
C158 DDR_A_D10 17 18 DDR_A_D11 R191 R188 1 2 SA_ODT1
0.022U_0402_25V7K R185 19 DQ3 DQ7 20 U45 66.5_0402_1%
100K_0402_5%
2 1.8K_0402_1% DDR_A_D29 21 VSS VSS 22 DDR_A_D25 1 5 Q20
DQ8 DQ12 NC VCC
1
2 DDR_A_D28 23 24 DDR_A_D24 LBSS138LT1G_SOT-23-3
1
25 DQ9 DQ13 26 2 D R189 1 2 SB_ODT0
1 VSS VSS <5> DDR_PG_CTRL A SB_ODT0 <17> 1
R176 DDR_A_DQS#3 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_A_DQS3 29 DQS1# DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# <17,5> GND
@ 31 32 S
2
3
DDR_A_D30 33 VSS VSS 34 DDR_A_D27 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT R190 1 2 SB_ODT1
DQ10 DQ14 SB_ODT1 <17>
Note: Depend on Project DDR_A_D31 35 36 DDR_A_D26 66.5_0402_1%
37 DQ11 DQ15 38
DDR_A_D44 39 VSS VSS 40 DDR_A_D45
DQ16 DQ20 DDR_VTT_PG_CTRL <43>
DDR_A_D41 41 42 DDR_A_D40
43 DQ17 DQ21 44
VSS VSS DDR_A_DQS#[0..7] <6>
DDR_A_DQS#5 45 46
DDR_A_DQS5 47 DQS2# DM2 48
DQS2 VSS DDR_A_DQS[0..7] <6>
49 50 DDR_A_D42
DDR_A_D43 51 VSS DQ22 52 DDR_A_D46
DQ18 DQ23 DDR_A_D[0..63] <6>
DDR_A_D47 53 54
55 DQ19 VSS 56 DDR_A_D52
All VREF traces should DDR_A_D51 57 VSS DQ28 58 DDR_A_D53
DDR_A_MA[0..15] <6>
Layout Note: have 10 mil trace width DDR_A_D50 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS 62 DDR_A_DQS#6
+1.35V 63 VSS DQS3# 64 DDR_A_DQS6
Place near DDR connector for DQA easy access
65 DM3 DQS3 66
DDR_A_D49 67 VSS VSS 68 DDR_A_D54 1 @ 2
DQ26 DQ30 <36,37> ON/OFFBTN#
DDR_A_D48 69 70 DDR_A_D55 R8 0_0805_5%
DQ27 DQ31
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C110
71 72
VSS VSS
1 1 1 1
@ @
<6> DDRA_CKE0_DIMMA DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA DDRA_CKE1_DIMMA <6>
75 CKE0 CKE1 76
2 2 2 2 77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
<6> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
2 DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6 2
+1.35V DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
A1 A0
10U_0603_6.3V6M
C111
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C114
99 100
SA_CLK_DDR0 101 VDD VDD 102 SA_CLK_DDR1
1 1 1 1 <6> SA_CLK_DDR0 CK0 CK1 SA_CLK_DDR1 <6>
<6> SA_CLK_DDR#0 SA_CLK_DDR#0 103 104 SA_CLK_DDR#1 SA_CLK_DDR#1 <6>
105 CK0# CK1# 106
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
2 2 2 2 A10/AP BA1 DDR_A_BS1 <6> +1.35V
<6> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# <6>
111 BA0 RAS# 112
DDR_A_WE# 113 VDD VDD 114 DDRA_CS0_DIMMA#
<6> DDR_A_WE# DDRA_CS0_DIMMA# <6>
1
DDR_A_CAS# 115 WE# S0# 116 SA_ODT0
<6> DDR_A_CAS# CAS# ODT0
117 118 R56
DDR_A_MA13 119 VDD VDD 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
<6> DDRA_CS1_DIMMA# S1# NC
123 124 R296
2
+1.35V 125 VDD VDD 126 +VREF_CA 1 2
TEST VREF_CA SM_DIMM_VREFCA <6>
127 128 2_0402_1% 1
VSS VSS
1
DDR_A_D0 129 130 DDR_A_D5 @
DQ32 DQ36
0.1U_0402_16V7K
DDR_A_D1 131 132 DDR_A_D4 C162
DQ33 DQ37
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C117
133 134 1 R295 0.022U_0402_25V7K

VSS VSS 2
C120
1 1 1 DDR_A_DQS#0 135 136 1.8K_0402_1%
DQS4# DM4
1
DDR_A_DQS0 137 138
2
139 DQS4 VSS 140 DDR_A_D3
@ DDR_A_D2 141 VSS DQ38 142 DDR_A_D7 2 @ R294
2 2 2 DDR_A_D6 143 DQ34 DQ39 144 24.9_0402_1%
145 DQ35 VSS 146 DDR_A_D18
2
DDR_A_D21 147 VSS DQ44 148 DDR_A_D19
DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#2 Note: Depend on Project
153 VSS DQS5# 154 DDR_A_DQS2
3 155 DM5 DQS5 156 3
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
DQ43 DQ47 +VREF_CA <17>
161 162
+0.675VS DDR_A_D36 163 VSS VSS 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
DDR_A_DQS#4 169 VSS VSS 170
DQS6# DM6
1U_0402_6.3V6K
C121
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
C124
DDR_A_DQS4 171 172

173 DQS6 VSS 174 DDR_A_D35
1 1 1 1 VSS DQ54
@ @ DDR_A_D34 175 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D63
2 2 2 2 DDR_A_D62 181 VSS DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
195 DQ59 DQ63 196
Layout Note: 197 VSS VSS 198
Place near JDIMM1.203,204 199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMBDATA <17,37,8>
201 202
SA1 SCL PM_SMBCLK <17,37,8>
+0.675VS 203 204 +0.675VS
VTT VTT
205 206
GND1 GND2
2
1 207 208
BOSS1 BOSS2
Channel A
0.1U_0402_16V7K
C125
Rshort@
0_0402_5%
R211
Rshort@
0_0402_5%
R212
LCN_DAN06-K4406-0103
2 @
1
4 4
<Address: SA1:SA0=00>
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Note: Depend on Project
DIMM_1 REV H:4mm
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date DDRIII DIMMA
Custom 1.0
A B C D E
A B C D E
+1.35V
+1.35V +1.35V
JDIMM2
DDR_B_DQS#[0..7] <6>
1
+V_DDR_REFB 1 2
3 VREF_DQ VSS 4 DDR_B_D12
VSS DQ4 DDR_B_DQS[0..7] <6>
R57 DDR_B_D8 5 6 DDR_B_D9
R297 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8
DQ1 VSS DDR_B_D[0..63] <6>
2_0402_1% 9 10 DDR_B_DQS#1
2
1 2 11 VSS DQS0# 12 DDR_B_DQS1
<6> SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] <6>
1 13 14
1
@ DDR_B_D10 15 VSS VSS 16 DDR_B_D13
1 DQ2 DQ6
0.1U_0402_16V7K
C128
C159 DDR_B_D11 17 18 DDR_B_D15
0.022U_0402_25V7K R213 19 DQ3 DQ7 20
2 1.8K_0402_1% DDR_B_D28 21 VSS VSS 22 DDR_B_D25
DQ8 DQ12
DDR3 SO-DIMM B
1
2 DDR_B_D29 23 24 DDR_B_D24
2
25 DQ9 DQ13 26
1
R179
24.9_0402_1%
DDR_B_DQS#3
DDR_B_DQS3
27
29
VSS
DQS1#
VSS
DM1
28
30 DIMM_DRAMRST#
Reverse Type 1
@ 31 DQS1 RESET# 32
DIMM_DRAMRST# <16,5>
H=4.0mm
2
DDR_B_D26 33 VSS VSS 34 DDR_B_D30

Note: Depend on Project DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS VSS 46
DDR_B_DQS5 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D47
DDR_B_D46 51 VSS DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_B_D61
All VREF traces should DDR_B_D56 57 VSS DQ28 58 DDR_B_D60
Layout Note: have 10 mil trace width DDR_B_D57 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS 62 DDR_B_DQS#7
+1.35V 63 VSS DQS3# 64 DDR_B_DQS7
65 DM3 DQS3 66
DQ27 DQ31
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
71 72
VSS VSS
1 1 1 1
@ @
<6> DDRB_CKE0_DIMMB DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB DDRB_CKE1_DIMMB <6>
75 CKE0 CKE1 76
2 2 2 2 77 VDD VDD 78 DDR_B_MA15
DDR_B_BS2 79 NC A15 80 DDR_B_MA14
<6> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
2 DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6 2
+1.35V DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
A1 A0
10U_0603_6.3V6M
C133
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
C136
99 100
SB_CLK_DDR0 101 VDD VDD 102 SB_CLK_DDR1
1 1 1 1 <6> SB_CLK_DDR0 CK0 CK1 SB_CLK_DDR1 <6>
<6> SB_CLK_DDR#0 SB_CLK_DDR#0 103 104 SB_CLK_DDR#1 SB_CLK_DDR#1 <6>
105 CK0# CK1# 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
2 2 2 2 A10/AP BA1 DDR_B_BS1 <6>
<6> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# <6>
111 BA0 RAS# 112
DDR_B_WE# 113 VDD VDD 114 DDRB_CS0_DIMMB#
<6> DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# <6>
<6> DDR_B_CAS# DDR_B_CAS# 115 116 SB_ODT0 SB_ODT0 <16>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD VDD 120 SB_ODT1
A13 ODT1 SB_ODT1 <16>
<6> DDRB_CS1_DIMMB# DDRB_CS1_DIMMB# 121 122
123 S1# NC 124
+1.35V 125 VDD VDD 126 +VREF_CA
TEST VREF_CA +VREF_CA <16>
127 128
DQ33 DQ37
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C139
133 134 1
VSS VSS
0.1U_0402_16V7K
C142
1 1 1 DDR_B_DQS#0 135 136
DDR_B_DQS0 137 DQS4# DM4 138
@ DDR_B_D3 141 VSS DQ38 142 DDR_B_D6 2
2 2 2 DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_B_D16
DDR_B_D21 147 VSS DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#2
153 VSS DQS5# 154 DDR_B_DQS2 Note: Depend on Project
3 155 DM5 DQS5 156 3
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
+0.675VS DDR_B_D36 163 VSS VSS 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS#4 169 VSS VSS 170
DQS6# DM6
1U_0402_6.3V6K
C143
1U_0402_6.3V6K
C144
1U_0402_6.3V6K
C145
1U_0402_6.3V6K
C146
DDR_B_DQS4 171 172

1 1 1 1 VSS DQ54
@ @ DDR_B_D35 175 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_B_D51
2 2 2 2 DDR_B_D52 181 VSS DQ60 182 DDR_B_D55
+3VS DDR_B_D49 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#6
187 VSS DQS7# 188 DDR_B_DQS6
DM7 DQS7
2
189 190
R229 DDR_B_D48 191 VSS VSS 192 DDR_B_D54
10K_0402_5% DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
195 DQ59 DQ63 196
Layout Note: 197 VSS VSS 198
1
Place near JDIMM1.203,204 199 SA0 EVENT# 200

+3VS VDDSPD SDA PM_SMBDATA <16,37,8>
201 202
SA1 SCL PM_SMBCLK <16,37,8>
+0.675VS 203 204 +0.675VS
VTT VTT
205 206
207 GND1 GND2 208
BOSS1 BOSS2
2
1
Channel B
0.1U_0402_16V7K
C147
Rshort@
0_0402_5%
R231
LCN_DAN06-K4406-0103
@
4
2 4
1
<Address: SA1:SA0=10>
www.vinafix.vn
Note: Depend on Project
DIMM_2 REV H:4mm
2013/09/25 2016/09/25 Title
Issued Date Deciphered Date DDRIII DIMMB
Custom 1.0
A B C D E
1 2 3 4 5
UV1A
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
AF30 AH30 PCIE_GTX_CRX_P0 .1U_0402_16V7K 2 1 VGA@ CV1 PCIE_GTX_C_CRX_P0
<11> PCIE_CTX_C_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_GTX_C_CRX_P0 <11>
AE31 AG31 PCIE_GTX_CRX_N0 .1U_0402_16V7K 2 1 VGA@ CV2 PCIE_GTX_C_CRX_N0
<11> PCIE_CTX_C_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_GTX_C_CRX_N0 <11>
A AE29 AG29 PCIE_GTX_CRX_P1 .1U_0402_16V7K 2 1 VGA@ CV3 PCIE_GTX_C_CRX_P1 A

AD28 AF28 PCIE_GTX_CRX_N1 .1U_0402_16V7K 2 1 VGA@ CV4 PCIE_GTX_C_CRX_N1
AD30 AF27 PCIE_GTX_CRX_P2 .1U_0402_16V7K 2 1 VGA@ CV5 PCIE_GTX_C_CRX_P2

AC31 AF26 PCIE_GTX_CRX_N2 .1U_0402_16V7K 2 1 VGA@ CV6 PCIE_GTX_C_CRX_N2
AC29 AD27 PCIE_GTX_CRX_P3 .1U_0402_16V7K 2 1 VGA@ CV7 PCIE_GTX_C_CRX_P3

AB28 AD26 PCIE_GTX_CRX_N3 .1U_0402_16V7K 2 1 VGA@ CV8 PCIE_GTX_C_CRX_N3
AB30
AA31 PCIE_RX4P PCIE_TX4P
AC25
AB25
LVDS Interface
PCIE_RX4N PCIE_TX4N UV1F
AA29 Y23 +VGA_CORE

Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11
VARY_BL AB12 Topaz
Y30 AB27 DIGON
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N
W29 Y27 AL15

V28 PCIE_RX7P PCIE_TX7P Y26 TXCAP_DPA3P AK14
PCIE_RX7N PCIE_TX7N TXCAM_DPA3N
AH16
V30 W24 TX0P_DPA2P AJ15
B U31 NC#V30 NC#W24 W23 TX0M_DPA2N B
NC#U31 NC#W23 AL17
TX1P_DPA1P AK16
U29 V27 TX1M_DPA1N
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 TX2P_DPA0P AJ17
TX2M_DPA0N
PCI EXPRESS INTERFACE
T30 U24 AL19

R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N
R29 T26 TMDP

P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
TXCBP_DPB3P AJ19
P30 T24 TXCBM_DPB3N
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 TX3P_DPB2P AK20
TX3M_DPB2N
N29 P27 AH22
M28 NC#N29 NC#P27 P26 TX4P_DPB1P AJ21
NC#M28 NC#P26 TX4M_DPB1N
AL23
M30 P24 TX5P_DPB0P AK22
L31 NC#M30 NC#P24 P23 TX5M_DPB0N
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
C NC#K30 NC#N26 C
@ 2160856030-A0_FCBGA631
CLOCK
CLK_PCIE_VGA AK30
<8> CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32
<8> CLK_PCIE_VGA# PCIE_REFCLKN +0.95VGS
CALIBRATION
Y22 VGA_PCIE_CALRP RV1 1 VGA@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 VGA@ 2 1K_0402_5% N10 AA22 VGA_PCIE_CALRN RV3 1 VGA@ 2 1K_0402_1% +3VGS
TEST_PG PCIE_CALR_RX
For CRB reserved
PLTRST_VGA# AL27
PERSTB
5
@
VCC
@ 2160856030-A0_FCBGA631 PLT_RST# 1 RV167
IN1 4 DGPU_PW ROK_R 1 2
OUT DGPU_PW ROK <48>
2
GND
<48,9> DGPU_PW RGD IN2 0_0402_5%
1
RV56
3
+3VGS UV11 100K_0402_5%
MC74VHC1G08DFT2G_SC70-5 @
@
2
5
VCC
D D
1
<36,9> PLT_RST# IN1 4 PLTRST_VGA#
2 OUT
GND
<10,9> DGPU_HOLD_RST# IN2
www.vinafix.vn
1
RV52
3
UV8 100K_0402_5%
MC74VHC1G08DFT2G_SC70-5 VGA@ Title
VGA@
Issued Date 2013/09/25 Deciphered Date 2016/09/25
PCIE/LVDS
2
Custom 1.0
Date:
ZSWAA/ZCWAA
Monday, February 10, 2014
LA-B301P
Sheet 18 of 52
1 2 3 4 5
1 2 3 4 5
UV1B
+3VGS
DBG_DATA[12:16]
Available on Jet/Sun
only, NC balls on Topaz. AF2 +3VGS +3VGS +3VGS +1.8VGS
NC#AF2 AF4
NC#AF4
1 N9 AG3 2
TV3 DBG_DATA16 NC#AG3
2
1 L9 AG5 CV166 2 JET@
TV4 DBG_DATA15 NC#AG5
1 AE9 DPA RV71 RV72
6 1 TV5 1 Y11 DBG_DATA14 AH3
VGA_SMB_DA2 0.1U_0402_10V7K 10K_0402_5% 10K_0402_5% CV170
<36,8> EC_SMB_DA2 TV6 1 AE8 DBG_DATA13 NC#AH3 AH1 1
JET@ @ JET@ 0.1U_0402_10V7K
TV7 DBG_DATA12 NC#AH1 1
1 AD9
TV8
1
QV1A 1 AC10 DBG_DATA11 AK3 JET@
TV1 DBG_DATA10 NC#AK3 UV9
5
2N7002DW-T/R7_SOT363-6 1 AD7 AK1 JET@
TV9 1 AC8 DBG_DATA9 NC#AK1 1 8
VGA@ DVO JET@ 33_0402_5% 33_0402_5%
3 4 TV2 1 AC7 DBG_DATA8 AK5 1 2 2 VCCA VCCB 7 1 2
VGA_SMB_CK2 GPU_VID3 RV75 GPU_VID3_GPIO_15 RV77 SVI2_SVD SVI2_SVD <48>
<36,8> EC_SMB_CK2 TV10 DBG_DATA7 NC#AK5 A1 B1
A 1 AB9 AM3 GPU_VID1 RV76 1 2 GPU_VID1_GPIO_20 3 6 RV78 1 2 SVI2_SVC A
TV11 DBG_DATA6 NC#AM3 A2 B2 SVI2_SVC <48>
QV1B 1 AB8 JET@ 33_0402_5% DIR 5 4
TV12 DBG_DATA5 DIR GND
2N7002DW-T/R7_SOT363-6 1 AB7 AK6 33_0402_5%JET@
TV13 DBG_DATA4 NC#AK6
2
VGA@ 1 AB4 AM5 SN74LVC2T45DCTR_SM8
TV14 1 AB2 DBG_DATA3 NC#AM5
TV15 DPB
1 Y8 DBG_DATA2 AJ7
TV16 DBG_DATA1 NC#AJ7
1 Y7 AH6 RV73 RV74
TV17 DBG_DATA0 NC#AH6 10K_0402_5% 10K_0402_5%
1
AK8 JET@ @
+3VGS NC#AK8 AL7
NC#AL7
RP2 @ W6
1 8 JTAG_TRSTB V6 NC#W6
2 7 JTAG_TDI NC#V6 V4 JET@
3 6 JTAG_TMS AC6 NC#V4 U5 +3VGS 10K_0402_5% CV169 10U_0603_6.3V6M
4 5 JTAG_TCK AC5 NC#AC5 NC#U5 RV79 2 1 DIR 2 1
NC#AC6
NC#W3
W3 3.3V TO 1.8V LEVEL SHIF
10K_8P4R_5% AA5 V2 JET@ CV167
AA6 NC#AA5
NC#AA6 DPC
NC#V2 2 1 0.1U_0402_10V7K For JET/SUN to support SVI2 reaulator
Y4
NC#Y4
NC#W5
W5 JET@ DNI for TOPAZ
BP_0 U1 AA3 PLL_ANALOG_OUT
@ 1 FB_VDDCI W1 NC#U1 NC#AA3 Y2
TV25 NC#W1 NC#Y2 +1.8VGS +1.8VGS +VGA_CORE
BP_1 U3
NC#U3
1
RP1 Y6 J8
1 8 GPU_DOWN# @ 1 PLL_Analog_in AA1 NC#Y6 NC#J8 RV83
TV26 NC#AA1
2 7 VGA_SMB_CK2 16.2K_0402_1% VCCSENSE_VGA JET@ 1 RV161 2 0_0402_5%
2
3 6 VGA_SMB_DA2 TOPAZ@ VSSSENSE_VGA JET@ 1 RV160 2 0_0402_5%
+3VGS
4 5 RV84 RV87
2
10K_0402_5% 10K_0402_5%
47K_0804_8P4R_5% I2C TOPAZ@ @
VGA@
1
R1
R3 SCL FB_GND TOPAZ@ 1 RV158 2 0_0402_5%
+VGA_CORE SDA VSSSENSE_VGA <48>
SVI2_SVD FB_VDDC TOPAZ@ 1 RV159 2 0_0402_5%
VCCSENSE_VGA <48>
AM26 SVI2_SVC
R AK26
B GENERAL PURPOSE I/O B
U6 AVSSN#AK26
U10 GPIO_0 AL25
GPIO_1 G
2
T10 AJ25
U8 VGA_SMB_DA2 GPIO_2 AVSSN#AJ25
U7 VGA_SMB_CK2 SMBDATA
SMBCLK B
AH24 50 ohm trace for diffenent pair
(From <36>
EC)
T9 AG25 RV89 RV88
GPU_DOWN# GPIO_5_AC_BATT AVSSN#AG25
PCC_GPIO_6 T8 10K_0402_5% 10K_0402_5%
1
T7 GPIO_6 DAC1 AH26 @ TOPAZ@
P10 GPIO_7_BLON HSYNC AJ27 WAKE#
P4 GPIO_8_ROMSO VSYNC
P2 GPIO_9_ROMSI
GPIO_10_ROMSCK
1
N6 AD22 Pull down for
+VGA_CORE N5 GPIO_11 RSET RV163
GPIO_12 none OBFF design.
+1.8VGS N3 AG24 4.7K_0402_5%
RV82 2 TOPAZ@1 4.7K_0402_5% BP_0 GPU_VID3

Y9
N1
GPIO_13
GPIO_14_HPD2
AVDD
AVSSQ
AE22 VGA@ AMD SVI2 Master Interface
2
M4 GPIO_15_PWRCNTL_0 AE23
GPIO_16 VDD1DI Pin Name Type
RV81 2 TOPAZ@1 4.7K_0402_5% BP_1 @ R6
GPIO_17_THERMAL_INT VSS1DI
AD23 PD/PU Description
10K_0402_5% W10
RV8 1 2 GPIO19_CTF M2 GPIO_18 Serial VID clock.
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12 I/O Push-pull clock output for the SVI2 data bus;
P7 GPIO_20_PWRCNTL_1 CEC_1 GPIO_SVC
N8 GPIO_21 1.8 V PU driven by the GPU. Point-to-point connection to
GPIO_22_ROMCSB (VDD_GPIO18) the SVI2 voltage regulator controller.
AK10 AK12 TOPAZ@1 RV155 2 0_0402_5% SVI2_SVD
@ AM10 GPIO_29 RSVD#AK12 AL11 TOPAZ@1 RV156 2 0_0402_5% SVI2_SVT
GPIO_30 RSVD#AL11 SVI2_SVT <48>
1 RV162 2 CLK_REQ_VGA#_R N7 AJ11 TOPAZ@1 RV157 2 0_0402_5% SVI2_SVC
<8> CLK_REQ_VGA# CLKREQB RSVD#AJ11
0_0402_5% Serial VID data.
JTAG_TRSTB L6 Push-pull data output for the SVI2 data bus; driven
JTAG_TDI L5 JTAG_TRSTB Topaz SVI2 I/O by the GPU. Sets the voltage, power-state
JTAG_TCK L3 JTAG_TDI
JTAG_TCK 1.8 V indicator, load-line slope, and voltage offsets for
JTAG_TMS L1 AL13 GPIO_SVD (VDD_GPIO18) PD
TV22 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13 two voltage rails. Point-to-point connection to
TESTEN K7 JTAG_TDO GENLK_VSYNC the SVI2 voltage regulator controller.
AF24 TESTEN
+VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
RV53 1 JET@ 2 10K_0402_5% GPIO_28_FDO AB13 SWAPLOCKB Serial VID telemetry.
W8 GENERICA
C GENERICB Push-pull data input driven by the SVI2 voltage C
Enable MLPS: W9 I/O regulator controller. Continuously streams the
W7 GENERICC AC19
GENERICD PS_0 PS_0 <25> 1.8 V voltage and current telemetry information to the GPU.
- Install on Jet/Sun AD10 GPIO_SVT (VDD_GPIO18)
AJ9 GENERICE AD19 Also provides and indication when positive voltage
- DNI for Topaz @
1 AL9 NC#AJ9 PS_1 PS_1 <25>
transitions are complete (VOTFC).
TV27 NC#AL9 AE17 PS_2 <25>
AC14 PS_2
1 PX_EN AB16 HPD1 AE20
TV23 PX_EN PS_3 PS_3 <25>
Add test point on
PX_EN for debug. AE19
AC16 TS_A
+3VGS DBG_VREFG
Enable JTAG access +3VGS
TSVDD Ref.CRB Design
DDC/AUX
VGA@ 2 1M_0402_5%
2
2
120ohm 0 1 PLL/CLOCK DDC1CLK
AE6 RV10 1
RV9 AE5 RV91
5.11K_0402_5%
0.1u 0 1 DDC1DATA 10K_0402_5%
AD2 YV1 VGA@ TOPAZ@
@ 1u 1 1 AUX1P AD4 +VGA_CORE 4 3 XTALOUT
NC OSC
1
1
10u 0 1 AUX1N
TESTEN AC11 XTALIN 1 2 RV90
DDC2CLK AC13 OSC NC 1 2
2 2 PCC_GPIO_6 OCP_L
DDC2DATA 27MHZ 10PF +-20PPM X3G027000DA1H OCP_L <48>
2
XTALIN AM28 AD13 CV9 CV10 1K_0402_5%
XTALOUT AK28 XTALIN AUX2P AD11 15P_0402_50V8J 15P_0402_50V8J CVT90 TOPAZ@
XTALOUT AUX2N
2
VGA@ 1 1 VGA@ 0.1U_0402_10V7K

RV11 RV23 1 @ 2 10K_0402_5% XO_IN AC22 AD20 FB_GND TOPAZ@ 1 Peak Current Control (PCC) CKT
RV24 1 @ 2 10K_0402_5% XO_IN2 AB22 XO_IN NC#AD20 AC20 FB_VDDC
1K_0402_5%
VGA@
XO_IN2 NC#AC20 Reversed (Topaz only)
AE16
1
NC#AE16 AD16
Reserved signal, for NC#AD16
normal ASIC operation. SEYMOUR/FutureASIC AC1
T4 DDCVGACLK AC3
T2 DPLUS THERMAL DDCVGADATA
On-die thermal sensor power. DMINUS
D +1.8VGS +TSVDD D
VGA@ LV1 (1.8V@13mA TSVDD) GPIO_28_FDO R5
1 2 +TSVDD AD17 GPIO28_FDO
BLM15BD121SN1D_0402 AC17 TSVDD
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
www.vinafix.vn
TSVSS
CV11
CV12
CV13
1 1 1
@ 2160856030-A0_FCBGA631
2 2 2
@
@
VGA@
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2013/09/25 Deciphered Date 2016/09/25 JET_MSIC
Custom 1.0
1 2 3 4 5
1 2 3 4 5
UV1E
UV1G
+3VS to +3VGS (25mA) AA27
DP POWER NC/DP POWER
AB24 GND
AG15 AE11 AB32 GND
AG16 DP_VDDR#AG15 NC#AE11 AF11 AC24 GND
+3VGS +1.8VGS AF16 DP_VDDR#AG16 NC#AF11 AE13 AC26 GND AB10
+3VS AG17 DP_VDDR#AF16 NC#AE13 AF13 AC27 GND GND AB15
+3VALW AG18 DP_VDDR#AG17 NC#AF13 AG8 AD25 GND GND AB6
DP_VDDR#AG18 NC#AG8 GND GND
2
VGA@ AG19 AG10 AD32 AC9
A
RV20 1.8V@40mA AF14 DP_VDDR#AG19 NC#AG10 AE27 GND GND AD6
A
470_0805_5% DP_VDDR#AF14 AF32 GND GND AD8

GND GND
2
VGA@ 2@ AG27 AE7
AH32 GND GND AG12
RV22 CV18 Vgs=-4.5V,Id=3A,Rds<97mohm
CV20
CV21
3 1
100K_0402_5% 0.1U_0402_16V7K K28 GND GND AH10

1 1 GND GND
VGA@ +0.95VGS AG20 AF6 K32 AH28
VGA@ RV21 1 AG21 DP_VDDC#AG20 NC#AF6 AF7 L27 GND GND B10
AO3413_SOT23
1
DP_VDDC#AG21 NC#AF7 GND GND
3
S
QV2B 47K_0402_5% AF22 AF8 M32 B12
10U_0603_6.3V6M
1U_0402_6.3V4Z
2N7002DW -T/R7_SOT363-6 5 PXS_PW REN# 1 2 2
G 2 2 AG22 DP_VDDC#AF22 NC#AF8 AF9 N25 GND GND B14
0.95V@32mA AD14 DP_VDDC#AG22 NC#AF9 N27 GND GND B16
VGA@
VGA@
QV3 +3VGS DP_VDDC#AD14 P25 GND GND B18
CV19
D
2
0.01U_0402_25V7K
4
1
VGA@ P32 GND GND B20
R27 GND GND B22
CV22
CV23
2N7002DW-T/R7_SOT363-6
GND GND
6
VGA@ 1 1 AG14 AE1 T25 B24
1 AH14 DP_VSSR NC#AE1 AE3 T32 GND GND B26
VGA@
QV2A
AM14 DP_VSSR NC#AE3 AG1 U25 GND GND B6
PXS_PW REN 2 AM16 DP_VSSR NC#AG1 AG6 U27 GND GND B8
0.1U_0402_10V6K
1U_0402_6.3V4Z
<10,45,48,9> PXS_PW REN 2 2 DP_VSSR NC#AG6 GND GND
AM18 AH5 V32 C1
AF23 DP_VSSR NC#AH5 AF10 W25 GND GND C32
VGA@
VGA@
1
AG23 DP_VSSR NC#AF10 AG9 W26 GND GND E28

AM20 DP_VSSR NC#AG9 AH8 W27 GND GND F10
AM22 DP_VSSR NC#AH8 AM6 Y25 GND GND F12
AM24 DP_VSSR NC#AM6 AM8 Y32 GND GND F14
AF19 DP_VSSR NC#AM8 AG7 GND GND F16
AF20 DP_VSSR NC#AG7 AG11 GND F18
AE14 DP_VSSR NC#AG11 GND F2
DP_VSSR GND F20
M6 GND F22
B N13 GND GND F24 B
AF17 AE10 N16 GND GND F26
DPAB_CALR NC#AE10 N18 GND GND F6
N21 GND GND
GND F8
P6 GND GND G10
@ 2160856030-A0_FCBGA631 P9 GND GND G27
+1.35V to +1.35VGS (6.5A) R12
R15
GND
GND
GND
GND
G31
G8
R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
+1.35V +1.35VGS T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
VGA@ U17 GND GND K2
1 GND GND
AO4354_SOIC-8 QV5 CV171 U20 K22
8 1 VGA@ U9 GND GND K6
470_0805_5%
GND GND
2
7 2 1U_0402_6.3V6K V13
6 3 2 RV164 V16 GND
5 VGA@ V18 GND
Y10 GND
Y15 GND
4
RV165 Y17 GND

1 VGA@ 2 Y20 GND
B+ GND
1 220K_0402_5% R11 A32
GND VSS_MECH
1
VGA@ T11 AM1

0.1U_0402_25V6
RV166 VGA@ AA11 GND VSS_MECH AM32

C CV174 820K_0402_5% QV4A M12 GND VSS_MECH C
VGA@ 2 5 PXS_PW REN# 2 2N7002DW -T/R7_SOT363-6 N11 GND
QV4B V11 GND
2
2N7002DW -T/R7_SOT363-6 GND

4
VGA@
@ 2160856030-A0_FCBGA631
D D
www.vinafix.vn
Title
Size
JET_Power/GND
Document Number Rev
Custom 1.0
Date:
ZSWAA/ZCWAASheet
LA-B301P
20 of 52
1 2 3 4 5
1 2 3 4 5
PCIE_PVDD Jet CRB Design PCIE_VDDC/BIF_VDDC Jet CRB Design

1u 1 1 1u 6 6
10u 1 1 10u 1 1
A
VDDR1 Jet CRB Design UV1D +1.8VGS A
0.01u 1 1 AM30 (PCIE_PVDD: 1.8V@100mA)
+1.35VGS
0.1u 1 1 MEM I/O PCIE_PVDD
PCIE
CV39
CV40
(VDDR1: 1.35V@2A) H13 AB23
2.2u 5 5 H16 VDDR1 NC#AB23 AC23
1 1
VDDR1 NC#AC23
CV31
CV33
CV32
CV34
CV35
CV36
CV37
CV38
10u 1 1 H19 AD24
0.01U_0402_16V7K
0.1U_0402_10V6K
J10 VDDR1 NC#AD24 AE24
10U_0603_6.3V6M
1U_0402_6.3V4Z
2 1 1 1 1 1 1 1 VDDR1 NC#AE24 2 2
J23 AE25
VDDR1 NC#AE25
VGA@
VGA@
J24 AE26
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
2.2U_0402_6.3V5M
1 2 2 2 2 2 2 2 VDDR1 NC#AF25
VGA@
VGA@
K10 AG26
VDDR1 NC#AG26
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
K23
VDD_CT Jet CRB Design K24 VDDR1
VDDR1
1u 1 1 K9
L11 VDDR1 PCIE_VDDC
L23
L24
L12 VDDR1 PCIE_VDDC L25
L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22
VDDR3 Jet CRB Design L22 VDDR1 PCIE_VDDC N23 (PCIE_VDDC: 0.95V@1A)
VDDR1 PCIE_VDDC N24
PCIE_VDDC
1u 1 1 PCIE_VDDC
R22
CV41
CV42
CV43
CV44
CV45
CV46
CV52
T22
+1.8VGS LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1 1
V22
(VDDCT: 1.8V@13mA) AA20 PCIE_VDDC
AA21 VDD_CT
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDD_CT 2 2 2 2 2 2 2
CV47
AB20 AA15
MPLL_PVDD Jet CRB Design VDD_CT CORE VDDC
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
B 1 AB21 N15 B
VDD_CT VDDC
1u 1 1 +3VGS VDDC
N17
R13
10u 2 2 I/O VDDC R16
1U_0402_6.3V4Z
2 (VDDR3: 3V@25mA) AA17 VDDC R18
VDDR3 VDDC
VGA@
AA18 Y21
VDDR3 VDDC
CV48
AB17 T12
AB18 VDDR3 VDDC T15
1 VDDR3 VDDC T17
SPLL_PVDD Jet CRB Design V12 VDDC T20
VDDR4 VDDC
1u 1 1 Y12 U13
1U_0402_6.3V4Z
2 U12 VDDR4 VDDC U16 (Topaz XT VDDC: TBD@19.5A) +VGA_CORE
10u 1 1 VDDR4 VDDC
VGA@
U18
VDDC V21 (Jet Pro VDDC: 0.800V to 1.075V@18A)
VDDC V15
VDDC V17
VDDC V20 Topaz XT (TDP 18W/DDR3): VDDC + VDDCI (Merged)@24A
VDDC
POWER
Y13
SPLL_VDDC Jet CRB Design VDDC Y16 Jet Pro (TDP 18W/DDR3): VDDC + VDDCI (Merged)@21A
VDDC
0.1u 1 1 VDDC
Y18
AA12
1u 1 1 VDDC
VDDC
M11
N12
VDDC U11
VDDC
PLL
+0.95VGS
C C
R21
+1.8VGS BIF_VDDC U21 (BIF_VDDC: 0.95V@0.8A)
LV2 VGA@ BIF_VDDC
1 2 (MPLL_PVDD: 1.8V@90mA) +MPLL_PVDD L8
MPLL_PVDD
CV49
CV50
CV51
MBK1608221YZF_2P
+VGA_CORE
1 1 1 ISOLATED
+1.8VGS
LV3 VGA@
CORE I/O
M13 (Jet Pro VDDCI: 0.95V GDDR5@1125MHz 4.5A)
1 2 (SPLL_PVDD: 1.8V@75mA ) H7 VDDCI M15
10U_0603_6.3V6M
10U_0603_6.3V6M
+SPLL_PVDD
1U_0402_6.3V4Z
2 2 2 SPLL_PVDD VDDCI
CV53
CV54
BLM15BD121SN1D_0402 M16
VDDCI
VGA@
VGA@
VGA@
1 1 M17
+0.95VGS VDDCI M18
LV4 VGA@ VDDCI M20
1 2 (SPLL_VDDC: 0.95V@100mA ) H8 VDDCI M21
10U_0603_6.3V6M
+SPLL_VDDC
1U_0402_6.3V4Z
2 2 BLM15BD121SN1D_0402 SPLL_VDDC VDDCI N20

VDDCI
VGA@
VGA@
J7
SPLL_PVSS
CV55
CV56
1 1
@ 2160856030-A0_FCBGA631
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2
VGA@
VGA@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL JET_Power
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ZSWAA/ZCWAA LA-B301P
www.vinafix.vn
1 2 3 4 5
1 2 3 4 5
UV1C
MDA[63..0] GDDR5/DDR3 GDDR5/DDR3

<23,24> MDA[63..0]
MDA0 K27 K17 MAA0
MAA[15..0] MDA1 J29 DQA0_0 MAA0_0/MAA_0 J20 MAA1
<23,24> MAA[15..0] DQA0_1 MAA0_1/MAA_1
MDA2 H30 H23 MAA2
DQMA[7..0] MDA3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA3
<23,24> DQMA[7..0] DQA0_3 MAA0_3/MAA_3
MDA4 G29 G24 MAA4
QSA[7..0] MDA5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA5
<23,24> QSA[7..0] DQA0_5 MAA0_5/MAA_5
MDA6 F32 J19 MAA6
QSA#[7..0] MDA7 F30 DQA0_6 MAA0_6/MAA_6 K19 MAA7
A <23,24> QSA#[7..0] A
MDA8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA13
MDA9 F27 DQA0_8 MAA0_8/MAA_13 L17 MAA15
MDA10 A28 DQA0_9 MAA0_9/MAA_15
MDA11 C28 DQA0_10 J14 MAA8
MDA12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA9
MDA13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA10
MDA14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA11
Place close to GPU (within 25mm) MDA15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA12
MDA16 A25 DQA0_15 MAA1_4/MAA_12 G11 A_BA2
DQA0_16 MAA1_5/MAA_BA2 A_BA2 <23,24>
MDA17 C25 J16 A_BA0
+1.35VGS +1.35VGS DQA0_17 MAA1_6/MAA_BA0 A_BA0 <23,24>
MDA18 E25 L15 A_BA1
DQA0_18 MAA1_7/MAA_BA1 A_BA1 <23,24>
MDA19 D24 G14 MAA14
MDA20 E23 DQA0_19 MAA1_8/MAA_14 L16
MEMORY INTERFACE
MDA21 F23 DQA0_20 MAA1_9/RSVD
DQA0_21
1
1
MDA22 D22 E32 DQMA0
VGA@ VGA@ MDA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 DQMA1
RV26 RV27 MDA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 DQMA2
40.2_0402_1% 40.2_0402_1% MDA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 DQMA3
MDA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 DQMA4
2
2
MDA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 DQMA5
+MVREFDA +MVREFSA MDA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 DQMA6
MDA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 DQMA7
MDA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
DQA0_30
1
1
1 1 MDA31 C17 H28 QSA0
VGA@ VGA@ VGA@ VGA@ MDA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 QSA1
RV28 CV57 RV29 CV58 MDA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 QSA2
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z MDA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 QSA3
2 2 MDA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 QSA4
2
2
B MDA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 QSA5 B
MDA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 QSA6
MDA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 QSA7
MDA39 C13 DQA1_6 EDCA1_3/QSA1_3
MDA40 E11 DQA1_7 H27 QSA#0
MDA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 QSA#1
MDA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 QSA#2
MDA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 QSA#3
MDA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 QSA#4
MDA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 QSA#5
MDA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 QSA#6
MDA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 QSA#7
Place all these components very close to GPU (within 25mm) MDA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
and keep all components close to each other. MDA49 A7 DQA1_16 L18 ODTA0
DQA1_17 ADBIA0/ODTA0 ODTA0 <23>
MDA50 C7 K16 ODTA1
DQA1_18 ADBIA1/ODTA1 ODTA1 <24>
VGA@ VGA@ MDA51 F7
RV30 RV31 MDA52 A5 DQA1_19 H26 CLKA0
DQA1_20 CLKA0 CLKA0 <23>
49.9_0402_1% 10_0402_1% MDA53 E5 H25 CLKA#0
DQA1_21 CLKA0B CLKA#0 <23>
1 2 2 1 VRAM_RST#_R MDA54 C3
<23,24> VRAM_RST# DQA1_22
MDA55 E1 G9 CLKA1
DQA1_23 CLKA1 CLKA1 <24>
MDA56 G7 H9 CLKA#1
DQA1_24 CLKA1B CLKA#1 <24>
1
1 1 MDA57 G6
VGA@ VGA@ @ MDA58 G1 DQA1_25 G22 RASA#0
DQA1_26 RASA0B RASA#0 <23>
CV59 RV32 CV128 MDA59 G3 G17 RASA#1
120P_0402_50V8J DQA1_27 RASA1B RASA#1 <24>
5.1K_0402_1% 68P_0402_50V8J MDA60 J6
2 2 DNI MDA61 J1 DQA1_28 G19 CASA#0
CASA#0 <23>
2
MDA62 J3 DQA1_29 CASA0B G16 CASA#1

DQA1_30 CASA1B CASA#1 <24>
MDA63 J5
DQA1_31 H22 CSA#0
C CSA0B_0 CSA#0 <23> C
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 CSA#1
CSA1B_0 CSA#1 <24>
J25 K13
RV33 1 VGA@ 2 120_0402_1% MEM_CALRP0 K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 CKEA0
Route 50ohms single-ended/8mil trace width CKEA0 J17 CKEA1
CKEA0 <23>
CKEA1 CKEA1 <24>
G25 W EA#0
WEA0B W EA#0 <23>
VRAM_RST#_R L10 H10 W EA#1
DRAM_RST WEA1B W EA#1 <24>
RV34 @ 1 2 51.1_0402_1% CLKTESTA_R CV60 @1 2 0.1U_0402_16V4Z CLKTESTA K8
RV35 @ 1 2 51.1_0402_1% CLKTESTB_R CV61 @1 2 CLKTESTB L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short @ 2160856030-A0_FCBGA631

debug only, for clock observation,if not need, DNI.
D D
www.vinafix.vn
Title
Size Document Number
MEM IF Rev
Custom 1.0
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits <Channel A0>

MDA[63..0]
<22,24> MDA[63..0]
MAA[15..0]
<22,24> MAA[15..0]
DQMA[7..0]
+1.35VGS <22,24> DQMA[7..0] +1.35VGS
<22,24> QSA[7..0]
QSA[7..0]
Channel A0, Data Group 0
1
1
A QSA#[7..0] A
VGA@
<22,24> QSA#[7..0]
VGA@ MDA0
RV36 RV37
4.99K_0402_1% UV4 4.99K_0402_1% UV5 MDA1
MDA2
2
2
+VREFC_A1A M8 E3 MDA16 +VREFC_A2A M8 E3 MDA30
H1 VREFCA DQL0 F7 MDA23 H1 VREFCA DQL0 F7 MDA27
VREFDQ DQL1 F2 MDA21 VREFDQ DQL1 F2 MDA31 MDA3
DQL2 DQL2
1
1
MAA0 N3 F8 MDA22 MAA0 N3 F8 MDA24
VGA@
1
VGA@ MAA1 P7 A0 DQL3 H3 MDA18 Data Group 2 VGA@
1
VGA@ MAA1 P7 A0 DQL3 H3 MDA29 Data Group 3 MDA4
RV39 CV62 MAA2 P3 A1 DQL4 H8 MDA19 RV38 CV63 MAA2 P3 A1 DQL4 H8 MDA26
4.99K_0402_1% 0.1U_0402_10V6K MAA3 N2 A2 DQL5 G2 MDA17 4.99K_0402_1% 0.1U_0402_10V6K MAA3 N2 A2 DQL5 G2 MDA28 MDA5
2 MAA4 P8 A3 DQL6 H7 MDA20 2 MAA4 P8 A3 DQL6 H7 MDA25
MDA6
2
2
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5
MAA7 R2 A6 D7 MDA5 MAA7 R2 A6 D7 MDA11 MDA7
MAA8 T8 A7 DQU0 C3 MDA3 MAA8 T8 A7 DQU0 C3 MDA9
MAA9 R3 A8 DQU1 C8 MDA4 MAA9 R3 A8 DQU1 C8 MDA13 DQMA0
MAA10 L7 A9 DQU2 C2 MDA1 MAA10 L7 A9 DQU2 C2 MDA15
MAA11 R7 A10/AP DQU3 A7 MDA6 Data Group 0 MAA11 R7 A10/AP DQU3 A7 MDA10 Data Group 1 QSA0
MAA12 N7 A11 DQU4 A2 MDA0 MAA12 N7 A11 DQU4 A2 MDA12
MAA13 T3 A12 DQU5 B8 MDA7 MAA13 T3 A12 DQU5 B8 MDA8 QSA#0
MAA14 T7 A13 DQU6 A3 MDA2 MAA14 T7 A13 DQU6 A3 MDA14
MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS
A_BA0 M2 B2 A_BA0 M2 B2
<22,24> A_BA0 A_BA1 N8 BA0 VDD D9 A_BA1 N8 BA0 VDD D9 MDA8
<22,24> A_BA1 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7
<22,24> A_BA2 BA2 VDD K2 BA2 VDD K2 MDA9
VDD K8 VDD K8
VDD N1 VDD N1 MDA10
B CLKA0 J7 VDD N9 CLKA0 J7 VDD N9 B
<22> CLKA0 CLKA#0 K7 CK VDD R1 CLKA#0 K7 CK VDD R1 MDA11
<22> CLKA#0 CKEA0 K9 CK VDD R9 CKEA0 K9 CK VDD R9
<22> CKEA0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS MDA12
ODTA0 K1 A1 ODTA0 K1 A1 MDA13
<22> ODTA0 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CSA#0 CLKA0 CSA#0
<22> CSA#0
RASA#0 J3 CS/CS0 VDDQ C1 CLKA#0 RASA#0 J3 CS/CS0 VDDQ C1 MDA14
<22> RASA#0 CASA#0 K3 RAS VDDQ C9 CASA#0 K3 RAS VDDQ C9
<22> CASA#0 WEA#0 L3 CAS VDDQ D2 WEA#0 L3 CAS VDDQ D2 MDA15
<22> WEA#0 WE VDDQ WE VDDQ
1
E9 E9
VDDQ F1 RV42 RV43 VDDQ F1 DQMA1
QSA2 F3 VDDQ H2 40.2_0402_1% 40.2_0402_1% QSA3 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 VGA@ VGA@ QSA1 C7 DQSL VDDQ H9 QSA1
DQSU VDDQ DQSU VDDQ
QSA#1
2
DQMA2 E7 A9 DQMA3 E7 A9
DQMA0 D3 DML VSS B3 DQMA1 D3 DML VSS B3
DMU VSS
VSS
E1
G8
1
VGA@
DMU VSS
VSS
E1
G8
QSA#2 G3 VSS J2 CV64 QSA#3 G3 VSS J2
QSA#0 B7 DQSL VSS J8 0.01U_0402_25V7K QSA#1 B7 DQSL VSS J8 MDA16
DQSU VSS M1 2 DQSU VSS M1
VSS M9 VSS M9 MDA17
VSS P1 VSS P1
T2 VSS P9 VRAM_RST# T2 VSS P9 MDA18
<22,24> VRAM_RST# RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 MDA19
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
MDA20
1
1
J1 B1 J1 B1
VGA@ L1 NC/ODT1 VSSQ B9 VGA@ L1 NC/ODT1 VSSQ B9 MDA21
C RV40 J9 NC/CS1 VSSQ D1 RV41 J9 NC/CS1 VSSQ D1 C
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 MDA22
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
MDA23
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 DQMA2
VSSQ G9 VSSQ G9
VSSQ VSSQ QSA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 QSA#2
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@
+1.35VGS +1.35VGS +1.35VGS
MDA24
MDA25
CV179
MDA26
CV70
CV71
CV72
CV73
CV74
CV85
CV86
CV87
CV88
CV89
1 1 1 1 1 1 1 1 1 1 1 MDA27
MDA28
2 2 2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
MDA29
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
MDA30
MDA31
DQMA3
D D
QSA3
Need closed to UV4 side Need closed to UV5 side QSA#3
www.vinafix.vn
Title
Size
VRAM A Lower
Document Number Rev
Custom 1.0
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits <Channel A1>

MDA[63..0]
<22,23> MDA[63..0]
MAA[15..0]
<22,23> MAA[15..0]
DQMA[7..0]
+1.35VGS <22,23> DQMA[7..0]
QSA[7..0] +1.35VGS
<22,23> QSA[7..0]

1
QSA#[7..0]
<22,23> QSA#[7..0]
1
A VGA@ A
RV44 VGA@
4.99K_0402_1% UV6 RV45 MDA32
4.99K_0402_1% UV7
MDA33
2
+VREFC_A3A M8 E3 MDA38
2
H1 VREFCA DQL0 F7 MDA36 +VREFC_A4A M8 E3 MDA51
VREFDQ DQL1 F2 MDA37 H1 VREFCA DQL0 F7 MDA52 MDA34
DQL2 VREFDQ DQL1
1
MAA0 N3 F8 MDA35 F2 MDA49

1 A0 DQL3 DQL2 MDA35
1
VGA@ VGA@ MAA1 P7
A1 DQL4
H3 MDA39 Data Group 4 1 MAA0 N3
A0 DQL3
F8 MDA54
RV46 CV95 MAA2 P3
A2 DQL5
H8 MDA32 VGA@ VGA@ MAA1 P7
A1 DQL4
H3 MDA50 Data Group 6 MDA36
4.99K_0402_1% 0.1U_0402_10V6K MAA3 N2 G2 MDA34 RV47 CV96 MAA2 P3 H8 MDA55
2 MAA4 P8 A3 DQL6 H7 MDA33 4.99K_0402_1% 0.1U_0402_10V6K MAA3 N2 A2 DQL5 G2 MDA48
MDA37
2
MAA5 P2 A4 DQL7 2 MAA4 P8 A3 DQL6 H7 MDA53
2
MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 D7 MDA42 MAA6 R8 A5 MDA38
MAA8 T8 A7 DQU0 C3 MDA44 MAA7 R2 A6 D7 MDA60
MAA9 R3 A8 DQU1 C8 MDA43 MAA8 T8 A7 DQU0 C3 MDA59 MDA39
MAA10 L7 A9 DQU2 C2 MDA45 MAA9 R3 A8 DQU1 C8 MDA63
MAA11 R7 A10/AP DQU3 A7 MDA41 Data Group 5 MAA10 L7 A9 DQU2 C2 MDA56 DQMA4
A11 DQU4 A10/AP DQU3
MAA12 N7
A12 DQU5
A2 MDA46 MAA11 R7
A11 DQU4
A7 MDA62 Data Group 7 QSA4
MAA13 T3 B8 MDA40 MAA12 N7 A2 MDA57
MAA14 T7 A13 DQU6 A3 MDA47 MAA13 T3 A12 DQU5 B8 MDA61
MAA15 M7 A14 DQU7 MAA14 T7 A13 DQU6 A3 MDA58 QSA#4
A15/BA3 +1.35VGS MAA15 M7 A14 DQU7
A15/BA3 +1.35VGS
<22,23>
<22,23>
A_BA0
A_BA1
A_BA0
A_BA1
M2
N8 BA0 VDD
B2
D9 A_BA0 M2 B2
A_BA2 M3 BA1 VDD G7 A_BA1 N8 BA0 VDD D9
<22,23> A_BA2 BA2 VDD K2 A_BA2 M3 BA1 VDD G7 MDA40
VDD K8 BA2 VDD K2
VDD N1 VDD K8 MDA41
CLKA1 J7 VDD N9 VDD N1
B <22> CLKA1 CLKA#1 K7 CK VDD R1 CLKA1 J7 VDD N9 MDA42 B
<22> CLKA#1 CKEA1 K9 CK VDD R9 CLKA#1 K7 CK VDD R1
<22> CKEA1 CKE/CKE0 VDD +1.35VGS CKEA1 K9 CK VDD R9 MDA43
CKE/CKE0 VDD +1.35VGS
ODTA1 K1 A1 MDA44
<22> ODTA1 CSA#1 L2 ODT/ODT0 VDDQ A8 ODTA1 K1 A1
<22> CSA#1
RASA#1 J3 CS/CS0 VDDQ C1 CSA#1 L2 ODT/ODT0 VDDQ A8 MDA45
<22> RASA#1 K3 RAS VDDQ C9 J3 CS/CS0 VDDQ C1
CASA#1 CLKA1 RASA#1
<22> CASA#1 WEA#1 L3 CAS VDDQ D2 CLKA#1 CASA#1 K3 RAS VDDQ C9 MDA46
<22> WEA#1 WE VDDQ E9 WEA#1 L3 CAS VDDQ D2
VDDQ F1 WE VDDQ E9 MDA47
VDDQ VDDQ
1
QSA4 F3 H2 F1
QSA5 C7 DQSL VDDQ H9 RV48 RV49 QSA6 F3 VDDQ H2 DQMA5
DQSU VDDQ 40.2_0402_1% 40.2_0402_1% QSA7 C7 DQSL VDDQ H9
VGA@ VGA@ DQSU VDDQ QSA5
DQMA4 E7 A9
QSA#5
2
DQMA5 D3 DML VSS B3 DQMA6 E7 A9
DMU VSS E1 DQMA7 D3 DML VSS B3
VSS G8 DMU VSS E1
QSA#4
QSA#5
G3
B7 DQSL
VSS
VSS
J2
J8
1
VGA@ QSA#6 G3
VSS
VSS
G8
J2
DQSU VSS M1 CV97 QSA#7 B7 DQSL VSS J8
VSS M9 0.01U_0402_25V7K DQSU VSS M1 MDA48
VSS P1 2 VSS M9
T2 VSS P9 VSS P1 MDA49
<22,23> VRAM_RST# RESET VSS T1 VRAM_RST# T2 VSS P9
L8 VSS T9 RESET VSS T1 MDA50
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS MDA51
1
J1 B1
NC/ODT1 VSSQ MDA52
1
VGA@ L1 B9 J1 B1
RV50 J9 NC/CS1 VSSQ D1 VGA@ L1 NC/ODT1 VSSQ B9
C 243_0402_1% L9 NC/CE1 VSSQ D8 RV51 J9 NC/CS1 VSSQ D1 MDA53 C
NCZQ1 VSSQ E2 243_0402_1% L9 NC/CE1 VSSQ D8
MDA54
2
VSSQ E8 NCZQ1 VSSQ E2
2
VSSQ F9 VSSQ E8
VSSQ G1 VSSQ F9 MDA55
VSSQ G9 VSSQ G1
VSSQ VSSQ G9 DQMA6
96-BALL VSSQ
SDRAM DDR3 96-BALL QSA6
H5TC2G63FFR-11C_FBGA96 SDRAM DDR3
X76@ H5TC2G63FFR-11C_FBGA96 QSA#6
X76@
+1.35VGS +1.35VGS
MDA56
MDA57
CV103
CV104
CV105
CV106
CV107
CV118
CV119
CV120
CV121
CV122
1 1 1 1 1 1 1 1 1 1 MDA58
MDA59
2 2 2 2 2 2 2 2 2 2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
MDA60
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
MDA61
MDA62
MDA63
D DQMA7 D
Need closed to UV6 side Need closed to UV7 side QSA7

QSA#7
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Title
Size
VRAM A Upper
Document Number Rev
Custom 1.0
1 2 3 4 5
1 2 3 4 5
MLPS
Pin Name Type PD/PU Description MLPS Bit Strap Name Legacy Description Settings
Power-state indicator.
Permits the voltage regulator to activate power-saving PS_0[1] ROM_CONFIG[0] If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,
I/O features. GPIO[13:11] 001
GPIO_0 PD-reset PS_0[2] ROM_CONFIG[1] ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current
3.3 V IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PS_0[3] ROM_CONFIG[2] databooks for details.
(VDDR3) PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag
PS_0[4] N/A GENLK_VSYNC Reserved for internal use only. Must be 1 at reset. 1
(Optional) An input which allows the system to
request a fastpower reduction by setting STRAP_BIF_ Re-defined strap to indicate PCIe GEN3 capability.
A
I/O GPIO_5_AC_BATT to low (0 V). The resulting state PS_1[1] GEN3_EN_A GPIO_2 1 = PCIe GEN3 supported. 0 A
GPIO_5_AC_BATT 3.3 V PD-reset transition may disturb the display momentarily. 0 = PCIe GEN3 not supported.
(VDDR3) Power reductions that are less time critical
should use the standard software methods in order
to prevent display disturbances. Determines whether or not the PCIe reference clock power
management capability is reported in the PCI configuration space
PS_1[2] STRAP_BIF_ (otherwise known as CLKREQB).
CLK_PM_EN GPIO_8 0 = The CLKREQB power management capability is disabled 0
Voltage control signals for the core (VDDC and VDDCI).
At reset, these signals will be inputs with weak 1 = The CLKREQB power management capability is enabled
GPIO_6 internal pulldown resistors.
The VBIOS can define all voltage-control signals to be
GPIO_15_PWRCNTL_0 I/O either 3.3-V or open-drain outputs (all signals must PS_1[3] N/A GENLK_CLK Reserved for internal use only. Must be 0 at reset.
PD-reset 0
3.3 V be the same type).
GPIO_20_PWRCNTL_1 (VDDR3) The output states (high/low) of these pins are
programmable for each AMD PowerPlay state when they Transmitter (Tx) power savings enable.
GPIO_29 PS_1[4] TX_PWRS_ENB GPIO_0 1
are used as voltage control signals. 0 = 50% Tx output swing.
GPIO_30 Note: GPIO_29 and GPIO_30 are only available on 28-nm 1 = Full Tx output swing.
ASICs, and are NC on earlier generation ASICs.
PCI EXPRESS transmitter, deemphasis enable.
PS_1[5] TX_DEEMPH_EN GPIO_1 0 = Tx deemphasis disabled. 1
I Serial-ROM output from ROM.
3.3 V General purpose I/O or open-drain output. 1 = Tx deemphasis enabled.
GPIO_8_ROMSO (VDDR3) PD-reset
Design: No use external VGA ROM, so use the test point.
PS_2[1] N/A N/A Reserved. 0
Serial-ROM input to ROM.
GPIO_9_ROMSI General purpose I/O or open-drain output.
PS_2[2] N/A N/A Reserved. 0
O Serial-ROM clock to ROM.
GPIO_10_ROMSCK 3.3 V General purpose I/O or open-drain output.
B
(VDDR3) PD-reset To enable the external BIOS ROM device. B
BIOS-ROM chip select. PS_2[3] BIOS_ROM_EN GPIO_22 0
0 = Disable the external BIOS ROM device.
Used to enable the ROM for ROM read and program 1 = Enable the external BIOS ROM device.
GPIO_22_ROMCSB operations.
Design: No use external VGA ROM, so use the test
points. VGA disable determines whether or not the card will be recognized as the
system's VGA controller.
PS_2[4] BIF_VGA_DIS GPIO_9 0 = VGA controller capacity enabled. 0
I/O Thermal monitor interrupt.
GPIO_17_THERMAL_INT 3.3 V PD-reset An input from an external temperature sensor (ALERTb). 1 = The device will not be recognized as the system’s VGA controller.
(VDDR3)
Critical temperature fault (CTF) (active high) will PS_2[5] N/A N/A Reserved. 0
output 3.3 V if the on-die temperature sensor exceeds
O a critical temperature so that the motherboard can
protect the ASIC from damage by removing power. PS_3[1] BOARD_CONFIG[0] Base on
GPIO_19_CTF 3.3 V PD-reset N/A Board configuration related strapping (such as memory ID).
The CTF setpoint is 109 by default, and is PS_3[2] BOARD_CONFIG[1] VRAM ID
(VDDR3) PS_3[3] BOARD_CONFIG[2]
programmed during ASIC initialization. See the
advisory for AMD PowerPlay states for more details.
PS_0[5] AUD_PORT_CONN_ Together with PS_0[5] form the three-bit strap option to indicate the number of
(Optional) Voltage control signal for the PS_3[4] PINSTRAP[0] audio-capable display outputs. In a given ASIC there are as many endpoints as
I/O memory-voltage regulator. PS_3[5] there are digital display outputs, though not all outputs are audio capable.
GPIO_21 3.3 V PD-reset AUD_PORT_CONN_ 111 = No usable endpoints.
Note: This signal must be low (0 V) at reset
(VDDR3) PINSTRAP[1] N/A 110 = One usable endpoint.
(failure to do so will prevent booting). 101 = Two usable endpoints.
AUD_PORT_CONN_ 100 = Three usable endpoints.
Disable MLPS: PU 10K ohm to 3.3V. PINSTRAP[2] 011 = Four usable endpoints. 111
I/O 010 = Five usable endpoints.
(Do not install for Mars)
GPIO_28_FDO 3.3 V PD-reset 001 = Six usable endpoints.
Enable MLPS: PD 10K ohm to GND. 000 = All endpoints are usable.
C (VDDR3) (Install for Mars) C
Supports the CLKREQB feature for saving power to turn

CLKREQB O on/off the REFCLK clock on the ASIC. Primary Memory Aperture Size
On/off regulator switch in AMD PowerXpress? (switchable MLPS Strap Requested at PCI Configuration
graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO Bits[5:4] Bits[3:1] Capacitor R_pu R_pd Size of the Primary ROM_CONFIG [2:0] MLPS configuration
PX_EN O PD mode). Memory Apertures
Low (0 V) switches the regulators on. (Default) PS_0[5:1] 11 001 NC 8.45K 2K
Bits[5:1] PU(1%) PD(1%) Cap
PX_EN is tri-state before internal TEST_PG is asserted 128 MB 000
and PERSTb is deasserted. xx000 NC 4.75k
PS_1[5:1] 11 000 NC NC 4.75K
256 MB 001 xx001 8.45k 2.00k
PS_2[5:1] 00 000 680 nF NC 4.75K

xx010 4.53k 2.00k
+1.8VGS PS_3[3:1]
64 MB 010 xx011 6.98k 4.99k
CV15
Memory ID P/N Vendor Configuration Size PS_3[5:1] 11 XXX NC X X
xx100 4.53k 4.99k
Reserved 011
1
TOPAZ@
0.01U_0402_16V7K X76@ @ @ VGA@
xx101 3.24k 5.62k
000 SA000068U40 Samsung K4W2G1646Q-BC1A 1G
RV12 RV13 RV14 RV15 512 MB Not supported xx110 3.40k 10.0k
4.53K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1%
001 SA00006H400 Hynix H5TC2G63FFR-11C 1G 00 for JET Mapping to VRAM type
xx111 4.75k NC
2
<19> PS_0 1 GB Not supported

<19> PS_1 10 for Topaz 00xxx 680nF
<19> PS_2 010 SA00005XB00 Micon MT41K128M16JT-107G:K 1G
<19> PS_3
2 GB Not supported 01xxx 82nF
1
D
011 SA000076P00 Samsung K4W4G1646D-BC1A 2G 10xxx 10nF D
@ 1 JET@ 1 @ 1 @ 1 X76@ VGA@ VGA@ VGA@ 4 GB Not supported
CV14 CV15 CV16 CV17 RV18 RV19 RV16 RV17
2K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
11xxx NC
100 SA00006E800 Hynix H5TC4G63AFR-11C 2G
0.01U_0402_16V7K
0.68U_0402_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2
www.vinafix.vn
101 SA000065D00 Micon MT41K256M16HA-107G:E 2G

Title
Issued Date 2013/09/25 Deciphered Date 2016/09/25 JET_MSIC
Custom 1.0
Date:
Sheet 25 of 52
1 2 3 4 5
5 4 3 2 1
Close to LT2 Close to Pin18 Close to LT3

Mode Configure
+3VS +3VS_RT
80mil +SWR_VDD +SWR_V12 ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
100mil 100mil EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 Rshort@ 2
RT1 0_0805_5% 1 1 1 1 1 1 1 1 1 EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
CT4
CT5
CT6
CT7
CT8
CT9
CT10
CT11
CT12
Default mode
2 2 2 2 2 2 2 2 2
Close to Pin3
+DP_V33 +3VS_RT +3VS_RT
LVDS@
10U_0603_6.3V6M
0.1U_0402_16V4Z
D 0.1U_0402_16V4Z D
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@
2
1 1 1 Close to Pin13 Close to
2
Pin27 Close to Pin7 RT12
CT1
CT2
CT3
RT4 LVDS@ 4.7K_0402_5%
@ 4.7K_0402_5%
2 2 2 +3VS_RT
1
UT2 MIIC_SDA MIIC_SCL
1
LVDS@ 19
TXEC+ LCD_TXCLK+ <27>
LVDS@ LVDS@ LVDS@ LT1 2 1 +DP_V33 40mil 3 20
LCD_TXCLK- <27>
DP_V33 TXEC-
2
FBMA-L11-201209-221LMA30T_0805
LVDS@ 100mil 13 21 RT6 RT7
SWR_VDD TXE2+ LCD_TXOUT2+ <27>
Power
100mil LT2 2 1 +SWR_VDD 40mil 18 22
LCD_TXOUT2- <27> LVDS@ 4.7K_0402_5% @ 4.7K_0402_5%
PVCC TXE2-
LVDS
FBMA-L11-201209-221LMA30T_0805
+SWR_V12 40mil 12 23 LCD_TL_TXOUT1+ PIN30 PIN31
1
11 SWR_LX TXE1+ 24 LCD_TL_TXOUT1-
40mil
SWR / LDO Mode select 40mil 27
7
SWR_VCCK
VCCK
TXE1-
25 LCD_TL_TXOUT0+
40mil DP_V12 TXE0+ 26 LCD_TL_TXOUT0-
TXE0-
LDO mode is adopted as default power regulator mode.
Also can implement SWR mode by add inductor. +3VS_RT
2
RTD2132R +LCD_VDD
1 LVDS@ 2 4.7K_0402_5%
H_EDP_AUXP_C_TL LCD_EDID_DATA_TL RT9
AUX_P
DP-IN
H_EDP_AUXN_C_TL 1 14 TL_INVT_PWM
AUX_N GPIO(PWM OUT) TL_INVT_PWM <27>
RT10 1 LVDS@ 2 4.7K_0402_5%
GPIO
15 80mil LCD_EDID_CLK_TL
H_EDP_TXP0_C_TL 5 GPIO(Panel_VCC) 16 PCH_PWM_TL
H_EDP_TXN0_C_TL 6 LANE0P GPIO(PWM IN) 17 ENBKL_TL 1 2 PCH_PWM_TL <9>
LANE0N GPIO(BL_EN) EC_ENBKL_R <36,9>
RT14 @ 0_0402_5%
9 LVDS 29 LCD_EDID_CLK_TL PCH_PWM_TL

<36> EC_SMB_CK3 10 CIICSCL1 MIICSCL1 28 LCD_EDID_DATA_TL
<36> EC_SMB_DA3 CIICSDA1 EDID MIICDA1
Other
1
C LVDS@ C
32 ROM 31 MIIC_SCL RT13
<27,9> H_EDP_HPD HPD MIICSCL0 30 MIIC_SDA 100K_0402_5%
8 MIICSDA0
4 DP_REXT 33
2
DP_GND GND
2
RT8 LVDS@ RTD2132R-VE-CG_QFN32_5X5
12K_0402_1%
LVDS@
1
Close to Pin8
+LCD_VDD
+LCD_VDD 80mil
1
2
RT113
IEDP@ CT13 100K_0402_5%
C476 1 2 0.1U_0402_10V6K H_EDP_AUXP_C_R 4.7U_0603_6.3V6K LVDS@
LVDS@ 1
2
IEDP@ RP4 LVDS@
C477 1 2 0.1U_0402_10V6K H_EDP_AUXN_C_R LCD_EDID_CLK_TL 1 8
LCD_EDID_CLK <27>
LCD_EDID_DATA_TL 2 7 Close to Panel conn.
LCD_EDID_DATA <27>
LVDS@ LCD_TL_TXOUT0- 3 6
LCD_TXOUT0- <27>
C478 1 2 0.1U_0402_10V6K H_EDP_AUXP_C_TL LCD_TL_TXOUT0+ 4 5
LCD_TXOUT0+ <27>
<5> H_EDP_AUXP
LVDS@ 0_0804_8P4R_5%
C479 1 2 0.1U_0402_10V6K H_EDP_AUXN_C_TL
<5> H_EDP_AUXN
LVDS@ RP5 IEDP@
B C480 1 2 0.1U_0402_10V6K H_EDP_TXP0_C_TL H_EDP_AUXP_C_R 1 8 B
<5> H_EDP_TXP0 2 7
H_EDP_AUXN_C_R
LVDS@ H_EDP_TXN0_C_R 3 6
C481 1 2 0.1U_0402_10V6K H_EDP_TXN0_C_TL H_EDP_TXP0_C_R 4 5 PIN15 PIN16 Accept voltage input (high level)
<5> H_EDP_TXN0
IEDP@ 0_0804_8P4R_5%
C482 1 2 0.1U_0402_10V6K H_EDP_TXP0_C_R 2132S TL_ENVDD 2132S 3.3V
IEDP@
C483 1 2 0.1U_0402_10V6K H_EDP_TXN0_C_R 2132R +LCD_VDD * 2132R 1.5~3.3V
* Version R internal Power Switch, can * Version R has internal level shifter, remove
Place co-lay Resistor back to back on TOP and BOT output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform
Different between 2132S and 2132R(N)
2132S 2132R(N)
IEDP@
C62 1 2 0.1U_0402_10V7K
<5> H_EDP_TXP1 LCD_TXOUT1+ <27> 1. Support SWR mode 1. Support LDO mode and SWR mode
C63
IEDP@
1 2 0.1U_0402_10V7K
2. Internal ROM
<5> H_EDP_TXN1 LCD_TXOUT1- <27>
3. Support LCD_VDD(internal Power switch)
LVDS@ 4. Integrates Level shifter
LCD_TL_TXOUT1+ R42 1 2 0_0402_5%
A A
LVDS@
LCD_TL_TXOUT1- R43 1 2 0_0402_5%
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LVDS Translator - RTD2132R(N)-CG
Custom 1.0
5 4 3 2 1
A B C D E
USB20_P5_R 1 Rshort@ 2
USB20_P5 <11>
R4280 0_0402_5%
4
DLW21HN900HQ2L_4P
3
LCD POWER CIRCUIT (For EDP panel only)
4 3
BTO : TOUCH_EMI@
1 2
1 2
L61 @TOUCH_EMI@
1 USB20_N5_R 1 Rshort@ 2
I rush=2A 1
USB20_N5 <11>
R4281 0_0402_5% W=80mils
+LCD_VDD +3VS
U1 IEDP@
1 Rshort@ 2 +LCD_VDD_R 1 5
OUT IN
EMI request - Close to JLVDS connector 1 R106 0_0805_5%
C4 2
@ GND IEDP@
1 Rshort@ 2 3 4 LCD_ENVDD_R 1 R15 2
OC EN LCD_ENVDD <9>
R11 0_0402_5% 4.7U_0603_6.3V6K 2 0_0402_5%
1
DLW21HN900HQ2L_4P SY6288C20AAC_SOT23-5 1
USB20_N7_R 4 3 SA000079400 C29
4 3 USB20_N7 <11>
R3 @
IEDP@ 0.1U_0402_25V6
USB20_P7_R 1 2 2
USB20_P7 <11>
2
1 2 100K_0402_5%
L62 @CAM_EMI@
1 Rshort@ 2
R9 0_0402_5%
Change L62 P/N from SM070003Y00 to SM070003K00
LVDS colay eDP cable Camera & MIC

D29 ESD@
Pin define will be change after ME ready USB20_P7_R 4 3 USB20_N7_R
2 4 3 2
+3VS
Camera
5 2
+3VS Vbus GND
20mils
JLVDS @
1 Rshort@ 2 +3VS_LVDS_CAM 1 2
1 2 LCD_EDID_CLK <26>
R432 0_0603_5% USB20_P7_R 3 4
3 4 LCD_EDID_DATA <26>
USB20_N7_R 5 6 INT_MIC_CLK
7 5 6 8 INT_MIC_DATA INT_MIC_CLK <35>
9 7 8 10 LED_PWM INT_MIC_DATA <35>
<26> LCD_TXOUT0+ 11 9 10 12 BKOFF#_R
<26> LCD_TXOUT0- 13 11 12 14 6 1
INT_MIC_DATA INT_MIC_CLK
<26> LCD_TXOUT1+ 15 13 14 16 H_EDP_HPD <26,9> 6 1
<26> LCD_TXOUT1- 15 16 +3VS
<26> LCD_TXOUT2+
17
17 18
18 SC300001400 close to LVDS conn.
19 20
<26> LCD_TXOUT2- 21 19 20 22
<26> LCD_TXCLK+ 21 22 +LCD_VDD Irush=1.5A 60mils
23 24
<26> LCD_TXCLK- 25 23 24 26
27 25 26 28 +5VS
29 27 28 30 JTOUCH @
29 30 +LCD_INV Irush=1.5A 60mils Touch 20mils
1 Rshort@ 2 +5VS_LVDS_TOUCH 1
31 32 R431 0_0603_5% USB20_N5_R 2 1
31 32 USB20_P5_R 3 2
E-T_3753K-F30N-07R BKOFF# 4 3
5 4
6 5
3 7 6 3
8 GND
GND
ACES_50208-00601-P01
Irush=1.5A 60mils B+
+LCD_INV
L63
2 1 D92 @ESD@
FBMA-L11-201209-221LMA30T_0805 6 3 USB20_N5_R
EMI@ I/O4 I/O2
+5VS
5 2
IEDP@ VDD GND
1 2
PCH_PWM_EDP <9>
D90 RB751V40_SC76-2
USB20_P5_R 4 1 BKOFF#
I/O3 I/O1
LED_PWM 1 2 AZC099-04S.R7G_SOT23-6
TL_INVT_PWM <26>
BKOFF#_R 1 2 1 Rshort@ 2 BKOFF# D91 RB751V40_SC76-2
BKOFF# <36>
D15 RB751V40_SC76-2 R436 0_0402_5% LVDS@ close to JTOUCH conn.
1
R434 R435
10K_0402_5% 47K_0402_5%
2
4 4
Change D15,D90,D91 P/N from
SCS0340L010 to SCS00003500
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for X code.

LVDS
Custom 1.0
A B C D E
A B C D E
PS8401
PS8201
HDMI TMDS BUS Choke

1 1
Colay Cap Colay Resistor
Componet close to Conn.

Impedance depend on platform design guide
ZZZ HDMI45@
HDMI Royalty
+HDMI_5V_OUT
RP3 HDMI@
HDMI W/Logo + HDCP
+3VS 1 8 HDMI_SCLK
2 7 HDMI_SDATA
3 6 UMA_HDMI_CLK
HDMI W/O Logo: RO0000001HM
4 5 UMA_HDMI_DATA +3VS +3VS HDMI W/Logo: RO0000002HM
2.2K_0804_8P4R_5% HDMI W/Logo + HDCP: RO0000003HM
please manually load
this virtual material to 45@ BOM
2
G
UMA_HDMI_CLK 3 1 HDMI_SCLK
<9> UMA_HDMI_CLK
2
2 2
D
Q18
BSH111_SOT23-3
UMA_HDMI_DATA 3 1 HDMI@ HDMI_SDATA
<9> UMA_HDMI_DATA
D
+HDMI_5V_OUT Q19
R145 BSH111_SOT23-3
HDMI_HPD_U 1 2 HDMI_HPD_C HDMI@
1K_0402_5% HDMI@
HDMI@ 2 2 1
+3VS
2
R186 C265 R571

5
U9 100K_0402_5% 0.1U_0402_10V7K 2.2K_0402_5%

HDMI@ HDMI@
HDMI POWER CIRCUIT
OE#
P
2 4 HDMI_HPD 1 HDMI_HPD
A Y HDMI_HPD <10,9>
1
G
74AHCT1G125GW_SOT353-5 VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m

HDMI@
Current Limit: TYP=0.8A ; MAX=1A
3
Change L8,L9,L10,L11 P/N

from SM070003Y00 to SM070003K00 +HDMI_5V_OUT
U16 HDMI@
1 5
DLW21HN900HQ2L_4P OUT IN +5VS
HDMI@
1 2 H_DVI_TXC+ 4 3 HDMI_R_CK+ 1 2
<5> H_HDMI_TXC+ 4 3 GND
C16 0.1U_0402_10V7K C259
HDMI@ HDMI@ 3 4
1 2 H_DVI_TXC- 1 2 HDMI_R_CK- 0.1U_0402_10V7K FLG EN
<5> H_HDMI_TXC- 1 2 2
C22 0.1U_0402_10V7K AP2151DWG-7_SOT25-5
3 L8 EMI@ SA00006H000 3
HDMI@ L9 EMI@
1 2 H_DVI_TXD0- 1 2 HDMI_R_D0-
<5> H_HDMI_TX0- 1 2
C24 0.1U_0402_10V7K
<5> H_HDMI_TX0+
HDMI@
1 2 H_DVI_TXD0+ 4
4 3
3 HDMI_R_D0+ HDMI Connector
C23 0.1U_0402_10V7K RP9 HDMI@
DLW21HN900HQ2L_4P HDMI_R_D0+ 1 8 JHDMI @
HDMI_R_D0- 2 7 HDMI_HPD_C 19
HDMI_R_CK+ 3 6 18 HP_DET
+HDMI_5V_OUT +5V
HDMI_R_CK- 4 5 17
HDMI_SDATA 16 DDC/CEC_GND
680_8P4R_5% HDMI_SCLK 15 SDA
14 SCL
HDMI@ DLW21HN900HQ2L_4P 13 Reserved
1 2 H_DVI_TXD1+ 4 3 HDMI_R_D1+ RP10 HDMI@ HDMI_R_CK- 12 CEC
<5> H_HDMI_TX1+ 4 3 HDMI_R_D2+ 1 8 11 CK-
C25 0.1U_0402_10V7K
HDMI@ HDMI_R_D2- 2 7 HDMI_R_CK+ 10 CK_shield
1 2 H_DVI_TXD1- 1 2 HDMI_R_D1- HDMI_R_D1+ 3 6 HDMI_R_D0- 9 CK+
<5> H_HDMI_TX1- 1 2 4 5 8 D0-
C26 0.1U_0402_10V7K HDMI_R_D1-
L10 EMI@ HDMI_R_D0+ 7 D0_shield
680_8P4R_5% HDMI_R_D1- 6 D0+
5 D1-
HDMI_R_D1+ 4 D1_shield 20
1
Q24 D 3 D1+ GND 21
HDMI_R_D2-
2 2 D2- GND 22
4
+5VS D2_shield GND 4
G HDMI@ HDMI_R_D2+ 1 23
HDMI@ L11 EMI@ D2+ GND
1 2 H_DVI_TXD2- 1 2 HDMI_R_D2- S 2N7002KW_SOT323-3 ACON_HMR2U-AK120C
3
<5> H_HDMI_TX2- 1 2
C28 0.1U_0402_10V7K
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HDMI@
1 2 H_DVI_TXD2+ 4 3 HDMI_R_D2+
<5> H_HDMI_TX2+ 4 3
C27 0.1U_0402_10V7K
DLW21HN900HQ2L_4P
Common CHOKE use 90ohm HDMI Conn.
1.0
A B C D E
5 4 3 2 1
+1.8VS_CRT +1.8VS_DAC
+3VS +3VS_6513 +1.8VS_CRT +1.8VS_RXVDD Close to Pin7
Close to Pin36 +1.8VS_CRT Close to Pin44 Close to Pin46 CRT@
Close to Pin25 1 2 5mil
1 Rshort@ 2 15mil 1 Rshort@ 2 5mil LD3 TAI-TECH FCM1608KF-600T05
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RD1 0_0603_5% LD2 0_0603_5% Rated current 500mA, DC 0.1ohm
CRT@
CRT@
D 15mil D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
CRT@
CRT@
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
@
CRT@
CRT@
CRT@
CRT@
1 1 1 1 1
CD13
CD14
CD16
CD15
1 1 1 1 1 1 1
@
@
CD8
CD9
CD10
CD11
CD12
2 2 2 2
CD1
CD3
CD4
CD2
CD5
CD6
CD7
2 2 2 2 2
2 2 2 2 2 2 2
Close to Pin24
Close to Pin13 Close to Pin31 Close to Pin10
Close to Pin14 Close to Pin12
+3VS_6513
+3VS
+1.8VS_CRT
ISPSCL_R +1.8VS_RXVDD
ISPSDA_R
4
3
2
1
CRT@
RPD1
5mil
5mil
5mil
5mil
1315mil
15mil
3515mil
15mil
3815mil
15mil
2.2K_0804_8P4R_5%
CRT@
5
6
7
8
48
36
39
12
14
44
46
UD1
1
2
PCSDA
+3VS_6513
DDCSCL
IVDD33
IVDD33
IVDDO
IVDDO
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DDCSDA
C
<9> H_DP_HPD 40 PCSCL C
HPD
1
45 1 2 CD17 0.1U_0402_16V4Z UMA_CRT_DATA

RD2 26 MCUVDDH
4.7K_0402_5% <5> H_DP1_C_P0 RX0P 5mil
27 CRT@ UMA_CRT_CLK
<5> H_DP1_C_N0 RX0N
CRT@
29 47
<5> H_DP1_C_P1
2
30 RX1P MCURSTN
<5> H_DP1_C_N1 RX1N
28 @ T1
RD3 2 @ 1 1M_0402_5% URDBG
+3VS
CD18 15 ISPSCL_R CRT@ 1 2 RD4 22_0402_5%
RD11 2 @ 1 100K_0402_5% CRT@ 0.1U_0402_16V7K ISPSCL 16 ISPSDA_R CRT@ 1 2 RD5 22_0402_5%
2 1 H_DDI1_AUXP_C 20 ISPSDA
<9> H_DDI1_AUXP RXAUXP
2 1 H_DDI1_AUXN_C 19 23 UMA_CRT_CLK_R CRT@ RD6 2 1 22_0402_5% UMA_CRT_CLK
<9> H_DDI1_AUXN RXAUXN VGADDCCLK UMA_CRT_CLK <30>
CRT@ CD19 21 UMA_CRT_DATA_R CRT@ RD7 2 1 22_0402_5% UMA_CRT_DATA UMA_CRT_DATA <30>
RD12 2 @ 1 100K_0402_5% 0.1U_0402_16V7K VGADDCSDA
+3VS
18 3
DCAUXP VSYNC UMA_CRT_VSYNC <30>
RD8 2 @ 1 1M_0402_5% 17 4
DCAUXN HSYNC UMA_CRT_HSYNC <30>
+1.8VS_CRT 5mil 25 10 +1.8VS_DAC

31 AVCC VDDC
AVCC 5mil
5mil
B
+1.8VS_CRT 5mil 22
PVCC
IT6513FN B
11
IORP UMA_CRT_R <30>
9
IOGP UMA_CRT_G <30>
+1.8VS_RXVDD 5mil 24
DVDD18 8
IOBP UMA_CRT_B <30>
41
NC/VGADETECT
8
7
6
5
RD9
5 RSET 1 2 100_0402_1% RPD2
32 RSET CRT@ RD10
+1.8VS_CRT 5mil ASPVCC 8mil 75_0804_8P4R_1%
1M_0402_5%
CRT@
7 +1.8VS_DAC XTALOUT_6513 @ XTALIN_6513
1
2
3
4
VDDA
8mil
CRT@ YD1
6 COMP 1 2 CD20 27MHZ_10PF_X3G027000BA1H-U
PCSDA 43 COMP 0.1U_0402_16V4Z Crystal
PCSDA 8mil
PCSCL 42 3 4
PCSCL 34 XTALIN_6513 OUT GND
XTALIN 33 XTALOUT_6513 2 1
XTALOUT GND IN
PWDNB
18P_0402_50V8J
1
@
18P_0402_50V8J
1
PAD
@ @
RPD2 CD21
2 CD22
150_0804_8P4R_1%
37
49
+3VS_6513 2
@
A A
CRT@
1 2
If there is a pull down 150 resister near the
CRT conn., please change RPD2 to 150 too .
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RD13 10K_0402_5%

Issued Date Title
Deciphered Date
DP-CRT_ITE IT6513FN
1.0
Date: Sheet 29 of 52
5 4 3 2 1
A B C D E
CRT CONNECTOR
1 1
<29> UMA_CRT_R L6 1 2 NBQ100505T-800Y_0402 CRT_R_L

CRT@EMI@
<29> UMA_CRT_G L12 1 2 NBQ100505T-800Y_0402 CRT_G_L
CRT@EMI@
<29> UMA_CRT_B L7 1 2 NBQ100505T-800Y_0402 CRT_B_L
CRT@EMI@
JCRT @
6
T102PAD 11
CRT@ CRT@ CRT@ CRT@ CRT@ CRT_R_L 1
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
CRT@
1 1 1 1 1 1 7
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 2
8 G 16
2 2 2 2 2 2 HSYNC 13 17
G
CRT_B_L 3
9
+HDMI_5V_OUT
VSYNC 14
T161PAD 4
10
CRT_DDC_CLK 15
5
USE HDMI POWER J-L_TNBNRACZZ013015
2 2
+HDMI_5V_OUT U49 CRT@ +HDMI_5V_OUT

1 8 1 2
VCC_SYNC BYP C18 0.22U_0402_16V7K
+3VS 2 3 CRT_R_L
VCC_VIDEO VIDEO1
2
+3VS 7 4 CRT_G_L R153 R159
VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%
CRT@ CRT@
<29> UMA_CRT_DATA UMA_CRT_DATA 10 5 CRT_B_L
1
DDC_IN1 VIDEO3
<29> UMA_CRT_CLK UMA_CRT_CLK 11 9 CRT_DDC_DAT

DDC_IN2 DDC_OUT1
3 UMA_CRT_VSYNC 13 12 CRT_DDC_CLK 3
<29> UMA_CRT_VSYNC SYNC_IN1 DDC_OUT2
R62 CRT@
UMA_CRT_HSYNC 15 14 VSYNC_R 1 2 22_0402_5% VSYNC
<29> UMA_CRT_HSYNC SYNC_IN2 SYNC_OUT1
R64 CRT@
6 16 HSYNC_R 1 2 22_0402_5% HSYNC
GND SYNC_OUT2
TPD7S019-15DBQR_SSOP16
CRT@
4 4
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CRT
1.0
A B C D E
A B C D E
SATA HDD/SSD Conn.

Close to JHDD
JHDD @
1
GND 2 SATA_PTX_C_DRX_P0 C511 1 2 0.01U_0402_25V7K
RX+ 3 SATA_PTX_DRX_P0 <7>
SATA_PTX_C_DRX_N0 C512 1 2 0.01U_0402_25V7K
RX- 4 SATA_PTX_DRX_N0 <7>
GND 5 SATA_PRX_DTX_N0 C513 1 2 0.01U_0402_25V7K
TX- 6 SATA_PRX_C_DTX_N0 <7>
SATA_PRX_DTX_P0 C514 1 2 0.01U_0402_25V7K
TX+ 7 SATA_PRX_C_DTX_P0 <7>
GND
1 8 1
3.3V 9
3.3V 10 +3VS
3.3V 11
24 GND 12
23 GND GND 13
GND GND 14
5V 15
5V 16
5V 17 +5VS
GND 18
Rsv 19
GND 20 +5VS
12V 21
Place closely JHDD SATA CONN.
12V
1.2A
22
12V
1 1 1
LCN_ASF98-2231S10-0002 C516 C517
C515 0.1U_0402_10V7K 0.1U_0402_10V7K
10U_0805_10V4Z
2 2 2
SATA ODD Conn

+5VS_ODD Place components closely ODD CONN.
Power Consumption 1.1A
1 1 1
Peak 1800 mA
2 C518 C519 C520 2
Read (CD) 1100 mA
10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K
Read (DVD) 950 mA 2 2 2
Write 1300 mA
Standby 20mA
JODD Conn@
1
GND 2 SATA_PTX_C_DRX_P1 C521 1 2 0.01U_0402_25V7K
A+ 3 SATA_PTX_DRX_P1 <7>
SATA_PTX_C_DRX_N1 C522 1 2 0.01U_0402_25V7K
A- 4 SATA_PTX_DRX_N1 <7>
GND 5 SATA_PRX_DTX_N1 C523 1 2 0.01U_0402_25V7K
B- 6 SATA_PRX_C_DTX_N1 <7>
SATA_PRX_DTX_P1 C524 1 2 0.01U_0402_25V7K
B+ 7 SATA_PRX_C_DTX_P1 <7>
GND
8
DP 9 ODD_DETECT# <10,7>
+5V +5VS_ODD
10
+5V 11
14 MD 12 ODD_DA# <10>
15 GND GND 13
GND GND
SANTA_201902-1
3 3
4 4
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SATA HDD/SSD/ODD
1.0
A B C D E
A B C D E
NGFF-Slot1-E-Key-WLAN +3V_W LAN
0.1U_0402_10V7K
JW LAN @ 1 1 1
+3V_W LAN 69 CM6 CM8 CM7
68 GND2
GND1 67 2 2 2
66 GND_75 65 0.1U_0402_10V7K 4.7U_0603_6.3V6K
64 3.3VAUX_74 RSVD_73 63
1 1
62 3.3VAUX_72 RSVD_71 61
RSVD_70 GND_69
Close to JWLAN
60 59
58 RSVD_68 RSVD/PCIE_TX_N1 57
56 RSVD_66 RSVD/PCIE_TX_P1 55
54 RSVD_64 GND_63 53
52 I2C_IRQ RSVD/PCIE_RX_N1 51
50 I2C_CLK RSVD/PCIE_RX_P1 49
48 I2C_DAT GND_57 47
<36> W L_OFF# W_DISABLE1# PEWAKE0# W LAN_W AKE# <36>
46 45 CLKREQ_W LAN# <10,8>
<36> BT_ON W_DISABLE2# CLKREQ0#
44 43
<33,37,9> PLT_RST_BUF# PERST0# GND_51
42 41 CLK_W LAN# <8>
<9> CLK_EC SUSCLK(32KHz) REFCLK_N0
40 39 CLK_W LAN <8>
38 COEX1 REFCLK_P0 37
36 COEX2 GND_45 35
COEX3 PER_TX_N0 PCIE_PRX_W LANTX_N4 <11>
34 33 PCIE_PRX_W LANTX_P4 <11>
32 CLink_CLK PER_TX_P0 31
<36> E51_RXD
30 CLink_DATA GND_39 29
WLAN/ WiFi
<36> E51_TXD CLink_RST PET_RX_N0 PCIE_PTX_C_W LANRX_N4 <11>
28 27 PCIE_PTX_C_W LANRX_P4 <11>
26 UART_CTS PET_RX_P0 25
Debug card using UART_RTS GND_33
24
UART_RX
23
22 SDIO_RST 21
20 UART_TX SDIO_WAKE 19
18 UART_WAKE SDIO_DAT3 17
16 GND_18 SDIO_DAT2 15
14 LED2# SDIO_DAT1 13
12 PCM_IN SDIO_DAT0 11
2
pin 8-15 10 PCM_OUT SDIO_CMD 9 2
8 PCM_SYNC SDIO_CLK 7
Removed for key A 6 PCM_CLK GND_7 5
LED1# USB_D- USB20_N4 <11>
4
3.3VAUX_4 USB_D+
3
USB20_P4 <11> WiMax/ BT
2 1
3.3VAUX_2 GND_1
BELLW _80152-3221
3 3
4 4
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NGFF-WLAN
1.0
A B C D E
5 4 3 2 1
Left USB 2.0 x 1

LAN/USB Small board Conn
Current Limit 2A
+USB_VCCC Change LR9 P/N from SM070003Y00 to SM070003K00
JLAN @ W=80mils
+5VALW +5VALW +USB_VCCC
1 Check Output Caps are on sub-board or not.
1 2 @ UR3
2 3 LR9 EMI@ 1
3 LAN_OFF# <36> 1 OUT
D 4 1 2 USB20_N2 CR6 5 D
4 5 USB20_N2_L 1 2 USB20_N2 <11> IN 2
5 GND
10U_0603_6.3V6M
6 USB20_P2_L <36> USB_EN#2 4
6 7 4 3 USB20_P2 2 EN 3
7 4 3 USB20_P2 <11> OCB USB_OC#2 <10,11,36>
8
8 PCIE_PRX_C_LANTX_P3 <11>
9 DLW21HN900HQ2L_4P R5 1 @EMI@ 2 0_0402_5% SY6288D20AAC_SOT23-5
9 PCIE_PRX_C_LANTX_N3 <11>
10 SA00007AO00
10 11 PCIE_PTX_C_LANRX_P3 <11>
EMI@ L56
11 12 PCIE_PTX_C_LANRX_N3 <11> 3 4
12 13 3 4 CLK_LAN <8>
CLK_LAN_R
13 14 CLK_LAN#_R
14 15 2 1
15 16 2 1 CLK_LAN# <8>
16 17 EC_SWI# <36,9>
ISOLATE# DLW21HN900HQ2L_4P
17 18 LANCLK_REQ# 1 2
18 19 PLT_RST_BUF# R4 0_0402_5%
19 PLT_RST_BUF# <32,37,9>
20 @EMI@
20 +3V_LAN
21
21 22
22 23 PL <35>
23 24 PR <35>
27 24 25 EXT_MIC_L <35>
28 G1 25 26 NBA_PLUG# <35>
G2 26
+3V_LAN > 40 mil
E-T_6905-E26N-01R
@ PJ77
1 2
+3V_LAN 1 2 +3VALW_PCH
JUMP_43X39
C C
LAN WOL
LAN_EN ISOLATEB
+3VS
S0 Sx S0 Sx
For LAN function ----------------------------------------------
0 0 0 0 1 1
1
RL24 2 1 10K_0402_5% LANCLK_REQ# 0 1 0 0 1 1

+3VS
1K_0402_5%
RL8
1 0 1 1 1 1
@ 1 1 1 1 1 0*
2
ISOLATE# RL433 1 Rshort@ 2 0_0402_5%

<10,8> LAN_EN WOL_EN# <36>
*
2
G
S3: after SUSP# assert low over 100ms

<8> CLKREQ_LAN#
1 3 LANCLK_REQ# RL9 S4/S5: after SYSON assert low over 100ms
15K_0402_5%
D
Sx Enable Sx Disable
QL53 Wake up Wake up
2N7002KW_SOT323-3
WOL_EN# LOW HIGH +3V_LAN rising time (10%~90%) need > 1ms and <100ms.
B B
TPM BADD ADDRESS 1

2
UT1
GPIO0/XOR_OUT VSB
TPM@
5
19
+3VALW
+3VS
+3VS +3VALW
6 GPIO1 VDD1 24
EEh - EFh @ Close to Pin5
0 1 2 9 GPIO2/GPX VDD2
15 GPIO3/BADD
* Floating 7Eh - 7Fh RT5 10K_0402_5% 1 1
GPIO4/CLKRUN# 8 CT34 CT14
TEST 1 1 1 1 Close to Pin10
10U_0603_6.3V6M
0.1U_0402_10V7K
26 CT17 CT21 CT22 CT33
<36,8> LPC_AD0 23 LAD0
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
<36,8> LPC_AD1 20 LAD1 3 2 2
For EMI <36,8> LPC_AD2 LAD2 NC0 2 2 2 2
17 10
<36,8> LPC_AD3 LAD3 VDD3 11
CLKOUT_LPC1 VSS3 12
28 NC1 13
LPCPD# NC2
1
CLKOUT_LPC1 21 14
<8> CLKOUT_LPC1 22 LCLK NC3 TPM@
RT11 TPM@
<36,8> LPC_FRAME# PLT_RST_BUF# 16 LFRAME#
22_0402_5% @EMI@ TPM@ TPM@ TPM@ TPM@
27 LRESET# 4
<10,36> SERIRQ 7 SERIRQ VSS0 18
2
PP VSS1 25
1 VSS2
CT42 @EMI@
10P_0402_50V8J NPCT650AA0WX_TSSOP28
2
A A
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TPM
1.0
5 4 3 2 1
5 4 3 2 1
D D
Right rear USB2.0 Conn. Right side USB 3.0 x 1 W/O Sleep&Charge
Change L71,L72,LR7,LR8 P/N
from SM070003Y00 to SM070003K00
EMI@ LR7 L71 EMI@ EMI@ LR8

2 1 USB20_P0_R 1 2 U3RXDP2_L 2 1 USB20_N1_R
<11> USB20_P0 2 1 <11> U3RXDP2 1 2 <11> USB20_N1 2 1
3 4 USB20_N0_R 4 3 U3RXDN2_L 3 4 USB20_P1_R

C <11> USB20_N0 3 4 <11> U3RXDN2 4 3 <11> USB20_P1 3 4 C
DLW21HN900HQ2L_4P DLW21HN900HQ2L_4P DLW21HN900HQ2L_4P
CLOSE UR1
+5VALW +USB_VCCB W=80mils
CR14
1 1 1 1 1 1
100U_D2_6.3VM_R17M
CR1 CR4 @ L72 EMI@
Current Limit 2A CR2 CR3 CR5 +
<11> U3TXDP2
1 2 U3TXDP2_C 1
1 2
2 U3TXDP2_C_L
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
0.1U_0402_10V7K
C526 0.1U_0402_10V7K
2 2 2 2 2
2 1 2 U3TXDN2_C 4 3 U3TXDN2_C_L
+5VALW W=80mils +USB_VCCB <11> U3TXDN2
C528 0.1U_0402_10V7K 4 3
DLW21HN900HQ2L_4P
UR1
1
5 OUT
IN 2
4 GND
<36> USB_EN#0 EN 3 USB_OC#0 <10,11,36> W=80mils
OCB JUSBF @
SY6288D20AAC_SOT23-5 D88 @ESD@ U3TXDP2_C_L 9
U3TXDP2_C_L 1 1 SSTX+
SA00007AO00 10 9 U3TXDP2_C_L +USB_VCCB 1
U3TXDN2_C_L 8 VBUS
U3TXDN2_C_L 2 2 SSTX-
9 8 U3TXDN2_C_L USB20_N1_R 2
JUSBR @ 7 D-
4 4 GND
+USB_VCCB 1 U3RXDP2_L 7 7 U3RXDP2_L USB20_P1_R 3 10
USB20_N0_R 2 VBUS U3RXDP2_L 6 D+ GND 11
D- 5 5 SSRX+ GND
USB20_P0_R 3 U3RXDN2_L 6 6 U3RXDN2_L 4 12
4 D+ U3RXDN2_L 5 GND GND 13
5 SHIELD 3 3 SSRX- GND
B B
6 GND OCTEK_USB-09EAEB
7 GND 8
8 GND
GND YSCLAMP0524P_SLP2510P8-10-9
SANTA_360131-1
A A
5 4
www.vinafix.vn Security Classification
Issued Date 2013/09/25
Compal Secret Data
Deciphered Date 2016/09/25
3 2
Size Document Number
Custom
Title
Date:
RUSB/S&C
1
Sheet 34 of 52
Rev
1.0
5 4 3 2 1
60 mil +PVDD 1 Rshort@ 2

20 mil
+MIC2_VREFO +5VS
UA1 1 2 RA1 0_0603_5% +AVDD1 1 Rshort@ 2
16 1 +DVDD CA3 1 1 RA2 0_0603_5%
RA3 4.7K_0402_5% 29 MONO-OUT DVDD 9 +DVDD 0.1U_0402_10V7K CA1 CA2
PR_R 2 1 +MIC1-VREFO-R 30 MIC2-VREFO DVDD-IO For AMD & Baytrail, name Pin9 +DVDD-IO close to pin41 CA4 0.1U_0402_10V7K
PR_L 2 1 +MIC1-VREFO-L 31 MIC1-VREFO-R 26 +AVDD1 2 1 10U_0603_6.3V6M
MIC1-VREFO-L AVDD1
close to pin26 1U_0402_6.3V6K
RA5 4.7K_0402_5% 40 +AVDD2 2 2
15 AVDD2
JDREF 1
41 +PVDD CA5
AC_VREF 28 PVDD1 46 +PVDD 0.1U_0402_10V7K
VREF PVDD2 36 +DVDD
RA7
CPVDD For EMI reserve close to pin46
PR_L 2 147_0402_1% HPOUT_L 32 2
PR_R 2 1 HPOUT_R 33 HPOUT-L(PORT-I-L) 2 INT_MIC_DATA <27>
RA4 47_0402_1% HPOUT-R(PORT-I-R) GPIO0/DMIC-DATA 3 INT_MIC_CLK_R RA8 CAM_EMI@
CA6 1 2 1U_0402_6.3V6K CBN 35 GPIO1/DMIC-CLK FBMA-10-100505-301T INT_MIC_CLK <27>
CBP 37 CBN 8 AZ_SDIN0_HD_R 2 1 22_0402_5% +DVDD 1 Rshort@ 2
220P_0402_50V7K
CBP SDATA-IN AZ_SDIN0_HD <7> +3VS
EMI@
5 RA9 RA10 0_0603_5%
D
CA9 1 2 1U_0402_6.3V6K CPVEE 34 SDATA-OUT AZ_SDOUT_HD <7> 20 mil 1 D
CPVEE 6 AZ_BITCLK_HD +AVDD2 1 Rshort@ 2 CA10
BCLK AZ_BITCLK_HD <7> +1.5VS
LDO1-CAP 27 1 RA11 0_0603_5% 1U_0402_6.3V6K
LDO1-CAP 2
CA8
CA7 1 2 4.7U_0402_6.3V6M LDO2-CAP 39 10 CA11
CA12 1 2 4.7U_0402_6.3V6M LDO3-CAP 7 LDO2-CAP SYNC AZ_SYNC_HD <7>
LDO3-CAP 12 MONO_IN 1U_0402_6.3V6K
PCBEEP 2 1
close to pin, 10mil SPKL- 43 close to pin3 CA15
SPKL+ 42 SPK-OUT-L- 13 SENSE_A 0.1U_0402_10V7K
SPKR- 44 SPK-OUT-L+ Sense A 14 +3VALW
SPKR+ 45 SPK-OUT-R- Sense B 2
Reserve for solve pop noise SPK-OUT-R+
CA14 4.7U_0402_6.3V6M
RA12 19 1 2
MIC1-L(PORT-B-L) 20 mil
1
1 @ 2 EC_MUTE_INT_R 48 20
<36> EC_MUTE_INT 0_0402_5% SPDIF-OUT/GPIO2 MIC1-R(PORT-B-R) 17 CA13
MIC2-L(PORT-F-L) 18 EXT_MIC 4.7U_0402_6.3V6M
2
4 MIC2-R(PORT-F-R) RA15 1K_0402_5%
25 DVSS 22 LINE1-L CA16 1 2 2.2U_0402_6.3V6M LINE1-L_C 1 2 PR_L
AVSS1 LINE1-L(PORT-C-L) close to pin1
38 21 LINE1-R CA17 1 2 2.2U_0402_6.3V6M LINE1-R_C 1 2 PR_R close to pin36
1 2 LDO1-CAP 49 AVSS2 LINE1-R(PORT-C-R) 24 RA16 1K_0402_5%
RA17 100K_0402_5% Thermal Pad LINE2-L(PORT-E-L) 23
LINE2-R(PORT-E-R)
11
1 2 RESETB AZ_RST_HD# <7>
2
CA18 4.7U_0402_6.3V6M 47
PDB
2
EC_MUTE# <36> CA19
DGND ALC233-VB MQFN 48P RA19 0.01U_0402_25V7K
4.7K_0402_5% 1
@ESD@
close to pin, 10mil @
AGND
1
1 Rshort@ 2
Reserve for solve noise issue RA20 0_0603_5%
1 Rshort@ 2
AC_VREF Internal AMP For EMI reserve RA21 0_0603_5%
EC_MUTE# 1 @ 2
1 2 Hight Enable close to codec RA22 0_0603_5%
@ LOW Disable 1 @EMI@ 2
CA21 CA22 RA24 0_0603_5%
C 0.1U_0402_10V7K 2.2U_0402_6.3V6M AZ_BITCLK_HD RA23 2 1 CA20 1 2 1 @EMI@ 2 C
2 1 10_0402_5% EMI@ 10P_0402_50V8J EMI@ RA25 0_0603_5%
Beep sound Combo Jack

Change material
RA26 2.2K_0402_5% For EMI protection
1 2 to SM01000GK00
+MIC2_VREFO use SM01000GK00
PCI Beep CA23 EMI@
1 RA27 2 1 2 MONO_IN EXT_MIC LA2 1 2 EXT_MIC_L <33> LA1
<10> PCH_SPKR 1 Rshort@ 2 0_0402_5%
47K_0402_5% SBY100505T-470Y-N_2P PR_R PR <33>
0.1U_0402_10V7K
100P_0402_50V8J
1
LA3
2
PR_L 1 Rshort@ 2 0_0402_5% PL <33>
CA24
RA28 CA25
100P_0402_50V8J 2
4.7K_0402_5% 1 1
@ CA27
CA26
100P_0402_50V8J
1
100P_0402_50V8J
@EMI@ 2 2 @EMI@
For better sound
by customer request
place close to chip

(ALC233 supported IPhone headset/ Headphone/ MIC in)
1 2
B +3VS B
RA29 100K_0402_5%
1 2 SENSE_A
<33> NBA_PLUG# RA30 200K_0402_5%
for Combo Jack normal Open
SPK
For EMI reserve SPK Conn.

close to codec DA8
3
SPKL+ 1 Rshort@ 2 SPK_L1 1
RA32 0_0603_5% 2
SPKL- 1 Rshort@ 2 SPK_L2

RA33 0_0603_5% YSDA0502C_SOT23-3
@ESD@
1 1
CA28 JSPK @
1000P_0402_50V7K CA29 SPK_L1 1
@EMI@ SPK_L2 2 1
1000P_0402_50V7K 2
2 2 SPK_R1 3 6
@EMI@ 3 GND
SPK_R2 4 5 EXT_MIC EXT_MIC_L RING2 RING2_L
4 GND
DA9 Speaker 4 ohm: 40mil
A CVILU_CI4404M1HRT-LF A
3 Speaker 8 ohm: 20mil
SPKR+ 1 Rshort@ 2 SPK_R1 1
RA34 0_0603_5% 2
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RA13 LA2 CA24
SPKR- 1 Rshort@ 2 SPK_R2 YSDA0502C_SOT23-3 close to small board connector
RA35 0_0603_5% @ESD@
1 1
@EMI@ @EMI@
CA30 CA31
1000P_0402_50V7K 1000P_0402_50V7K
2 2
ALC233/233VB
1.0
5 4 3 2 1
A B C D E
+3VL +3VL
CB3 RB1 1 Rshort@ 2 0_0402_5% H_PROCHOT# <5>

<47> VR_HOT#
0.1U_0402_10V7K
0.1U_0402_10V7K 0.1U_0402_10V7K 1 2
1
1 1 1 1 1
For EMI CB1 CB2 @ @ CB5 D QB1 CB8
0.1U_0402_10V7K H_PROCHOT#_EC 2 47P_0402_50V8J
111
125
CB4 G
22
33
96
67
9
CLK_PCI_EC 2 2 2 2 UB1 S 2
2N7002K_SOT23-3
0.1U_0402_10V7K BATT_PRES 1 2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
3
1
@ CB9 100P_0402_50V8J
RB4
10_0402_5% ACIN 1 2
@EMI@ 1 21 CB10 100P_0402_50V8J
1 2 GATEA20/GPIO00 GPIO0F 23 WL_BT_LED# <37> 1
<10> KB_RST# USB_EN#0 <34>
2
3 KBRST#/GPIO01 BEEP#/GPIO10 26 TRANS_PRSNT

1 <10,33> SERIRQ SERIRQ GPIO12
CB11 4 27
<33,8> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 +3VS
22P_0402_50V8J
<33,8> LPC_AD3 7 LPC_AD3
@EMI@
2 <33,8> LPC_AD2 LPC_AD2 PWM Output
8 63 BATT_PRES
<33,8> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_PRES <40> H_PROCHOT#_EC 1 2
<33,8> LPC_AD0 LPC_AD0LPC & MISC GPIO39 USB_OC#0 <10,11,34>
@
65 RB6 10K_0402_5%
CLK_PCI_EC 12 ADP_I/GPIO3A 66 ADP_I <40,41>
<8> CLK_PCI_EC CLK_PCI_EC AD Input GPIO3B ADP_V <41>
PLT_RST# 13 75 TRANS_SEL
<18,9> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 +3VL
+3VL 20 EC_RST# IMON/GPIO43 EC_ENBKL_R <26,9>
RB2
<10> EC_SCI# 38 EC_SCII#/GPIO0E
47K_0402_5%
1 2 <38> WOWL_EN GPIO1D 68 1 2
EC_RST# LID_SW#
DAC_BRIG/GPIO3C 70 DFAN1 <7>
RB35 47K_0402_5%
1 2 EN_DFAN1/GPIO3D 71
DA Output IREF/GPIO3E
CB12 0.1U_0402_10V7K KSI0 55 72 WLAN_WAKE# 1 2
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F VCCST_PWRGD <12,44>
RB37 47K_0402_5%
KSI2 57 KSI1/GPIO31
KSI2/GPIO32
Reserve this signal to EC by SW demand
KSI3 58 83 +3VS
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <35> 2011/10/18a
KSI4 59 84
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 EC_SMB_CK3 PM_SLP_S4# <9>
KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_SMB_DA3 EC_SMB_CK3 <26> TP_CLK 1 2
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EC_SMB_DA3 <26>
KSI7 62 87 TP_CLK RB13 4.7K_0402_5%
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <37>
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37> TP_DATA 1 2
KSO2 41 KSO1/GPIO21 RB14 4.7K_0402_5%
KSI[0..7] KSO3 42 KSO2/GPIO22 97
<37> KSI[0..7] KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98
KSO[0..17] 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 GPU_DOWN# <19>
KSO5
<37> KSO[0..17] KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 PWRME_CTRL <7>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <40>
2 KSO7/GPIO27 SPI Device Interface 2
KSO8 47 VCIN0_PH connect to power portion +3VS
KSO9 48 KSO8/GPIO28 119
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SDIO <8>
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SDI <8> EC_SMB_CK3 1 2
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SCK <8>
@
KSO12 51 128 RB15 2.2K_0402_5%
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_CS0# <8>
KSO14 53 KSO13/GPIO2D EC_SMB_DA3 1 @ 2
KSO15 54 KSO14/GPIO2E 73 WLAN_WAKE# RB16 2.2K_0402_5%
KSO16 81 KSO15/GPIO2F ENBKL/GPIO40 74 WLAN_WAKE# <32>
KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 WOL_EN# <33>
RPB1 KSO17/GPIO49 FSTCHG/GPIO50 90
BATT_CHG_LED#/GPIO52 91 BATT_FULL_LED# <37>
1 8 77 CAPS_LED#/GPIO53 92 CAPS_LED# <37>
EC_SMB_CK1 EC_SMB_CK1 GPIO
+3VL <40,41> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PBTN_LED# <37>
2 7 EC_SMB_DA1 EC_SMB_DA1 78 93 SYSON 1 2
3 6 EC_SMB_CK2 <40,41> EC_SMB_DA1 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_CHG_LOW_LED# <37>
+3VS <19,8> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <43>
RB10 4.7K_0402_5%
4 5 EC_SMB_DA2 EC_SMB_DA2 80 121
<19,8> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VCCST_PG_EC <12> 1 2
SUSP#
2.2K_8P4R_5% PM_SLP_S4#/GPIO59 RB21 10K_0402_5%
6 100
<9> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PCH_RSMRST# <9>
<9> PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <10>
<7> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC PROCHOT_IN <40>
<10,11,33> USB_OC#2
PROCHOT_IN connect to power portion
17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0_PH_L
RB29 1 2 0_0402_5% PCH_RTCRST#_R 18 GPIO0B VCOUT0_PH/GPXIOA07 105
<7> PCH_RTCRST# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <27>
19 GPIO 106
<33> USB_EN#2 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# <9>
<33> LAN_OFF# 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN <38>
<7> FAN_SPEED1 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 EC_SWI# <33,9>
<32> WL_OFF# E51_TXD 30 EC_PME#/GPIO15 VCOUT0_PH_L 1 Rshort@ 2
1 2 E51_TXD <32> E51_TXD E51_RXD 31 EC_TX/GPIO16 110 ACIN VS_ON <42>
RB34 0_0402_5%
<32> E51_RXD 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN <41,9>
RB27 100K_0402_5%
<9> PCH_PWROK EC_ON <42>
VCOUT0_PH connect to power portion (9012 only)
3 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 3
2 1 <32> BT_ON 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <16,37>
EC_MUTE_INT GPI LID_SW#
<37> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <37>
RB28 4.7K_0402_5%
SUSP#/GPXIOD05 117 SUSP# <38,44,46>
GPXIOD06 118 EC_PECI 1 2
PECI_KB9012/GPXIOD07 H_PECI <5> Close to EC
AGND/AGND
122 RB19 43_0402_5%

<35> EC_MUTE_INT 123 XCLKI/GPIO5D 124 +EC_V18R @ESD@
GND/GND
GND/GND
GND/GND
GND/GND
<42,9> POK XCLKO/GPIO5E V18R SUSP# 1 2

1
GND0
CB14 180P_0402_50V8J
CB15
4.7U_0805_10V4Z
KB9012QF-A4_LQFP128_14X14 2
11
24
35
94
113
69
Reserve TRANS_PRSNT for panel timing tuning.
+3VL
Signal pull high is default status (ROM only mode).
If signal pull low, EC will send translator code to chip.(EP mode)
2
+3VL LVDS@
RB23
10K_0402_5%
2
RB26
1
LVDS@ 10K_0402_5% Voltage Comparator Pins FOR 9012 A3 TRANS_PRSNT
2
IEDP@
1
TRANS_SEL VCIN0 pin109 >1.2V <1.2V RB22

VCIN1 pin102 10K_0402_5%
2
RB25 HIGH
1
4
@ 10K_0402_5% VCOUT0 pin104
(default) LOW 4
LOW
1
VCOUT1 pin103 HIGH (default)
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For Translator select

LPC-EC-KB9012&930
1.0
A B C D E
5 4 3 2 1
LED Small board to Conn PBTN/B to M/B

Power Button
+3VL
2
NOTICE: ON/OFFBTN# have
R469 pull-hign resistance on
100K_0402_5% motherboard
1
ON/OFFBTN# ON/OFFBTN# <16,36>
JLED @
1 +5VALW
1 2
D 2 3 BATT_FULL_LED# <36> D
BATT_CHG_LOW_LED# <36> JPWR @
3 4 1 +5VALW
4 5 WL_BT_LED# <36> 1
7 2 PBTN_LED# <36>
8 G1 5 6 5 2 3 ON/OFFBTN#
G2 6 6 G1 3 4
E-T_6916K-Q06N-00L G2 4
TJG-533-V-T/R_6P E-T_6916K-Q04N-03R
3 1
4 2
SW3
5
6
KEYBOARD CONN. Card Reader + TP + Lid SW

JKB @
1
<36> NUM_LED# 1
2 JCARD @
3 2 1
<36> CAPS_LED# 3 +3VS 1
+3VS
2 1 +3VS_CAP 4 2
R483 300_0402_5% KSI1 5 4 3 2
KSI6
KSI5
6
7
5
6
7
<32,33,9> PLT_RST_BUF#
<8> CLKREQ_CR#
+3VL
4
5
3
4
5
Screw Hole
KSI0 8 6
KSI4 9 8 7 6
9 <11> PCIE_PTX_C_CRRX_P2 7
KSI3 10 R7 1 @EMI@ 2 0_0402_5% 8 CPU
C 10 <11> PCIE_PTX_C_CRRX_N2 8 C
KSI2 11 <11> PCIE_PRX_C_CRTX_P2
9
KSI7 12 11 L57 EMI@ 10 9 H1 H2 H3
12 <11> PCIE_PRX_C_CRTX_N2 10
KSO15 13 3 4 11 H_3P7 H_4P3x4P0 H_4P1
KSO12 14 13 <8> CLK_CR 3 4 CLK_CR_R 12 11 @ @ @
KSO11 15 14 CLK_CR#_R 13 12
1
KSO10 16 15 2 1 14 13
KSO9 17 16 <8> CLK_CR# 2 1 15 14
17 <36> LID_SW# 15
KSO8 18 DLW21HN900HQ2L_4P <10,9> TP_INTR#
16
KSO13 19 18 1 2 17 16
19 <36> TP_DATA 17 PTH NPTH
KSO7 20 R6 0_0402_5% 18
20 <36> TP_CLK 18
KSO6 21 @EMI@ TP_I2CSDA1 19
KSO14 22 21 TP_I2CSCL1 20 19 H4 H5 H6 H7 H10
KSO5 23 22 20 H_3P0 H_3P0 H_3P0 H_4P2x3P2N H_3P0N
KSO3 24 23 R477 1 @ 2 0_0402_5% @ @ @ @ @
24 <10> PM_I2CSDA1
KSO4 25 R478 1 @ 2 0_0402_5%
<10> PM_I2CSCL1
1
KSO0 26 25 21
KSO1 27 26 R475 1 2 0_0402_5% 22 GND
27 <16,17,8> PM_SMBDATA GND
KSO2 28 R476 1 2 0_0402_5%
28 <16,17,8> PM_SMBCLK
29 H8 H9 H11 H12 H13
30 29 ACES_50578-0200N-001 H_3P0 H_3P0 H_3P0 H_3P1 H_3P0
KSO17 31 30 @ @ @ @ @
32 31
1
KSO16 33 32
2 1 +3VS_NUM 34 33
+3VS 34
R480 300_0402_5% 35
GND1 36
GND2
CVILU_CF17341U0R0-NH
KSI[0..7]
KSO[0..17]
KSI[0..7]
KSO[0..17]
<36>
<36>
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
B @ @ @ @ B
CPU GPU
1
ISPD UC1
R1 PN
4005UR1@ UC1
R3 PN
4005UR3@
UV1 TOPAZ@
ZZZ
SA000072Q70 SA000072Q60
DAZ15H00100
I3-4005U I3-4005U
TOPAZ XT S3 FCBGA 631P GPU 0FD
PCB LA-B301PR10 UC1 4200UR1@ UC1 4200UR3@
SA00006SM80 SA00006SM90
UV1 JET@
I5-4200U I5-4200U
UC1 4010UR1@ UC1 4010UR3@
SA00006SXA0 SA00006SX90 JET PRO S3 FCBGA 631P GPU 0FD
I3-4010U I3-4010U
UC1 2990UR1@
SA00007LM00
2990U
A A
UC1 4210UR1@
SA00007LO00
www.vinafix.vn
I5-4210U
UC1 4015UR1@
SA00007LN00 Issued Date 2013/09/25 2016/09/25 Title
Deciphered Date
TP/ISPD/KB/Screw
I3-4015U Size Document Number Rev
1.0
5 4 3 2 1
A B C D E
VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+3VALW TO +3VS +5VALW
+5VS For ESD
PJ3 @
+5VALW TO +5VS 1
2
U3
VIN1 VOUT1
14
13
+5VS_LS 1 2
Load Switch C537

1U_0402_6.3V6K
1
SUSP# 3
VIN1
ON1
VOUT1
CT1
12
C538
1
180P_0402_50V8J
2
PAD-OPEN 4x4m
1
C539 +5VS +5VALW
@ +5VALW 4 11 0.1U_0402_10V7K
2 VBIAS GND C540 330P_0402_50V7K @
SUSP# 5 10 1 2 2
ON2 CT2 +3VS
+3VALW 6 9 PJ5 @
VIN2 VOUT2 1 1
7 8 +3VS_LS 1 2 C549 C550
VIN2 VOUT2 0.1U_0402_10V7K 0.1U_0402_10V7K
1 1
15 PAD-OPEN 4x4m 1 ESD@ @ESD@
GPAD C541 2 2
1 TPS22966DPUR_SON14_2X3 @
@ C542
2 0.1U_0402_10V7K
1U_0402_6.3V6K
2
+5VS TO +5VS_ODD
Need mount RM3 if system
+5VALW
don't support ZPODD
+5VS 1 Rshort@ 2 +5VS_ODD

RM3 0_0805_5%
1
R482
100K_0402_5%
Part number is SA000070S00
2
VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm +5VS_ODD
+5VS PCH_PWR_EN# PCH_PWR_EN# <13>
6
U7 ZPODD@
ZPODD@
1 7 +5VS_ODD_LS 1 2 Q195A
2 VIN VOUT 8 RM6 0_0805_5% 2 2N7002DW-T/R7_SOT363-6
2 VIN VOUT <36> PCH_PWR_EN 2
C543 1
1U_0402_6.3V6K 3 6
<10> ODD_EN
1
ON CT
1 1
@ ZPODD@ C544
2 4 C545 0.1U_0402_10V7K
+5VS VBIAS 5 270P_0402_50V7K @
GND 9 2 2
GND
TPS22967DSGR_SON8_2X2 +5VALW
+0.675VS +1.05VS_VTT
2
please refer to the table to choose C545
R485
2
100K_0402_5%
R486 R487
22_0805_5% 470_0805_5%
1
SUSP
1
6
+3VALW TO +3V_WLAN
1
D Q189 Q60 D
Need mount RM5 if system Q5539A
2 2N7002DW-T/R7_SOT363-6 2 SUSP 2
don't support ISCT <36,44,46> SUSP# G G
for WOWL
1
1 Rshort@ 2 S 2N7002KW_SOT323-3 S
3
+3VS +3V_WLAN
RM5 0_0805_5% 2N7002KW_SOT323-3
Part number is SA000070S00

3 VIN 0.8V-5.5V (VBIAS=5V),IMAX=4A,Rds=22mohm +3V_WLAN 3
+3VALW
U8 ISCT@
ISCT@
1 7 +3V_WLAN_LS 1 2
2 VIN VOUT 8 RM7 0_0805_5%
C546 VIN VOUT
1
1U_0402_6.3V6K WOWL_EN 3 6
<36> WOWL_EN ON CT
1 1
@ ISCT@ C547
2 4 C548 0.1U_0402_10V7K
+5VALW VBIAS 5 270P_0402_50V7K @
GND 9 2 2
GND
TPS22967DSGR_SON8_2X2
+3VALW
please refer to the table to choose C548

1
RM4
10K_0402_5% NOISCT@
2
WOWL_EN
1
RM2
10K_0402_5% ISCT@
2
4 4
A B
www.vinafix.vn Security Classification
Issued Date 2013/09/25
Compal Secret Data
Deciphered Date 2016/09/25
C D
Size
Title
Date:
Document Number
DC-DC INTERFACE
E
Sheet 38 of 52
Rev
1.0
5 4 3 2 1
Mark Green frame that means this part is not belong to layout module part .
Function Field :
D D
Support 37.1
RTC 38.2
EMI Part 47.1
VIN
@ PJP1
PF1 EMI@ PL1
ACES_50299-00401-001
5A_32V_F1206HI5000V032TM FBMA-L11-201209-121LMA50T_0805
1 DC_IN 1 2 DC_IN_S1 1 2
1 2
2 3
3 4 1 2
4 EMI@ PL2
FBMA-L11-201209-121LMA50T_0805
1
EMI@ PC1 EMI@ PC2 EMI@ PC3 EMI@ PC4
2 1000P_0603_50V7K 100P_0603_50V8 100P_0603_50V8 1000P_0603_50V7K
2
C C
B B
A A
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Title
Issued Date Deciphered Date
DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 ZSWAA/ZCWAA LA-B301P 1.0
5 4 3 2 1
5 4 3 2 1
Function Field :
Support 37.1
D
OTP 39.7 D
EMI Part 47.1
ESD DIODE 47.2
OTP
VMB
PF2 EMI@ PL3
+3VL
@ PJP2 10A_24V_F1206HB10V024TM FBMA-L11-201209-121LMA50T_0805
1 BATT_S1 1 2 1 2 <36,41> ADP_I
1 2
BATT+
2
1
3
3 +RTC_R
1
4
4 5 BATT_P5 1 2 PR6 PR9
5 6 EC_SMDA EMI@ PL4 12.1K_0402_1%
6 1K_0402_1%
7 EC_SMCA FBMA-L11-201209-121LMA50T_0805
2
7
1
10 8 @ PR8 @ PR10
2
GND 8
1
11 9 PR1 EMI@ PC6 0_0402_5% 0_0402_5%
GND 9
100K_0402_1%_TSM0B104F4251RZ
1K_0402_1% EMI@ PC5 0.01U_0402_25V7K 1 2 1 2
<36> PROCHOT_IN <36> VCIN0_PH
SUYIN_200045MR009G171ZR 1000P_0402_50V7K
2
2
1
PR7
1
20K_0402_1% @ PC7
PH1
C 0.1U_0402_10V7K C
1
EMI@ PD2
2
PJSOT24C_SOT23-3
2
EMI@ PD1 2
PJSOT24C_SOT23-3 1
3
2
PR2
6.49K_0402_1%
1 2
+3VL
1
Initial Recovery
PR3
1K_0402_1%
2
1
PR5 PR4
45W 0.55V 0.43V
BATT_PRES <36>
100_0402_1% 100_0402_1% UMA
2
EC_SMB_DA1 <36,41>
Initial Recovery
EC_SMB_CK1 <36,41>
B B
CPU
OTP 90 C 70 C
A A
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Battery Conn / OTP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
5 4 3 2 1
5 4 3 2 1
Module model information Mark Green frame that means this part is not belong to layout module part .
BQ24735A_V1.mdd
BQ24735A_V2.mdd Function Field :
Regulator 40.1
Support 40.2
1
D B+
D 2 D
G PQB05
EMI Part 47.1
2N7002KW_SOT323-3
S
PRB11
3
PRB12
1 2 1 2
1M_0402_5% 3M_0402_5%
VIN PQB04
P1 SI7716ADN-T1-GE3_POWERPAK8-5 P2 PQB07
1 1 PRB50 EMI@ PLB01 CHG_B+ SI7716ADN-T1-GE3_POWERPAK8-5
2 2 0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30% 1
5 3 3 5 1 4 1 2 2
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
5 3
2200P_0402_50V7K
0.1U_0402_25V6
2 3
0.01U_0402_25V7K
@EMI@ PCB23
@EMI@ PCB24
4
4
1
1
0_0402_5%
PCB25
PCB26
0.01U_0402_50V7K
PQB03
@ PCB10
@ PRB10
4
1
AON6414AL VIN
PCB11
PCB27
2
2
2
VF = 0.5V
2
2
3
2
PDB01
BQ24725A_ACDRV_1
0.1U_0402_25V6
BAS40CW_SOT323-3
0.1U_0402_25V6
BQ24725A_BATDRV 1 2 BQ24725A_BATDRV_1
1
1
PCB13
PCB15
PRB27
1 1
1 2
10_1206_1%
PCB01 4.12K_0603_1%
0.047U_0402_25V7K
PRB26
2
PCB14 1 2
0.1U_0402_25V6 VF = 0.37V
5
2.2_0603_5%
PRB25
C PDB02 C
BQ24725A_VCC2
RB751V-40_SOD323-2
AON7408L
PRB28
BQ24725A_ACP
PQB01
0_0402_5%
BQ24725A_REGN
BQ24725A_BST2
2
DH_CHG 1 2 4
BQ24725A_LX
4.12K_0603_1%
4.12K_0603_1%
1
PCB22 BATT+
PRB15
PRB16
DH_CHG
1 2
PLB03 PRB51
3
2
1
1U_0603_25V6K 1 2 4.7UH_5.5A 7X7X3 MOLDING 0.01_1206_1%
BQ24725A_ACN
BQ24725A_LX 1 2 CHG1 4
2
PCB21
5
1U_0603_25V6K 2 3
20
19
18
17
16
PUB00
CSON1
1
EMI@ PRB02
4.7_1206_5%
1 CSOP1
BTST
PHASE
HIDRV
VCC
REGN
10U_0805_25V6K
10U_0805_25V6K
21
PAD
AON7406L
0.1U_0402_25V6
0.1U_0402_25V6
PCB05
PCB06
1
1
PQB02
1 15 DL_CHG 4
ACN LODRV
1
PCB28
PCB29
2
2
2 14
2
ACP GND PRB24
3
2
1
680P_0402_50V7K
10_0603_1%
EMI@ PCB02
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PRB23
2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN PCB20
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV
+3VL ACOK BATDRV
PRB17 100K_0402_1%
ACDET
IOUT BQ24735RGRR_QFN20_3P5X3P5
SDA
SCL
ILIM
B B
<36,9> ACIN
6
10
+3VALW
BQ24725A_ACDET
BQ24725A_ILIM 1 2
VIN
BQ24725A_IOUT
PRB21
0.01U_0402_25V7K
1 316K_0402_1%
100K_0402_1%
1
PRB22
PCB19
PRB18
422K_0402_1%
1
1 2
VIN
2 PRB13
2
309K_0402_1%
2
Vin Dectector ADP_V <36>
Min. Typ Max.
1
0.047U_0402_25V7K
L-->H 17.16V 17.63V 18.12V
1
66.5K_0402_1%
PRB14 @ PCB12
EC_SMB_CK1 <36,40>
H-->L 16.76V 17.22V 17.70V 0.1U_0402_10V7K
100P_0402_50V8J
1
47K_0402_1%
PCB16
2
PCB17
1
PRB19
2
VILIM = 20*ILIM*Rsr EC_SMB_DA1 <36,40>
2
ILIM = 3.3*100/(100+107)/20/0.02
2
@ PRB20
2
= 3.986 A 0_0402_5%
1 2
ADP_I <36,40>
For A51 ADP_V function
1
A A
Close EC chip @ PCB18

@PCB18
100P_0402_50V8J
2
www.vinafix.vn
Issued Date Deciphered Date Title
CHARGER
Custom ZSWAA/ZCWAA LA-B301P 1.0
5 4 3 2 1
5 4 3 2 1
SY8206B_V2.mdd
Function Field :
D Regulator 35.1 D
Support 35.2
EMI Part 47.1
PR304
499K_0402_1%
ENLDO_3V5V 1 2
3.3V LDO 150mA~300mA B+
PU300 PC303 PR303
B+
1
1M_0402_1%
EMI@ PL301 7 1 3V5V_EN_3 0.01U_0402_25V7K 1K_0402_5%
EN2 EN1
PR305
HCB2012KF-121T50_0805 1 2 1 2
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN FB PR301 PC301
10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_3V 2 1 2
2
BS
1
1
0_0603_5%
@EMI@ PC313
EMI@ PC314
PC311
0.1U_0603_25V7K
PL303
2
2
10 LX_3V 1 2
LX +3VALWP
9 4 2.2UH_PCMB063T-1R0MS_12A_20%
GND OUT +3VALWP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
EMI@ PR302
1
1
4.7_1206_5%
2 5
PG LDO +3VLP
PC305
PC306
PC307
SY8206BQNC_QFN10_3X3
Ipeak : 5A
2
1
Imax : 3.5A
3V_SN
<36,9> POK PC309
2
4.7U_0603_6.3V6M Iocp : 6A
2
PR310
470P_0603_50V7K
100K_0402_1% FSW : 750KHz
1
EMI@ PC302
1 2
+3VL
C C
2
@ PJ303
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
PR306 @ PJ302
2.2K_0402_5% 1 2
1 2 +3VLP 1 2 +3VL
<36> EC_ON JUMP_43X39
@ PR307
1 2
<36> VS_ON Place to 3V EN1 pin
0_0402_5%
@ PR311
0_0402_5%
3V5V_EN 1 2 3V5V_EN_3
Module model information
1M_0402_1%
4.7U_0402_6.3V6M
0.047U_0402_16V4Z
1
1
PR308
PC304
PC312
SY8208C_V2.mdd 2
2
@
2
B+ EMI@ PL351
HCB2012KF-121T50_0805
1 2 5V_VIN
B B
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PU350 PC353 PR353

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
IN EN
1
1
@EMI@ PC363
EMI@ PC364
PC361
PC362
1 2 1 2
3 5V_FB PR351 PC351
FB 0_0603_5% 0.1U_0603_25V7K +5VALWP
2
@ 6 BST_5V 1 2 1 2
BS PL353
2.2UH_PCMB063T-1R0MS_12A_20%
Ipeak : 8A
9 10 LX_5V 1 2 +5VALWP
Imax : 5.6A
GND LX
VCC_3V 5 4
Iocp : 9A
VCC OUT
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7_1206_5%
@EMI@ PR352
4.7U_0603_6.3V6M
150U_D2_2V_Y
1
1 FSW : 750KHz
1
2 7
PG LDO VL
1
PC365
PC355
PC356
PC357
PC358
PC360
+
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
2
2
2
1
2@
PC359
@ PJ352
+5VALWP 1 2 +5VALW
1 2
5V_SN
2
JUMP_43X118
680P_0603_50V7K
1
@EMI@ PC352
2
A A
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+3VALW / +5VALW
5 4 3 2 1
5 4 3 2 1

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
Function Field :
D D
Regulator 35.3
Support 35.4
EMI Part 47.1
EMI@ PLW01
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PRW01
0_0603_5%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
BST_1.35V 1 2 BOOT_1.35V
+1.35VP
@EMI@ PCW17
EMI@ PCW18
1
1
PCW15
PCW16
DH_1.35V +0.675VSP
2
10U_0805_6.3V6K
10U_0805_6.3V6K
SW_1.35V
1
PCW01
PCW06
PCW07
+1.35VP
5
0.1U_0603_25V7K
16
17
18
19
20
2
2
Ipeak : 10A
PHASE
BOOT
VTT
UGATE
VLDOIN
21
PQW01 PAD
Imax : 7A AON7408L_DFN8-5 4 DL_1.35V 15 1
LGATE VTTGND
Iocp : 12A
C 14 2 C
FSW : 500KHz PLW03 1 PRW03 PGND VTTSNS
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 13.7K_0402_1% DIS@ PUW00
1 2 1 2 CS_1.35V 13 3
+1.35VP PCW14 CS RT8207MZQW_WQFN20_3X3 GND
1
1U_0603_10V6K
5
1 2 12 4 VTTREF_1.35V
VDDP VTTREF
FDMC7692S_MLP8-5
DIS@ PQW02
1 @EMI@ PRW02 PRW14

DIS@ PCW05
150U_D2_2V_Y
4.7_1206_5% 5.1_0603_5%
+ 1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1 2
VDD VDDQ
1
PGOOD
4 PCW10
TON
1
2 @EMI@ PCW02 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PCW13
+5VALW
2
1U_0603_10V6K
10
6
1
2
3
EN_0.675VSP
FB_1.35V
TON_1.35V
EN_1.35V
PRW10
8.06K_0402_1%
UMA@ PRW12
UMA@PRW12 1 2 +1.35VP
DIS@ PRW12 510K_0402_1%
825K_0402_1% 1.35V_B+ 1 2
1
@ PRW04 PRW11
0_0402_5% 10K_0402_1%
1 2
2
<36> SYSON
1
@ PCW12
B 0.1U_0402_10V7K B
2
@ PJW02 @PRW05
@ PRW05
+1.35VP 1 2 +1.35V 0_0402_5%
1 2 1 2
JUMP_43X118 <16> DDR_VTT_PG_CTRL
1
@ PCW11
0.1U_0402_10V7K
2
@ PJW04
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39
For UMA SKU +1.35V near HW VDDQ
+1.35VP UMA@ PUW00

22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
RT8207P
UMA@ PCW61
UMA@ PCW62
UMA@ PCW63
UMA@ PCW64
UMA@ PCW65
UMA@ PCW66
@UMA@ PCW67
@UMA@ PCW68
1
UMA@ PQW02
SI7716ADN-T1-GE3_POWERPAK8-5
A A
2
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+1.35V / +0.675VS
5 4 3 2 1
5 4 3 2 1

SY8206D_V1.mdd
D Function Field : D
Regulator 35.5
Support 35.6
EMI Part 47.1
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
@ PRH05
0_0402_5%
1 2
SUSP# <36,38,46>
1
PRH06 @ PCH11
1M_0402_1% 0.22U_0402_10V6K
2
2
@EMI@ PRH02 @EMI@ PCH02 +1.05VSP
4.7_1206_5% 680P_0603_50V7K
EMI@ PLH01 1 2 SNB_1.05V 1 2
HCB2012KF-121T50_0805 PUH00
Ipeak : 5A
B+ 1 2 B+_1.05V 8
IN EN
1 PRH01
0_0603_5%
PCH01
0.1U_0603_25V7K
Imax : 3.5A
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_1.05V 2 1 2 PLH03
C BS Iocp : 6A C
EMI@ PCH14
@EMI@ PCH15
1UH_PCMB063T-1R0MS_12A_20%
1
9
GND LX
10 LX_1.05V 1 2
+1.05VSP FSW : 800KHz
PCH12
PCH13
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
330P_0402_50V7K
15K_0402_1%
1
4
FB
PRH12
PCH18
PCH05
PCH06
PCH07
PCH08
3 7
+3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
@ PJH02
2
+3VS 1 2 +1.05V_PGOOD 2
PG LDO
5 LDO_3V +1.05VSP 1
1 2
2
+1.05VS_VTT
PCH17
PRH11
10K_0402_5% SY8206DQNC_QFN10_3X3 JUMP_43X118
1
<12,36> VCCST_PWRGD
PRH13
4.7U_0603_6.3V6K
20K_0402_1%
2
1
PCH16 Pin 7 BYP is for CS.

Common NB can delete +3VALW and PC15
2
The current limit is set to 6A, 8A or 12A when this pin

B is pull low, floating or pull high B
A A
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+1.05VS
5 4 3 2 1
5 4 3 2 1
SY8033_V1.mdd
Function Field :
D D
Regulator 35.15
Support 35.16 +0.95VGSP
EMI Part 47.1 Ipeak : 3A
Imax : 2.1A
Iocp : 4A
FSW : 1MHz
4
DIS@ PLF03
@ PJF01 10 2 LX_0.95V 1UH_PH041H-1R0MS_3.8A_20%
PG
+3VALW 1 2 PVIN LX 1 2
1 2 9 3 +0.95VGSP
PVIN LX
68P_0402_50V8J
JUMP_43X79 @ PJF02
1
4.7_0603_5%
@EMI@ PRF02
8 1 2
SVIN +0.95VGSP 1 2 +0.95VGS
22U_0603_6.3V6M
22U_0603_6.3V6M
DIS@ PCF12
DIS@ PCF10
22U_0805_6.3VAM 6 DIS@ PRF11 JUMP_43X79
2
FB
1
DIS@ PCF05
DIS@ PCF06
5 20K_0402_1%
2
EN
NC
NC
TP
2
DIS@ PRF04
2
0_0402_5%
11
1
1 2 +0.95VSP_ON FB_0.95V
<10,20,45,48,9> PXS_PWREN
0.1U_0402_16V7K
1
1
680P_0402_50V7K
@EMI@ PCF02
DIS@ PUF00
1
DIS@ PCF11
DIS@ PRF05 SY8033BDBC_DFN10_3X3
1M_0402_5% DIS@ PRF12
C 34K_0402_1% C
2
2
2
2
DIS@ PC1810 +1.8VGSP
22U_0805_6.3VAM
1 2
Ipeak :1A
@ PJ1801
Imax : 0.7A
JUMP_43X79
+3VALW 1 2 DIS@ PU1800
Iocp : 2.5A
1 2 SY8032ABC_SOT23-6 DIS@ PL1803
1UH_PH041H-1R0MS_3.8A_20%
FSW : 1MHz
4 3 LX_1.8V 1 2
IN LX +1.8VGSP
5 2
PG GND
68P_0402_50V8J
B @ PJ1802 B
22U_0603_6.3V6M
22U_0603_6.3V6M
6 1 1 2
FB EN +1.8VGSP 1 2 +1.8VGS
1
DIS@ PC1812
1
1
DIS@ PC1805
DIS@ PC1806
DIS@ PR1804 DIS@ PR1811 JUMP_43X79
0_0402_5% @EMI@ PR1802 20K_0402_1%
2
1 2 +1.8VSP_ON 4.7_0603_5%
<10,20,45,48,9> PXS_PWREN
2
0.1U_0402_16V7K
2
1
DIS@ PC1811
FB_1.8V
1
DIS@ PR1805
1M_0402_1%
1
2
1
2
@EMI@ PC1802 DIS@ PR1812

680P_0402_50V7K 10K_0402_1%
2
A A
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Note:Use VCCSA_SEL to switch High & Low Level for VID[1]
(ie. VCCSA_SEL) due to the VID[0] is don't care for this setting.
+0.95VGS / +1.8VS
5 4 3 2 1
5 4 3 2 1
APL5930_V1.mdd
Function Field :
D D
Regulator 35.31
Support 35.32
EMI Part 47.1
+3VALW +5VALW
1
+1.5VSP
1
PCM13
1
@ PJM01 1U_0402_6.3V6K
JUMP_43X39 Ipeak : 0.5A
2
2
Imax : 0.35A
2
PCM11 PUM00
Iocp : 4.2A
1
4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
6
5 VCNTL 3
2
@ PRM04 9 VIN VOUT 4
0_0402_5% VIN VOUT
+1.5VSP
1.54K_0402_1%
1 2 8 @ PJM02
<36,38,44> SUSP# 7 EN
1
+1.5V_EN 2 +1.5V_FB +1.5VSP 1 2 +1.5VS
GND
POK FB 1 2
PRM11
0.1U_0402_16V7K
PCM14
1
C 0.01U_0402_25V7K JUMP_43X79 C
2
1
1
PCM12
@ PRM05
@PRM05 PCM05
2
47K_0402_5% 22U_0603_6.3V6M
2
2
@
2
1
PRM12
1.74K_0402_1%
2
B B
A A
www.vinafix.vn
+1.5VS
5 4 3 2 1
5 4 3 2 1
TPS51622_V2A.mdd for IC portion
TPS51624_V2B.mdd for SW portion
VR_HOT#
PR606 10K ohm for 100 degree CPU
PR606 8K ohm for 110 degree Frequency = 1MHz
Function Field : OCP Current 39 A
D D
VREF DCR: 0.85m +-7% ohm
Regulator 36.1 PH601 B value: 4250k 1%
100K_0402_1%_TSM0B104F4251RZ
Driver 36.2 PH602 B value: 3435k 1%
1
IMON
Support 36.3
PHZ01
36.5K_0402_1%
75_0402_1%
681K_0402_1%
1
2 PRZ13 1
4700P_0402_25V7K
442K_0402_1%
Output Cap 36.4
@ PRZ17
PRZ15
@ PRZ22
PCZ12
1
PRZ19
Acoustic Cap 37.2 75_0402_1%
2
2
EMI Part 47.1
2
0.01U_0402_16V7K
VIN MAX 19.5V
2
SLEWA
1
9.09K_0402_1%
VIN MIN 12V
1
PRZ21
OCP-I B-RAMP F-IMAX O-USR
PCZ13
MAX current 32A
1
150K_0402_1%
20K_0402_1%
100K_0402_1%
56K_0402_1%
2
2 PRZ20 1
1
PRZ23 Thermal current 10A
PRZ14
PRZ18
PRZ16
39K_0402_1%
EMI@ PLZ01 Dynamic current 27A
FBMA-L11-201209-121LMA50T_0805
2
1 2 OCP 38.4A
2
Switching frequency 1.2MHz
1 2
B+ EMI@ PLZ02 CPU_B+ Boot voltage 1.7V
PRZ24 FBMA-L11-201209-121LMA50T_0805 1
10K_0402_5% DC Load- line 2m Ohm
CPU_B+ 1 2 PCZ31 +
33U_25V_M
C 2 C
16
15
14
13
12
11
10
PUZ00
OCP-I
THERM
VBAT
SLEWA
B-RAMP
F-IMAX
IMON
O-USR
@ PRZ07
0_0402_5%
CSP1 17 8 1 2
CSP1 VR_ON VR_ON <12>
PWM1
CSN1 18 7 SKIP# PUZ01
CSN1 SKIP# PCZ01 9 PLZ03
19 6 PWM1 0.1U_0402_25V6 8 PGND2 0.15UH_FDUE0630-HR1_40A_20%
CSN2 PWM1 1 2 7 PWM 4 LX_CORE 1 4
20 5 PRZ12 BOOT VSW 3 +CPU_CORE
CSP2 TPS51624RSM_QFN32_4X4 PWM2 1 2 1 2 6 PGND1 2 2 3
21 4 +1.05VS_VTT PRZ01 5 BOOT_R VDD 1 SKIP#-1
1 2 SKIP#
+3VS PU3 N/C 10K_0402_1% VIN SKIP#
EMI@ PRZ04
4.7_1206_5%
2.2_0603_5%
CSP
22 3 @ PRZ32
N/C PGOOD VGATE <12>
PRZ11 CSD97374CQ4M_SON8_3P5X4P5 0_0402_5%
VSSSENSE 23 2 1 2 CPU_B+ 1 2 CSP1
<12> VSS_SENSE GFB VDD +3VS
VR_HOT#
10K_0402_1%_TSM0A103F34D1RZ
1_0603_5% PRZ33
10U_0805_25V6K
10U_0805_25V6K
ALERT#
VCCSENSE 24 1
2200P_0402_50V7K
DROOP
<12> VCC_SENSE
2
VFB VDIO
COMP
1
680P_0603_50V7K
1U_0603_10V6K
0.1U_0402_25V6
VREF
1 2
VCLK
2.55K_0402_1%
GND
PAD
V5A
1
PCZ11
PCZ33
PCZ34
@EMI@ PCZ35
EMI@ PCZ04
PHZ02
EMI@PCZ36
0.15U_0402_10V6K
0.15U_0402_10V6K
PCZ19
9.53K_0402_1%
1U_0603_10V6K
25
26
27
28
29
30
31
32
33
1
2
1
PRZ34
PCZ20
PCZ21
3.01K_0402_1%
1
+5VS
2
PRZ35
@
2
B @ PCZ14 B
PRZ27
1 2 1 2
4.87K_0402_1%
2
100P_0402_50V8J
VR_SVID_ALRT#
1 PRZ25 2 CSN1
VREF
VR_SVID_DAT
VR_SVID_CLK
10K_0402_5%
1
PCZ16
1 2 1 2 0.33U_0603_10V7K +CPU_CORE
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PRZ26 PCZ15
4.75K_0402_1% 1500P_0402_50V7K
1
PCZ61
PCZ62
PCZ63
PCZ64
PCZ65
PCZ66
PCZ67
PCZ68
1 2
+5VALW
1U_0603_10V6K
PRZ28
1
PCZ17
2
10_0603_1%
+CPU_CORE
2
220U_D2 SX_2VY_R9M
+1.05VS_VTT 1
1
1
22U_0603_6.3V6M
PCZ69
22U_0603_6.3V6M
PCZ70
22U_0603_6.3V6M
PCZ71
22U_0603_6.3V6M
PCZ72
22U_0603_6.3V6M
PCZ73
22U_0603_6.3V6M
PCZ74
22U_0603_6.3V6M
@ PCZ75
22U_0603_6.3V6M
@ PCZ76
+
PCZ77
2
2
2@
130_0402_1%
54.9_0402_1%
1
<36> VR_HOT#
1
PRZ30
PRZ31
PCZ18
0.1U_0402_25V6
2
2
A VR_SVID_CLK A
<12> VR_SVID_CLK
VR_SVID_ALRT#
<12> VR_SVID_ALRT#
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VR_SVID_DAT
<12> VR_SVID_DAT

CPU_CORE
5 4 3 2 1
5 4 3 2 1
Function Field :
Regulator 43.1 Close VGA chip
Support 43.2 <19> VSSSENSE_VGA<19> VCCSENSE_VGA
Output Cap 43.9 Module model information
EMI@ PLV01
EMI Part 47.1 RT8880A_V1A.mdd for IC portion
1
PCV14 HCB2012KF-121T50_0805
0.01U_0402_50V7K 1 2
RT8880A_V1B.mdd for SW portion
2
VGA_B+ EMI@ PLV02
1 2 1 2 +VGA_CORE HCB2012KF-121T50_0805
1 2
PRV16 PRV15 B+
@ PCV13
5
D D
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
10_0402_5% 10_0402_5% 680P_0402_50V7K
@EMI@ PCV28
@EMI@PCV28
EMI@ PCV29
2 1
1
PCV26
PCV27
1 2
AON7518_DFN8-5
1
2K_0402_1%
PRV32
PQV03
PRV13
@PCV15
@ PCV15 0_0603_5%
2
330P_0402_50V7K UGATE2 1 2 4
PRV14 PRV12
10K_0402_1% @ 240K_0402_1% PHASE2
2
1 2 1 2
3
2
1
VGA_B+ BOOT2 1 2 BOOT2-11 2 1 4
+VGA_CORE
PCV12 PCV11 1 2
@EMI@ PRV05
@EMI@PRV05
2 3
4.7_1206_5%
560P_0402_50V7K 68P_0402_50V8J PRV02 PCV02 PLV04
1
1 2 1 2 PRV11 2.2_0603_1% 0.22U_0603_25V7K 0.22UH_PCME064T-R22MS0R985_28A _20%
100K_0402_1% PRV33
2.61K_0402_1%
AON7516_DFN8-5
1 2 1 2
PQV04
2
+5VS LGATE2 4 PCV30
UGATE2
BOOT2
COMP_VGA
SNB_APU2 .1U_0402_16V7K
TONSET
680P_0603_50V7K
@EMI@PCV05
PCV05
ISEN1N
ISEN2N
ISEN1P
ISEN2P
FB
+5VS
3
2
1
@EMI@
@PRV34
@ PRV34
4.12K_0402_1%
1 2
13
12
11
10
1
COMP
FB
ISEN3P
ISEN1P
ISEN2P
PWM3
BOOT2
UGATE2
VSEN
ISEN3N
ISEN1N
ISEN2N
TONSET
ISEN2P
ISEN2N-1
53
GND
14 52 PHASE2 PRV35
RGND PHASE2 787_0402_1%
IMON_VGA 15 51 LGATE2 ISEN2N 1 2
IMON LGATE2
0.1U_0402_25V6
PCV16 VREF_VGA 16 50 PVCC
V064 PVCC
PCV31
1U_0402_6.3V6K +1.8VGS
1 2 17 49 LGATE1
C
IMONA LGATE1 +5VS C
2
PRV36 VDDIO 18 48 PHASE1 PRV26 @
<18> DGPU_PWROK VDDIO PHASE1
0_0402_5% 0_0402_5%
1 2 19 47 UGATE1 PVCC 1 2
PWROK UGATE1
DGPU_PWRGD
20 PUV00 46 BOOT1
<19> SVI2_SVC SVC BOOT1
RT8880BGQW_WQFN52_6X6 VCC 1 2
21 45
2.2U_0603_10V7K
2.2U_0603_10V7K
<19> SVI2_SVD SVD LGATEA1 PRV27
1
22 44
PCV19
PCV18
<19> SVI2_SVT 10_0603_5%
SVT PHASEA1
30K_0402_1%
1
23 43
2
OFS UGATEA1
PRV17
24 42
OFSA BOOTA1
SET1 25 41 VGA_B+
2
SET1 PWMA2
SET2 26 40
SET2 TONSETA
10U_0805_25V6K
10U_0805_25V6K
PGOODA
ISENA2N
ISENA1N
ISENA2P
ISENA1P
@EMI@PCV22
PCV22
EMI@PCV23
PCV23
2200P_0402_50V7K
0.1U_0402_25V6
PGOOD
COMPA
VSENA
OCP_L
IBIAS
100K_0402_1%_TSM0B104F4251RZ
VCC
FBA
1
PCV20
PCV21
PRV18
EN
AON7518_DFN8-5
@EMI@
EMI@
3.6K_0402_1% PRV28
PQV01
1 2 0_0603_5%
27
28
29
30
31
32
33
34
35
36
37
38
39
2
UGATE1 1 2 4
1
<18,9> DGPU_PWRGD
PHV01
PRV19 PHASE1
IBIAS
VCC
21K_0402_1%
3
2
1
OCP_L <19> BOOT11 2 1
BOOT1-1 2 1 4
+VGA_CORE
2
VREF_VGA 1 2
Pull high at HW side +3VS
@EMI@ PRV04
@EMI@PRV04
2 3
4.7_1206_5%
+5VS PRV01 PCV01 PLV03
1
1
100K_0402_1%
PRV25 2.2_0603_1% 0.22U_0603_25V7K 0.22UH_PCME064T-R22MS0R985_28A _20%

0.47U_0402_6.3V6K
100K_0402_5% PRV29
1
PCV17
PRV24
2.61K_0402_1%
AON7516_DFN8-5
PXS_PWREN <10,20,45,9> 1 2 1 2
0.1U_0402_25V6
PQV02
2
2
1
PCV32
LGATE1 4 PCV24
SNB_APU1 .1U_0402_16V7K
680P_0603_50V7K
2
B B
@EMI@ PCV04
@EMI@PCV04
3
2
1
2
@ PRV30
@PRV30
SET1
4.12K_0402_1%
PRV21 PRV20 1 2
20.5K_0402_1% 124K_0402_1%
1 2 1 2
ISEN1P
ISEN1N-1
PRV23 PRV22 +5VS
470_0402_1% 124K_0402_1%
1 2 1 2 +VGA_CORE PRV31
787_0402_1%
2.2uF x 16pcs ISEN1N 1 2
SET2
0.1U_0402_25V6
1
PCV25
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2
1
1
PC702
PC703
PC704
PC705
PC706
PC707
PC708
PC709
PC710
PC711
PC712
PC713
PC714
PC715
PC716
PC717
@
2
2
VGA_CORE
TDC 24A
EDC 36A
+VGA_CORE +VGA_CORE
OCP current > 43.2A
1uF x 2pcs 10uF x 8pcs Load line -1mV/A
FSW=450kHz
DCR 0.98mohm +/-5%
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
1U_0402_6.3V6K
330U_D2_2V_Y
560U_D2_2V_Y
1 1
TYP MAX
1
+ +
PC718
PC719
PC720
PC721
PC722
PC723
PC724
PC725
PC726
PC727
PC728
PC729
PC700
PC701
A
H/S Rds(on) : 27mohm , 34mohm A
2
2 2
L/S Rds(on) : 5.3mohm , 6.5mohm
www.vinafix.vn
0.1uF x 2pcs
Issued Date Title
Deciphered Date
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom ZSWAA/ZCWAA LA-B301P 1.0
5 4 3 2 1
5 4 3 2 1
PWR PIR (Product Improve Record)

ZSWAA LA-B301P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
PVT GERBER_OUT DATE: 2013/12/02
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
Item Date Page Action Component Request
D
----------------------------------------------------------------------------------------------------------------------------------------------------------------- D
1) 11/21 48 Change PRZ12 change to 10K and pull high +1.05VS_VTT For design change
2) 11/21 48 Delete PRZ29 removed HW portion pull high
5) 11/25 41,48 Change PH1,PHZ01 part number change to SL200002H00 change for common PN
6) 11/25 48 Change PHZ02 part number change to SL200002F00 change for common PN
7) 11/25 42 Change change PQB03 to SB00000NW00 AON6414AL change for allocation
8) 12/03 48 Change PRZ27 change to 4.87K change for compensation
9) 12/03 41 Change PF2 change to 1206 footprint component SP040005P00 for ME limitation
10) 12/03 44 Change change PQW02 to SB00000GW00 SI7716 at UMA SKU change for allocation
11) 12/03 48 Change PRZ19 change to 316K for CPU core conversation fine tune
12) 12/03 48 Change PRZ20 change to 56K for CPU core conversation fine tune

PV REGRESSION GERBER_OUT DATE: 2014/01/06
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
13) 01/03 40 Change change DC in jack footprint for customer request
C
14) 01/03 43 Add Add PR312 0ohm 0402 for HW 5V drop fine tune C
15) 01/08 43 Change change PR312 to 15ohm for HW 5V drop fine tune
16) 01/08 47 Change change PRZ19 to 442kohm for CPU core conversation fine tune
17) 01/15 41 Delete PCB10 2200p for B2B fine tune
18) 01/15 41 Change PCB11 0.1u change to 0.01u for B2B fine tune
19) 01/16 43 Add PR302,PC302 mount and PC302 change to 470p for EMI request
20) 01/16 42 change PCB16 2200p change to 0.047u for decoupling cap fine tune
21) 01/22 47 Add PRZ04,PCZ04 mount for EMI request
22) 01/22 41 Add PRB02,PCB02 mount for EMI request
23) 01/22 47 change PCZ31 100u change to 33u for sourcer request

Pre-MP GERBER_OUT DATE: 2014/02/10
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
24) 02/07 42 Delete remove PR312 15ohm for HW request
25) 02/07 48 Change change net name from VREF to VREF_VGA resolve duplicate net name
B
change net name from VREF to IMON_VGA B
change net name from VREF to COMP_VGA
26) 02/10 42,44,46 Change change PR311,PRH05,PRM04 footprint to 0ohm shortpad common design rule
A A
www.vinafix.vn
Power-PIR
Custom 1.0
5 4 3 2 1
5 4 3 2 1
HW PIR (Product Improve Record)

ZSWAA LA-B301P Schematic Change List
REVISION: 0.1
Gerber-out date: 2013/10/29

D
---------------------------------------------------------------------------------------------------------------------------------------------- D
1) 10/15 37 Add CB14 on SUSP# For ESD request
2) 10/15 16,17 Change Swap DDR data of JDIMM1 & JDIMM2 For common module layout
3) 10/15 08 Add RH91 on CLK_REQ_VGA# For follow AMD GPU reference schematic
4) 10/15 34 Reserve CR6 to +5VALW For power switch common design
5) 10/15 35 Add CR2,CR3,CR5 to +USB_VCCB For power switch common design
6) 10/16 37 Add RB11,RB12 For colay EC 9022
7) 10/16 37 Add RB13,RB14 For colay Normal pad & Click pad
8) 10/17 38 Add R8,R9 For colay Normal pad & Click pad
9) 10/17 27 Add R15,C29 on LCD_ENVDD For tune LCD_VDD sequence
10) 10/18 34 Swap LR9 For smooth USB signal
11) 10/18 37 Change DFAN1 to Pin 70 For EC request
12) 10/20 34 Remove RT2, RT3 For no need
13) 10/22 39 Change RM5,RM6,RM7 to 0_0805 For max current design
14) 10/22 10 Add Test point on GPIO10 For SW debug
15) 10/22 07 Add Test point on GPIO34 For SW debug
16) 10/23 16 Reserve 0_0805 For DQA's experiment
17) 10/23 05 Change R23 to 121_0402_1% For Intel check list
C
18) 10/23 38 Remove SW2 For layout space concern C
19) 10/23 30 Reserve RD11, RD12 For Intel check list
20) 10/24 08 Change Y2 to 4 pin For common part
21) 10/24 10 Add RH4, RH6, RH9, RH10 For SW request
22) 10/24 26 Change RT1 from 0603 to 0805 For current concern
23) 10/24 09 Add RH7, RH8 For SW request
24) 10/24 27 Change JTOUCH from 4pin to 6pin For module pin define
25) 10/27 20 Change QV5 to AO4354 For sourcer request
26) 10/27 34 Change UT1 P/N to SA00007IO00 For TPM2.0
B B
A A
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HW-PIR
1.0
5 4 3 2 1
5 4 3 2 1

REVISION: 0.2

D
---------------------------------------------------------------------------------------------------------------------------------------------- D
01) 11/22 36 Delete RA22 For audio codec
02) 11/22 36 Add Add a reserve 0ohm resistor RA25 For EMI request
03) 11/22 27 Change Change D15 P/N from SCS00002G00 to SCS00000Z00 For material shortage
04) 11/22 27,29,34,35 Change Change L10,L11,L62,L71,L72,L8,L9,LR7,LR8,LR9 P/N
from SM070003Y00 to SM070003K00 For material shortage
05) 11/22 05 Change Change R184 from SD013470080 to SD028470080 The same as CRB board
06) 11/26 26 Change Change RT14 config. from @ to LVDS@ For BKOFF circuit
07) 11/26 09 Change Change RH19 config. to IEDP@ For BKOFF circuit
08) 11/26 09 Connect Connect EC_ENBKL_R_CPU to AND GATE U50.1 For BKOFF circuit
09) 11/26 27 Change Change U50.1 from EC_ENBKL_R to EC_ENBKL_R_CPU For BKOFF circuit
10) 11/26 27 Change Change U50 and R433 config. from IEDP@ to always mount For BKOFF circuit
11) 11/26 27 Change Change D15 and R436 config. from LVDS@ to @ For BKOFF circuit
12) 11/26 36 Change Change UB1.26 (EC GPIO12) from NC to TRANS_PRSNT For BKOFF circuit
13) 11/26 36 Add Add a pull high 10Kohm (RB23) to +3VL and a pull down
10Kohm (RB22) to GND on TRANS_PRSNT For BKOFF circuit
14) 11/27 27 Change Change D15 P/N from SCS00000Z00 to SCS0340L010 For BOM reduce
15) 11/27 29 Change Change UD1.25, UD1.31, UD1.22, UD1.32 from
C
+1.8VS_RXVCC to +1.8VS_CRT For DP to CRT translator C
16) 11/27 29 Change UD1.45 pull high from +3VS to +3VS_6513 For DP to CRT translator
17) 11/27 29 Add Add test point on UD1.37 For DP to CRT translator
18) 11/27 29 Add Add RPD2 symbol for 150ohm For DP to CRT translator
19) 11/27 33 Change Change LAN/USB Small board Connector pin
(JLAN.3 to JLAN.6) define For LAN/USB Small board
20) 11/27 35 Change Change UA1 all analog outpout net name to PR_L/PR_R Unify net name
21) 11/27 35 Change Change CA15 0.1u cap from 16V4Z to 10V7K Don't need to use 16V4Z
22) 11/27 35 Change Add net name Line1-L_C & Line1-L_R on UA1 pin 21.22 For trace length table
23) 11/27 35 Detete Delete ALC233 co-lay component RA6, RA30, UA1 Change to ALC233VB Only
24) 11/27 35 Change Swap RA21 & RA22 BOM structure Balance caps alignment
25) 11/28 29 Change Change test point T2 to a pull high 10Kohm (RD13)
to +3VS_6513 For DP to CRT translator
26) 11/28 27 Add Add a reserved ESD diode (D92) for JTOUCH For ESD requeset
27) 11/28 07 Change Change Dual ESD diode (D13) to two single diodes
(D16,D17) For RTC circuit
28) 11/28 07 Change Change R437.1 connecting from +RTCBATT to +RTCVCC For RTC circuit
29) 11/29 07 Change Change R437 from 0ohm to 1kohm For RTC circuit
B
30) 11/29 33,37 Change Change L56,L57 from SM070001U00 to SM070003K00 For EMI request B
31) 11/29 33,37 Change Change L56,L57 from @EMI@ to EMI@ For EMI request
32) 11/29 33,37 Change Change R4,R5,R6,R7 from EMI@ to @EMI@ For EMI request
33) 11/29 34 Change Change CR2,CR3,CR5 from 22U_0603 to 22U_0805 For droop issue
34) 11/29 35 Change Change CA15 from SE076104K80 to SE102104K00 For BOM change
35) 11/29 07 Change Change R277.2 net name from N113579902 to +RTCBATT_R For RTC circuit
36) 12/01 33,37 Change Swap L56,L57 pin define For layout request
37) 12/01 27 Add Add R9,R11 on EMI camera choke For EMI request
38) 12/01 27 Change Change L62 from CAM_EMI@ to @CAM_EMI@ For EMI request
A A
www.vinafix.vn
HW-PIR-2
1.0
5 4 3 2 1
5 4 3 2 1

REVISION: 0.3

----------------------------------------------------------------------------------------------------------------------------------------------
D 01) 12/12 09 Change Change RH19 BOM structure from IEDP@ to always mount For LVDS & eDP cost down plan D
02) 12/12 26 Change Change RT14 BOM structure from LVDS@ to @ For LVDS & eDP cost down plan
03) 12/12 27 Delete Delete U50,R433 For LVDS & eDP cost down plan
04) 12/12 27 Change Change D15,R436 BOM structure from @ to always mount For LVDS & eDP cost down plan
05) 12/12 36 Change Change RB22 BOM structure from @ to IEDP@ For LVDS & eDP cost down plan
06) 12/12 36 Change Change RB23 BOM structure from @ to LVDS@ For LVDS & eDP cost down plan
07) 12/12 07 Change Change R277,D17 BOM structure from always mount to @ For RTC circuit
08) 12/12 07 Change Change R437 BOM structure from @ to always mount For RTC circuit
09) 12/30 11 Add Add two reserved resistors R167,R168 For no use USB over current
10) 12/30 11 Change Change UC1.AL3 connect to USB_OC#0_R For no use USB over current
11) 12/30 11 Change Change UC1.AH2 connect to USB_OC#2_R For no use USB over current
12) 01/03 34 Add Add a reserved capacitor CR7 on +USB_VCCB For USB
13) 01/03 13 Add Add a jumper PJ2 between +3VALW to +3VALW_PCH For +3VALW to +3VALW_PCH
14) 01/06 38 Add Add C549 and C550 For ESD's request
15) 01/06 37 Change Change JLED footprint from E-T_6916K-Q06N-00L_6P
to ACES_51524-0060N-001_6P For DFX's request
16) 01/06 37 Change Change JPWR footprint from E-T_6916K-Q04N-03R_4P
to ACES_50504-0040N-001_4P For DFX's request
C 17) 01/06 35 Change Change UA1 Compal PN from SA00007BF00 to SA00007BF10 For audio codec C
18) 01/07 13 Change Change CH111,CH112,CH113,Q10,RH3 BOM structure

from always mount to @ For +3VALW to +3VALW_PCH
19) 01/14 27 Change Change D29 BOM structure from @ESD@ to ESD@ For ESD's request

REVISION: 1.0

----------------------------------------------------------------------------------------------------------------------------------------------
01) 01/21 07,09,27 Change Change D90,D91,D15,D16,D21,D17 from SCS0340L010
to SCS00003500. For X code
02) 01/21 31 Change Change JHDD footprint from SANTA_191503-1_22P-T
to LCN_ASF98-2231S10-0002_22P. For DFX's request
03) 01/21 37 Change/Add Change CPU R1 BOM config and add R3 BOM config For CPU BOM config
04) 01/29 33,36 Add Add a GPIO pin LAN_OFF# for UB1.25 and connected to
B JLAN.3 For Disable/Enable LAN chip B
05) 01/29 36 Add Add a GPIO pin PCH_RTCRST#_R for UB1.18 and connected
to a 0ohm resistor (RB29) and connected to PCH_RTCRST#. For RTC reset
06) 01/29 34 Add Add a reserved capacitor 100uF (CR14) for +USB_VCCB. For USB droop
07) 02/05 07,09,27,35 Change Change 0ohm resistor (RH19,R436,R32,R431,R432,RA11,
RA1,RA2,RA10,R106) footprint to 0ohm short pad. For 0ohm short pad
08) 02/05 35 Delete/Change Delete RA13,RA18 and change UA1.18 to EXT_MIC
and UA1.20 to +3VALW For audio codec
09) 02/05 37 Change Change SW3 BOM config from mount to un-mount. For Pre-MP phase
10) 02/06 26,27,29,35 Change Change 0ohm resistor (RT1,RD1,LD2,RA20,RA21,R4280,
R4281,R11,R9) footprint to 0ohm short pad,
and BOM config to Rshort@. For 0ohm short pad
11) 02/07 07,09,12,27 Change Change 0ohm resistor (RH19,R65,R178,R235,R174,R211,

,35,16,17,36 R212,R231,R436,LA1,LA3,RB34,RB1,R32,R431,R432,RA32,
RA33,RA34,RA35,RA11,RA1,RA2,RA10,R106) BOM config
to Rshort@. For 0ohm short pad
12) 02/07 34 Delete Delete CR7. For USB droop
A 13) 02/07 38 Change Change 0ohm resistor (RM3,RM5) footprint to 0ohm A
short pad, and BOM config to Rshort@. For 0ohm short pad
14) 02/10 37 Change Change screw hole size for H1,H2,H3. For ME's request
www.vinafix.vn
HW-PIR-3
1.0
5 4 3 2 1

Compal La-B301p Zswaa r10 - Pre-Mp - 20140210a

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Compal La-B301p Zswaa r10 - Pre-Mp - 20140210a

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A B C D E

AMD GPU Jet Pro/Topaz XT S3 (Single Rank)

LA-B301P REV 1.0 Schematic

Intel Processor (Haswell ULT/Broadwell U)

HDMI Conn. Touch Screen

Lynx Point - LP/

Wildcat Point - LP 5V 480MHz USB20 port 7

NGFF Slot 1 PCIe Gen1 1x PCH SATA HDD/SSD

1168pin BGA DP 2X 5.4GT/s DP to CRT Translator

LPC BUS HD Audio

DESIGN CURRENT 2A +LCD_VDD

SYSON: Enable 1.35V

DESIGN CURRENT 1.5A +0.675VS

( O MEANS ON X MEANS OFF )

Explain SA000072Q70 SA00006SM80 SA00006SXA0 SA00007LM00 SA00007LO00 SA00007LN00

BTO 4005UR1@ 4200UR1@ 4010UR1@ 2990UR1@ 4210UR1@ 4015UR1@

Description EMI CAM_EMI CRT_EMI TPM_EMI TOUCH_EMI

Explain EMI CAM_EMI CRT_EMI TPM_EMI TOUCH_EMI

EC SM Bus1 Address EC SM Bus2 Address

Power Device HEX Address Power Device HEX Address

S1(Power On Suspend) HIGH HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

AMD GPU G3 LOW LOW LOW

CRT@ C76 1 2 0.1U_0402_16V7K H_DP1_N0 C54 C45

R23 1 2 121_0402_1% SM_RCOMP1 AV60 DDR3 H63 BPM#5 @ T151

DDR3 Compensation Signals

XDP_TDI R87 1 XDP@ 2 51_0402_5%

XDP_PREQ# R88 1 @ 2 51_0402_5%

XDP_TDO R89 1 XDP@ 2 51_0402_5%

XDP_TCK R90 1 XDP@ 2 51_0402_5%

XDP_TRST# R91 1 @ 2 51_0402_5%

DDR_A_D0 AH63 AU37

HDA for AUDIO

<36> PWRME_CTRL 1 Rshort@ 2

2 +FAN2 3 VIN GND 6 R29 10K_0402_5%

2nd source SA00005JO00

0812 -> Add R277 for RTC reserve charge

A Change D16,D17 P/N from A

C43 A25 PCH_X1

CLKREQ_WLAN# pull high on page 10

+3VS AU14 AN2

AC2 SPI C-LINK AF4 @ T25

PCH_SMBDATA pull high on page 10

RH16 2 1 1K_0402_5% PCH_SPIDO3 PCH_SMBCLK 3 4

@ESD@ R206 SYSTEM POWER MANAGEMENT

<36,41> ACIN 1 2 PCH_ACIN

Change D21 P/N from 1: Port B or C is detected

RH7 HASW ELL@ 0_0402_5% T26 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6

T162 @ P1 D60 H_THERMTRIP#

PM_I2CSDA1 R274 1 @ 2 1K_0402_5%

+3VS PM_I2CSCL1 R272 1 @ 2 1K_0402_5%

10K_0402_5% ZPODD@ R269 1 @ 2 1K_0402_1% PCH_SPKR

ZPODD SKU 1 SPKR / GPIO81 : NO REBOOT

1: Intel ME TLS with confidentiality 1: ENABLED 1: ENABLED (Have internal PU)

PCIE_GTX_C_CRX_N0 F10 AN8

<33> PCIE_PRX_C_LANTX_N3 G11

+3VALW _PCH C167 G23

C 2 0_0402_5% T46 @ P61 RSVD_TP VCC G33 C

43_0402_1% VCC VCC

VCC_SENSE_R 2 Rshort@ 1 R178

<14> VSS_SENSE_R 2 Rshort@ 1 R235

R233 Security Classification Compal Secret Data Compal Electronics, Inc.

K9 +3VALW _PCH +RTCVCC