Computer Architecture

Deepak John
COE,Poonjar
 COMPUTER TYPES

Computers are classified based on the

parameters like
• Speed of operation
• Cost
• Computational power
• Type of application

Deepak John, Department Of IT ,COE ,Poonjar

DESK TOP COMPUTER

• Processing &storage units, visual display &audio uits,

keyboards
• Storage media-Hard disks, CD-ROMs
• Eg: Personal computers which is used in homes and offices
• Advantage: Cost effective, easy to operate, suitable for general
purpose educational or business application
NOTEBOOK COMPUTER

• Compact form of personal computer (laptop)

• Advantage is portability

Deepak John, Department Of IT ,COE ,Poonjar

WORK STATIONS
• More computational power than PC
•Costlier
•Used to solve complex problems which arises in
engineering application (graphics, CAD/CAM etc)

ENTERPRISE SYSTEM (MAINFRAME)

•More computational power
•Larger storage capacity
•Used for business data processing in large organization
•Commonly referred as servers or super computers

Deepak John, Department Of IT ,COE ,Poonjar

SERVER SYSTEM

• Supports large volumes of data which frequently need to

be accessed or to be modified
•Supports request response operation

SUPER COMPUTERS

•Faster than mainframes

•Helps in calculating large scale numerical and algorithm
calculation in short span of time
•Used for aircraft design and testing, military application
and weather forecasting
Deepak John, Department Of IT ,COE ,Poonjar
 Basic Terminology
• Computer
– A device that accepts
input, processes data,
stores data, and produces
output, all according to a
series of stored
instructions.
• Hardware
– Includes the electronic and
mechanical devices that
process the data; refers to
the computer as well as
peripheral devices.
Deepak John, Department Of IT ,COE ,Poonjar
• Software
– A computer program that
tells the computer how to
perform particular tasks.
• Network
– Two or more computers and
other devices that are
connected, for the purpose
of sharing data and
programs.
• Peripheral devices
– Used to expand the
computer’s input, output
and storage capabilities.
 Basic Terminology
• Input
– Whatever is put into a computer system.
• Data
– Refers to the symbols that represent facts, objects, or ideas.
• Output
– Consists of the processing results produced by a computer.
• Processing
– Manipulation of the data in many ways.
• Memory
– Area of the computer that temporarily holds data waiting to be
processed, stored, or output.
• Storage
– Area of the computer that holds data on a permanent basis when
it is not immediately needed for processing.

Deepak John, Department Of IT ,COE ,Poonjar

 Basic Terminology

•Assembly language program (ALP) – Programs are written

using mnemonics

•Mnemonic – Instruction will be in the form of English like form

•Assembler – is a software which converts ALP to MLL

(Machine Level Language)

•HLL (High Level Language) – Programs are written using

English like statements

•Compiler - Convert HLL to MLL, does this job by reading

source program at once

Deepak John, Department Of IT ,COE ,Poonjar

 Basic Terminology
•Interpreter – Converts HLL to MLL, does this job statement
by statement

•System software – Program routines which aid the user in

the execution of programs eg: Assemblers, Compilers

•Operating system – Collection of routines responsible for

controlling and coordinating all the activities in a computer
system

Deepak John, Department Of IT ,COE ,Poonjar

 FUNCTIONAL UNITS OF COMPUTER
• Input Unit
• Output Unit
• Central processing Unit (ALU and Control Units)
• Memory
• Bus Structure
Processor
Input
Control
Memory

ALU
Output

Deepak John, Department Of IT ,COE ,Poonjar

INPUT UNIT:
•Converts the external world data to a binary format, which can be
understood by CPU
•Eg: Keyboard, Mouse, Joystick etc
OUTPUT UNIT:
•Converts the binary format data to a format that a common man can
understand
•Eg: Monitor, Printer, LCD, LED etc
CPU
•The “brain” of the machine
•Responsible for carrying out computational task
•Contains ALU, CU, Registers
•ALU Performs Arithmetic and logical operations
•CU Provides control signals in accordance with some timings which in
turn controls the execution process
•Register Stores data and result and speeds up the operation

Deepak John, Department Of IT ,COE ,Poonjar

MEMORY
•Stores data, results, programs
•Two class of storage
(i) Primary (ii) Secondary
•Two types are RAM or R/W memory and ROM read only memory
•ROM is used to store data and program which is not going to change.
•Secondary storage is used for bulk storage or mass storage

Deepak John, Department Of IT ,COE ,Poonjar

 Basic Operational Concepts
Basic Function of Computer
• To Execute a given task as per the appropriate program
• Program consists of list of instructions stored in memory

Interconnection between
Processor and Memory

Deepak John, Department Of IT ,COE ,Poonjar

Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are
 Two registers-MAR (Memory Address Register) and MDR
(Memory Data Register) : To handle the data transfer
between main memory and processor. MAR-Holds addresses,
MDR-Holds data
 Instruction register (IR) : Hold the Instructions that is
currently being executed
 Program counter: Points to the next instructions that is to
be fetched from memory
Deepak John, Department Of IT ,COE ,Poonjar
 Typical Operating Steps
• Programs reside in the memory through input
devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded
into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
Deepak John, Department Of IT ,COE ,Poonjar
 Typical Operating Steps (Cont’)
• Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to
the next instruction
Deepak John, Department Of IT ,COE ,Poonjar
 BUS STRUCTURE
Connecting CPU and memory
The CPU and memory are normally connected by three
groups of connections, each called a bus: data bus, address
bus and control bus

Connecting CPU and memory using three buses

Deepak John, Department Of IT ,COE ,Poonjar
 Bus Structure
• Single-bus

Deepak John, Department Of IT ,COE ,Poonjar

 Speed Issue
• Different devices have different
transfer/operate speed.
• If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be
very low.
• How to solve this?
• A common approach – use buffers.

Deepak John, Department Of IT ,COE ,Poonjar

Memory Locations, Addresses,
and Operations
• Memory consists of n bits

many millions of first word

storage cells, each of second word

which can store 1 bit.

• Data is usually •
•
accessed in n-bit •
groups. n is called
word length. i th word

•
•
•

last word

Figure Memory words.

Deepak John, Department Of IT ,COE ,Poonjar

• A k-bit address memory has 2k memory locations, namely
0 – 2k-1, called memory space.
24-bit memory: 224 = 16,777,216 = 16M (1M=220)
32-bit memory: 232 = 4G (1G=230)
• byte-addressable memory.
• Byte locations have addresses 0, 1, 2, … If word length is
32 bits, the successive words are located at addresses 0,
4, 8,…

Deepak John, Department Of IT ,COE ,Poonjar

 Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the
word
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure . Byte and word addressing.

Deepak John, Department Of IT ,COE ,Poonjar
• Address ordering of bytes
• Word alignment
– Words are said to be aligned in memory if they
begin at a byte address. that is a multiple of the
num of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….

Deepak John, Department Of IT ,COE ,Poonjar

Instruction and Instruction
Sequencing
 “Must-Perform” Operations
• Data transfers between the memory and the
processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

Deepak John, Department Of IT ,COE ,Poonjar

 Register Transfer Notation
• Identify a location by a symbolic name standing
for its hardware binary address (LOC, R0,…)
• Contents of a location are denoted by placing
square brackets around the name of the location
(R1←[LOC], R3 ←[R1]+[R2])
Assembly Language Notation
 Represent machine instructions and programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]

Deepak John, Department Of IT ,COE ,Poonjar

 CPU Organization
• Single Accumulator
– Result usually goes to the Accumulator
– Accumulator has to be saved to memory quite often
• General Register
– Registers hold operands thus reduce memory traffic
– Register bookkeeping
• Stack
– Operands and result are always in the stack

Deepak John, Department Of IT ,COE ,Poonjar

 Instruction Formats
• Three-Address Instructions
– ADD R1, R2, R3 R1 ← R2 + R3
• Two-Address Instructions
– ADD R1, R2 R1 ← R1 + R2
• One-Address Instructions
– ADD M AC ← AC + M
• Zero-Address Instructions
– ADD TOS ← TOS + (TOS – 1)

Opcode Operand(s) or Address(es)

Deepak John, Department Of IT ,COE ,Poonjar

 Instruction Formats
Example: Evaluate (A+B) ∗ (C+D)
• Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1 ∗ R2

Deepak John, Department Of IT ,COE ,Poonjar

 Instruction Formats
Example: Evaluate (A+B) ∗ (C+D)
• Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1 ∗ R2
6. MOV X, R1 ; M[X] ← R1

Deepak John, Department Of IT ,COE ,Poonjar

 Instruction Execution and Straight-
Line Sequencing
Address Contents
For executing the pgm,address of
Begin execution here i Move A,R0
3-instruction first instruction placed in PC and
i+4 Add B,R0 program
segment the processor control circuits use
i+8 Move R0,C the information in the PC to fetch
and execute instructions, one at a
time ,in the order of increasing
A addresses is called straight line
sequencing

B Data for
the program

Two-phase procedure
-Instruction fetch
C
-Instruction execute

Figure A program for C ← [Α] + [Β].

Deepak John, Department Of IT ,COE ,Poonjar

Instruction Execution
Instruction execution is a 3-phase process:
instr fetch:
select an instr. from MM based on the current value of
the PC & place it in the IR.
instr decode:
decode and fetch the operand values.
instr execute:
perform the appropriate data transformations and
store the results. In the case of sequencing/branch
instructions, updatethe PC if necessary.

Deepak John, Department Of IT ,COE ,Poonjar

 BRANCHING

A straight line program for adding n

numbers Using a loop to add n numbers
Deepak John, Department Of IT ,COE ,Poonjar
 BRANCHING
• Branch instruction are those which changes the normal
sequence of execution.
• Sequence can be changed either conditionally or
unconditionally.
• Accordingly we have conditional branch instructions and
unconditional branch instruction.
• Conditional branch instruction changes the sequence
only when certain conditions are met.
• Unconditional branch instruction changes the sequence
of execution irrespective of condition of the results.

Deepak John, Department Of IT ,COE ,Poonjar

 Condition Codes
• Condition code flags
• Condition code register / status register
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
• Different instructions affect different flags

Deepak John, Department Of IT ,COE ,Poonjar

Addressing Modes
• The different ways in which the location of an operand is specified in
an instruction are referred to as addressing modes.
Name Assembler syntax Addressingfunction
Register Mode-Operand is
Immediate #Value Op erand = Value
the contents of a processor
register Register Ri EA = Ri
Absolute Mode -Operand Absolute(Direct) LOC EA = LOC
is in a memory Location
Effective Address:is any Indirect (Ri ) EA = [Ri ]
operand to an instruction (LOC) EA = [LOC]
which references memory. Index X(R i) EA = [Ri ] + X

Basewith index (Ri ,Rj ) EA = [Ri ] + [Rj ]

Basewith index X(R i,Rj ) EA = [Ri ] + [Rj ] + X
and offset

Relative X(PC) EA = [PC] + X

Autoincrement (Ri )+ EA = [Ri ] ;

Increment Ri

Autodecrement − (Ri ) Decrement Ri ;

EA = [Ri]

Deepak John, Department Of IT ,COE ,Poonjar

 Immediate Addressing
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
Instruction

Opcode Operand

Deepak John, Department Of IT ,COE ,Poonjar

 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
Instruction

Opcode Address A Memory

Operand

Deepak John, Department Of IT ,COE ,Poonjar

 Indirect Addressing
• Effective address of the operand is the contents of a register or
memory location whose address appears in the instruction.
• EA = (A)
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to accumulator.
• Multiple memory accesses to find operand, Hence slower
Instruction

Opcode Address A
Memory

Pointer to operand

Operand

Deepak John, Department Of IT ,COE ,Poonjar

 Register Addressing
• Operand is held in register named in address filed
• EA = R
– Shorter instructions
– Faster instruction fetch
• No memory access,Very fast execution
• Ex:Add R4,R3 ie R4 <- R4 + R3

Instruction

Opcode Register Address R

Registers

Operand
Deepak John, Department Of IT ,COE ,Poonjar
 Register Indirect Addressing
• EA = (R)
• Operand is in memory cell pointed to by contents of
register R
• Mov (R1),A

Instruction

Opcode Register Address R

Registers Memory

Pointer to Operand Operand

Deepak John, Department Of IT ,COE ,Poonjar

 Autoincrement / Autodecrement
 Access & update in 1 instr.
• Relative Address
-EA = PC + Relative Addr 0
1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
103
104

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• Indexed
– EA = Index Register + Relative Addr

XR = 2

100
AR = 100
101
102 1 1 0 A
103
104

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• Base Register
– EA = Base Register + Relative Addr

AR = 2

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array

Deepak John, Department Of IT ,COE ,Poonjar

 Indexing and Arrays
• Index mode – the effective address of the operand is
generated by adding a constant value to the contents of a
register.
• Index register
X(Ri): EA = X + [Ri]
• The constant X may be given either as an explicit number
or as a symbolic name representing a numerical value.

Deepak John, Department Of IT ,COE ,Poonjar

 Relative Addressing
• Relative mode – the effective address is determined by
the Index mode using the program counter in place of
the general-purpose register.
• X(PC) – note that X is a signed number
• Branch>0 LOOP
• This location is computed by specifying it as an offset
from the current value of PC.
• Branch target may be either before or after the branch
instruction, the offset is given as a singed num.

Deepak John, Department Of IT ,COE ,Poonjar

Assembly Language
 Assembly Language Instructions
• Built from two pieces
Add R1, R3, 3

Opcode Operands
What to do with the data Where to get data and
(ALU operation) put the results
• An instruction has the following format:

Deepak John, Department Of IT ,COE ,Poonjar

 Types of Instructions
• Data Transfer Arithmetic
Instructions
Name Mnemonic
Name Mnemonic
Load LD
Increment INC
Store ST
Decrement DEC
Move MOV Add ADD
Exchange XCH Subtract SUB
Input IN Multiply MUL
Output OUT Divide DIV
Push PUSH Add with carry ADDC
Pop POP Subtract with borrow SUBB
Negate NEG

Deepak John, Department Of IT ,COE ,Poonjar

 Data Manipulation Instructions
• Logical & Bit Manipulation
• Shift
Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right through carry RORC
Complement carry COMC Rotate left through carry ROLC
Enable interrupt EI
Disable interrupt DI

Deepak John, Department Of IT ,COE ,Poonjar

Program Control Instructions
Name Mnemonic Conditional Branch Instructions
Branch BR
Mnemoni Tested
Jump JMP Branch Condition
c Condition
Skip SKP BZ Branch if zero Z=1
Call CALL BNZ Branch if not zero Z=0
Return RET BC Branch if carry C=1
Compare BNC Branch if no carry C=0
CMP
(Subtract) BP Branch if plus S=0
Test (AND) TST BM Branch if minus S=1
BV Branch if overflow V=1
Branch if no
BNV V=0
overflow

Deepak John, Department Of IT ,COE ,Poonjar

Deepak John, Department Of IT ,COE ,Poonjar
 Assembly Directive
• For an assembler to produce an object code, it
has to know the following:
1. How to interpret the name (sum = 200)
2. Where to place the instructions in the memory
3. Where to place the data operands in the memory

Deepak John, Department Of IT ,COE ,Poonjar

• Assembler Directives
Allows the programmer to specify other information needed
translate the source program into the object program
• EQU-simply equates a symbolic name to a numeric value.
• ORIGIN-tells the assembler where to load instructions and data
into memory.
• DATAWORD- states that the data value 100, is to be placed in the
memory (at address 204).
• RESERVE- declares that a memory block of 400 bytes, is to be
reserved for data.
• RETURN -directive indicates where the execution of the program
should be terminated.
• END -directive tells the assembler where is the end of the source
program.

Deepak John, Department Of IT ,COE ,Poonjar

 Assembler
• The assembler is a program that replaces all symbols in
the source code with the binary codes.
• The assembler also replaces names and labels with the
actual values.
• The assembler scans through a source program, keep
tracks of all names and the numerical values in a symbol
table. When names appear, they are replaced with
values from this table.
• Normally use two pass assembler

Deepak John, Department Of IT ,COE ,Poonjar

Deepak John, Department Of IT ,COE ,Poonjar
Stacks
• Stack is a list of data Stack 0

elements that can be Pointer .

.
added or removed at register
.
one end only (top). It SP -28
Current

is LIFO ( Last in first 17

Top
element
out)
739
• Stack is usually used Stack
.
to handle control .

between a main .
Bottom
43
program and BOTTOM
element
subroutines .
.
• SP-Stack pointer is a .
2k-1
processor register
used to keep track of PUSH: inserting an Element
the address of the POP: removing an element
element of the stack
that is at the Top
Deepak John, Department Of IT ,COE ,Poonjar
 SP 19

-28 -28

17 SP 17

739 Stack 739

. .
. .
. .
43 43

NEWITEM 19 ITEM -28

(a) After push from NEWITEM (b) After pop into ITEM
Deepak John, Department Of IT ,COE ,Poonjar
 Subroutines
• Only one copy of subroutine is store in a memory to save
space. Any program that want to use a subroutine simply
branches to its starting location.
• When a subroutine returns, the assembler has to make
sure that it returns to the appropriate location. The
simplest way is to use a link register to save the content of
the PC when a subroutine is called.

Deepak John, Department Of IT ,COE ,Poonjar

Memory Calling Program Memory Subroutine SUB
Location Location
.
.
.

200 Call SUB 1000 first instruction

204 next instruction .

.
.

.
.
. Return

1000

PC 204

Link 204

Call Return

Deepak John, Department Of IT ,COE ,Poonjar

• The link register cannot support the nested subroutine
calls (a subroutine calling another subroutine).
• Using a stack concept, nested subroutine calls can be
carried out at any depth.
– Call instruction : pushes the content of the PC to the stack and
loads the beginning of subroutine address to the PC.
– Return instruction : pops the return address from a stack and
copy it to a PC.

Deepak John, Department Of IT ,COE ,Poonjar

• Parameter passing
1. Can be done using registers. The called program can
place a set of parameters in a set of registers before
calling a subroutine. The subroutine then uses those
values and returns the result via another register.
2. Can also be done by placing parameters in the
stack together with the return address.

Deepak John, Department Of IT ,COE ,Poonjar

 Interrupt
• An interrupt is a request from I/O device for
service by processor
• Processor provides requested service by
executing interrupt service routine (ISR)
• Contents of PC, general registers, and some
control information are stored in memory .
• When ISR completed, processor restored, so
that interrupted program may continue

Deepak John, Department Of IT ,COE ,Poonjar

PERFORMANCE

•Time taken by the system to execute a program

•Parameters which influence the performance are

•Clock speed
•Type and number of instructions available
•Average time required to execute an instruction
•Memory access time
•Power dissipation in the system
•Number of I/O devices and types of I/O devices connected
•The data transfer capacity of the bus

Deepak John, Department Of IT ,COE ,Poonjar

 Basic Instruction Cycle
• Basic computer operation cycle
– Fetch the instruction from memory into a control
register (PC)
– Decode the instruction
– Locate the operands used by the instruction
– Fetch operands from memory (if necessary)
– Execute the operation in processor registers
– Store the results in the proper place
– Go back to step 1 to fetch the next instruction

Deepak John, Department Of IT ,COE ,Poonjar