DIGITAL CIRCUITS AND

SYSTEMS

Electronic & Communication Engineering

Danang University of Technology
 Voltage Voltage Levels
VDD
- Positive/Negative logic
system
Logic value 1
-V0,max: max. voltage level that
V1,min
a logic circuit recognizes as low
- V1,min: min. voltage level that a
Undefined logic circuit recognizes as high
- Exact V0,max ,V1,min values
V 0,max depend on used technology,
normally 40% VDD and 60% VDD
Logic value 0

V SS (Gnd)

Logic values as voltage levels.

 x = "low" x = "high" NMOS
- Most popular used transistor
(a) A simple switch controlled by the input x
is MOSFET: NMOS & PMOS
Gate
- 4 electrical terminals. In logic
circuits the substrate terminal is
Source Drain
connected to Gnd for NMOS
Substrate (Body)
- No physical difference
between source and drain
(b) NMOS transistor terminals
- By convention, the source
VG
terminal is the node with lower
voltage for NMOS
VS VD

(c) Simplified symbol for an NMOS transistor

NMOS transistor as a switch.

 Remarks
- Silicon is an electrical semiconductor.
- A transistor is fabricated by creating areas in the silicon
substrate that have an excess of either positive or negative
electrical charge.
- The gate terminal is made of poly-silicon which is
preferable to metal as it can be fabricated with extremely
small dimensions.
- The gate is electrically isolated from the rest of transistor by
a layer of SiO2.
- Transistor’s operation is governed by electrical fields caused
by voltages applied to its terminal
 NMOS off
V = 0V
G

SiO 2

V = 0V
S
V
D

++++++ ++++ +++++++++++++++ ++++++

++++++ ++++++++++++ ++++++
+++++++++++ +++++++++++++++++++++++
+++++++++ Substrate (type p) +++++++++

Source (type n) Drain (type n)

(a) WhenV GS = 0 V, the transistor is off

NMOS transistor when turned off: back-to-back diodes represent

very high resistance (1012 ohm) between drain & source
 VDD
NMOS on
VG = 5 V

SiO2

VS = 0 V
VD = 0 V

++++++ ++++ +++ ++++++

++++++ ++++++
+++++++++++ +++++++++++++++++
+++++++++ ++ +++++++ ++++++++++

Channel (type n)
(b) When VGS = 5 V, the transistor is on

NMOS transistor when turned on: If the gate-to-source

voltage VGS is greater than a certain minimum positive voltage,
called VT (typically 0,2 VDD), then the switch is closed.
 Channel
-The positive voltage on the gate attracts free electrons
existing in the type-n source and drain terminals & other
areas of the transistor towards the gate. Because of SiO2
layer, electrons gather in region of the substrate between
source & drain terminals, which results into channel
connecting source & drain.

+ W2
W1
+

L
L

(a) Small transistor (b) Larger transistor

- The size of channel is determined by length L & width W
 x = "high" x = "low"
PMOS
- Most popular used transistor
(a) A switch with the opposite behavior
is MOSFET: NMOS & PMOS
Gate
- 4 electrical terminals. In logic
circuits the substrate terminal is
Drain Source connected to to VDD for PMOS
VDD
Substrate (Body) - No physical difference
between source and drain
(b) PMOS transistor
terminals
- By convention, the source
VG
terminal is the node with higher
voltage for PMOS
VS VD

(c) Simplified symbol for a PMOS transistor

PMOS transistor as a switch.

 VD VD = 0 V VD
Operations
VG - When the NMOS transistor is
turned on, its drain is pulled
VS = 0 V down to Gnd
Closed switch Open switch
whenVG = VDD whenVG = 0 V

(a) NMOS transistor

VS = VDD VDD VDD

- When the PMOS transistor is

VG
turned on, its drain is pulled up
to to VDD
VD VD VD = VDD
Open switch Closed switch
whenVG = VDD whenVG = 0 V

(b) PMOS transistor

NMOS and PMOS transistors in logic circuits.

 VDD
NMOS NOT
R R
+ - VX=0V, tr is turned off -->
5V
- Vf Vf Vf=5V
Vx Vx
- When VX=5V, tr is turned
on, its drain is pulled down
to Gnd --> Vf=0V
(a) Circuit diagram (b) Simplified circuit diagram

- Exact Vf depends on R &

tr., typically is 0.2V
x f x f
- R is used to limit the
current during turning on of
(c) Graphical symbols
tr. (problem?)
A NOT gate built using NMOS
technology.
 VDD

NMOS NAND
Vf - Series connection of NMOS to
Vx
1
create the logic AND function
x1 x2 f - VX1= VX2=5V, tr is turned off --
Vx
0 0 1 > Vf=5V
2 0 1 1
1 0 1
- When VX=5V, trs are turned
1 1 0 on, their drains are pulled down
(a) Circuit (b) Truth table
to Gnd --> Vf will be closed to
0V
x1 x1
x2
f
x2
- If only one of trs is turned off,
f
then Vf will be pulled up to 5V
- R is used to limit the current
(c) Graphical symbols
during turning on of tr.
NMOS realization of a NAND (problem?)
gate.
 V DD
NMOS NOR

- Parallel connection of
x1 x2 f NMOS to create the logic
Vf
0 0 1 NOR function
Vx
1
Vx
2 0 1 0 - Either VX1= 5V or VX2=5V,
1 0 0
1 1 0 Vf will be closed to 0V
- If both Vx =0V --> Vf will
(b) Truth table
(a) Circuit be pulled up to 5V

x1 x1
x2 f x2 f

(c) Graphical symbols

NMOS realization of a NOR
gate.
 VDD VDD
NMOS AND

Vf - AND realization by following a

A
NAND gate with an Inverter
Vx1

x1 x2 f

Vx2 0 0 0
0 1 0
1 0 0
1 1 1

(a) Circuit (b) Truth table

x1 x1
f f
x2 x2

(c) Graphical symbols

NMOS realization of an AND gate.

 V DD VDD
NMOS OR
- OR realization by
Vf following a NOR gate with
x1 x2 f an Inverter
0 0 0
Vx Vx 0 1 1
1 2

1 0 1
1 1 1

(a) Circuit (b) Truth table

x1 x1
x2 f x2 f

(c) Graphical symbols

NMOS realization of an OR gate.

 PDN Structure
VDD

- All mentioned structures can be

characterized by a block diagram
with PDN (pull-down network)
Vf

Vx
1
Pull-down network
(PDN)
Vx
n

Structure of an NMOS circuit.

 PDN-PUN - All mentioned structures can be
characterized by a block diagram
with PDN (pull-down network)
V DD
- The CMOS concept: replacing the
pull-up device with a pull-up network
(PUN) that is built using PMOS tr.
Pull-up network
(PDN & PUN networks are
(PUN) complements of each other)
- For any given values of the inputs,
V f either the PDN pulls Vf down to Gnd

Vx
or the PUN pulls Vf up to VDD
1
Pull-down network - The PDN & PUN have equal
(PDN) numbers of trs. (the networks are
Vx
n
duals of one another)
- Whenever the PDN has NMOS trs.
Structure of a CMOS circuit. in series, the PUN has PMOS trs. in
parallel, and vice versa
 VDD
CMOS NOT
R
- When Vx= 0V, T1 is ON &
VDD
Vf T2 is OFF, Vf= 5V. Since T2
Vx is OFF, no current flows
through trs.
T1 - When Vx= 5V, T2 is ON &
T1 is OFF, Vf= 0V. Since T1
Vx Vf NMOS realization of NOT gate
is OFF, no current flows
x T1 T2 f
T2 through trs.
0 on off 1 - KEY: no current flows in
1 off on 0 CMOS Inverter
(a) Circuit (b) Truth table and transistor states

CMOS realization of a NOT gate.

 Logic expression of NAND gate: f = x1 x2 = x1 + x2
Look at Truth Table, f=1 when either x1 or x2 = 0, thus PUN must
be active in this case (pull up Vf to “1”), and two PMOS transistors
must be connected in parallel.
V DD
The PDN must implement the complement of f :
f = x1 x2
Since !f=1 when both x1 and x2 = 1, PDN must
T1 T 2 have two NMOS trs. connected in series.

Vf

Vx T3 x1 x2 T1 T2 T3 T4 f
1

0 0 on on off off 1
0 1 on off off on 1
Vx T4
2 1 0 off on on off 1
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

CMOS realization of a NAND gate.
 CMOS NOR
VDD

f = x1 + x2 = x1 x2
Vx T1
1

Vx T2
2

x1 x2 T1 T2 T3 T4 f
Vf
0 0 on on off off 1
T3 T4 0 1 on off off on 0
1 0 off on on off 0
1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

! f = x1 + x2
CMOS realization of a NOR gate.
 CMOS AND
V DD VDD

Vf

Vx
1

Vx
2

CMOS realization of an AND gate:

connecting a NAND gate to an Inverter
 VDD
Example 3.1
Consider the following function:
f = x1 + x2 x3
Since all variables appear in their
complemented form, we can directly
derive the PUN: 1 PMOS tr. controlled by Vf
x1 in parallel with a series combination of
Vx
2 PMOS trs. controlled by x2 & x3 1

Vx
2
For PDN, take complemented form of f
Vx
which leads to result as shown in Fig. 3

f = x1 + x2 x3 = x1 ( x2 + x3 )
Consider the following function : Example 3.2
( )
f = x1 + x2 + x3 x4
Build a circuit using CMOS to implement this functionality
 VDD
Example 3.2

Consider the following function :

(
f = x1 + x2 + x3 x4 )
Vf Step 1: Build PUN
Vx
1
(
f = x1 + x2 + x3 x4)
Vx
2
Step 2: Build PDN

Vx
! f = x1 (x2 x3 + x4 )
3

Vx
4
 Voltage Levels

V DD

Vf Vx Vx Vf
1 2

Vx L L H
1
L H H
H L H
Vx H H L
2

(a) Circuit (b) Voltage levels

Voltage levels in the NAND gate

 x1 x2 f Voltage Levels
0 0 1 x1
0 1 1 f
x2
1 0 1
1 1 0
(a) Positive logic truth table and symbol of NAND gate

Positive logic system: higher voltages represent logic

value 1 & lower voltages represent logic value 0

Negative logic systems: the association between
voltages and logic values is reversed
x1 x2 f

1 1 0 x1
1 0 0 f
x2
0 1 0
0 0 1

(b) Negative logic truth table and symbol of NAND gate

 Integrated Circuit Chips

Large variety of chips that implement various functions that are
useful in the design of digital hardware

The chips range from very simple ones with low functionality to
extremely complex chips

Eg. A digital hardware product may require a µP to perform
some arithmetic operations, memory chips to provide storage
capability, and interface chips that allow easy connection to input
and output devices

Three main types of chips:

Standard chips

Programmable logic devices

Custom chips
Characterizing Standard Chips: Digital ICs
characterized several ways as follows:
Circuit Complexity
Gives measure of number of transistors or
gates
Within single package
Four general categories
SSI - Small Scale IC
< 12 gates or so
MSI - Medium Scale IC
< 100 gates or so
LSI - Large Scale IC
< 1000 gates or so
VLSI – Very Large Scale IC
> 1000 gates or so
Circuit Topology
Describes the input and output structure of the device
Three general categories
TTL - Transistor Transistor Logic
Bipolar transistors on input and output
Output section looks like described circuit
Referred to as totem pole output

ECL - Emitter Coupled Logic

Bipolar
Logic done in emitter circuitry rather than
collector
High speed

MOS - Metal Oxide Semiconductors

MOS transistors on input and output
SSI Circuits
Let’s look now at some SSI circuits
Referred to as glue logic in today’s design
Most designs highly integrated
VLSI
Gate arrays
Array logics
Glue logic provides means of interconnection
SSI circuits fall into 3 general categories
Basic gates
Simple combinations of gates
Buffer and driver gates
Basic Gates
These implement fundamental logic functions
AND OR
NAND NOR
NOT
 Standard Chip Examples
- 74LS00 is built by TTL tech.
- 74HC00 is fabricated by CMOS
technology
- Most popular chips used today
are the CMOS variants

(a) Dual-inline package

VDD

Gnd

(b) Structure of 7404 chip

A 7400-series chip.
 DD
V

7404

7408 7432

1
x
x2
3
x
f
An implementation of f = x1 x2 + x2 x3
- Because of their low logic capacity, the standard
chips are seldom used in practice.
- One exception: many modern products include
standard chips containing buffers (logic gates that
are usually used to improve the circuit speed)
Pin 12

Pin 14

Pin 16

Pin 18

Pin 19
Pin 11

Pin 13

Pin 15

Pin 17
Pin 1
Pin 2

Pin 4

Pin 6

Pin 8

Pin 3

Pin 5

Pin 7

Pin 9
The 74244 buffer chip comprises 8 tri-state
buffers
 VDD
Vx
Vf
(a) Implementation of a buffer
x f
(b) Graphical symbol
A non-inverting buffer
Buffer
- When a logic gate has to drive a large
capacitive load, buffers are often used
to improve performance: f = x
- Buffers can be created with different
amounts of drive capability, depending
on the sizes of the transistors (will be
discussed later …)
- As used for driving higher-than-
normal capacitive loads, buffers have
trs. that are larger than normal
- Not only for high speed performance,
buffers are also used when high
current flow is needed to drive external
devices (e.g. use buffer to control LED)
 Inverting Buffer
-Inverting buffer produces the same output as an inverter but
is built with relatively large transistors
- As shown in figure, for large values of n an inverting buffer
could be used for the inverter labeled as N1

N1
f To inputs of
x
n other inverters

Inverter that drives n other inverters

 e= 0 Tri-state buffer has
additional control
x f
e input, called enable e

x f
e= 1
x f

(a) A tri-state buffer (b) Equivalent circuit

e e

e x f x f x f
0 0 Z
0 1 Z (a) (b)
1 0 0 Four types of tri-
1 1 1
state buffers. e e

(c) Truth table x f x f

(c) (d)
 Multiplexer
From Truth Table, derive canonical SOP form
f ( s, x1 , x2 ) = sx1 x2 + sx1 x2 + s x1 x2 + sx1 x2
( ) ( )
= sx1 x2 + x2 + s x1 + x1 x2 = sx1 + sx2
 An application of tri-state buffers: Multiplexer

x1 f

x2

Multiplexer based on Logic gates

- A transmission gate: switch that connects x to f
- A switch is turned on by setting VS = 5V & V!S = 0V.
s
+ Vx= 0V: NMOS is
turned on, Vf = 0 (drain is
x f s f pulled down to Gnd –
0 Z source)
s
1 x + Vx= 5V: PMOS is
turned on, Vf = 5V (drain
(a) Circuit (b) Truth table
is pulled up to VDD –
source)
s= 0
e
x f=Z s
x f
s= 1 x f
x f=x s

(c) Equivalent circuit (d) Graphical symbol (e) Implementation

 s f e x f

0 0 Z
0 Z
0 1 Z
1 x
1 0 0
1 1 1
Truth table: Transmission gate

Truth table: Tri-state buffer

x
1 x1 f

s s

x2
x f
2

A 2-to-1 multiplexer built A 2-to-1 multiplexer built

using transmission gates. using tri-state buffers.
 XOR Gate
x1
x1 x2 f = x1 ⊕ x2
x2
0 0 0
0 1 1
1 0 1
1 1 0

f = x1 ⊕ x2 Truth table

CMOS implementation

CMOS Exclusive-OR (XOR) gate.

 x 1 x2 f = x 1 ⊕ x2

0 0 0
0 1 1
x1
1 0 1 f = x1 ⊕ x2
x2
1 1 0

(a) Truth table (b) Graphical symbol

x1
x2

f = x1 ⊕ x2

(c) Sum-of-products implementation

Logic gate based Exclusive-OR (XOR) gate.

 PLD
x1 x2 x3

NOR plane

VDD VDD VDD

S1

VDD

S2

VDD

S3

NOR plane f1 f2

An example of a NOR-NOR PLA.

 Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

Programmable logic device as a black box.

 x1 x2 xn
PLA

Input buffers -Be realized in Sum-Of-Products form

and - Each Pk is configured to implement
inverters
any AND function of xi
x1 x1 xn xn - Each fm is configured to implement
any OR function of Pk
P1

AND plane OR plane

Pk

f1 fm
General structure of a PLA (Programmable Logic Array).
 x1 x2 x3
f1 = x1 x2 + x1 x3 + x1 x2 x3
Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

Gate-level diagram of a PLA

f1 f2
How to implement ?
 x1 x2 x3

OR plane
P1

P2

P3

P4

AND plane

- Customary schematic for the PLA in previous Figure f1 f2

- Constraint: size of AND plane (only 4 product terms)
 x1 x2 x3
PAL

P1

f1
P2

P3

f2
P4

AND plane
- Programmable switches present 2 difficulties in manufacturing
- PAL (Programmable Array Logic): programmable AND plane,
fixed OR plane -> less flexibility than PLA
 Select
Enable

f1
Flip-flop

D Q

Clock

To AND plane

Extra circuitry added to OR-gate to provide additional functionality

 FF represent a memory element, depend on signal clock
that the OR gate output will be hold at certain time point
 Multiplexer selects output either from OR gate or from Q
output of the D-FF.
A SPLD programming unit (courtesy of Data IO Corp).
 CPLD

I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

Structure of a Complex Programmable Logic Device (CPLD).

 CPLD Section
PAL-like block (details not shown)

PAL-like block
- A CPLD consists of
many PAL-like blocks
D Q
interconnected via
switches
-A commercial CPLD has
D Q
2-100 PAL-like blocks
- Each PAL-l.b. has 3
macrocells.
D Q - Each macrocell some
OR gates ….

A section of the CPLD

 (a) CPLD in a Quad Flat Pack (QFP) package

To computer

Printed
circuit board

(b) JTAG programming

CPLD packaging and programming.

 FPGA

-FPGA differ from CPLD (no

AND OR gates)
- Use logic blocks to
implement required functions
- 3 main resources: logic
blocks, I/O blocks,
interconnect. wires &
switches
- LB: 2-d array
- Interconnection: h. & v.
routing channels

A field-programmable gate array (FPGA).

 LUT (Look-Up Table)

A two-input lookup table (LUT)

- Each L.B. typically has a small number of inputs & outputs.

- The most commonly used L.B. is LUT (lookup table) which
contains storage cells. The stored values (0/1) is produced as
the output of the storage cell.
- LUTs have various sizes which are defined by number of
inputs
 Gate Multiplexer
From Truth Table, derive canonical SOP form

f ( s, x1 , x2 ) = sx1 x2 + sx1 x2 + s x1 x2 + sx1 x2

( ) ( )
= sx1 x2 + x2 + s x1 + x1 x2 = sx1 + sx2
x1
LUT Multiplexer
0/1

0/1 x1 x2 f1
f
0/1 0 0 1
0 1 0
0/1
1 0 0
x2 1 1 1

(a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2

- A two-variable TT has 4 rows 

x1
needs 4 cells.
1 - Three multiplexers controlled by
0
f1 x1 & x2
0
- Explain principle ?
1
x2

(c) Storage cell contents in the LUT

A two-input lookup table (LUT).
 Example
x1
x2

Try to check its function by 0/1

using Truth Table … 0/1

0/1
0/1
f
0/1
0/1
0/1
0/1
x3

A three-input LUT.
 LUT Extra Circuit

Select

Out
Flip-flop
In1
In2 LUT D Q
In3
Clock

Inclusion of a flip-flop in an FPGA logic block.

- The FF is used to store the value of its D input under control of

its clock input.
 x3 f
LUT in FPGA

- Two-input LUTs x1
- Four wires in each
routing channel x1 0 x2 0
- Fig. shows 0 f1 1 f2
0 0
programmed states of x2 x2
1
x3
0
the L.Bs. & switches
+ Blue switches: ON
+ Black switches: OFF

f1 = x1 x2
f1 0
f 2 = x2 x3 1
1
f
f2
1
f = f1 + f 2

Section of a programmed FPGA.

 Remarks
- Each logic function must be small enough to fit within a single L.B.
- User’s circuit is automatically translated into the required form by
using CAD tools
- When a circuit is implemented in an FPGA, the L.B. are
programmed to realize the necessary functions, and the routing
channels are programmed to make the required interconnections
between L.Bs.
- The storage cells in the LUTs in an FPGA are volatile: they lose their
stored values whenever the power supply for the chip is turned off.
- Instead of being re-programmed every time, a small memory chip
that holds its data permanently, called PROM, is included on the
circuit board that houses the FPGA. The storage contents are
automatically loaded from PROM to FPGA when power is applied to
the chips
 Custom Chip
- Provide largest no. of logic gates, highest circuit speed, lowest power
- Whereas a PLD is prefabricated, a custom chip is created from scratch
- The process of defining where trs. & wires are placed on chip is called CHIP LAYOUT
- A typical chip has many long rows of logic gates with a large number of wires between rows
+ Blue wire on one layer/ Black wire on another layer
+ Blue square: hard-wired connection (via) between layers

x1 f2

x2
x3
f1

A section in a standard-cell chip. Chips made using this technology are

called ASICs (application-specific integrated circuits)
A sea-of-gates gate array
 f1

x1

x2

x3

The logic function f1 = x2x3+x1x3 in the gate array