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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LC_Atalk is
Port ( in_ready, buffer_picked, qb, qa: in std_logic;
clk: in std_logic;
T0, T1, T2: out std_logic );
end LC_Atalk;
begin
process(clk) -- proceso secuencial
begin
if clk='1' and clk'event then
e_p <= e_s; -- con el pulso de reloj
end if;
end process;
process(e_p, in_ready, buffer_picked, qb, qa) --en función del estado presente y las entradas, cambia las salidas y el
estado siguiente
begin
case e_p is
when A =>
T0 <= '1';
T1 <= '0';
T2 <= '0';
if (in_ready = '0') then
e_s <= A;
elsif (in_ready='1' and not(qb='1' and qa='1')) then – Si in_ready es ‘1’ y el Contador no ha llegado a 3 pasa del estado T0 al
estado T1 (AB)
e_s <= B;
elsif (in_ready='1' and qb='1' and qa='1') then – Si in_ready es ‘1’ y el Contador llegó a 3 pasa del estado T0 al estado T2 (AC)
e_s <= C;
end if;
when B =>
T0 <= '0';
T1 <= '1';
T2 <= '0';
if (in_ready = '1') then
e_s <= B;
else
e_s<=A;
end if;
when C =>
T0 <= '0';
T1 <= '0';
T2 <= '1';
if (buffer_picked = '0') then
e_s <= C;
else
e_s<=A;
end if;
end case;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity ProcDatos is
port (T2, T1, T0, clk: in std_logic;
in_ready, buffer_picked: in std_logic;
dato: in std_logic_vector(3 downto 0);
in_received, buffer_full, qb, qa: out std_logic;
RA, RB, RC, RD : out std_logic_vector(3 downto 0));
end ProcDatos;
Begin
T <= T2&T1&T0; -- El operador & permite concatenar 3 bits
process(clk)
begin
if (clk = '1' and clk'event) then
case T is
when "001" => -- estado T0
if ( in_ready='0') then
in_received <= '0';
else
case C is -- Analizamos que hacer según los valores del contador C
when "0000" =>
RA <= dato; -- Registro Ra carga el dato
C <= C + 1; -- aumenta el contador
when "0001" =>
RB <= dato;
C <= C + 1;
when "0010" =>
RC <= dato;
C <= C + 1;
when others => null; -- para que no tenga en cuenta las demás combinaciones después de 0011 en el case
end case;
end if;
when "010" => -- estado T1
in_received <= '1'; Se activa(‘1’) in_received al cargar el dato en uno de los registros RA,RB o RC y
permanece en ‘1’ mientras in_ready sea ‘1’(Estado T1)
if in_ready = '0' then – in_received =‘0’ si in_ready se pone en ‘0’ (Se pasa al Estado T0)
in_received <= '0';
end if;
when "100" => -- estado T2
buffer_full <= '1';
if buffer_picked = '1' then
buffer_full <= '0';
C<=''0000'';
end if;