COA DIGITAL ASSIGNMENT-1

ECE3004
Name:N. Pavan kailash
Reg no:18BEC0891
Slot:F2+TF2
Faculty:Jaya Krishna.P
School:Sense
1. a. Draw the clear Block Diagram of the Microprocessor / Micro controller/ IP
core selected.
b. Give the Internal Diagram of each and every block.
 2. Provide the Instruction set of the Micro-processing element (Microprocessor/
Micro controller/ IP core) with clock cycle required/Machine cycle required,
memory required, flags affected, type of instruction based on addressing
modes, operation, etc.

INSTRUCTION SET:
Characteristics Symbol Max
Mi Ty
n p. Uni t Remar ks
Motor power supply VM 2.5 - 16.0 V -
Motor output current Iout - 1.1 2.0 A
(Note
1)
ERR pin output voltage VLO - - 5.5 V -

Vref reference voltage Vref 0 - 1.8 V -

 Characteristics Symbol Test condition Min Unit
Typ Ma
. x
HIGH VIN(H) Logic input (Note1) 1.5 — 5.5 V

Logic input voltage LOW VIN(L) Logic input (Note1) 0 — 0.7 V

Logic input hysteresis voltage VIN(HY Logic input (Note1) — 60 — mV

S)

HIGH IIN(H) VIN(H) = 3.3 V — 33 45 μA

Logic input current LOW IIN(L) VIN(L) = 0 V — — 1 μA

LOW — — 0.5 V
ERR pin output VOL(LO IOL = 5 mA, output =
voltage ) L
IM1 Output pins = — — 0.1 μA
open
Standby
Mode

Current consumption

IM2 Output pins =

open EN pin — 2.8 3.5 mA
=L
in releasing Standby
mode
IM3 Output pins =
open Full step — 3.3 4.3 mA
resolution
fCLK=75 kHz
High- IOH VM = 18 V, Vout = 0 — — 1 μA
Output leakage side V
current
Low- IOL VM = Vout = 18 V -1 — — μA
side

Motor current channel ΔIout1 Current differential -5 0 5 %

differential between Ch

Motor current setting accuracy ΔIout2 Iout = 1.1 A -5 0 5 %

Motor output ON resistance Tj = 25°C, — 0.6 Ω
(High side Ron(H VM = 12 V, Iout = 1 0.4
+L) A 8
+ Low side)

Vref input current Vref = 1.8 V

Iref — 0 1 μA
Thermal shutdown TjTSD — 145 165 175 °C
(TSD) threshold
(Note1)

UVLO release voltage At rising VM

(Note 2) VUVLO 2.1 2.3 — V

— — 200 — mV
UVLO hysteresis voltage Vhys_u
vlo
Over current detection ISD VM = 12V 2.5 3.2 4.2 A
(ISD) threshold
(Note3)

CLK input frequency fCLK — — — 400

kH
z
Inside filter of CLK input tCLK(H) The CLK(H) minimum 500 — — ns
minimum High width pulse width
Inside filter of CLK tCLK(L) The CLK(L) minimum 500 — — ns
input minimum Low pulse width
width

tr — 10 20 30 ns

Output transistor switching

specific

—
tf 10 20 30 ns
— — 840 — ns
tpLH(C
LK)
— — 900 — ns
tpHL(C
LK)
Analog noise blanking VM = 12 V
time AtBLK 340 540 740 ns

ROSC = 47 kΩ VM -15 — %
Oscillator frequency ∆fOSC = 2.5 V to 16 V +1
accuracy
M 5
fOSCM ROSC = 47 kΩ 1076
Oscillator reference
126 145 kH
frequency
6 6 z
Chopping frequency fchop Output: Active, fOSCM — 79 —
= 1266 kHz kH
z

Min
Characteristics Symbol Test condition Typ Ma Unit No.in
. x Timing
Chart
Serial CLK frequency fSCLK VIN = 3.3 V 1.0 — 25 MHz —

CLK cycle tsCKW VIH = 3.3 V, VIL 46 — — ns —

= 0 V, tr = tf
= 23 ns

tw(CLK) 40 — — ns 1
Minimum CLK pulse VIN = 3.3 V
width twp(CLK 20 — — ns 2
)

twn(CLK 20 — — ns 3
 )
Minimum LATCH pulse tLATCH VIN = 3.3 V 20 — — ns 4
width (H)
tsuSIN 10 — — ns 5
Data setup time CLK VIN = 3.3 V

tsuLT - 10 — — ns 6
CLK
thSIN - 10 — — ns 7
Data hold time CLK VIN = 3.3 V

thLT - 40 — — ns 8
CLK
LATCH cycle tcL VIN = 3.3 V 1.3 — — μs 9
T 2
3. Explain Micro processing element (Microprocessor / Micro controller / IP core)
Architecture.

TOSHIBA CD process Integrated Circuit Silicon Monolithic TC78H670FTG.

The TC78H670FTG is a two-phase bipolar stepping motor driver using a PWM chopper
which incorporate DMOS with low on-resistance in output transistors. The clock-in
decoder is built in.
Toshiba TC78H670FTG Bipolar Stepping Motor Driver exhibits built-in dual H-Bridges,
2.5V to 16V power supply operating voltage, and 2A output current (maximum). This
motor driver is a two-phase bipolar stepping motor driver, which uses a PWM chopper and
incorporates DMOS with low on-resistance in output transistors. The
TC78H670FTG stepping motor driver allows full, half, quarter, 1/8, 1/16, 1/32, 1/64, and
1/128 step operations. Additionally, this driver features a built-in sense resistor less current
control architecture (advanced current detection system) and VCC regulator for internal
circuit.
The TC78H670FTG Bipolar Stepping Motor Driver offers Thermal shutdown
(TSD), Over-current Shutdown, Motor-load Open, and Under-voltage Lockout (UVLO)
error detect functions with flag output function. This motor driver comes in a small QFN
package with a thermal pad (16 pins).
4. Correlate the Micro processing element (Microprocessor/ controller/IP core)
architecture with architectures discussed in Module 1 and II .

Is there a relation between the instruction set (RISC and CISC) and the architecture of
the processor/microcontroller? I find Harvard architecture processors with RISC
instruction set and Von neumann architecture processors with CISC instruction set (I'm
not sure if this is always true). Is there a reason relating the architecture to the
instruction set?

No, there is no relationship (e.g., RISC = Harvard / CISC = von Neumann). You can
build either of them either way. The PowerPC, SPARC, and ARM are RISC and von
Neumann. Seymour Cray's machines were RISC (although the term had not yet
been invented when he designed most of them) and von Neumann. I don't believe
the Harvard Mark I was RISC as it had some rather complex instructions (e.g.,
interpolate value from function tape) and it was clearly Harvard.

The issue gets complex with modern machines that use cache. Both the Pentium and
PowerPC are considered to be von Neumann, from the point of view of the
programmer, but run internally using instruction and data caches as Harvard. The
Pentium is CISC and the PowerPC is RISC. To make it even more complex, current
Pentium implementations "translate" the CISC instructions from the instruction cache
into RISC like microinstructions, before actually executing them.
The circuitry that performs the actions defined by the microcode in many (but not all)
CISC processors is, in itself, a processor which in many ways is reminiscent in
structure to very early CPU designs. In the early 1970s, this gave rise to ideas to
return to simpler processor designs in order to make it more feasible to cope without
(then relatively large and expensive) ROM tables and/or PLA structures for
sequencing and/or decoding. The first (retroactively) RISC-labeled processor (IBM 801
– IBM's Watson Research Center, mid-1970s) was a tightly pipelined simple machine
originally intended to be used as an internal microcode kernel, or engine, in CISC
designs, but also became the processor that introduced the RISC idea to a somewhat
larger public. Simplicity and regularity also in the visible instruction set would make it
easier to implement overlapping processor stages (pipelining) at the machine code
level (i.e. the level seen by compilers). However, pipelining at that level was already
used in some high performance CISC "supercomputers" in order to reduce the
instruction cycle time (despite the complications of implementing within the limited
component count and wiring complexity feasible at the time). Internal microcode
execution in CISC processors, on the other hand, could be more or less pipelined
depending on the particular design, and therefore more or less akin to the basic
structure of RISC processors
It uses Von Neumann architecture to produce a simple and flat memory
Map
 4 PGND_A ← ← Ach Power GND pin
5 OUT_A+ ← ← A channel motor output(+) pin
6 OUT_A- ← ← A channel motor output(-) pin
7 OUT_B- ← ← B channel motor output(-) pin
8 OUT_B+ ← ← B channel motor output(+) pin
9 PGND_B ← ← Bch Power GND pin
1 VREF ← ← Current threshold reference pin
0

1 OSCM ← ← Internal oscillator frequency setting

1 pin

1 STB ← ← Standby pin

2 Y

EN/ERR ← ← Enable(Motor output

1 ON/OFF) pin / Error
3 detection flag output pin
MODE0: Step mode select
1 MODE0 UP-DW S_DATA pin UP-DW: Step mode
4 setting pin
S_DATA: Serial data input
pin

MODE1: Step mode select

1 MODE1 SET_EN LATCH pin SET_EN: Step mode
5 setting enable pin LATCH:
Latch enable pin
MODE2: Step mode select
1 MODE2 CLK S_CLK pin CLK:
6 Step Clock input
pin S_CLK: Serial clock
input pin

6. Explain the type of algorithm used for signed / unsigned Calculations (Addition,
Multiplication, etc.).

There are various multiplication instructions of TC78H670FTG IC, looking only at

32bit variants and ignoring BMI2, you will find these: imul r/m32 (32x32->64 signed
multiply)
 imul r32, r/m32 (32x32->32 multiply) *
imul r32, r/m32, imm (32x32->32 multiply) * mul
r/m32 (32x32->64 unsigned multiply)
Notice that only the "widening" multiply has an unsigned counterpart. The two forms in the
middle, marked with an asterisk, are both signed and unsigned multiplication, because for
the case where you don't get that extra "upper part", that's the same thing. So signedness
doesn't matter for multiplication (at least not for the kind of multiplication you use in C)
and for some other operations, namely:
• addition and subtraction
• bitwise AND, OR, XOR, NOT
• negation
• left shift
comparing for equality the ic doesn't offer separate signed/unsigned versions for those,
because there's no difference anyway. But for some operations there is a difference, for
example: division (idiv vs div) remainder (also idiv vs div) right shift (sar vs shr)
comparing for bigger than / smaller than But that last one is special, the ic doesn't have
separate versions for signed and unsigned of this either, instead it has one operation
(cmp, which is really just a nondestructive sub) that does both at once, and gives several
results (multiple bits in "the flags" are affected). Later instructions that actually use those
flags (branches, conditional moves, s etcc) then choose which flags they care about.