Berry DG15 Discrete/UMA Schematics Document Arrandale Intel PCH 2009-10-12 REV: X00

5 4 3 2 1
D D
Berry DG15 Discrete/UMA Schematics Document

Arrandale
C
Intel PCH C
2009-10-12
REV : X00
B
DY :None Installed B
UMA:UMA platform installed

DIS:DIS platform installed
Madisan:gDDR3 1GB platform installed
Colay :Manual modify BOM
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
Berry X00
Date: W ednesday , October 14 , 2009 Sheet 1 of 92
5 4 3 2 1
5 4 3 2 1
1.Madison-LP; 1GB
(64Mx16b*8)
##OnMainBoard
Berry Block Diagram INPUTS
CPU DC/DC
ISL62883
OUTPUTS
47
2.Park-XT;512MB
(64Mx16b*4)
(1 and 2 co-lay)
(Discrete/UMA co-lay) +PWR_SRC
SYSTEM DC/DC
+VCC_CORE 39 ,
VRAM
1GB/512MB
Project code : 91.4HH01.001 INPUTS
TPS51218
OUTPUTS
49
PCB P/N : 48.4HH01.0SA

D 4 D
85, 86 , 87 ,88 +PWR_SRC +1.05V_VTT 4
DDR3 Revision : 09909-SA SYSTEM DC/DC

RT8205B 46
800MHz Intel CPU
INPUTS OUTPUTS
DDRIII 800/1066 Channel A +5V_ALW2 4
DDRIII Slot 0 +3.3V_RTC_LDO
800/1066 18 +PWR_SRC +5V_ALW
Clock Generator AMD Graphic PCIe x 16
Arrandale +3.3V_ALW
+15V_ALW
SLG8SP585
7 Madison-LP / Park-XT (Discrete only)
DDRIII 800/1066 Channel B DDRIII Slot 1 SYSTEM DC/DC
(Discrete only) 800/1066 19
TPS51116 50
INPUTS OUTPUTS
+1.5V_SUS 4
80,81,82,83,84 8,9,10,11,12,13,14 +PWR_SRC +0.75V_DDR_VTT
+V_DDR_REF
PCIE x 1 Mini-Card
USB x 1 802.11a/b/g SYSTEM DC/DC
FDIx4x2 TPS51611 53
C
Discreet/UMA Co-lay (UMA only) DMIx4 INPUTS OUTPUTS C
PCIE x 1
10/100 NIC RJ45 +PWR_SRC +CPU_GFX_CORE
4
Realtek CONN
HDMI Level 57 RTL8103T
VGA
HDMI shifter
57 RT8208B 89
Intel SATAx1 / USB2.0x1
INPUTS OUTPUTS
LVDS(Dual Channel)
PCIE x 3
ESATA/USB +PWR_SRC +VGA_CORE
LCD PCH HM57 Combo
54
RGB CRT TI CHARGER 5
BQ24745 45
Mini-Card
14 USB 2.0/1.1 ports SATA x 1 PCIE x 1,USB x 1 INPUTS OUTPUTS
CRT SIM
ETHERNET (10/100/1000Mb) WWAN +DC_IN +PWR_SRC
+PBATT
CRT Board High Definition Audio 26
Left Side: 77 SATA ports (6) USB 2.0 x 4 SYSTEM DC/DC
4
USB x 2 PCIE ports (8)
USB 2.0 x 1 Right Side: APL5930 51
USB x 1
76 INPUTS OUTPUTS
Bluetooth USB2.0 x 4 LPC I/F
73 +3.3V_ALW +1.8V_RUN
B ACPI 1.1 +1.8V_RUN_VGA B
PCI/PCI BRIDGE SYSTEM DC/DC

CAMERA CardReader SD/MMC+/MS/ APL5930 90 3
54 USB 2.0 x 1
20,21,22,23,24,25,26,27,28 Realtek 78
MS Pro/xD INPUTS
26
OUTPUTS
AZALIA RTS5138 +1.5V_SUS +1.0V_RUN_VGA
Switches
INPUTS OUTPUTS
SATA x 2 +1.5V_SUS +1.5V_RUN
Internal Analog MIC Azalia HDD +5V_ALW +5V_RUN
59 +3.3V_ALW +3.3V_RUN
CODEC
HP1
IDT
Flash ROM LPC debug port ODD PCB LAYER
70 59
4MB 62 L1:Top
92HD79B1 L2:VCC
MIC IN 30 L3:Signal
KBC L4:Signal
SPI SMBus L5:GND
NUVOTON L6:Bottom
A <Core Design> A
NPCE781BA0DX 37
2CH SPEAKER Wistron Corporation

Title
Thermal Block Diagram
Flash ROM Touch Int. Main:G7922 Size Document Number Rev
256kB 62 PAD KB Sec.EMC2102 58 A3
Berry X00
68 68 2539
5 4 3 2 1
5 4 3 2 1
+1.0V_RUN_VGA APL5930KAI
RT8208B +VGA_CORE For Discrete
D D
+PWR_SRC TPS51116
Adapter
ISL62883 TPS51218 TPS51611

AO4407A +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
Charger
BQ24745 +VCC_CORE +1.05V_VTT +CPU_GFX_CORE
AO4468
Battery +PBATT For UMA
RT8205B +1.5V_RUN
For Discrete
C
+1.5V_RUN_CPU C
+3.3V_ALW
+15V_ALW +3.3V_RTC_LDO +5V_ALW2 +5V_ALW
RT9715BGF AO4468 RT9715BGF AO4468 PA102FMG

SI2301CDS APL5930KAI
+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_RUN_VGA +3.3V_LAN

+KBC_PWR +1.8V_RUN
For Discrete
I/O Board USB Power CRT Board USB Power
RT9198-33PBG
APL5930KAI SI3456BD RTS5138 RTL8103T
B B
+3.3V_CRT_LDO
+1.8V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +1.2V_LOM
For Discrete
Power Shape
Regulator LDO Switch

A <Core Design> A
Wistron Corporation
Title
Power Block Diagram

A3
Berry X00
Date: Thursday , October 15 , 2009 Sheet 3 of 92
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN KBC SMBus Block Diagram
+5V_RUN
‧ ‧
+3.3V_RUN ‧
SRN2K2J-1-GP SRN2K2J-1-GP
‧
DIMM 1 SRN10KJ-5-GP
PCH_ SMB _CLK

‧ ‧ PCH_ SMBCLK
TouchPad Conn.
SMBCLK
SCL
1 SMBDATA PCH_ SMB _DATA
‧ ‧ PCH_ SMBDATA
SDA
PSDAT1 TPDATA ‧ TPDATA TPDATA
1
+3.3V_ALW
SMBus Address:A0 PSCLK1 TPCLK
‧ TPCLK TPCLK
2N7002SPT
‧ +KBC_PWR
SRN2K2J-8-GP
‧
SML1CLK KBC_ SCL1
SRN4K7J-8-GP
SML1DATA KBC_ SDA1 To KBC DIMM 2
2N7002DW-1-GP
+3.3V_ALW ‧ PCH_SMBCLK
SCL SRN100J-3-GP Battery Conn.
SML0CLK SML0_ CLK
‧ PCH_ SMBDATA
SDA
SCL1 BAT_ SCL PBAT_ SMBCLK1 CLK_SMB
SMBus address:16
SML0DATA SML0_DATA
‧ SMBus Address:A4
SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB
SRN2K2J-1-GP
+3.3V_RUN Clock BQ24745
‧ XDP ‧ PCH_ SMBCLK
Generator
SCLK
KBC SCL
SDA SMBus address:12

PCH SRN2K2J-1-GP
‧ PCH_ SMBDATA
SDATA
NPCE781BA0DX
UMA SMBus address:D2 +3.3V_RUN
2
SDVO_CTRLCLK PCH_ HDMI_ CLK Level PCH_ HDMI_ CLK
‧
2
SDVO_CTRLDATA PCH_ HDMI_ DATA

Shift PCH_ HDMI_ DATA Minicard +3.3V_RUN
UMA
‧ PCH_ SMBCLK
WLAN ‧
SRN4K7J-8-GP
+3.3V_RUN
‧ PCH_ SMBDATA
SMB_CLK
SMB_DATA
Thermal
‧ THERM _SCL SCL
SMBus address:7A
‧ ‧ THERM _SDA SDA
SRN2K2J-1-GP Minicard GPIO73/SCL2 KBC_SCL1
W-WAN
2N7002DW-1-GP
UMA SRN0J-6-GP GPIO74/SDA2 KBC_SDA1
PCH_ SMBCLK
SMB_CLK
L_DDC_CLK LDDC_ CLK _PCH
PCH_ SMBDATA
SMB_DATA
L_DDC_DATA LDDC_ DATA_ PCH
UMA
+3.3V_RUN_VGA
CRT_DDC_CLK PCH_ CRT _DDCCLK
CRT_DDC_DATA PCH_ CRT _DDCDATA

‧
SRN2K2J-1-GP
DIS
3
LCD CONN
DDC1CLK 3
DDC1DATA
SRN0J-6-GP
DDC2CLK VGA _ CRT _DDCCLK
DDC2DATA VGA _ CRT _DDCDATA
+3.3V_RUN DIS +5V_RUN
VGA ‧ ‧
+3.3V_RUN
SRN2K2J-1-GP SRN2K2J-1-GP
UMA
‧
SRN0J-6-GP UMA
CRT_ DDCCLK_ CON
CRT_ DDCDATA_ CON

CRT CONN
+3.3V_RUN_VGA +5V_RUN
UMA
2N7002DW-1-GP
‧
‧
+5V_RUN SRN2K2J-1-GP
SRN2K2J-1-GP
4 4
DIS
IFPC_AUX_I2CW_SCL GPU _HDMI_ CLK
TSCBTD3305CPWR
IFPC_AUX_I2C_SDA# GPU_HDMI_DATA
HDMI CONN <Core Design>
Wistron Corporation
Title
SMBUS Block Diagram

A2 Berry X00
Date: W ednesday, October 14, 2009 Sheet 4 of 92
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPKR_PORT_D_L-
SPKR_PORT_D_R+ SPEAKER
Codec
DP1 EMC2102_DP1
92HD79B1
SC470P50V3JN-2GP
MMBT3904-3-GP HP1_PORT_B_L HP
HP1_PORT_B_R
2
DN1 EMC2102 _DN1
OUT 2
Place near CPU

Thermal PWM CORE
G7922R61U
DP2 THRMDA
VGA_THERMDA
VGA HP0_PORT_A_L MIC
DN2 THRMDC HP0_PORT_A_R
VGA_THERMDC VREFOUT_A_OR_F IN
Place near GPU(DISCRETE only).
MMBT3904-3-GP
3 3
DMIC_CLK/GPIO1
System Sensor(UMA only) DMIC0/GPIO2
DP3 EMC2102_ DP3
MMBT3904-3-GP
SC470P50V3JN-2GP
DN3 EMC2102_DN3
PORTC_L
Put under CPU(T8 HW shutdown) Analog
PORTC_R
VREFOUT_C MIC
4 4
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custo m
Berry X00
Date: Wednesday, October 14, 2009 Sheet 5 of 92
A B C D E
A B C D E
PCH Strapping Processor Strapping

Calpella Schematic Checklist Rev.0_7 Calpella Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down. 1: Disabled - No Physical Display Port attached to
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ CFG[4] Embedded 1
- 10-kΩ weak pull-up resistor. DisplayPort Embedded DisplayPort.
4 Presence 4
0: Enabled - An external Display Port device is
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-kΩ wea k Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1#/GPIO51 required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0) = Configures DMI for ESI compatible operation (for server s impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.

Disable ME in Manufacturing Mode: Connect to ground with 1-kΩ
pull-down resistor.
3 3
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor .
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-kΩ weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-kΩ weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
2 circuits for analog rails. 2
PCIE Routing USB Table SATA Table

USB SATA
Pair Device Pair Device
LANE1 RESERVED 0 USB2 (CRT Board)
0 HDD
LANE2 MiniCard WLAN 1 USB3 (CRT Board)
1 ODD
2 WLAN (I/O Board)
LANE3 LAN 2 HM55 no support
3 RESERVED
3 HM55 no support
LANE4 W-WAN 4 CARD READER
4 ESATA
5 BLUETOOTH
LANE5 RESERVED 5 RESERVED
6 HM55 no support
LANE6 RESERVED 7 HM55 no support

8 USB1 (I/O Board)
1 LANE7 H55/HM55 no support
<Core Design>
1
9 USB0 (I/O Board ESATA)
Wistron Corporation
LANE8 H55/HM55 no support 10 RESERVED 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
11 W-WAN (I/O Board) Taipei Hsien 221, Taiwan, R.O.C.
12 RESERVED Title
13 CAMERA Table of Content

A3
Berry X00
5 4 3 2 1
SSID = CLOCK
+3.3V_RUN
+3.3V_RUN_SL585 +1.05V_VTT
D R701 D
+1.05V_RUN_SL585_IO
R702
1 2
1 2
0R3J-0-U-GP
C702
0R3J-0-U-GP C709 C710 C711
C708
DY C701 C703 C704 C705 C706 C707
DY DY
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
+3.3V_RUN
R703
1 2 CPU _ STOP#
C 2K2R2J-2-GP C
U701
4 6 CLK _ VGA _ 27M _ NSS_ R 4 DIS 1 RN701 CLK_VGA_27M_NSS

CLK_DREF# DOT_96# 27MHZ CLK _ VGA _ 27M _ SS_ R
3 DOT_96 27MHZ_SS 7 3 2 SRN33J-5-GP-U CLK_VGA_27M_SS
SRN0J-6-GP CLK_DREF
2 3 CLKIN_DMI#_C 14
CLKIN_DMI# SRC_2#
1 4 CLKIN _ DMI _ C 13 CPU _ STOP# EC701 EC702
CLKIN_DMI SRN0J-6-GP SRC_2 CPU_STOP# 16
25 CK _ PW RGD R704 DY SC4D7P50V2CN-1GP DY SC4D7P50V2CN-1GP
RN702 CLK _ PCIE _ SATA# _ C
CKPW RGD/PD# FSC
CLK_PCIE_SATA# 2 3 11 30 2 1 CLK_PCH_14M
CLK _ PCIE _ SATA _ C
SRC_1/SATA# REF_0/CPU_SEL 33R2J-2-GP
CLK_PCIE_SATA 1 4 10 SRC_1/SATA
RN703 22 28 CLK _ XTAL _ IN
CLK_CPU_BCLK#
CLK_CPU_BCLK 23
CPU_0# XTAL_IN
27 CLK _ XTAL _ OUT DY EC703
CPU_0 XTAL_OUT
19 31 SC4D7P50V2CN-1GP
CPU_1# SDA
20 CPU_1 SCL 32
PCH_SMBDATA +3.3V_RUN_SL585
PCH_SMBCLK
B B
SLG8SP585VTR-G P
R705
10KR2J-3-GP
CK _ PW RGD
+1.05V_VTT
FSC 0 1
. Q701
133MHz X701 R706 2N7002E-1-GP
SPEED 100MHz CLK _ XTAL _ IN 1 2 CLK_XTAL_OUT
DY 4K7R2J-2-GP .
.
(Default) . .
X-14D31818M-37GP
C712 82.30005.901 C713

SC12P50V2JN-3GP SC12P50V2JN-3GP FSC
VR_CLKEN#
R707
10KR2J-3-GP
A <Core Design> A
Wistron Corporation
Title
Clock Generator SLG8SP585

Berry X00
5 4 3 2 1
D D
DMI_PTX_CRXN0 A24
DMI_PTX_CRXN1 C23
DMI_PTX_CRXN2 B22
DMI_PTX_CRXN3 A21 PEG RXN15
PEG RXN14
B24 PEG RXN13
DMI_PTX_CRXP0
D23 PEG RXN12
DMI_PTX_CRXP1
B23 PEG RXN11
DMI_PTX_CRXP2
DMI_PTX_CRXP3 A22 PEG_RXN10
PEG_RXN9
D24 PEG RXN8
DMI_CTX_PRXN0
G24 PEG RXN7
DMI_CTX_PRXN1
F23 PEG RXN6
DMI_CTX_PRXN2
DMI_CTX_PRXN3 H23 PEG RXN5
PEG RXN4
D25 PEG RXN3
DMI_CTX_PRXP0
F24 PEG RXN2
DMI_CTX_PRXP1
E23 PEG RXN1
DMI_CTX_PRXP2
G23 PEG RXN0
DMI_CTX_PRXP3
PEG RXP15
PEG RXP14
C E22
PEG RXP13
PEG RXP12
FDI_TXN0
FDI_TXN1 D21 PEG RXP11
D19 PEG RXP10
FDI_TXN2
D18 PEG RXP9
FDI_TXN3
G21 PEG RXP8
FDI_TXN4
E19 PEG RXP7
FDI_TXN5
FDI_TXN6 F21 PEG RXP6
G18 PEG RXP5
FDI_TXN7
PEG RXP4
PEG RXP3
D22 PEG_RXP2
FDI_TXP0
FDI_TXP1 C21 PEG_RXP1
D20 PEG RXP0
FDI_TXP2
FDI_TXP3 C18
G22 PEG C TXN15
FDI_TXP4
E20 PEG C TXN14
FDI_TXP5
FDI_TXP6 F20 PEG C TXN13
G19 PEG C TXN12
FDI_TXP7
PEG C TXN11
F17 PEG C TXN10
FDI_FSYNC0
E17 PEG C TXN9
FDI_FSYNC1
PEG C TXN8
C17 PEG C TXN7
FDI_INT
PEG C TXN6
F18 PEG C TXN5
FDI_LSYNC0
D17 PEG C TXN4
FDI_LSYNC1
PEG C TXN3
PEG C TXN2
PEG C TXN1
B PEG C TXN0
R804
1KR2J-1-GP PEG C TXP15
DIS RN801 PEG C TXP14
PEG C TXP13
SRN1KJ-4-GP PEG C TXP12
PEG_C_TXP11
PEG_C_TXP10
PEG C TXP9
PEG C TXP8
PEG C TXP7
PEG C TXP6
PEG C TXP5
PEG C TXP4
PEG C TXP3
PEG C TXP2
PEG C TXP1
PEG C TXP0
SEC. 62.10053.561
A
CPU (PCIE/DMI/FDI)
Berry X00
Date: Thursday October 22 2009 Sheet 8 of 92
5 4 3 2 1
SSID = CPU
CPU1A 1 OF 9
PEG_ICOMPI B26 PEG _IRCOMP _ R R801 1 2 49D9R2F-GP

A26 R802 1 2 750R2F-GP
PEG_ICOMPO
DMI_RX#0 PEG_RCOMPO B27
A25 EXP _ RBIAS
DMI_RX#1 PEG_RBIAS PEG _ RXN[0..15]
DMI_RX#2 PEG_RXN[0..15]
K35 _
DMI_RX#3 PEG_RX#0 _
J34
PEG_RX#1 _
DMI_RX0 PEG_RX#2 J33
G35 _
DMI_RX1 PEG_RX#3 _
DMI_RX2 PEG_RX#4 G32
DMI_RX3 PEG_RX#5 F34
PEG_RX#6 F31
D35 _
DMI_TX#0 PEG_RX#7
E33 _
DMI_TX#1 PEG_RX#8 _
DMI_TX#2 PEG_RX#9 C33
D32 _
DMI_TX#3 PEG_RX#10 _
B32
PEG_RX#11 _
DMI_TX0 PEG_RX#12 C31
B28 _
DMI_TX1 PEG_RX#13 _
DMI_TX2 PEG_RX#14 B30
A31 _
DMI_TX3 PEG_RX#15 PEG _ RXP[0..15]
PEG_RXP[0..15]
J35 _
PEG_RX0
H34 _
PEG_RX1
PEG_RX2 H33
F35
_
_
C
FDI_TX#0 PEG_RX3 _
G33
FDI_TX#1 PEG_RX4 _
FDI_TX#2 PEG_RX5 E34
F32 _
FDI_TX#3 PEG_RX6 _
FDI_TX#4 PEG_RX7 D34
F33 _
FDI_TX#5 PEG_RX8 _
B33
FDI_TX#6 PEG_RX9 _
FDI_TX#7 PEG_RX10 D31
A32 _
PEG_RX11 _
PEG_RX12 C30
FDI_TX0 PEG_RX13 A28
B29
FDI_TX1 PEG_RX14 _ PEG _ TXN[0..15]
FDI_TX2 PEG_RX15 A30 PEG_TXN[0..15]
FDI_TX3
FDI_TX4 PEG_TX#0 L33 _ _ DIS1 2 C816 SCD1U16V2KX-3GP PEG _ TXN15
FDI_TX5 PEG_TX#1 M35 _ _ DIS1 C815 SCD1U16V2KX-3GP PEG _ TXN14
FDI_TX6 PEG_TX#2
M33 _ _ DIS1 2 C814 SCD1U16V2KX-3GP PEG _ TXN13
FDI_TX7 PEG_TX#3 M30 _ _ DIS1 C813 SCD1U16V2KX-3GP PEG _ TXN12
PEG_TX#4 L31 _ _ DIS1 2 C812 SCD1U16V2KX-3GP PEG _ TXN11
FDI_FSYNC0 PEG_TX#5 K32 _ _ DIS1 2 C811 SCD1U16V2KX-3GP PEG _ TXN10
FDI_FSYNC1 PEG_TX#6 M29 _ _ DIS1 C810 SCD1U16V2KX-3GP PEG _ TXN9
PEG_TX#7
J31 _ _ DIS1 2 C809 SCD1U16V2KX-3GP PEG _ TXN8
FDI_INT PEG_TX#8 K29 _ _ DIS1 C808 SCD1U16V2KX-3GP PEG _ TXN7
PEG_TX#9 H30 _ _ DIS1 C807 SCD1U16V2KX-3GP PEG _ TXN6
FDI_LSYNC0 PEG_TX#10 H29 _ _ DIS1 C806 SCD1U16V2KX-3GP PEG _ TXN5
FDI_LSYNC1 PEG_TX#11 F29 _ _ DIS1 2 C805 SCD1U16V2KX-3GP PEG _ TXN4
PEG_TX#12 E28 _ _ DIS1 2 C804 SCD1U16V2KX-3GP PEG _ TXN3
PEG_TX#13 D29 _ _ DIS1 2 C803 SCD1U16V2KX-3GP PEG _ TXN2

D27 _ _ DIS1 C802 SCD1U16V2KX-3GP PEG _ TXN1
PEG_TX#14
PEG_TX#15 C26 _ _ DIS1 2 C801 SCD1U16V2KX-3GP PEG _ TXN0 B
PEG _ TXP[0..15]
PEG_TXP[0 ..15]
DIS PEG_TX0
L34 _ _ DIS1 C832 SCD1U16V2KX-3GP PEG _ TXP15
PEG_TX1 M34 _ _ DIS1 2 C831 SCD1U16V2KX-3GP PEG _ TXP14
PEG_TX2 M32 _ _ DIS1 C830 SCD1U16V2KX-3GP PEG _ TXP13
PEG_TX3 L30 _ _ DIS1 C829 SCD1U16V2KX-3GP PEG _ TXP12
PEG_TX4 M31 DIS1 2 C828 SCD1U16V2KX-3GP PEG_TXP11
PEG_TX5
K31 DIS1 2 C827 SCD1U16V2KX-3GP PEG_TXP10
PEG_TX6 M28 _ _ DIS1 2 C826 SCD1U16V2KX-3GP PEG _ TXP9
PEG_TX7 H31 _ _ DIS1 C825 SCD1U16V2KX-3GP PEG _ TXP8
PEG_TX8 K28 _ _ DIS1 C824 SCD1U16V2KX-3GP PEG _ TXP7
PEG_TX9 G30 _ _ DIS1 C823 SCD1U16V2KX-3GP PEG _ TXP6
PEG_TX10 G29 _ _ DIS1 2 C822 SCD1U16V2KX-3GP PEG _ TXP5

PEG_TX11 F28 _ _ DIS1 C821 SCD1U16V2KX-3GP PEG _ TXP4
PEG_TX12 E27 _ _ DIS1 2 C820 SCD1U16V2KX-3GP PEG _ TXP3
PEG_TX13 D28 _ _ DIS1 2 C819 SCD1U16V2KX-3GP PEG _ TXP2
PEG_TX14 C27 _ _ DIS1 C818 SCD1U16V2KX-3GP PEG _ TXP1
PEG_TX15 C25 _ _ DIS1 2 C817 SCD1U16V2KX-3GP PEG _ TXP0
CLARKU1NF
62.10055.341
<Core Design>
A
Wistron Corporation
Title
, ,
5 4 3 2 1
Processor Compensation Signals
SSID = CPU
+1.05V_VTT S3_RST_GATE#
CPU1B 2 OF 9
Processor Pullups
1 2 H_COMP3 AT23 RN901
R902 20R2F-GP
COMP3 BCLK _CPU _ C _ P 1
BCLK A16 4 BCLK_CPU_P
R901 1 2 49D9R2F-GP H _ CATERR# 1 2 H _ COMP2 AT24 B16 BCLK _ CPU _ C _ N 2 3
COMP2 BCLK# BCLK_CPU_N
R903 20R2F-GP +1.5V_SUS
1 2 H _ COMP1 G16 AR30 BCLK_ITP_P SRN0J-6-GP
R907 1
COMP1 BCLK_ITP
2 68R2-GP H _ PROCHOT# R904 49D9R2F-GP
BCLK_ITP# AT30 BCLK _ITP _ N
1 2 H _ COMP0 AT26 RN902
R905 49D9R2F-GP
COMP0 CLK _EXP _C _ P 1 R908
PEG_CLK E16 4 CLK_EXP_P
R906 1 2 68R2-GP H _ CPURST# D16 CLK _ EXP _ C _ N 2 3 Q901 1KR2J-1-GP
D DY TPAD14-GP TP901 1 SKTOCC# _ R AH24
PEG_CLK# CLK_EXP_N
BSS138-7F-GP D
SKTOCC# SRN0J-6-GP
A18
DPLL_REF_SSCLK
DPLL_REF_SSCLK# A17
H _ CATERR# AK14 S D
CATERR# DDR3_DRAMRST#
PM_EXTTS#0_C
F6 SM _ DRAMRST#
SM_DRAMRST# RN903 +1.05V_VTT
H_PECI AT15 PECI
AL1 SM _ RCOMP _ 0 4 1
SM_RCOMP0 SM _ RCOMP _ 1
AM1 3 2 1 2
SM_RCOMP1 SM _ RCOMP _ 2 R909 0R2J-2-GP
SM_RCOMP2 AN1
AN26 SRN10KJ-5-GP
H_PROCHOT# PROCHOT#
AN15 PM _ EXTTS#0 _ C 1 4
PM_EXT_TS#0 PM_EXTTS#0
AP15 PM _ EXTTS#1 _ C 2 3
PM_EXT_TS#1 PM_EXTTS#1
H_THERMTRIP# AK15 RN904

THERMTRIP# SRN0J-6-GP
DDR3 Compensation Signals
AT28 XDP _ PRDY#
PRDY# XDP _ PREQ# SM _ RCOMP _ 0 R913 1
PREQ# AP27 2 100R2F-L1-GP-U
AN28 XDP _ TCLK SM _ RCOMP _ 1 R914 1 2 24D9R2F-L-GP

H _ CPURST# TCK XDP _ TMS
AP26 RESET_OBS# TMS AP28
AT27 XDP _ TRST# SM _ RCOMP _ 2 R916 1 2 130R2F-1-GP
TRST#
AL15 AT29 XDP _ TDI _ R
H_PM_SYNC PM_SYNC TDI
AR27 XDP _ TDO _ R
TDO XDP _ TDI _ M
TDI_M AR29
AN14 AP29 XDP _ TDO _ M
VCCPWRGOOD_1 TDO_M +1.05V_VTT
C R910 AN25 H _ DBR# _ R 1
R911
2 XDP_DBRESET#
C
VCCPW RGOOD
DBR# XDP _ TMS
1 2 AN27 1 2
H_PW RGD VCCPWRGOOD_0 0R2J-2-GP R919 DY 51R2J-2-GP
0R2J-2-GP R912 XDP _ OBS0 XDP _ TDI_ R 1 2
PM_DRAM_PW RGD 1 2 VDDPW RGOOD _ R AK13
BPM#0 AJ22
AK22 XDP _ OBS1 +1.5V_RUN_CPU R920 DY 51R2J-2-GP
SM_DRAMPW ROK BPM#1 XDP _ OBS2 XDP _ PREQ# 1 2
0R2J-2-GP
BPM#2 AK24
AJ24 XDP _ OBS3 R922 DY 51R2J-2-GP
BPM#3 XDP _ OBS4
H_VTTPW RGD AM15 VTTPWRGOOD BPM#4 AJ25
AH22 XDP _ OBS5 R915 XDP _ TCLK 1 2
BPM#5
AK23 XDP _ OBS6 1KR2J-1-GP R923 DY 51R2J-2-GP
H_PW RGD_XDP AM26
BPM#6
AH23 XDP_OBS7 DY
TAPPW RGOOD BPM#7
For EMI PLT_RST# 1 2 PLT _ RST# _ R AL14 RSTIN# SM _ DRAMRST#

R917
XDP _ RST# _ R 1K54R2F-GP R918
VCCPW RGOOD 750R2F-GP CLARKU1NF
VDDPW RGOOD _ R +3.3V_RUN
H _ VTTPW RGD R921
PLT _ RST# _ R
XDP _ DBRESET# DY 100KR2J-1-GP
EC906 EC905 EC904 EC903 EC902 EC901 U901
DY DY DY DY DY DY 1 A VCC
5
1.5CPU_1.05VTT_PW RGD 2 B
3 4 VTT_PW RGD_C
GND Y
B NL17SZ08DFT2G - GP DY R927 B
XDP _TDI _ R 1 2 XDP _ TDI
XDP1
1K54R2F-GP
R928 DY 0R2J-2-GP
NP1 XDP_TRST#
VDDPW RGOOD _ R XDP _ TDO _ M 1 2 XDP _ TDO
+1.5V_SUS +1.5V_RUN_CPU 1
61
2 R929 DY 0R2J-2-GP
62
XDP_PREQ#
XDP _ PRDY#
3
5
4
6 For S3 Reduction DY
R930
750R2F-GP
R931
0R2J-2-GP
R924 R925 7 8 R932
1K1R2F-GP DY 1K1R2F-GP XDP _ OBS0 9 10
XDP _ OBS1 11 12 XDP _ TDI_ M 1 2
13 14 R933 DY 0R2J-2-GP
XDP _ OBS2 15 16
VDDPW RGOOD _ R XDP _ OBS3 17 18 XDP _ TDO _ R 1 2
19 20 R934 0R2J-2-GP
21 22
R926 23 24 Scan Chain Stuff --> R928, R931, R934 JTAG MAPPING
3KR2F-GP 25 26 +1.05V_VTT
XDP _ OBS4 27 28 (Default) No Stuff --> R929, R933
XDP _ OBS5 29
DY 30 CPU Only Stuff --> R928, R929
31 32
XDP _ OBS6 33 34 C901 No Stuff --> R931, R934, R933
+1.05V_VTT XDP _ OBS7 SCD1U16V2KX-3GP
35 36
DY GMCH Only Stuff --> R933, R934
37 38
H _ PW RGD H _ CPUPW RGD _ XDP BCLK _ ITP_ P R936 No Stuff --> R928, R929, R931
1
R935 1 DY 2
2 1KR2J-1-GP PM _PW RBTN# _ XDP
39
41
40
42 BCLK _ ITP_ N 51R2J-2-GP
PM_PW RBTN#_R
R937 DY 0R2J-2-GP 43 44
H _ PW RGD _ XDP 1 2 PCIE _ CLK _ XDP _ P 45 46 XDP_ RST#_ R 1 2H_CPURST#
A R938 DY 0R2J-2-GP 47 48 R939 DY 1KR2J-1-GP
XDP_DBRESET#
<Core Design>
A
49 50
C902 51 52 XDP_TDO
DY SCD1U16V2KX-3GP
SML0_DATA
SML0_CLK 53 54 XDP_TRST# Wistron Corporation
55 56 XDP _ TDI 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
XDP _ TCLK 57 58 XDP _ TMS Taipei Hsien 221, Taiwan, R.O.C.
59 60
63 Title
64
NP2 XDP_RST#_R 1 2
DY0R2J-2-GP CPU (THERMAL/CLOCK/PM )
R940 Size Document Number Rev
STC-CONN60A-GP-U1 PLT_RST#
Berry X00
5 4 3 2 1
SSID = CPU CPU1D 4 OF 9
CPU1C 3 OF 9
SB_CK0 W8 M_CLK_DDR2
M _ B _ DQ[63..0] W9
M_B_DQ[63..0] SB_CK#0 M_CLK_DDR#2
AA6 M_CLK_DDR0 M _ B _ DQ0 B5 M3 M_CKE2
SA_CK0 M _ B _ DQ1 SB_DQ0 SB_CKE0
SA_CK#0 AA7 M_CLK_DDR#0 A5 SB_DQ1
M _ A_ DQ[63..0] P7 M _ B _ DQ2 C3
M_A_DQ[63..0] SA_CKE0 M_CKE0 SB_DQ2
M _ A _ DQ0 A10 M _ B_ DQ3 B3 V7
SA_DQ0 SB_DQ3 SB_CK1 M_CLK_DDR3
D M _ A _ DQ1 C10 M _ B_ DQ4 E4 V6 D
SA_DQ1 SB_DQ4 SB_CK#1 M_CLK_DDR#3
M _ A _ DQ2 C7 M _ B_ DQ5 A6 M2 M_CKE3
M _ A _ DQ3 SA_DQ2 M _ B_ DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 A4 SB_DQ6
M _ A _ DQ4 B10 Y5 M _ B_ DQ7 C4
SA_DQ4 SA_CK#1 M_CLK_DDR#1 SB_DQ7
M _ A _ DQ5 D10 P6 M_CKE1 M _ B_ DQ8 D1
M _ A _ DQ6
SA_DQ5 SA_CKE1 M _ B_ DQ9
SB_DQ8
E10 SA_DQ6 D2 SB_DQ9
M _ A _ DQ7 A8 M _ B_ DQ10 F2 AB8 M_CS#2
M _ A _ DQ8 SA_DQ7 M _ B_ DQ11 SB_DQ10 SB_CS#0
D8 SA_DQ8 F1 SB_DQ11 SB_CS#1 AD6 M_CS#3
M _ A _ DQ9 F10 AE2 M _ B_ DQ12 C2
SA_DQ9 SA_CS#0 M_CS#0 SB_DQ12
M _ A_ DQ10 E6 AE8 M_CS#1 M _ B_ DQ13 F5
M _ A_ DQ11
SA_DQ10 SA_CS#1 M _ B_ DQ14
SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M _ A_ DQ12 E9 M _ B_ DQ15 G4 AC7 M_ODT2
M _ A_ DQ13 SA_DQ12 M _ B_ DQ16 SB_DQ15 SB_ODT0
B7 SA_DQ13 H6 SB_DQ16 SB_ODT1 AD1 M_ODT3
M _ A_ DQ14 E7 AD8 M _ B_ DQ17 G2
SA_DQ14 SA_ODT0 M_ODT0 SB_DQ17
M _ A_ DQ15 C6 AF9 M_ODT1 M _ B_ DQ18 J6
M_A_DQ16
SA_DQ15 SA_ODT1 M_B_DQ19
SB_DQ18
H10 SA_DQ16 J3 SB_DQ19
M_A_DQ17 G8 M_B_DQ20 G1
M _ A_ DQ18 SA_DQ17 M _ B_ DQ21 SB_DQ20 M_ B_ DM0
K7 SA_DQ18 G5 SB_DQ21 SB_DM0 D4
M _ A_ DQ19 J8 M _ B_ DQ22 J2 E1 M_ B_ DM1
M _ A_ DQ20
SA_DQ19 M _ B_ DQ23
SB_DQ22 SB_DM1 M_ B_ DM2
G7 SA_DQ20 J1 SB_DQ23 SB_DM2 H3
M _ A_ DQ21 G10 M _ B_ DQ24 J5 K1 M_ B_ DM3
M _ A_ DQ22
SA_DQ21 M _ A_ DM0 M_ B_ DQ25
J7 B9 K2 AH1
M _ A_ DQ23 SA_DQ22 SA_DM0 M _ A_ DM1 M_ B_ DQ26 SB_DQ25 SB_DM4 M_ B_ DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0]
M _ A_ DQ24 L7 H7 M _ A_ DM2 M_ B_ DQ27 M1 AR4 M_ B_ DM6
M _ A_ DQ25
SA_DQ24 SA_DM2 M _ A_ DM3 M_ B_ DQ28
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0]
M _ A_ DQ26 M8 AG6 M _ A_ DM4 M_ B_ DQ29 K4
M _ A_ DQ27
SA_DQ26 SA_DM4 M _ A_ DM5 M_ B_ DQ30
SB_DQ29
L9 SA_DQ27 SA_DM5 AM7 M_A_DM[7..0] M4 SB_DQ30
M _ A_ DQ28 L6 AN10 M _ A_ DM6 M_ B_ DQ31 N5
SA_DQ28 SA_DM6 SB_DQ31 M_B_DQS[7..0]
M _ A_ DQ29 K8 AN13 M _ A_ DM7 M_ B_ DQ32 AF3
SA_DQ29 SA_DM7 M_A_DQS#[7..0] SB_DQ32
C M _ A_ DQ30 N8 M _ B_ DQ33 AG1 C
SA_DQ30 SB_DQ33 M_B_A[15..0]
M _ A_ DQ31 P9 M _ B_ DQ34 AJ3 D5 M_ B_ DQS#0
M _ A_ DQ32
SA_DQ31 M _ B_ DQ35
SB_DQ34 SB_DQS#0 M_ B_ DQS#1
AH5 M_A_DQS[7..0] AK1 F4
M _ A_ DQ33 SA_DQ32 M _ B_ DQ36 SB_DQ35 SB_DQS#1 M_ B_ DQS#2
AF5 SA_DQ33 AG4 SB_DQ36 SB_DQS#2 J4
M _ A_ DQ34 AK6 C9 M _ A_ DQS#0 M_ B_ DQ37 AG3 L4 M_ B_ DQS#3
SA_DQ34 SA_DQS#0 M_A_A[15..0] SB_DQ37 SB_DQS#3
M _ A_ DQ35 AK7 F8 M _ A_ DQS#1 M_ B_ DQ38 AJ4 AH2 M_ B_ DQS#4
M _ A_ DQ36
SA_DQ35 SA_DQS#1 M _ A_ DQS#2 M_ B_ DQ39
SB_DQ38 SB_DQS#4 M_ B_ DQS#5
AF6 SA_DQ36 SA_DQS#2 J9 AH4 SB_DQ39 SB_DQS#5 AL4
M _ A_ DQ37 AG5 N9 M _ A_ DQS#3 M_ B_ DQ40 AK3 AR5 M_ B_ DQS#6
M _ A_ DQ38 SA_DQ37 SA_DQS#3 M _ A_ DQS#4 M_ B_ DQ41 SB_DQ40 SB_DQS#6 M_ B_ DQS#7
AJ7 SA_DQ38 SA_DQS#4 AH7 AK4 SB_DQ41 SB_DQS#7 AR8
M _ A_ DQ39 AJ6 AK9 M _ A_ DQS#5 M_ B_ DQ42 AM6
M _ A_ DQ40
SA_DQ39 SA_DQS#5 M _ A_ DQS#6 M_ B_ DQ43
SB_DQ42
AJ10 SA_DQ40 SA_DQS#6 AP11 AN2 SB_DQ43
M_A_DQ41 AJ9 AT13 M_A_DQS#7 M_B_DQ44 AK5
M_A_DQ42
SA_DQ41 SA_DQS#7 M_B_DQ45
SB_DQ44
AL10 AK2
M _ A_ DQ43 SA_DQ42 M _ B_ DQ46 SB_DQ45
AK12 SA_DQ43 AM4 SB_DQ46
M _ A_ DQ44 AK8 M _ B_ DQ47 AM3
M _ A_ DQ45
SA_DQ44 M _ B_ DQ48
SB_DQ47 M_ B_ DQS0
AL7 SA_DQ45 AP3 SB_DQ48 SB_DQS0 C5
M _ A_ DQ46 AK11 C8 M _ A_ DQS0 M_ B_ DQ49 AN5 E3 M_ B_ DQS1
M _ A_ DQ47
SA_DQ46 SA_DQS0 M _ A_ DQS1 M_ B_ DQ50
SB_DQ49 SB_DQS1 M_ B_ DQS2
AL8 F9 AT4 H4
M _ A_ DQ48 SA_DQ47 SA_DQS1 M _ A_ DQS2 M_ B_ DQ51 SB_DQ50 SB_DQS2 M_ B_ DQS3
AN8 SA_DQ48 SA_DQS2 H9 AN6 SB_DQ51 SB_DQS3 M5
M _ A_ DQ49 AM10 M9 M _ A_ DQS3 M_ B_ DQ52 AN4 AG2 M_ B_ DQS4
M _ A_ DQ50
AR11 SA_DQ50 SA_DQS4 AH8 AN3 SB_DQ53 SB_DQS5 AL5
M _ A_ DQ51 AL11 AK10 M _ A_ DQS5 M_ B_ DQ54 AT5 AP5 M_ B_ DQS6
M _ A_ DQ52
AM9 AN11 AT6 SB_DQS7 AR7
M _ A_ DQ53 SA_DQ52 SA_DQS6 M _ A_ DQS7 M_ B_ DQ56 SB_DQ55
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M _ A_ DQ54 AT11 M _ B_ DQ57 AP6
M _ A_ DQ55
SA_DQ54 M _ B_ DQ58
SB_DQ57
AP12 SA_DQ55 AP8 SB_DQ58
M _ A_ DQ56 AM12 M _ B_ DQ59 AT9
M _ A_ DQ57
SA_DQ56 M _ B_ DQ60
SB_DQ59
AN12 SA_DQ57 AT7 SB_DQ60
M _ A_ DQ58 AM13 Y3 M _ A _ A0 M_ B_ DQ61 AP9
B
M _ A_ DQ59
SA_DQ58 SA_MA0 M _ A _ A1 M_ B_ DQ62
SB_DQ61 B
AT14 SA_DQ59 SA_MA1 W1 AR10 SB_DQ62
M _ A_ DQ60 AT12 AA8 M _ A _ A2 M_ B_ DQ63 AT10 U5 M_ B_ A0
M _ A_ DQ61
SA_DQ60 SA_MA2 M _ A _ A3
SB_DQ63 SB_MA0 M_ B_ A1
AL13 SA_DQ61 SA_MA3 AA3 SB_MA1 V2
M _ A_ DQ62 AR14 V1 M _ A _ A4 T5 M_ B_ A2
M _ A_ DQ63
SA_DQ62 SA_MA4 M _ A _ A5 SB_MA2 M_ B_ A3
AP14 SA_DQ63 SA_MA5 AA9 SB_MA3 V3
V8 M _ A _ A6 R1 M _ B _ A4
SA_MA6 M _ A _ A7
SB_MA4 M _ B _ A5
SA_MA7 T1 M_B_BS0 AB1 SB_BS0 SB_MA5 T8
Y9 M_A_A8 W5 R2 M_B_A6
SA_MA8 M_B_BS1 SB_BS1 SB_MA6
M_A_BS0 AC3 U6 M_A_A9 M_B_BS2 R7 R6 M_B_A7
SA_BS0 SA_MA9 M _ A _ A10
SB_BS2 SB_MA7 M _ B _ A8
M_A_BS1 AB2 SA_BS1 SA_MA10 AD4 SB_MA8 R4
M_A_BS2 U7 T2 M _ A _ A11 R5 M _ B _ A9
SA_BS2 SA_MA11 M _ A _ A12
SB_MA9 M _ B _ A10
SA_MA12 U3 M_B_CAS# AC5 SB_CAS# SB_MA10 AB5
AG8 M _ A _ A13 Y7 P3 M _ B _ A11
SA_MA13 M_B_RAS# SB_RAS# SB_MA11
T3 M _ A _ A14 AC6 R3 M _ B _ A12
SA_MA14 M_B_W E# SB_W E# SB_MA12
AE1 V9 M _ A _ A15 AF7 M _ B _ A13
M_A_CAS# SA_CAS# SA_MA15 SB_MA13
AB3 P5 M _ B _ A14
M_A_RAS# SA_RAS# SB_MA14
AE9 N1 M _ B _ A15
M_A_W E# SA_W E# SB_MA15
CLARKU1NF
CLARKU1NF
A <Core Design> A
Wistron Corporation
Title
CPU (DDR)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1E 5 OF 9
AJ13
RSVD#AJ13
D AJ12 D
RSVD#AJ12
AP25
RSVD#AP25
AL25 AH25
RSVD#AL25 RSVD#AH25
AL24 AK26
RSVD#AL24 RSVD#AK26
AL22
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF_37
M27
CFG0 RSVD#M27
L28 AJ26
RSVD#L28 RSVD#AJ26
PCI-Express Configuration Select J17
SA_DIMM_VREF RSVD#AJ27
AJ27
H17
R1101 SB_DIMM_VREF
G25
3KR2F-GP RSVD#G25
DY 1:Single PEG G17
RSVD#G17
CFG0 0:Bifurcation enabled E31
RSVD#E31
E30
RSVD#E30
AL28
RSVD#AL28
CFG0 AM30 AL29
TPAD14-GP TP1101 CFG1 CFG0 RSVD#AL29
1 AM28 AP30
TPAD14-GP TP1102 CFG2 CFG1 RSVD#AP30
1 AP31 AP32
TPAD14-GP TP1103 CFG3 CFG2 RSVD#AP32
1 AL32 AL27
CFG3 CFG4 CFG3 RSVD#AL27
AL30 AT31
CFG4 RSVD#AT31
CFG3 - PCI-Express Static Lane Reversal TPAD14-GP TP1104 1 CFG5 AM31
CFG5 RSVD#AT32
AT32
TPAD14-GP TP1105 1 CFG6 AN29 AP33
R1104 CFG7 CFG6 RSVD#AP33
DIS 3KR2J-2-GP 1 :Normal Operation TPAD14-GP TP1106 1 CFG8
AM32
AK32
CFG7 RSVD#AR33
AR33
CFG8
CFG3 0 :Lane Numbers Reversed TPAD14-GP TP1107 1 CFG9 AK31
CFG9
C TPAD14-GP TP1108 1 CFG10 AK28 C
CFG10
15 -> 0, 14 -> 1, ... TPAD14-GP
TPAD14-GP
TP1109
TP1110
1 CFG11
CFG12
AJ28
CFG11
1 AN30 AR32
TPAD14-GP TP1111 CFG13 CFG12 RSVD#AR32
1 AN32
TPAD14-GP TP1112 CFG14 CFG13
1 AJ32
TPAD14-GP TP1113 CFG15 CFG14
1 AJ29 E15
TPAD14-GP TP1114 CFG16 CFG15 RSVD_TP#E15
1 AJ30 F15
TPAD14-GP TP1115 CFG17 CFG16 RSVD_TP#F15
1 AK30 A2
CFG17 KEY
H16 D15
RSVD_TP_86 RSVD#D15
C15
RSVD#C15
AJ15
RSVD#AJ15
AH15
CFG4 RSVD#AH15
CFG4 - Display Port Presence B19
RSVD#B19
A19
R1105 RSVD#A19
3KR2F-GP 1:Disabled; No Physical Display Port
DY CFG4
A20
B20
RSVD#A20
attached to Embedded Display Port RSVD#B20
AA5
0:Enabled; An external Display Port SA_CK2
U9 AA4
RSVD#U9 SA_CK#2
device is connected to the Embedded T9
RSVD#T9 SA_CKE2
R8
AD3
Display Port AC9
SA_CS#2
AD2
RSVD#AC9 SA_ODT2
AB9 AA2
RSVD#AB9 SA_CK3
AA1
SA_CK#3
R9
SA_CKE3
AG7
SA_CS#3
AE3
SA_ODT3
CFG7 V4
SB_CK2
CFG7(Reserved) - Temporarily used for early SB_CK#2
V5
N2
R1106 Clarksfield samples. SB_CKE2
B
3KR2F-GP
J29
RSVD#J29 SB_CS#2
AD5 VSS (AP34) can be left NC is B
J28
DY CFG7 Clarksfield (only for early samples pre-ES1) -
RSVD#J28 SB_ODT2
AD7
W3 CRB implementation; EDS/DG
SB_CK3
Connect to GND with 3.01K Ohm/5% resistor. SB_CK#3
W2 recommendation to GND.
N3
SB_CKE3
AE5
SB_CS#3
Note: Only temporary for early CFD sample SB_ODT3
AD9
(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report]. AP34 RSVD _ VSS 1 2
VSS
For a common M/B design (for AUB and CFD),
R1107
the pull-down resistor shouble be used. Does 0R2J-2-GP
not impact AUB functionality.
CLARKU1NF
A A
<Core Design>
Wistron Corporation
Title
Size Document Number

CPU (RESERVED) Rev
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = CPU CPU1F 6 OF 9
+VCC_CORE
+1.05V_VTT
PROCESSOR CORE POWER

AG35 AH14
VCC VTT0
AG34 AH12
VCC VTT0 C1209 C1210 C1211 C1212 C1203 C1204 C1213 C1214
AG33 AH11
+VCC_CORE 48A AG32
VCC
VCC
VTT0
VTT0
AH10
DYC1202 DY DY DY DY
AG31 J14
VCC VTT0
D AG30 J13 D
VCC VTT0
AG29 H14
C1201 C1205 C1206 C1207 C1215 C1208 VCC VTT0
AG28 H12
VCC VTT0
DY DY AG27
AG26
VCC VTT0
G14
G13
VCC VTT0
AF35 G12
VCC VTT0
AF34 G11
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0 +1.05V_VTT
AF31 F12
VCC VTT0
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14
C1216 C1217 C1218
The decoupling capacitors, filter
AF28 E12
AF27
VCC VTT0
D14 recommendations and sense resistors on the
VCC VTT0
C1219 C1220 C1221 C1222 C1223 C1224
AF26
VCC VTT0
D13
DY CPU/PCH Rails are specific to the CRB
AD35 D12
AD34
VCC VTT0
D11 Implementation. Customers need to follow the
VCC VTT0
DY DY AD33
VCC VTT0
C14 recommendations in the Calpella Platform
DY AD32
AD31
VCC VTT0
C13
C12 Design Guide.
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
VCC VTT0
AD26 A13
VCC VTT0
AC35 A12
VCC VTT0
AC34 A11
VCC VTT0
AC33
C1226 C1228 C1229 C1230 C1231 C1232 VCC +1.05V_VTT
AC32
C1225 C1227 VCC
DY AC31
VCC
DY DY DY DY DY AC30
AC29
VCC VTT0
AF10
AE10
VCC VTT0 C1233 C1234
AC28 AC10
VCC VTT0
C AC27 AB10 C
VCC VTT0
AC26 Y10
VCC VTT0
AA35
AA34
VCC VTT0
W10
U10
DY
VCC VTT0
AA33 T10
VCC VTT0
AA32 J12
VCC VTT0
AA31 J11
VCC VTT0
AA30 J16
C1235 C1236 C1237 C1238 C1239 C1240 C1241 C1242 VCC VTT0
AA29 J15
VCC VTT0
AA28
VCC
DY DY DY AA27
AA26
VCC
VCC
Y35
Y34
VCC Please note that the VTT Rail
VCC
Y33
Y32
VCC Values are Auburndale
VCC
C1243
Y31
VCC VTT=1.05V; Clarksfield
Y30
VCC
DY Y29
VCC
VTT=1.1V
Y28
VCC
Y27
VCC
Y26
VCC
V35 AN33 PSI#
VCC PSI#
V34
VCC
V33 H_VID[6..0]
VCC H _ VID0
V32 AK35
VCC VID H _ VID1
V31 AK33
VCC VID H _ VID2
V30 AK34
VCC VID H _ VID3
V29 AL35
VCC VID H _ VID4
V28 AL33
VCC VID H _ VID5
V27 AM33
VCC VID H_VID6
V26 AM35
VCC VID
U35 AM34 PM_DPRSLPVR
VCC PROC_DPRSLPVR
B U34 B
VCC
U33
VCC
U32
VCC H_VTTVID1 TP1201 TPAD14-GP
U31 G15 1
VCC VTT_SELECT
U30
VCC
U29
VCC H_VTTVID1 = Low, 1.1V
U28
U27
VCC H_VTTVID1 = High, 1.05V
VCC +VCC_CORE
U26
VCC
R35
VCC
R34
VCC
R33
VCC R1201
R32 AN35 IMVP_IMON
VCC ISENSE 100R2F-L1-GP-U
R31
VCC
R30
VCC
R29
VCC
R28 AJ34 VCC_SENSE
VCC VCC_SENSE
R27 AJ35 VSS_SENSE
VCC VSS_SENSE
R26
VCC
P35
VCC R1202
P34 B15 VTT_SENSE
VCC VTT_SENSE TP _ VSS _ SENSE _ VTT 1 100R2F-L1-GP-U
P33 A15
VCC VSS_SENSE_VTT TP1202 TPAD14-GP
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
A A
<Core Design>
CLARKU1NF
Wistron Corporation
Title
Size
CPU (VCC_CORE)
Document Number Rev
Berry X00
Date: Thursday, October 22, 2009 Sheet 12 of 92
5 4 3 2 1
5 4 3 2 1
SSID = CPU
+CPU_GFX_CORE
22A CPU1G 7 OF 9
AT21 VAXG
D AT19 VAXG VAXG_SENSE AR22 VCC_AXG_SENSE D
C1301 C1302 C1303 C1304 C1305 C1306 C1307 C1308 AT18 AT22 VSS_AXG_SENSE
VAXG VSSAXG_SENSE
AT16 VAXG
R1302
DY DY DY DY UMA UMA UMA UMA DIS AR21
AR19
VAXG
0R3J-0-U-GP
VAXG
AR18 VAXG
AR16 AM22 GFX_VID0
VAXG GFX_VID
AP21 VAXG GFX_VID AP22 GFX_VID1
AP19 VAXG GFX_VID AN22 GFX_VID2
AP18 VAXG GFX_VID AP23 GFX_VID3
AP16 VAXG GFX_VID AM23 GFX_VID4
AN21 AP24 GFX_VID5
VAXG GFX_VID
AN19 VAXG GFX_VID AN24 GFX_VID6
AN18 VAXG
AN16 R1305 2 UMA 1 4K7R2J-2-GP
VAXG
AM21 VAXG GFX_VR_EN AR25 GFX_VR_EN
AM19 VAXG GFX_DPRSLPVR AT25 GFX_DPRSLPVR
AM18 AM24 GFX _ IMON _ C 1 DY 2
VAXG GFX_IMON R1304 0R2J-2-GP GFX_IMON
AM16 VAXG
AL21 +1.5V_RUN_CPU
VAXG
AL19 1 2
AL18
VAXG R1303 DIS 1KR2J-1-GP
AL16
AK21
VAXG
VAXG
AJ1
3A
VAXG VDDQ
AK19 VAXG VDDQ AF1
C1309 C1310 C1311 C1312 C1313 C1314 C1315 TC1301
Please note that the VTT Rail AK18
AK16
VAXG VDDQ AE7
AE4
VAXG VDDQ +1.5V_SUS
Values are: Auburndale VTT=1.05V AJ21
AJ19
VAXG VDDQ AC1
AB7
DY SE330 U 2D5VDM-2GP
VAXG VDDQ
C
Clarksfield VTT=1.1V AJ18
AJ16
VAXG VDDQ AB4
Y1
S3 Reduction C
VAXG VDDQ
AH21 W7
VAXG VDDQ
AH19 VAXG VDDQ W4
AH18 U1 C1331 C1332 C1333 C1334
VAXG VDDQ
AH16 VAXG VDDQ T7 DY DY DY DY
VDDQ T4
P1
VDDQ
VDDQ N7
+1.05V_VTT N4
VDDQ
VDDQ L1
J24 VTT1 VDDQ H1
J23
VTT1
H25 VTT1
C1316 C1317
+1.05V_VTT
VTT0 P10
N10
VTT0
VTT0 L10
K10
2.6A
VTT0
C1318 C1319
+1.05V_VTT SC10U10V5KX-2GP SC10U10V5KX-2GP
18A VTT1 J22
K26 VTT1 VTT1 J20
J27 VTT1 VTT1 J18
J26 H21 +1.05V_VTT
C1320 C1321 C1322 C1323
VTT1 VTT1
J25 VTT1 VTT1 H20
B B
H19
DY H27
G28
VTT1 VTT1
VTT1 C1325
G27 VTT1
G26 C1324 DY SC4D7U6D3V3KX-GP
VTT1 SC10U10V5KX-2GP
F26 VTT1
E26 VTT1 VCCPLL L26
E25 L27
VTT1 VCCPLL
VCCPLL M26 1.35A +1.8V_RUN
C1328 C1329 C1330

C1326 C1327
SC1U6D3V2KX-GP SC10U6D3V5MX-3GP
CLARKU1NF
A <Core Design> A
Wistron Corporation
Title
CPU (VCC_ GFXCORE)

Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT20 VSS VSS AE34

AT17 VSS VSS AE33
AR31 AE32 K27
VSS VSS VSS
AR28 VSS VSS AE31 K9 VSS
D AR23 VSS VSS AE28 J32 VSS D
AR20 AE27 J30
VSS VSS VSS
AR17 VSS VSS AE26 J21 VSS
AR15 VSS VSS AE6 J19 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AR6 AC4 H28
VSS VSS VSS
AR3 VSS VSS AC2 H26 VSS
AP20 VSS VSS AB35 H24 VSS
AP10 AB32 H15
VSS VSS VSS
AN34 VSS VSS AB28 H5 VSS
AN31 VSS VSS AB27 H2 VSS
AN23 VSS VSS AB26 G34 VSS
AN20 VSS VSS AB6 G31 VSS
AN17 VSS VSS AA10 G20 VSS
AM29 VSS VSS Y8 G9 VSS
AM27 Y4 G6
VSS VSS VSS
AM25 VSS VSS Y2 G3 VSS
AM20 VSS VSS W 35 F30 VSS
C AM2 W 29 E35 C
VSS VSS VSS
AL34
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W 28
W 27
W 26
E32
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL9 U4 E11
VSS VSS VSS
AL6 VSS VSS U2 E8 VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS
AK27 VSS VSS T33 D33 VSS
AK25 T32 D30 AR34
VSS VSS VSS VSS_NCTF
AK20 VSS VSS T31 D26 VSS VSS_NCTF B34
AK17 VSS VSS T30 D9 VSS VSS_NCTF B2
AJ31 VSS VSS T29 D6 VSS
AJ23 VSS VSS T28 D3 VSS
AJ20 T27 C34 A35 TP _ MCP _ VSS_ NCTF1 1 TP1401
VSS VSS VSS VSS_NCTF#A35 TP _ MCP _ VSS_ NCTF2 TP1402
AJ17 VSS VSS T26 C32 VSS VSS_NCTF#AT1 AT1 1
AJ14 T6 C29 AT35 TP _ MCP _ VSS_ NCTF3 1 TP1403
VSS VSS VSS VSS_NCTF#AT35 TP _ MCP _ VSS_ NCTF4 TP1404
AJ11 R10 C28 B1 1
VSS VSS VSS VSS_NCTF#B1
AJ8 VSS VSS P8 C24 VSS RSVD_NCTF#A3 A3
AJ5 P4 C22 A33
VSS VSS VSS RSVD_NCTF#A33
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#A34 A34
AH35 VSS VSS N35 C19 VSS RSVD_NCTF#AP1 AP1
AH34 VSS VSS N34 C16 VSS RSVD_NCTF#AP35 AP35
AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AR1 AR1
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#AR35 AR35
AH31 VSS VSS N31 B21 VSS RSVD_NCTF#AT2 AT2
B B
AH27 N27 B11 C1
VSS VSS VSS RSVD_NCTF#C1
AH26 VSS VSS N26 B8 VSS RSVD_NCTF#C35 C35
AH20 N6 B6 RSVD_NCTF#B35 B35
VSS VSS VSS
AH17 VSS VSS M10 B4 VSS
AH13 VSS VSS L35 A29 VSS
AH9 L32 A27
VSS VSS VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 VSS VSS K34
AF2 VSS VSS K33
AE35 VSS VSS K30
CLARKU1NF CLARKU1NF
A <Core Design> A
Wistron Corporation
Title
CPU (VSS)
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY M_A_DM[7..0]
M_A_DQS#[7..0]
M_A_DQS[7..0]
DM1
M_A_A[15..0]
M_A_A0 98 NP1 Note:
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2 If SA0 DIM0 = 0, SA1_DIM0 = 0
96
M_A_A3 A2 SA0_ DIM0
95 110 M_A_RAS# SO-DIMMA SPD Address is 0xA0
M_A_A4 A3 RAS#
92 113 M_A_W E#
A4 WE#
M_A_A5 91
A5 CAS#
115 M_A_CAS#
SA1_ DIM0 SO-DIMMA TS Address is 0x30
M_A_A6 90
M_A_A7 A6
86 114 M_CS#0
A7 CS0#
M_A_A8 89
A8 CS1#
121 M_CS#1 If SA0 DIM0 = 1, SA1_DIM0 = 0
D M_A_A9 85 R1803 R1804 D
M_A_A10 107
A9
73 M_CKE0
10KR2J-3-GP 10KR2J-3-GP SO-DIMMA SPD Address is 0xA2
M_A_A11 A10/AP CKE0
84
A11 CKE1
74 M_CKE1 SO-DIMMA TS Address is 0x32
M_A_A12 83
M_A_A13 A12
119 101 M_CLK_DDR0
M_A_A14 A13 CK0
80 103 M_CLK_DDR#0
M_A_A15 A14 CK0#
78
A15
79 102 M_CLK_DDR1
M_A_BS2 A16/BA2 CK1
104 M_CLK_DDR#1
CK1#
109
M_A_BS0 BA0 M_A_DM0
108 11
M_A_BS1 BA1 DM0 M_A_DM1
M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_ A_ DM2
5 46
M_A_DQ1 DQ0 DM2 M_ A_ DM3
7 63
15 136
17 153
4 170
6 187
M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6
18 200 PCH_SMBDATA
M_A_DQ8 DQ7 SDA
21 202 PCH_SMBCLK
M_A_DQ9 DQ8 SCL
23
M_A_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#0
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 199
M_A_DQ13 DQ12 VDDSPD
24
M_A_DQ14 DQ13 SA0_ DIM0
34 197
M_A_DQ15 DQ14 SA0 SA1_ DIM0
36 201
M_A_DQ16 DQ15 SA1 C1801 C1802
39
M_A_DQ17 41
DQ16
77 SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
M_A_DQ25
57
DQ24 VDD4
82 SODIMM A DECOUPLING
59 87
M_A_DQ26 DQ25 VDD5 +1.5V_SUS
67 88
M_A_DQ27 DQ26 VDD6
69 93
M_A_DQ28 DQ27 VDD7
56 94
M_A_DQ29 DQ28 VDD8
C 58 99 C
M_A_DQ30 DQ29 VDD9
68 100
M_A_DQ31 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11 T C1801 C1803 C1804 C1805 C1806 C1807 C1808 C1809 C1810
129 106
M_A_DQ33 DQ32 VDD12
131 111
M_A_DQ34 141
DQ33 VDD13
112
DY
M_A_DQ35 143
DQ34 VDD14
117
DY DY DY
+V_DDR_REF M_A_DQ36 130
DQ35 VDD15
118
DY
M_A_DQ37 DQ36 VDD16
132 123
M_A_DQ38 DQ37 VDD17
140 124
M_A_DQ39 DQ38 VDD18
142
C1812 M_A_DQ40 DQ39
147 2
C1811 SC2D2U10V3KX-1GP C1813 M_A_DQ41 DQ40 VSS
149 3
SCD1U10V2KX-5GP DY SCD1U10V2KX-5GP M_A_DQ42 157
DQ41 VSS
8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 DQ43 VSS C1814 C1815 C1816 C1817
146 13
M_A_DQ45 DQ44 VSS
M_A_DQ46
148
DQ45 VSS
14 Layout Note:
158 19
M_A_DQ47 DQ46 VSS Place these Caps near
160 20
M_A_DQ48 DQ47 VSS
163 25 SO-DIMMA.
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
M_A_DQ53 DQ52 VSS
166 38
M_A_DQ54 DQ53 VSS
174 43
M_A_DQ55 DQ54 VSS
176 44
DQ55 VSS
2
M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
183 49
DQ57 VSS
M_A_DQ58
M_A_DQ59
191
193
DQ58 VSS
54
55
S3 Power Reduction
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 DQ60 VSS
182 61
M_A_DQ62 DQ61 VSS +0.75V_DDR_VTT
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
M_A_DQS#0 VSS
10 72
+0.75V_DDR_VTT M_A_DQS#1 DQS0# VSS R1806
27 127
M_A_DQS#2 DQS1# VSS 22R2J-2-GP
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
B M_A_DQS#5 DQS4# VSS B
152 138
C1818 M_A_DQS#6 DQS5# VSS
169 139
DY SC10U6D3V5KX-1GP M_A_DQS#7 186
DQS6# VSS
144
DQS7# VSS
145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
47 155
M_A_DQS3 DQS2 VSS
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
+0.75V_DDR_VTT
Place these caps 188
DQS7 VSS
168
172 Q1801
close to VTT1 and VSS
M_ODT0
116
ODT0 VSS
173 .
VTT2. 120 178
M_ODT1 ODT1 VSS
VSS
179 .
.
+V_DDR_REF 126
VREF_CA VSS
184 . .
1 185
VREF_DQ VSS 2N7002E-1 -GP
189
VSS
30 190
DDR3_DRAMRST# RESE T# VSS
DY DY VSS
195
196
84.2N702 . D31
VSS PS_S3CNTRL
+0.75V_DDR_VTT 203 205
V TT1 VSS
204 206
V TT2 VSS
H =4mm
DDR3-204P-47-GP
62.10017.P31
SEC. 62.10017.P11
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = MEMORY DM2
M_B_A0 98 NP1
A0 NP1 M_B_DM[7..0] +3.3V_RUN
M_B_ A1 97 NP2
M_B_A2 A1 NP2
96 M_B_DQS#[7..0]
M_B_ A3 A2
95 110 M_B_RAS#
M_B_ A4 A3 RAS#
92 113 M_B_W E#
M_B_ A5 A4 WE#
91 115 M_B_CAS# M_B_DQS[7..0]
M_B_A6 A5 CAS# R1902
90
M_B_ A7 A6 10KR2J-3-GP
86 114 M_CS#2 M_B_A[15..0]
M_B_ A8 A7 CS0#
89 121 M_CS#3
M_B_ A9 A8 CS1#
85
M_B_ A10 A9
M_B_ A11
107
A10/AP CKE0
73 M_CKE2 Note:
84 74 M_CKE3
M_B_ A12 A11 CKE1 SA1_ DIM1 If SA0 DIM0 = 0, SA1_DIM0 = 0
83
M_B_ A13 A12
119 101 M_CLK_DDR2 SO-DIMMA SPD Address is 0xA0
M_B_ A14 A13 CK0 SA0_ DIM1
80 103 M_CLK_DDR#2
A14 CK0#
M_B_ A15 78
A15
SO-DIMMA TS Address is 0x30
D 79 102 M_CLK_DDR3 D
M_B_BS2 A16/BA2 CK1
104 M_CLK_DDR#3
CK1#
M_B_BS0
109
BA0
R1903 If SA0 DIM0 = 1, SA1_DIM0 = 0
108 11 M_B_DM0 10KR2J-3-GP
M_B_BS1 BA1 DM0
28 M_B_ DM1 SO-DIMMA SPD Address is 0xA2
M_B_DQ[63..0] M_B_DQ0 DM1 M_B_DM2
M_B_ DQ1
5
DQ0 DM2
46
M_B_ DM3
SO-DIMMA TS Address is 0x32
7 63
M_B_DQ2 DQ1 DM3 M_B_DM4
15 136
M_B_ DQ3 DQ2 DM4 M_B_ DM5
17 153
4 170
6 187
M_B_ DQ6 DQ5 DM7
16
M_B_ DQ7 DQ6
18 200 PCH_SMBDATA
M_B_ DQ8 DQ7 SDA
21 202 PCH_SMBCLK
M_B_ DQ9 DQ8 SCL
23
M_B_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#1
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
M_B_DQ14 DQ13 SA0_ DIM1
34 197
M_B_DQ15 DQ14 SA0 SA1_ DIM1 C1901 C1902
36 201
M_B_DQ16 39
DQ15 SA1 SCD1U10V2KX-5GP DY SC2D2U10V3KX-1GP
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 122
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53 125
M_B_DQ20 DQ19 NC#/TEST
40
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 81
M_B_DQ24 DQ23 VDD3
57 82
M_B_DQ25 DQ24 VDD4
59 87
M_B_DQ26 DQ25 VDD5
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
C 130 118 C
M_B_DQ37 DQ36 VDD16
132 123
M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
M_B_DQ42
149
DQ41 VSS
3 SODIMM B DECOUPLING
157 8
M_B_DQ43 DQ42 VSS +1.5V_SUS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 DQ45 VSS
158 19
M_B_DQ47 DQ46 VSS
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS C1903 C1904 C1908 C1909 C1910
165 26
M_B_DQ50 DQ49 VSS C1905 C1906 C1907
175 31
M_B_DQ51 DQ50 VSS DY
M_B_DQ52
177
164
DQ51 VSS
32
37
DY DY
M_B_DQ53 166
DQ52 VSS
38
DY
M_B_DQ54 DQ53 VSS
174 43
M_B_DQ55 DQ54 VSS
176 44
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS C1911 C1912 C1913 C1914
182 61
M_B_DQ62 DQ61 VSS
M_B_DQ63
192
DQ62 VSS
65 Layout Note:
194 66
DQ63 VSS Place these Caps near
71
M_B_DQS#0 VSS
10 72 SO-DIMMB.
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_B_ DQS0 VSS
12 150
M_B_ DQS1 DQS0 VSS
29 151
M_B_ DQS2 DQS1 VSS
47 155
B M_B_ DQS3 DQS2 VSS B
64 156
+V_DDR_REF M_B_ DQS4 DQS3 VSS
137 161
M_B_ DQS5 DQS4 VSS
154 162
M_B_ DQS6 DQS5 VSS
171 167
M_B_ DQS7 DQS6 VSS
188 168
C1916 DQS7 VSS
172
C1915 SC2D2U10V3KX-1GP C1917 VSS
116 173
SCD1U10V2KX-5GP SCD1U10V2KX-5GP M_ODT2 ODT0 VSS
120 178
DY M_ODT3 ODT1 VSS
179
VSS
+V_DDR_REF 126 184
VREF_CA VSS
1 185
VREF_DQ VSS
189
+0.75V_DDR_VTT VSS
30 190
DDR3_DRAMRST# RESET# VSS
195
VSS
196
VSS
203 205
VTT1 VSS
204 206
VTT2 VSS
Place these caps

close to VTT1 and H = 8mm DDR3-204P-55-GP
VTT2. DY DY
62.10017.Q31
SEC. 62.10017.N71
Note:
SO-DIMMB SPD Address is 0xA4 SO-DIMMB is placed farther from
SO-DIMMB TS Address is 0x34 the Processor than SO-DIMMA
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2
Berry X00
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
U2001D 4 OF 10
PCH_VGA_BLEN T48 BJ46
L_BKLTEN SDVO_TVCLKINN RN2006
PCH_LCDVDD_EN T47 L_VDD_EN SDVO_TVCLKINP BG46
PCH_LBKLT_CTL Y48 BJ48

UM ASRN2K2J-1-GP
RN2001
L_BKLTCTL SDVO_STALLN
D
SDVO_STALLP BG48 D
GPU_LVDS_CLK 1 4 LDDC _ CLK _ PCH AB48
LDDC _ DATA _ PCH
L_DDC_CLK
2 3 Y45 BF45
GPU_LVDS_DATA UMA L_DDC_DATA SDVO_INTN
BH45
SRN0J-6-GP LCTRL _ CLK
SDVO_INTP
AB46 L_CTRL_CLK
LCTRL _ DATA V48 L_CTRL_DATA
LIBG AP39 T51
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK
TPAD14-GP TP2001 1LVDS _VBG AP41 T53 PCH_HDMI_DATA
RN2004 LVD_VBG SDVO_CTRLDATA
R2002 R2001 1 4 LVD _ VREFH AT43
LVD_VREFH
2 1 PCH _ LCDVDD _ EN Place near PCH 2K37R2F-GP 2 3 LVD _ VREFL AT42 BG44
DY UMA LVD_VREFL DDPB_AUXN
BJ44
100KR2J-1-GP SRN0J-6-GP
DDPB_AUXP
UMA DDPB_HPD AU38 HDMI_PCH_DET
PCH_LVDSA_TXC# AV53 LVDSA_CLK#
PCH_LVDSA_TXC AV51 LVDSA_CLK DDPB_0N BD42 HDMI_DATA2#_C UMA11 2 C2001 SCD1U10V2KX-5GP
HDMI_PCH_DATA2#
BC42 HDMI_DATA2_C UMA1 2 C2002 SCD1U10V2KX-5GP HDMI_PCH_DATA2
DDPB_0P HDMI _ DATA1# _ C C2003 SCD1U10V2KX-5GP
PCH_LVDSA_TX0# BB47 LVDSA_DATA#0 DDPB_1N BJ42 UMA1 HDMI_PCH_DATA1#
BA52 BG42 HDMI _ DATA1 _ C UMA1 2 C2004 SCD1U10V2KX-5GP
PCH_LVDSA_TX1# LVDSA_DATA#1 DDPB_1P HDMI_PCH_DATA1
PCH_LVDSA_TX2# AY48 BB40 HDMI _ DATA0# _ C UMA1 C2005 SCD1U10V2KX-5GP
LVDSA_DATA#2 DDPB_2N HDMI_PCH_DATA0#
AV47 BA40 HDMI _ DATA0 _ C UMA1 2 C2006 SCD1U10V2KX-5GP
+3.3V_RUN LVDSA_DATA#3 DDPB_2P HDMI_PCH_DATA0
AW 38 HDMI _ CLK# _ C UMA1 C2007 SCD1U10V2KX-5GP HDMI_PCH_CLK#
DDPB_3N HDMI _CLK _ C
PCH_LVDSA_TX0 BB48 LVDSA_DATA0 DDPB_3P BA38 UMA 2 C2008 SCD1U10V2KX-5GP HDMI_PCH_CLK
PCH_LVDSA_TX1 BA50 LVDSA_DATA1
Impedance:85 ohm PCH_LVDSA_TX2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
AB49
Close to VGA
DDPC_CTRLDATA
RN2002 AP48
PCH_LVDSB_TXC# LVDSB_CLK#
C AP47 BE44 C
UMA SRN2K2J-4-GP PCH_LVDSB_TXC LVDSB_CLK DDPC_AUXN
BD44
DDPC_AUXP
PCH_LVDSB_TX0# AY53
AT49
LVDSB_DATA#0 DDPC_HPD AV40 Impedance:85 ohm Impedance:100 ohm
PCH_LVDSB_TX1# LVDSB_DATA#1
LCTRL _ DATA PCH_LVDSB_TX2# AU52 BE40
LCTRL _ CLK
LVDSB_DATA#2 DDPC_0N
AT53 LVDSB_DATA#3 BD40
LDDC _ CLK _ PCH
DDPC_0P
DDPC_1N BF41
LDDC _ DATA _ PCH AY51 BH41
PCH_LVDSB_TX0 LVDSB_DATA0 DDPC_1P
PCH_LVDSB_TX1 AT48 LVDSB_DATA1 DDPC_2N BD38
PCH_LVDSB_TX2 AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
Close to ball <600mil
PCH_CRT_BLUE AA52 CRT_BLUE DDPD_CTRLCLK U50
PCH_CRT_GREEN AB53 DDPD_CTRLDATA U52
CRT_GREEN
PCH_CRT_RED AD53 CRT_RED
Need Level Shift BC46
DDPD_AUXN
PCH_CRT_DDCCLK
V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DDCDATA
V53 CRT_DDC_DATA DDPD_HPD AT38
R N 2005
BJ40
SRN150F -1-GP
UMA PCH_CRT_HSYNC Y53 CRT_HSYNC
DDPD_0N
DDPD_0P BG40
PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38
2.5V Tolerance CRT _ IREF AD48
DDPD_2N BF37
BH37
DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
B B
DDPD_3P BD36
R2007
IBEXPEAK-M-GP-NF
1KR2J-1-GP
20090918
<Core Design>
A A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
RN2101
PCI _ TRDY# 1 10 U2001E 5 OF 10
+3.3V_RUN
PCI _ DEVSEL# 2 9 PCI _ FRAME# H40 AY9
INT_PIRQA# PCI_REQ2#
AD0 NV_CE#0 +V_NVRAM_VCCQ
3 8 N34 AD1 NV_CE#1 BD1
PCI_IRDY# 4 7 INT_PIRQD# C44 AP15
AD2 NV_CE#2
+3.3V_RUN 5 6 PCI _ SERR# A38 AD3 NV_CE#3 BD8 DMI Termination Voltage
C36 AD4
SRN8K2J-2-GP-U J34 AD5 NV_DQS0 AV9 NV_CLE Set to Vss when low. R2102
A40
D45
AD6 NV_DQS1 BG8 Set to Vcc when high. DY1KR2J-1-GP
AD7
E36 AD8 NV_DQ0/NV_IO0 AP7
RN2103 H48 AP6
INT _ PIRQH#
AD9 NV_DQ1/NV_IO1 NV _ CLE
1 10 +3.3V_RUN E40 AD10 NV_DQ2/NV_IO2 AT6
D INT _ PIRQB# 2 9 PCI _ REQ1# C40 AT9 D
INT _ PIRQF# PCI _ PLOCK#
AD11 NV_DQ3/NV_IO3
3 8 M48 BB1
PCI _ REQ3# PCI_ PERR# AD12 NV_DQ4/NV_IO4
4 7 M45 AD13 NV_DQ5/NV_IO5 AV6
5 6 PCI _ REQ0# F53 BB3
+3.3V_RUN AD14 NV_DQ6/NV_IO6
M40 AD15 NV_DQ7/NV_IO7 BA4
SRN8K2J-2-GP-U M43 BE4
AD16 NV_DQ8/NV_IO8 +V_NVRAM_VCCQ
J36 BB6
+3.3V_RUN AD17 NV_DQ9/NV_IO9
K48 AD18 NV_DQ10/NV_IO10 BD6
+3.3V_RUN F40 BB7
AD19 NV_DQ11/NV_IO11
RN2102 C42 AD20 NV_DQ12/NV_IO12 BC8 Danbury Technology:
1 8 PCI _ STOP# K46 AD21 NV_DQ13/NV_IO13 BJ8 Disabled when Low. R2103
2
3
7
6
INT _ PIRQE#
INT _ PIRQC#
U2101 M51
J52
BJ6
BG6
Enable when High. DY1KR2J-1-GP
INT _ PIRQG#
4 5 5 VCC A 1 K51 AD24
PCI _ PLTRST# NV _ ALE
SRN8K2J-4-GP PLT_RST# 4
DY B 2
3
L34
F42
AD25 NV_ALE BD3
AY6 NV_CLE NV_ALE
Y GND AD26 NV_CLE
J40 AD27
G46 AD28
NL17SZ08DFT2G-GP F44 AU2 NV _ RCOMP 1 TP2105 TPAD14-GP
AD29 NV_RCOMP
M47 AD30
1 2 H36 AD31 NV_RB# AV7
R2101 0R2J-2-GP
J50 C/BE0# NV_W R#0_RE# AY8
BOOT BIOS Strap DY C2101 G42 C/BE1# NV_W R#1_RE# AY5
SC220P50V2KX-3GP H47 C/BE2#
PCI_GNT#1 PCI_GNT#0 BOOT BIOS Location G34 C/BE3# NV_W E#_CK0 AV11 USB
NV_W E#_CK1 BF5
0 0 LPC INT _ PIRQA# G38 PIRQA# Pair Device
INT _ PIRQB# H51 PIRQB#
C
0 1 Reserved INT _ PIRQC# B37 PIRQC# USBP0N H18 USB_PN0 0 USB2 (CRT Board) C
INT _ PIRQD# A44 J18
PIRQD# USBP0P USB_PP0
1 0 PCI USBP1N
A18 USB_PN1 1 USB3 (CRT Board)
PCI _ REQ0# F51 C18
REQ0# USBP1P USB_PP1
1 1 SPI(Default) PCI _ REQ1# A46 REQ1#/GPIO50 USBP2N N20 USB_PN2 2 WLAN (I/O Board)
PCI _ REQ2# B45 P20 USB_PP2
REQ2#/GPIO52 USBP2P
PCI _ REQ3# M53 REQ3#/GPIO54 USBP3N J20 3 X
L20
USBP3P
TPAD14-GP TP2102 1 PCI _ GNT0# F48 GNT0# USBP4N F20 USB_PN4 4 CARD READER
TPAD14-GP TP2103 1 PCI _ GNT1# K45 G20
GNT1#/GPIO51 USBP4P USB_PP4
RN2104 TPAD14-GP TP2104 1 PCI _ GNT2# F36 GNT2#/GPIO53 USBP5N A20 USB_PN5 5 BLUETOOTH
USB_OC#2_3 1 10 PCI_GNT3# H53 C20
+3.3V_ALW GNT3#/GPIO55 USBP5P USB_PP5
SMC_W AKE_SCI#_R 2 9 USB_OC#12_13
USBP6N
M22 6 X
USB _ OC#6 _ 7 3 8 USB _ OC#8 _ 9 INT_ PIRQE# B41 N22
PIRQE#/GPIO2 USBP6P
USB _ OC#0 _ 1 4 7 USB _ OC#10 _ 11 INT_ PIRQF# K53 PIRQF#/GPIO3 USBP7N B21 7 X
5 6 USB _ OC#4 _ 5 INT _ PIRQG# A36 D21
+3.3V_ALW PIRQG#/GPIO4 USBP7P
INT _ PIRQH# A48 PIRQH#/GPIO5 USBP8N H22 USB_PN8 8 USB1 (I/O Board)
SRN8K2J-2-GP-U J22
USBP8P USB_PP8
TPAD14-GP TP2110 1 PCIRST# K6 PCIRST# USBP9N E22 USB_PN9 9 ESATA (I/O Board COMBO)
USBP9P F22 USB_PP9
R2105 PCI _ SERR# E44 SERR# USBP10N A22 10 X
PCI _ GNT3# 1 2 PCI_ PERR# E50 C22
DY PERR# USBP10P
G24 USB_PN11 11 W-WAN (I/O Board)
4K7R2J-2-GP USBP11N
USBP11P H24 USB_PP11
PCI _ IRDY# A42 IRDY# USBP12N L24 12 X
H44 PAR USBP12P M24
PCI _ DEVSEL# F46 DEVSEL# USBP13N A24 USB_PN13 13 CAMERA
PCI _ FRAME# C46 C24
FRAME# USBP13P USB_PP13
B B
PCI _ PLOCK# D49 PLOCK#
A16 swap override Strap/Top-Block USBRBIAS# B25 USB _ RBIAS _ PN 1 2
Swap Override jumper PCI _ STOP# D41 STOP#
R2106
PCI _ TRDY# C48 D25 22D6R2F-L1-GP
TRDY# USBRBIAS
PCI_GNT#3 Low = A16 swap TPAD14-GP TP2115 1 PCH _ PME# M7 PME#
override/Top-Block OC0#/GPIO59 N16 USB _ OC#0 _ 1 USB_OC#0_1
PCI_PLTRST# D5 J16 USB_OC#2_3
Swap Override enabled PLTRST# OC1#/GPIO40
F16 USB_OC#4_5
High = Default PCLK _ FW H _ R OC2#/GPIO41 USB _ OC#6 _ 7
PCLK_FW H 1 N52 CLKOUT_PCI0 OC3#/GPIO42 L16
R2107 1 2 22R2J-2-GP CLK _ PCI _ FB_ R P53 E14 USB _ OC#8_ 9 USB_OC#8_9
CLK_PCI_FB CLKOUT_PCI1 OC4#/GPIO43
R2108 1 2 22R2J-2-GP PCLK _ KBC _ R P46 G16 USB _ OC#10 _ 11
PCLK_KBC CLKOUT_PCI2 OC5#/GPIO9
R2109 22R2J-2-GP P51 F12 USB _ OC#12 _ 13
CLKOUT_PCI3 OC6#/GPIO10 SMC _ W AKE _ SCI# _ R
P48 CLKOUT_PCI4 OC7#/GPIO14 T15
EC2101
IBEXPEAK-M-GP-NF
DY SC4D7P50V2CN-1GP
KBC CLK EMI
A <Core Design> A
Wistron Corporation
Title
PCH (PCI/USB/NVRAM)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
RN2201
FDI_PCH_TXP3 1 8 FDI_TXP3
FDI _ PCH _ TXN3 2 7 FDI_TXN3
FDI _ PCH _ TXN1 3 6
U2001C 3 OF 10 FDI _ PCH _ TXP1 4
UMA 5
FDI_TXN1
FDI_TXP1
BA18 FDI _ PCH _ TXN0
FDI_RXN0 FDI _ PCH _ TXN1 SRN0J-7-GP
DMI_CTX_PRXN0 BC24 BH17
DMI0RXN FDI_RXN1 FDI _ PCH _ TXN2
DMI_CTX_PRXN1 BJ22 BD16 RN2202
DMI1RXN FDI_RXN2 FDI _ PCH _ TXN3 FDI_ PCH_ TXN4
DMI_CTX_PRXN2 AW 20 BJ16 1 8 FDI_TXN4
DMI2RXN FDI_RXN3 FDI _ PCH _ TXN4 FDI_ PCH_ TXP4
DMI_CTX_PRXN3 BJ20 DMI3RXN BA16 2 7 FDI_TXP4
FDI_RXN4 FDI _ PCH _ TXN5 FDI_ PCH_ TXP0
BE14 3 6
D
DMI_CTX_PRXP0 BD24
FDI_RXN5
BA14 FDI _ PCH _ TXN6 FDI_ PCH_ TXN0 4
UMA 5
FDI_TXP0
FDI_TXN0
D
DMI0RXP FDI_RXN6 FDI _ PCH _ TXN7

DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12
BA20 SRN0J-7-GP
DMI_CTX_PRXP2 DMI2RXP
DMI_CTX_PRXP3 BG20 BB18 FDI _ PCH _ T XP0 RN2203
DMI3RXP FDI_RXP0 FDI _ PCH _ T XP1 FDI_ PCH_ TXP6
BF17 1 8 FDI_TXP6
FDI_RXP1 FDI _ PCH _ T XP2 FDI_ PCH_ TXN6
BE22 BC16 2 7
DMI_PTX_CRXN0
DMI_PTX_CRXN1 BF21
DMI0TXN FDI_RXP2
BG16 FDI _ PCH _ T XP3 FDI_ PCH_ TXN2 3
UMA 6
FDI_TXN6
FDI_TXN2
DMI1TXN FDI_RXP3 FDI _ PCH _ T XP4 FDI_ PCH_ TXP2
DMI_PTX_CRXN2 BD20 DMI2TXN FDI_RXP4 AW 16 4 5 FDI_TXP2
DMI_PTX_CRXN3 BE18 BD14 FDI _ PCH _ T XP5
DMI3TXN FDI_RXP5 FDI _ PCH _ T XP6 SRN0J-7-GP
FDI_RXP6 BB14
BD22 BD12 FDI _ PCH _ T XP7 RN2204
DMI_PTX_CRXP0 DMI0TXP FDI_RXP7
BH21 FDI _ PCH _ TXN7 1 8
DMI_PTX_CRXP1 DMI1TXP FDI_TXN7
BC20 R2201 FDI _ PCH _ TXP7 2 7
DMI_PTX_CRXP2
DMI_PTX_CRXP3 BD18
DMI2TXP
BJ14 FDI _ INT _ C 1 2
UMA 0R2J-2-GP FDI_INT
FDI _ PCH _ TXP5 3
UMA 6
FDI_TXP7
FDI_TXP5
DMI3TXP FDI_INT FDI_PCH_TXN5 4 5 FDI_TXN5
BF13 FDI_FSYNC0_C
+1.05V_VTT FDI_FSYNC0 SRN0J-7-GP
BH25 DMI_ZCOMP
R2202 BH13 FDI _ FSYNC1 _ C
DMI _ IRCOMP _ R
FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
BJ12 FDI _ LSYNC0 _ C RN2205
49D9R2F-GP
FDI_LSYNC0 FDI _ LSYNC1 _ C 1 8 FDI_LSYNC1
BG14 FDI _ LSYNC1 _ C FDI _ FSYNC1 _ C 2 7
FDI_LSYNC1 FDI _ LSYNC0 _ C 3
UMA 6
FDI_FSYNC1
FDI_LSYNC0
FDI _ FSYNC0 _ C 4 5 FDI_FSYNC0
SRN0J-7-GP
C C
XDP_DBRESET# T6 SYS_RESET# WAKE# J12 PCIE_W AKE#
M6 Y1 +3.3V_ALW
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN#
RN2206
PM_PW ROK R2204 1 2 0R2J-2-GP PM _ PW RGD B17 PW ROK
PM _ BATLOW # _ R 1 8
PM _ RI# 2 7
R2206 AC _ PRESENT _ EC 3 6
RN2207
1
0R2J-2-GP
2 MEPW ROK K5 MEPW ROK SUS_STAT#/GPIO61 P8 PM _ SUS _ STAT# 1
TP2201 TPAD14-GP
depend on Layout SUS _ PW R_ ACK 4 5
3 2 SRN10KJ-6-GP
4 1 LAN _ RST#1 A10 F3 PCH _ SUSCLK 1 2
LAN_RST# SUSCLK/GPIO62 PCH_SUSCLK_2102
R2209 0R2J-2-G P PCIE _ W AKE# 1 2
SRN10KJ-5-GP 1 2 R2210 1KR2J-1-GP
PCH_SUSCLK_KBC
D9 E4 PCH _ SLP _ S5# 1 R2211 10R2J-2-GP
PM_DRAM_PW RGD DRAMPW ROK SLP_S5#/GPIO63 TP2202
TPAD14-GP
1 2 PM _ RSMRST# _ R C16 H7 PM _ SLP _ S4#_ R 1 2
PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4#
R2213 0R2J-2-GP R2214 0R2J-2-GP
R2217
1 2 SUS _ PW R _ ACK M1 P12 PM _ SLP _ S3#_ R 1 2 PCH_ RSMRST# 1 2
SUS_PW R_DN_ACK SUS_PW R_DN_ACK/GPIO30 SLP_S3# PM_SLP_S3#
R2215 0R2J-2-GP R2216 0R2J-2-GP
PM_PW RBTN#_R
10KR2J-3-GP
1 2 PM _ PW RBTN# _ R P5 K8 SIO _ SLP _ M#_ R 1
PM_PW RBTN# PW RBTN# SLP_M#
R2218 0R2J-2-GP TP2203TPAD14-GP
1 2 AC _ PRESENT P7 N2 PM _ SLP _ DSW # 1

B AC_PRESENT_EC ACPRESENT/GPIO31 TP23 B
R2219 0R2J-2-GP TP2204TPAD14-GP
PM _ BATLOW # _ R A6 BJ10 H_ PM_ SYNC

BATLOW #/GPIO72 PMSYNCH H_PM_SYNC
PM _ RI# F14 F6 PM _ SLP_ LAN# 1

RI# SLP_LAN#/GPIO29 TP2205TPAD14-GP +3.3V_RUN
IBEXPEAK-M-GP-NF
PM _ CLKRUN# 1 2
Option to " Disable " clkrun. R2221

DY R2220
10KR2J-3-GP 10KR2J-3-GP
Pulling it down will keep the clks running.
A <Core Design> A
Wistron Corporation
Title
PCH (DM I/FDI/PM)

Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH +3.3V_ALW
+3.3V_ALW
U2001B 2 OF 10
BG30 B9 TPM _ ID1 2 1 RN2302

PERN1 SMBALERT#/GPIO11 PCH_GPIO11
BJ30 R2305 10KR2J-3-GP SRN2K2J-1-GP
PERP1 PCH _ SMB _ CLK
BF29 PETN1 SMBCLK H14
BH29 LPD _ SPI_ INTR# 2 1
PETP1 PCH _ SMB _ DATA R2311 10KR2J-3-GP
SMBDATA C8
D PCIE_RXN2 AW 30 PERN2 D
PCIE_RXP2
C2301 SCD1U10V2KX-4GP 1 2 PCIE _ C _ TXN2
BA30
BC30
PERP2 WLAN J14 TPM _ ID1 PCH _ SMB_ CLK
PCIE_TXN2
C2302 SCD1U10V2KX-4GP 1 PCIE _ C _ TXP2 PETN2 SML0ALERT#/GPIO60
PCIE_TXP2
2 BD30 PETP2
C6 SML0 _ CLK PCH _ SMB _ DATA
SML0CLK SML0_CLK
PCIE_RXN3 AU30 PERN3
AT30 G8 SML0 _ DATA +3.3V_ALW
PCIE_RXP3 PERP3 SML0DATA SML0_DATA
PCIE_TXN3
C2303 SCD1U10V2KX-4GP 1
C2306 SCD1U10V2KX-4GP 1 2
PCIE _ C _ TXN3
PCIE _ C _ TXP3
AU32
AV32
PETN3 LAN
PCIE_TXP3 PETP3 LPD _ SPI_ INTR#
SML1ALERT#/GPIO74 M14
BA32 +3.3V_ALW
PCIE_RXN4 PERN4
BB32 E10 KBC _ SCL1
PCIE_RXP4 PERP4 SML1CLK/GPIO58 KBC_SCL1
PCIE_TXN4
2
2
PCIE _ C _ TXN4
PCIE _ C _ TXP4
BD32
BE32
PETN4 W-WAN G12 KBC _ SDA1
RN2309
SRN2K2J-1-GP
RN2301
SRN2K2J-1-GP
PCIE_TXP4 PETP4 SML1DATA/GPIO75 KBC_SDA1
R2308
BF33 PERN5 UMA 10KR2J-3-GP
BH33 T13 CL_CLK 1
PERP5 CL_CLK1 TP2302 TPAD14-GP
BG32 PETN5
BJ32 T11 CL _ DATA 1 PEG _ CLKREQ# _ C
PETP5 CL_DATA1 TP2303 TPAD14-GP SML0 _ DATA KBC _ SCL1
BA34 T9 CL _ RST# 1
PERN6 CL_RST1# TP2304 TPAD14-GP SML0 _ CLK KBC _ SDA1 R2309
AW 34
PERP6
BC34 PETN6 DIS 10KR2J-3-GP
BD34 PETP6 DY
H1 PEG _ CLKREQ# _ C 1 2
PEG_A_CLKRQ#/GPIO47 PEG_CLKREQ#
AT34 R2310 0R2J-2-GP
PERN7
AU34 PERP7
AU36 AD43 CLK _ PCIE _ VGA#
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA#
AV36 AD45 CLK _ PCIE _ VGA
PETP7 CLKOUT_PEG_A_P CLK_PCIE_VGA
C C
BG34 AN4 CLK _ EXP _ N +3.3V_RUN
PERN8 CLKOUT_DMI_N CLK_EXP_N
BJ34 AN2 CLK _ EXP _ P
PERP8 CLKOUT_DMI_P CLK_EXP_P
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. BG36 PETN8
RN2303
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN BJ36 PETP8 2 3
AT1 1 4
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P AT3
AK48 SRN2K2J-1-GP
CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
AW 24 CLKIN _ DMI#
CLKIN_DMI_N CLKIN_DMI#
PCIE _ CLK _ RQ0# P9 BA24 CLKIN _ DMI
PCIECLKRQ0#/GPIO73 CLKIN_DMI_P CLKIN_DMI
Q2301
AM43 AP3 CLK _ CPU _ BCLK# PCH _ SMB_ DATA 6 1
CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK# PCH_SMBDATA
AM45 AP1 CLK _ CPU _ BCLK CLK_CPU_BCLK
CLKOUT_PCIE1P CLKIN_BCLK_P
5 2
PCIE _ CLK _ RQ1# U4
PCIECLKRQ1#/GPIO18
F18 CLK_DREF# 4 3
CLKIN_DOT_96N
CLKIN_DOT_96P E18 CLK_DREF
AM47 2N7002EDW -GP
CLK_PCIE_W LAN# CLKOUT_PCIE2N
AM48
CLK_PCIE_W LAN CLKOUT_PCIE2P
AH13 CLK_PCIE_SATA#
84.27002.F3F
CLKIN_SATA_N/CKSSCD_N PCH_SMBCLK
W LAN_CLKREQ# N4 PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P AH12 CLK_PCIE_SATA
PCH _ SMB _ CLK
AH42 P41 CLK _ PCH _ 14M

CLK_PCIE_LAN# CLKOUT_PCIE3N REFCLK14IN CLK_PCH_14M
CLK_PCIE_LAN AH41 CLKOUT_PCIE3P
2 1 PCIE _ CLK _ RQ3# A8 J42 CLK _ PCI_ FB
B PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB B
R2304 10KR2J-3-GP
CLK_PCIE_W W AN# AM51 CLKOUT_PCIE4N XTAL25_IN AH51 XTAL25 _ IN DIS uses 0ohm 63.R0034.1DL
AM53 AH53 XTAL25 _ OUT
CLK_PCIE_W W AN CLKOUT_PCIE4P XTAL25_OUT UMA uses 18pF 78.18034.1FL
M9 AF38 XCLK _ RCOMP R2306 1 2 90D9R2F-1-GP
W W AN_CLKREQ# PCIECLKRQ4#/GPIO26 XCLK_RCOMP +1.05V_VTT
XTAL25_IN C2308 COLAY

1
AJ50 T45 CLK_PCH_GPIO64 1 TP2301 TPAD14-GP SC18P50V2 J N-1-G P
CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64
AJ52 CLKOUT_PCIE5P R2303 X2301
PCIE _ CLK _ RQ5# H6 P43 CLK _ PCI_ LPC 1 P2305 TPAD14-GP UMA XTAL-25MHZ-102-GP
PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65 1M1R2J-GP
UMA
C2307
T42 CLK _ PCH _ REF14 1 TP2306 TPAD14-GP XTAL25 _ OUT 1
AK53
AK51
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66 UMA
+3.3V_ALW CLKOUT_PEG_B_P SC18P50V2JN-1-GP
PEG _ B _ CLKRQ# P13 N50 CLK48 _ GPIO 2 1 CLK_48M_CARD
PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 R2307 33R2J-2-GP
RN2307
1 8 W W AN _ CLKREQ#
2 7 PCIE _ CLK _ RQ0# IBEXPEAK-M-GP-NF
3 6 PEG _ B _ CLKRQ#
4 5 PCIE _ CLK _ RQ5#
DY EC2301
SRN10KJ-6-GP SC22P50V2JN-4GP
For EMI
A <Core Design> A
+3.3V_RUN RN2308
4 XDP _ DBRESET#
3 6 W LAN_CLKREQ#
XDP_DBRESET#
Wistron Corporation
2 7 INT_SERIRQ 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
INT_SERIRQ
1 8 PCIE _ CLK _ RQ1# Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-6-GP Title
PCH (PCI-E/SMBUS/CLOCK/CL)
Berry X00
5 4 3 2 1
5 4 3 2 1
PCH _ RTCX1 +RTC_CELL

SSID = PCH
1 2 PCH_RTCX2 R2401
R2402 10MR2J-L-GP 1 2
INTVRMEN- Integrated SUS
20KR2J-L2-GP
X2401
C2402
1.1V VRM Enable
SC1U6D3V2KX- G P High - Enable internal VRs
1 4
D U2001A 1 OF 10 LPC _ LAD[0..3] D

LPC_LAD[0..3]
2 3 C2401
SC12P50V2JN-3GP PCH _ RTCX1 B13 D33 LPC _ LAD0
+RTC_CELL PCH _ RTCX2
RTCX1 FWH0/LAD0 LPC _ LAD1
D13 RTCX2 FWH1/LAD1 B33
X-32D768KHZ-65-GP C32 LPC _ LAD2
R2403 FWH2/LAD2 LPC _ LAD3
FWH3/LAD3 A32
1 2 PCH _ RTCRST# C14
82.30001.A41 RTCRST#
C34
20KR2J-L2-GP SRTCRST#
FWH4/LFRAME# LPC_LFRAME#
D17 SRTCRST#
C2404 G2401 R2407 A34
SC1U6D3V2KX-GP SM_INTRUDER# LDRQ0#
GAP-OPEN 2 1 A16 F34
1M1R2J-GP INTRUDER# LDRQ1#/GPIO23
1 2 PCH _ INTVRMEN A14 AB9
+RTC_CELL INTVRMEN SERIRQ INT_SERIRQ
R2404 330KR2F-L-GP
R2405 1 2 33R2J-2-GP ACZ_BIT_CLK A30

PCH_AZ_CODEC_BITCLK HDA_BCLK
SATA0RXN AK7 SATA_RXN0_C
HDD
R2406 1 33R2J-2-GP ACZ _ SYNC _ R D29 AK6
PCH_AZ_CODEC_SYNC HDA_SYNC SATA0RXP SATA_RXP0_C
AK11 SATA _ TXN0 _ C C2409 1 SCD01U50V2KX-1GP
SATA0TXN SATA_TXN0
ACZ _ SPKR P1 AK9 SATA _ TXP0 _ C C2410 1 2 SCD01U50V2KX-1GP
ACZ_SPKR SPKR SATA0TXP SATA_TXP0
R2408 1 2 33R2J-2-GP ACZ _ RST# _ R C30

PCH_AZ_CODEC_RST# HDA_RST#
SATA1RXN AH6 SATA_RXN1_C
PCH_SDIN_CODEC G30 HDA_SDIN0

SATA1RXP
SATA1TXN
AH5
AH9 SATA _ TXN1 _ C C2405 1
SATA _ TXP1 _ C C2406 1
SCD01U50V2KX-1GP
SATA_RXP1_C
SATA_TXN1 ODD
SATA1TXP AH8 2 SCD01U50V2KX-1GP SATA_TXP1
F30 HDA_SDIN1
SATA2RXN AF11
C E32 AF9 C
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
SATA3RXN AH3
R2409 1 2 33R2J-2-GP ACZ _ SDATAOUT _ R B29 AH1
PCH_SDOUT_CODEC HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
ME_UNLOCK# H32 HDA_DOCK_EN#/GPIO33
SATA4RXN AD9 SATA_RXN4_C
J30 HDA_DOCK_RST#/GPIO13 SATA4RXP
SATA4TXN
AD8
AD6 SATA_TXN4_C
SATA_TXP4_C
C2407 1
C2408 1
2 SCD01U50V2KX-1GP
SATA_RXP4_C
SATA_TXN4 ESATA
NO REBOOT STRAP SATA4TXP AD5 2 SCD01U50V2KX-1GP SATA_TXP4
+3.3V_RUN
No Reboot Strap R23 TPAD14-GP TP2404 1 PCH _ JTAG _ TCK M3 JTAG_TCK SATA5RXN AD3
SATA5RXP AD1
1
DY 2 ACZ _ SPKR Low = Default TPAD14-GP TP2405 1 PCH _ JTAG _ TMS K3 JTAG_TMS SATA5TXN AB3
R2410 1KR2J-1-GP HDA_SPKR High = No Reboot SATA5TXP AB1
TPAD14-GP TP2406 1 PCH _ JTAG _ TDI K1 +1.05V_VTT
JTAG_TDI
TPAD14-GP TP2407 1 PCH _ JTAG _ TDO J2 AF16
JTAG_TDO SATAICOMPO R2412
TPAD14-GP TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI +3.3V_RUN
37D4R2F-GP
For EMI PCH _ SPI_ CLK R2413 1 2 15R2J-GP SPI _ CLK _ R BA2
PCH_SPI_CLK SPI_CLK
PCH _ AZ _ CODEC _ BITCLK PCH _ SPI_ CS0# R2414 1 2 15R2J-GP SPI_ CS#0_ R AV3 RN2401
B PCH_SPI_CS0# SPI_CS0# B
PCH _ AZ_ CODEC_ RST# SRN10KJ-5-GP
1 2 SPI _ CS1# AY3 T3
R2415 DY 0R2J-2-GP
SPI_CS1# SATALED# SATA_LED#
EC2402 PCH _ SPI_ DO R2416 1 2 15R2J-GP SPI _ MOSI_ R AY1 Y9 SATA _ DET#0_ R
PCH_SPI_DO SPI_MOSI SATA0GP/GPIO21
SCD1U16V2KX-3GP DY DY EC2401
SC22P50V2JN-4GP PCH _ SPI_ DI AV1 V1 SATA _ DET#1 _ R
PCH_SPI_DI SPI_MISO SATA1GP/GPIO19
IBEXPEAK-M-GP-NF
A <Core Design> A
Wistron Corporation
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
U2001F 6 OF 10
S _ GPIO Y3 AH45
BMBUSY#/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
SIO _ EXT _ SCI# C38
SIO_EXT_SCI# TACH1/GPIO1
PCH _ GPIO6 D37 TACH2/GPIO6
D
CLKOUT_PCIE7N AF48 D
SIO _ EXT _ W AKE# J32 AF47
SIO_EXT_W AKE# TACH3/GPIO7 CLKOUT_PCIE7P
SIO _ EXT _ SMI# F10
SIO_EXT_SMI# GPIO8
C2501 PCH _ GPIO12 K9 U2
SC47P50V2JN-3GP DY LAN_PHY_PWR_CTRL/GPIO12 A20GATE SIO_A20GATE
HOST _ ALTERT#1 T7 GPIO15

DGPU _ HOLD _ RST# AA2 AM3
SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N BCLK_CPU_N
+1.05V_VTT
PCH _ GPIO17 F38 AM1
TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P BCLK_CPU_P
PCH _ GPIO22 Y7 BG10

SCLOCK/GPIO22 PECI H_PECI
R2504
PCH_GPIO24 H10 T1 56R2J-4-GP
GPIO24 RCIN# SIO_RCIN#
C2502
SC47P50V2JN-3GP DY TPAD14-GP TP2502 1 PCH _ GPIO27 AB12 BE10 H_PW RGD
GPIO27 PROCPW RGD
+3.3V_RUN PCH _ GPIO28 V13 BD10 PCH _ THERMTRIP _ R 1 2
GPIO28 THRMTRIP# H_THERMTRIP#
RN2502 R2506 54D9R2F-L1-GP
PCH _ GPIO22 1 10 STP _ PCI# M11 STP_PCI#/GPIO34
PCH _ GPIO37 2 9 PCH _ GPIO38 Placed Within 2" from PCH
PCH _ GPIO36 3 8 DGPU _ HOLD _ RST# CLK _ SATA_ OE# V6
PCH _ GPIO48 S _ GPIO
SATACLKREQ#/GPIO35
4 7
5 6 PCH_TEMP_ALERT#_C PCH _ GPIO36 AB7 SATA2GP/GPIO36 TP1 BA22
SRN10KJ-L3-GP R2508 PCH _ GPIO37 AB13 AW 22

+3.3V_RUN 10KR2J-3-GP
SATA3GP/GPIO37 TP2
C PCH _ GPIO38 V3 BB22 C
SLOAD/GPIO38 TP3
PCH _ GPIO39 P3 AY45
SDATAOUT0/GPIO39 TP4
PCH _ GPIO45 H3 AY46
PCIECLKRQ6#/GPIO45 TP5
F1 PCIECLKRQ7#/GPIO46 TP6 AV43
S3_RST_GATE#
1
C2503 SCD047U16V2KX-1-GP PCH _ GPIO48 AB6 AV45
+3.3V_RUN SDATAOUT1/GPIO48 TP7
1 2 PCH _ TEMP _ ALERT# _ C AA4 AF13
PCH_TEMP_ALERT# SATA5GP/GPIO49 TP8
R2510 0R2J-2-GP
RN2503 PCH_GPIO57 F8 M18
PCH _ GPIO39
GPIO57 TP9
4 1
STP _ PCI# 3 2 N18
SRN100KJ-6-GP
TP10
A4 TP11 AJ24
VSS_NCTF_1
A49
TPAD14-GP TP2503 PCH _ NCTF _ 1 VSS_NCTF_2
1 A5 VSS_NCTF_3 TP12 AK41
RN2504 A50
PCH _ GPIO17
VSS_NCTF_4
1 8 A52 TP13 AK42
PCH _ GPIO6
VSS_NCTF_5
2 7 A53 VSS_NCTF_6
SIO _ EXT _ SCI# 3 6 B2 M32
SIO _ EXT _ W AKE# VSS_NCTF_7 TP14
4 5 B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
SRN10KJ-6-GP B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
B +3.3V_ALW B
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
PCH _ GPIO24 2 1 BH52 AA23
R2515 DY 100KR2J-1-GP BH53
VSS_NCTF_17 TP19
VSS_NCTF_18
BJ1 NC_1 AB45
VSS_NCTF_19
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
RN2501 BJ49
PCH _ GPIO12 TPAD14-GP TP2504 PCH _ NCTF _ 2 VSS_NCTF_22
1 10 1 BJ5 VSS_NCTF_23 NC_3 AB42
SIO _ EXT _ SMI# 2 9 S3_RST_GATE# BJ50
PCH _ GPIO28 PCH _ GPIO45 TPAD14-GP TP2505 PCH _ NCTF _ 3
VSS_NCTF_24
3 8 1 BJ52 VSS_NCTF_25 NC_4 AB41
HOST _ ALTERT#1 4 7 PCH_GPIO11 BJ53
PCH _ GPIO57
VSS_NCTF_26
5 6 D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
SRN10KJ-L3-GP D53 VSS_NCTF_29
E1 P6 INIT3 _ 3V# 1 TP2506TPAD14-GP
+3.3V_ALW TPAD14-GP TP2507 PCH _ NCTF _ 4
VSS_NCTF_30 INIT3_3V#
1 E53 VSS_NCTF_31
TP24 C10
IBEXPEAK-M-GP-NF
A <Core Design> A
Wistron Corporation
Title
PCH (GPIO/CPU)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH
+3.3V_RUN
1
DIS 2
R2601 0R2J-2-GP
+1.05V_VTT
U2001G POWER 7 OF 10 69mA
1.524A AB24 VCCCORE VCCADAC AE50 +VCCA _DAC _1 _ 2
C2603 C2604 C2605 +3.3V_CRT_LDO
AB26 VCCCORE
C2602 C2601 AB28 AE52
SC10U6D3V5KX-1GP AD26
VCCCORE VCCADAC UMA
D
SC1U10V2KX-1GP AD28
VCCCORE
AF53
UMA 1
UMA 2 1
UMA2 D
DY AF26
VCCCORE VSSA_DAC L2602 HCB1608KF-181-GP R2602 0R2J-2-GP
VCCCORE
AF28 VCCCORE VSSA_DAC AF51
AF30 VCCCORE
AF31 VCCCORE
AH26
VCCCORE +3.3V_RUN
AH28 VCCCORE +3VS_VCCA_LVD
AH30
AH31
VCCCORE
AH38 2
UMA1 300mA
VCCCORE VCCALVDS C2606 R2603 0R3J-0-U-GP
AJ30 VCCCORE DIS 1
+1.05V_VTT
AJ31
VCCCORE VSSA_LVDS AH39 1
R2604
2
0R2J-2-GP DY2 +1.8V_RUN
SCD1U10V2KX-5GP
AP43 +1.8VS _ VCCTX _ LVDS 1
UMA2 59mA
VCCTX_LVDS L2603 0R5J-5-GP
VCCTX_LVDS AP45
AK24
VCCTX_LVDS AT46
AT45
R2605 C2607 C2608
C2609
3.3V CRT LDO
VCCIO VCCTX_LVDS
DIS
DY SC10U6D3V5MX-3GP
UMA UMA
TP2602 1 TPAD14-GP VCCAPLLEXP BJ24 VCCAPLLEXP +5V_RUN +3.3V_CRT_LDO
VCC3_3 AB34
U2601
AN20 AB35 +3.3V_RUN
VCCIO VCC3_3
AN22 3 4
AN23
VCCIO
VCCIO VCC3_3 AD35 357mA 2
VIN
GNDDY
VOUT
AN24 VCCIO 1 EN NC#5 5
AN26 C2611
+1.05V_VTT VCCIO SCD1U10V2KX-5GP
AN28
C BJ26
VCCIO C2612 DY RT9198-33PBG-GP C2613 DY C
3.208A BJ28
VCCIO
VCCIO
SC1U10V2KX-1GP SC1U10V2KX-1GP
AT26
VCCIO Second 74.09091.H3F
C2614 C2615 C2616 C2617 C2618 AT28 VCCIO
UMA UMA AU26 VCCIO +1.8V_RUN
AU28 VCCIO
AV26
AV28
VCCIO
VCCIO VCCVRM AT24 35mA
AW 26 VCCIO
AW 28 VCCIO
BA26 AT16 0R2J-2-GP +1.05V_VTT
VCCIO VCCDMI +1.05VS_VCC_DMI R2606
BA28
BB26
BB28
VCCIO
VCCIO VCCDMI
AU16 1 2 61mA +1.8V_RUN +3.3V_RUN
VCCIO C2619
BC26 VCCIO
BC28 VCCIO SC1U6D3V2KX-GP R2607
+3.3V_RUN
BD26
BD28
VCCIO 0R2J-2-GP DY R2608
0R2J-2-GP
VCCIO +V_NVRAM_VCCQ
BE26 VCCIO VCCPNAND AM16
BE28 AK16
C2621
BG26
VCCIO
VCCIO
VCCPNAND
VCCPNAND AK20 156mA
BG28 VCCIO VCCPNAND AK19
SCD1U10V2KX-4GP BH27 AK15 C2620
VCCIO VCCPNAND SCD1U10V2KX-5GP
VCCPNAND AK13
AN30 VCCIO VCCPNAND AM12
AN31 VCCIO AM13
VCCPNAND
VCCPNAND AM15
B
357mA AN35 VCC3_3 +3.3V_RUN B
VCCAFDI _ VRM AT22 VCCVRM[1] R2609

+1.05V_VTT TP2601 1 VCCFDIPLL
TPAD14-GP
BJ18 VCCFDIPLL VCCME3_3 AM8
AM9
85mA 0R2J-2-GP
VCCME3_3
AM23 VCCIO AP11
VCCME3_3 PCH_VCCME3_3
VCCME3_3 AP9
C2623
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF
0924 SA +1.8V_RUN
R2610
VCCAFDI _ VRM 1 2
0R2J-2-GP
A <Core Design> A
Wistron Corporation
Title
PCH (POWER1)
Berry X00
5 4 3 2 1
5 4 3 2 1
+1.05V_VTT SSID = PCH

U2001J POWER 10 OF 10
TP2701 1 VCCACLK AP51 V24

TPAD14-GP
VCCACLK VCCIO
VCCIO V26
AP53 Y24 C2705
VCCACLK VCCIO
VCCIO Y26
DYSC1U10V2KX-1GP
AF23 V28 +3.3V_ALW
VCCLAN VCCSUS3_3
VCCSUS3_3 U28
AF24 VCCLAN U26
VCCSUS3_3
D
VCCSUS3_3 U24 D
P28
DCPSUSBYP VCCSUS3_3
Y20 DCPSUSBYP VCCSUS3_3 P26
N28 C2706
C2703
VCCSUS3_3 SCD1U10V2KX-4GP
VCCSUS3_3 N26
SCD1U10V2KX-4GP AD38 M28
VCCME VCCSUS3_3
M26
VCCSUS3_3
AD39 VCCME VCCSUS3_3 L28
VCCSUS3_3 L26
AD41 VCCME J28
+1.05V_VTT VCCSUS3_3
VCCSUS3_3 J26
AF43 H28
1.998A AF41
VCCME VCCSUS3_3
VCCSUS3_3 H26
VCCME VCCSUS3_3 G28
C2707 C2704 C2708 G26
VCCSUS3_3
AF42 F28
SC10U10V5KX-2GP DY VCCME VCCSUS3_3
F26
VCCSUS3_3 +3.3V_ALW +3.3V_ALW
V39 VCCME VCCSUS3_3 E28
VCCSUS3_3 E26
V41 VCCME VCCSUS3_3 C28
VCCSUS3_3 C26
V42 B27 +3.3V_RUN
VCCME VCCSUS3_3 C2709 D2701
VCCSUS3_3 A28
Y39 A26 SCD1U10V2KX-4GP CH751H-40PT-GP
VCCME VCCSUS3_3
+1.05V_VTT C2710 Y41 U23 +1.05V_VTT
L2702
SC1U10V2KX-1GP DY VCCME VCCSUS3_3
1 2 +1.05VS _VCCA _ A _ DPL Y42 V23 +5V_ALW D2702
IND-10UH-218-GP VCCME VCCIO
CH751H-40PT-GP
C C2712 F24 +5VALW _ PCH_ VCC5REFSUS 1 2 C
C2711 SC1U10V2KX-1GP
V5REF_SUS R2702 10R2J-2-GP
SC10U6D3V5MX-3GP DY +VCCRTCEXT V9 change 1uF
DCPRTC C2713 +5V_RUN
C2714 +1.8V_RUN SC1U10V2KX-1G P
SCD1U10V2KX-4GP K49 +5VS _ PCH_ VCC5REF 1 2
L2703 V5REF
AU24 R2701 10R2J-2-GP
VCCVRM
1 2 +1.05VS _VCCA _ B _ DPL DG update 1.62
IND-10UH-218-GP J38
C2717
VCC3_3 C2715
BB51
C2716
SC10U6D3V5MX-3GP DY SC1U10V2KX-1GP 72mA +1.05VS _VCCA _A _ DPL BB53
VCCADPLLA
VCCADPLLA VCC3_3 L38
+3.3V_RUN
SC1U10V2KX-1GP
M36
73mA +1.05VS _VCCA _B _ DPL BD51
BD53
VCCADPLLB
VCC3_3
N36
VCCADPLLB VCC3_3
+1.05V_VTT AH23 P36 C2718
VCCIO VCC3_3 SCD1U10V2KX-4GP
AJ35
VCCIO C2719
AH35 VCCIO VCC3_3 U35
1 2 +3.3V_RUN
C2720 C2721 C2722 AF34
SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
VCCIO SCD1U10V2KX-4GP
VCC3_3 AD13
AH34 VCCIO
AF32 VCCIO
AK3 VCCSATAPLL 1 TP2702
VCCSATAPLL TPAD14-GP
V12 DCPSST VCCSATAPLL AK1
+VCCSST
B +1.05V_VTT B
+1.05VALW _ INT _ VCCSUS Y22
C2725
DCPSUS
VCCIO AH22
SCD1U10V2KX-4GP C2726
SCD1U10V2KX-4GP +1.8V_RUN C2727
P18 AT20 SC1U10V2KX-1GP
VCCSUS3_3 VCCVRM
U19 VCCSUS3_3
+3.3V_ALW AH19
163mA U20 VCCSUS3_3
VCCIO
AD20
VCCIO
U22 VCCSUS3_3
C2728 AF22
SCD1U10V2KX-4GP +3.3V_RUN VCCIO
VCCIO AD19
V15 VCC3_3 AF20
VCCIO
VCCIO AF19
V16 VCC3_3 VCCIO AH20
C2729
SCD1U10V2KX-4GP Y16 AB19
VCC3_3 VCCIO
VCCIO AB20
+1.05V_VTT AB22
VCCIO +1.05V_VTT
AD22
1mA AT18 V_CPU_IO
VCCIO
VCCME AA34
C2730 C2731 C2732 Y34
SC10U6D3V5KX-1GP VCCME
AU18 V_CPU_IO VCCME Y35
VCCME AA35
A
+RTC_CELL A12 L30 +VCCSUSHDA 1

R2703
2
6mA <Core Design> A
VCCRTC VCCSUSHDA +3.3V_ALW
2mA 0R2J-2-GP Wistron Corporation

IBEXPEAK-M-GP-NF C2733 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
C2734 C2735 SC1U10V2KX-1GP Taipei Hsien 221, Taiwan, R.O.C.
Title
PCH (POWER2)
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PCH U2001I 9 OF 10

AY7 VSS VSS H49
B11 VSS VSS H5
B15 VSS VSS J24
B19 VSS VSS K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 K7
VSS VSS
B39 VSS VSS L14
B43 VSS VSS L18
B47 VSS VSS L2
D B7 VSS VSS L22 D
U2001H 8 OF 10 BG12 L32
VSS VSS
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AA22 AK32 BB30 M16
VSS VSS VSS VSS
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA30 AK46 BB5 M42
VSS VSS VSS VSS
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB39 VSS VSS AM20 BC44 VSS VSS P30
AB43 AM22 BC52 P32
VSS VSS VSS VSS
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
AD12 VSS VSS AM32 BE20 VSS VSS T12
C AD16 AM34 BE24 T41 C
VSS VSS VSS VSS
AD30 AM38 BE34 T49
VSS VSS VSS VSS
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 AV22 BE50 U32
VSS VSS VSS VSS
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 AN32 BF51 V19
VSS VSS VSS VSS
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 AP46 BH11 V32
VSS VSS VSS VSS
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 AR52 BH35 V45
VSS VSS VSS VSS
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 VSS VSS AT41 C50 VSS VSS V8
B B
AH16 VSS VSS AT47 D51 VSS VSS W2
AH24 VSS VSS AT7 E12 VSS VSS W 52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 AV16 E20 Y12
VSS VSS VSS VSS
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ2 AV38 E42 Y30
VSS VSS VSS VSS
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW 14 F5 VSS VSS P49
AJ34 VSS VSS AW 18 G10 VSS VSS Y5
AT5 VSS VSS AW 2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 AW 32 G2 P24
VSS VSS VSS VSS
AM41 VSS VSS AW 36 G22 VSS VSS T43
AN19 VSS VSS AW 40 G32 VSS VSS AD51
AK26 VSS VSS AW 52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 AY43 G44 Y47
VSS VSS VSS VSS
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
A H30 VSS VSS AK45 <Core Design> A
H34 VSS VSS AK39
H38 VSS AV14
VSS
H42 VSS Wistron Corporation
IBEXPEAK-M-GP-NF Title
PCH (VSS)
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
+AVDD +5V_RUN
D +3.3V_RUN D
+3.3V_RUN Close to codec R3002
1 2
Close to codec AUD _DVDDCORE 0R3J-0-U-GP +5V_RUN
C3006 +PVDD
C3001 SC1U10V2KX-1GP
SC10U6D3V5MX-3 G P 1 2
R3003 0R3J-0-U-GP
U3001
1 27
DVDD_CORE AVDD
38 1 2
AVDD AUD_AGND R3004 0R3J-0-U-GP
9
PCH _AZ _ CODEC_ BITCLK DVDD
39
PVDD
3 45
DVDD_IO PVDD
13 AUD _SENSE_ A
PCH _AZ_ CODEC_ BITCLK
SENSE_A AUD_ SENSE_ B AUD_AGND
6 14
C3007
PCH_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
DY SC4D7P50V2CN-1GP R3001 1 2 33R2J-2-GP PCH _SDIN_ CODEC_ C0 8
PCH_SDIN_CODEC HDA_SDI
28 AUD _EXT _ MIC_ L C3021 2 1SC1U10V2KX- MIC_IN_L
PCH _ SDOUT _ CODEC HP0_PORT _A_L AUD_ EXT_ MIC_ R C3022 1GP
5 29
PCH_SDOUT_CODEC HDA_SDO HP0_PORT _A_R MIC_IN_R
23 AUD_VREFOUT_B 1SC1U10V2KX- AUD_VREFOUT_B
PCH_AZ_CODEC_SYNC VREFOUT_A_OR_F close to1GP
udio jack
10
PCH_AZ_CODEC_SYNC HDA_SYNC AUD_HP1_JACK_L R3005 60D4R2F-GP
31 1 2
PCH_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R R3006 60D4R2F-GP
AUD_HP1_JACK_L2
11 32 1 2
+3.3V_RUN
PCH_AZ_CODEC_RST# HDA_RST# HP1_PORT_B_R AUD_HP1_JACK_R2
19 A U D_ INT _ MIC_ R_ L 1 2
PORT_C_L INT_MIC_L_R
PORT_C_R
20
A U D_ VREFOUT _ C
C3011 SC1U6D3V2KX-GP
Check
24 1 2
TPAD14-GP TP3001 AUD _DMIC_ CLK VREFOUT_C R3007 4K7R2J-2-GP
1 2
TP3002 DMIC_CLK/GPIO1
R3008 TPAD14-GP 1 AUD _DMIC_IN0 4 DMIC0/GPIO2 SPKR_PORT_D_L+
40 AUD_ SPK_ L+
AUD _SPK_ L- AUD_SPK_L+
C3012
R3009
1 20KR2J-L-GP
From SB
10KR2J-3-GP 41
SPKR_PORT_D_L- AUD_SPK_L-
46
DMIC1/GPIO0/SPDIF_OUT _1 2 1 SCD1U10V2KX-4GP SB _SPKR _R 1 2 ACZ_SPKR
C 43 AUD _SPK_ R- C
SPKR_PORT_D_R- AUD _SPK_ R+ AUD_SPK_R-
48 44 2 1 SCD1U10V2KX-4GP KBC _BEEP _R 1 2 KBC_BEEP
AMP_MUTE# SPDIF_OUT_0 SPKR_PORT_D_R+ AUD_SPK_R+
R3010
AMP_MUTE#
AMP_MUTE# 47
EAPD PORT_E_L
15
G3001
C3013 470KR2J-2-GP From EC
16
PORT_E_R
DUMMY-C2
AUD _VREFOUT _ B PUMP_ CAPN 17
PORT_F_L AUD _PC_ BEEP
35 18
CAP- PORT_F_R
C3014
SC2D2U25V5KX-1GP 36
PC_BEEP
12
AUD_PC_BEEP
CAP+
C3023
SC1U10V2KX-1GP
PUMP_CAPP
MONO_OUT
25 Trace width>15 mils
7
DVSS
33 22 AUD_CAP2
AVSS CAP2
30
26
AVSS
AVSS VREFFILT 21 AUD _VREFFLT Possible to remove for new IC
42 34 AUD _ V _ B
PVSS V-
49 37 AUD _VREG
GND VREG
92HD81B1A5NLGXUAX8-GP C3017
AUD_AGND
X01 will change to 92HD79B1

P/N:71.92H79.003 AUD_AGND AUD_AGND AUD_AGND AUD_AGND
Azalia I/F EMI Close to codec

B B
PCH _SDOUT _ CODEC
R3015
47R2J-2-GP
DY +AVDD R3016 +AVDD
20KR2F-L-GP R3014
1 2 2 1
AUD_HP1_JD#
R3018 R3019 0R3J-0-U-GP
2K49R2F-GP 2K49R2F-GP
R3017
2 1
AUD _SENSE_ A AUD_ SENSE_ B
0R3J-0-U-GP
C3019 R3021
SC1000P50V3JN-GP- U R3022 20KR2F-L-GP R3020
39K2R2F-L-GP 2 1
2 1 EXT_MIC_JD#
0R3J-0-U-GP
C3020 AUD_AGND
DY SCD1U10V2KX-4GP AUD_AGND
Close to Pin13
Close to Pin14 AUD_AGND
A A
<Core Design>
Wistron Corporation
Title
Audio Codec 92HD81B1
Cust o m X00
Date:
Berry
Thursday , October 22 , 2009 Sheet 30 of 92
3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A A
<Core Design>
Wistron Corporation
Title
Size
Reserved
Document Number Rev
Custo m
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 <Core Design> 1
Wistron Corporation
Title
Reserved
A3
Berry X00
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
10 mW solution remove
+KBC_PW R
+3.3V_RUN +3.3V_RUN
CAP close to VCC-GND pin pair
SSID = KBC
R3701
2 1 +3.3V_RTC_LDO 20090702 Update 10mW circuit +KBC_PW R
0R2J-2-GP
VBAT R3704
L3701
1
0R3J-0-U-GP
DY KBC _PW RBTN _EC#
1 2 1
+KBC_PW R R3703 0R2J-2-GP 100KR2J-1-GP
C3702 C3703 +3.3V_RTC_LDO
SCD1U10V2KX-4GP DY SC2D2U10V3KX-1GP +3.3V_RTC_LDO
Q2302
KBC _ SDA1
Madison KBC_ PW RBTN#
0707
THERM_SDA 4 3 KBC_PW RBTN# 3
R3705 D3702
DY 5 2 2K2R2J-2-GP BAT54C-U-GP R3706
10KR2J-3-GP
U3701A 1 OF 2 KBC _ SCL1 6 1
BAT_IN# THERM_SCL
D 2N7002EDW -GP DISCRETE_ID
R3708
KBC_ON# G Q3703 D
AD_IA
84.27002.F3F For 512MB/1GB VRAM option 1 DY 2 SI2301CDS-T1-GE3-GP
104 124 PCH_TEMP_ALERT# 0R2J-2-GP
VREF GPIO10/LPCPD# PLT_RST1#_ 1 AC_ IN#_ KBC
7
LRESET# +1.05V_VTT +3.3V_RUN +KBC_PW R
TP3704 1 KBC_GPIO91
97
98
GPI90/AD0 A/D LCLK
2
3
PCLK_KBC
LPC_LFRAME#
D3703
GPI91/AD1 LFRAME# LPC _ LAD0 +KBC_PW R BAT54C-U - GP
99 126
THERMTRIP_VGA# GPI92/AD2 LAD0 LPC _ LAD1
PSID_EC 100 127 LPC_LAD[0..3]
DISCRETE _ID GPI93/AD3 LAD1 LPC_ LAD2 R3710 E51_ RxD
108
GPIO05 LAD2
128 1
DY 2 3 AC_IN#
KBC _ THERMTRIP# 96
GPIO04 LPC LAD3
1
125
LPC_ LAD3 2K2R2J-2-GP R3711 10KR2J-3-GP 20090714
SERIRQ INT_SERIRQ Q3704
8 PM_CLKRUN# C3711
GPIO11/CLKRUN# H_THERMTRIP_R# 2
122 1 G
SUS_PW R_DN_ACK 101
KBRST#
121
SIO_RCIN#
SIO_A20GATE
DY
GPI94 GA20 ECSCI#_ KBC SCD1U16V2KX-3GP KBC_ ON#
105 29 D
3.3V_RUN_VGA_EN GPI95 ECSCI#/GPIO54
TP3703
1 KBC _ GPIO96
PCB_VER2
106
107
GPI96 D/A GPIO65/SMI#
9
123 ECSW I#_KBC
PANEL_BLEN
2 3 KBC_THERMTRIP# +KBC_PW R EC_ENABLE# S
GPI97 GPIO67/PW UREQ# H_THERMTRIP#
PH for Discrete 1 UMA Q3705
R3714 10KR2F-2-GP PMBS3904-1-GP
Internal PL for UMA RN3701 2N7002E-1-GP
64 68 THERMTRIP _ VGA# 5 4
PM_SLP_S3# GPIO01/TB2 GPIO74/SDA2 KBC_SDA1 84.2N702.D31
KBC _ PWRBTN _ EC#
AC_IN#_KBC
95
93
GPIO03 SMB GPIO73/SCL2
67
69
KBC_SCL1
BAT_ SCL
BAT_SDA
6
7
3
2
+KBC_PW R GPIO06 GPIO22/SDA1 BAT_SDA
94 70 ECRST# 8 1
R3715
LID_CLOSE#
PCB_ VER0 119
GPIO07 GPIO17/SCL1 BAT_SCL
D3701
DY
KBC _BIOS _ID GPIO23 SRN4K7J-10-GP
2 DIS 1 2K2R2J-2-GP 6
GPIO24 SIO_EXT_W AKE# 1
1.0V_RUN_VGA_EN 109
PCB_ VER1 GPIO30 ECSW I#_KBC +KBC_PW R
PW RLED#
120
65
GPIO31 SP GPIO66/G_PW M
81 1.8V_VGA_RUN_EN 3
KB_ DET# 3
RN3703
2
GPIO32/D_PW M LCD _CBL_ DET#
PW R_BTN_LED# 66 2 4 1
GPIO33/H_PW M
W HITE_LED#_KBC 16
GPIO40/F_PW M ECSMI#_ KBC SRN100KJ-6-GP
AD_OFF 17 84 BAS16PT-GP
GPIO42/TCK GPIO77
PCH_RSMRST# 20
GPIO43/TMS SPI GPIO76/SHBM
83 BLUETOOTH_EN
KBC _THERMTRIP # 1 R3722
PM_SLP_S4# 21
22
GPIO44/TDI GPIO GPIO75
82
91
W IFI_RF_EN
1
D3704 AC_IN#_KBC R 2516
R 2517
1 100K R 2J-1-GP
100K R 2J-1-GP
10KR2J-3-GP
PLTRST_DELAY# GPIO45/E_PW M GPIO81 WW AN_RADIO_DIS# SIO_EXT_SCI#
23
3V_5V_POK GPIO46/TRST# ECSCI#_KBC
PM_PW ROK 24 3
GPIO47
EC_SPI_W P#_R
EC _ ENABLE#
25
26
GPIO50/TDO
111 2
X01 change location PURE_HW _SHUTDOW N#
GPIO51 GPO83/SOUT_CR/BADDR1 E51_TxD
27 113
C BLON_OUT
IMVP_VR_ON
PSID_DISABLE#
28
73
GPIO52/RDY#
GPIO53
GPIO70
GPIO87/SIN_CR
GPO84/BADDR0
112
E51_RxD
AC_PRESENT_EC BAS16PT-GP
+3.3V_RUN C
GFX_CORE_EN 74 114 PM_LAN_ENABLE BLUETOOTH _EN R3712 1 2 10KR2J-3-GP
GPIO71 GPIO16 1.5CPU _ 1.05VTT_ PW RGD_ KBC
ME_UNLOCK# 75 14 1 1.5CPU_1.05VTT_PW RGD S5_ ENABLE R3713 1 10KR2J-3-GP
GPIO72 GPIO34
USB_PW R_EN# 110 15 S5_ENABLE R3723 0R2J-2-GP IMVP_ VR_ ON R3717 1 10KR2J-3-GP
GPO82/TRIS# GPIO36
SER/IR SIO_EXT_SMI# 1
D3705
RN3702
SIO _A20GATE 2
44 KBC_VCORF 3 ECSMI#_KBC SIO _RCIN# 1 4
VCORF
C3712 2 SRN10KJ-5-GP
+3.3V_RUN SC1U6D3V2KX-GP
BAS16PT-GP
NPCE781BA0DX-GP
Vendor recomment FW can do it Vendor recomment can remove
R3727
MB VERSION ID
10KR2J-3-GP
DY DY DY U3701B 2 OF 2
KCOL[0..16]
PCB_ VER0 VER2 VER1 VER0 77 53 KCOL0
PCH_SUSCLK_KBC 32KX1/32KCLKIN KBSOUT0/JENK#
X00 0 0 0
PCB_ VER1 52 KCOL1
PCB_ VER2 KBSOUT1/TCK KCOL2
51
KBSOUT2/TMS
X01 0 0 1
50 KCOL3
R3737 1 TOURBO_BOOST 79 KBSOUT3/TDI KCOL4
49
+KBC_PW R DY 32KX2 KBSOUT4/JEN0#
X02 0 1 0
10KR2J-3-GP 30 48 KCOL5
AMP_MUTE# GPIO55/CLKOUT KBSOUT5/TDO
R3731 47 KCOL6
KBSOUT6/RDY#
A00 0 1 1
10KR2J-3-GP 63 43 KCOL7
IMVP_PW RGD GPIO14/TB1 KBSOUT7
PM_PW RBTN#
LCD_TST_EN
117
31
GPIO20/TA2 KBC KBSOUT8
42
41
KCOL8
KCOL9
GPIO56/TA1 KBSOUT9 KCOL10
KBC_BEEP 32 40
GPIO15/A_PW M KBSOUT10 KCOL11
AMBER_LED#_KBC 118 39
BRIGHT NE SS GPIO21/B_PW M KBSOUT11 KCOL12
1 62 38
TP3705 GPIO13/C_PW M KBSOUT12/GPIO64 KCOL13
37
KBSOUT13/GPIO63 KCOL14
36
KBSOUT14/GPIO62 KCOL15
35
KBSOUT15/GPIO61/XOR_OUT KCOL16 TP3708
KB_DET# 13 34
GPIO12/PSDAT3 GPIO60/KBSOUT16
VGA STRAP option
KCOL17 TPAD14-GP
DIS LCD_CBL_DET#
THERMTRIP _VGA _ GATE_ C
12
GPIO25/PSCLK3 GPIO57/KBSOUT17
33 1
THERMTRIP_VGA_GATE 1 11 KROW [0..7]
B GPIO24 GPIO5
R3746 0R2J-2-GP LCD_TST
TPDATA
10
71
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1 KBSIN0
54 KROW 0 B
TPCLK 72 GPIO37/PSCLK1 PS/2 KBSIN1 55 KROW 1
UMA 0 0 56 KROW 2
KBSIN2 KROW 3
57
KBSIN3
Madisan 1 1
58 KROW 4
KBSIN4 KROW 5
EC_SPI_DI 86 59
F_SDI KBSIN5
Park 1 0
1 2 EC_SPI_DO_C 87 60 KROW 6
EC_SPI_DO F_SDO KBSIN6
EC_SPI_CS#
R3745 33R2J-2-GP 90
F_CS0# FIU KBSIN7
61 KROW 7
Reserved 0 1 For EMI EC_SPI_CLK R3734 1 2 33R2J-2-GP EC_SPI_CLK_C 92

F_SCK
85 ECRST#
VCC_POR#
PM_ PW ROK PCLK_ KBC NPCE781BA0DX-GP
EC3702 EC3703
SC470P50V2JN-GP SC470P50V2JN-GP
DY DY
ECRST#
1 PLT_RST1#_1
PLT_RST#
R3716 0R2J-2-GP
C3716 C3714
DY SC1U6D3V2KX-GP SC470P50V2JN-GP
1
DY
PURE_HW _SHUTDOW N#
Q3701
PMBS3906-GP
A A
<Core Design>
Wistron Corporation
Title
KBC Nuvoton NPCE781BA0DX Rev

Size Document Number
A2
Berry X00
D ate: Thursda y, October 22, 2009 Sheet 37 of 92
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Wistron Corporation A
Title
Reserved
A4
Berry X00
5 4 3 2 1
5 4 3 2 1
+5V_RUN
SSID = Thermal
+3.3V_RUN
R3901
C3902 C3901 10KR2J-3-GP
SC10U6D3V5MX-3GP SCD1U16V2KX-3G P
+3.3V_RUN
1. Place near CPU PWM CORE and PCH. EMC2102_FAN_TACH
EMC2102_FAN_TACH
D D
Layout notice : R3902
Both DN1 and DP1 routing 10 mil 49D9R2F-GP EMC2102_FAN_ DRIVE EMC2102_FAN_DRIVE
trace width and 10 mil spacing. 2 1 EMC2102 _VDD _ 3D3
near EMC2102
C3905 must be near Q3901
C3903
SCD1U16V2KX-3GP
C3904 C 3 905 +3.3V_RUN
SC470P50V2JN -GP SC 470P50V2JN-GP
Q3901
1
DY THERM_SCL
RN3901
THERM_SDA
PMBS3904-1-GP THERM_SCL 3 2
THERM_ SDA 4 1
SRN4K7J-8-GP
U3901
SRN10KJ-5-GP
EMC2102_ DN2_UMA THERM_ POWER_ OK# 3 2
THERMTRIP# 4 1
C3906
SC470P50V2JN-GP RN3902
UMA 1
DY
Q3902 1 21
PMBS3904-1-GP EMC2 1 02 _ DP2_ UMA VDD_3V NC#21
R3903 EMC2102_DN1 2 20
DN1 GND
2. System Sensor(UMA Only) UMA
R3904 EMC2102_DP1 3 19
DP1 ALERT# +3.3V_RUN
Layout notice : UMA
Both DN2 and DP2 routing 10 mil EMC2102_DN2 4
EMC2102 18 CLK _ 32K
DN2 CLK_IN
C trace width and 10 mil spacing. C
EMC2102_DP2 5 17 EM C2102 _ CLK_ SEL 1 2
DP2 CLK_SEL
Reserved DISCRETE R3905 0R2J-2-GP
DIS EMC2102_DN3 6
DN3 RESET#
16 EM 2102_ RESET# 1
TP3901
GND = Internal Oscillator Selected
1 2 C3907
VGA_THERMDC
R3906 0R2J-2-GP S C 470P50V2JN -GP EMC2102_ DP3 7 15 +3.3V = External 32.768kHz Clock Selected
DP3 NC#15
DIS
VGA_THERMDA 1 2
R3907 0R2J-2-GP
3.VGA Sensor(DISCRETE Only) GND = Channel 1 Main G7922R61U for GMT P/N:74.07922.0B3
Layout notice : OPEN = Channel 3
EMC2102-DZK-GP
SEC. EMC2102 for SMSC P/N:74.02102.A73
Both VGA_THERMDA and VGA_THERMDC routing +3.3V = Disabled
10 mil trace width and 10 mil spacing.
R3908
2 EMC2102_SHDN THERM_ POWER_ OK#
DY 1 THERMTRIP#
C3907 must be near Q3902 10KR2J-3-GP
+3.3V_RUN
R3909
C3908 C3909 2 1 EMC2102_ FAN_ mode
SC470P50V2JN-G P SC470P50V2JN-GP DY
Q3903
1
DY 10KR2J-3-GP +3.3V_RUN
PMBS3904-1-GP C63 must be +3.3V_RUN
near EMC2102 Q3904
R3911
B 4.HW T8 sensor 1 2 G B
0R2J-2-GP D PURE_HW_SHUTDOWN#
Layout notice : GND = Fan is OFF C3910 R3913
Both DN3 and DP3 routing 10 mil S SCD1U16V2KX-3GP 10KR2F-2-GP
OPEN = Fan is at 60% full-scale
trace width and 10 mil spacing.
+3.3V = Fan is at 75% full-scale 2N7002E-1-GP
84.2N702.D31 TRIP_SET Pin Voltage

V_DEGREE
V_DEGREE=(((Degree-75)/21)
PCH_SUSCLK_2102 C3911 R3914

SCD1U16V2KX-3GP 2K37R2F-GP
32K suspend clock output
T8 shutdown is set 88 deg-C.

. Q3905
2N7002E-1-GP
.
.
. . 84.2N702.D31
R3915
RUN_ENABLE CLK _ 32K _ R 1 2 CLK _ 32K
10R2J-2-GP
A C3913 A
DY SC4D7P50V2CN-1GP
<Core Design>
Wistron Corporation
Title
Thermal/Fan Controllor EMC2102

Custom X00
Berry
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend H_THERMTRIP#
R4201
1 2 H _ PW RGD _ R B
H_PW RGD DY DY Q4201
1KR2J-1-GP C4202 CHT2222APT-GP
SCD1U10V2KX-4GP
BAS16PT-GP DY
D 2 D
3 PURE_HW _SHUTDOW N#
3V_5V_EN 1
D4201
1 2 S5_ENABLE
R4203 1KR2J-1-GP
DY
Run Power +15V_ALW

AO4468 MAX 9A
Rds(on) = 18.5mOhm
+5V_RUN
+5V_ALW +5V_RUN
U4201
5 D G 4
R4204 6 D S 3 +5V_RUN Comsumption
100KR2J-1-GP 7 D S 2
C 8 D S 1 Peak current 7.73A C
R4205 C4203
SI4800BDY-T1-GP
1 2 5V _ RUN _ ENABLE SC10U6D3V5KX-1GP
+3.3V_RTC_LDO
10KR2J-3-GP
C4201 84.04800.D37
100KR2J-1-GP SC6800P25V2KX-1GP
PS_S3CNTRL
R4207
1 2 PS _ S3CNTRL
D G S
+3.3V_RUN
Q4202 AO4468 MAX 11.6A
2N7002EDW -GP Rds(on) = 18.5mOhm
84.27002.F3F +3.3V_ALW +3.3V_RUN
U4202 +3.3V_RUN Comsumption
S G D 5 D G 4
Peak current 8.14A
6 D S 3
7 D S 2
8 D S 1
PM_SLP_S3#
R4211 C4205
SI4800BDY-T1-GP
RUN _ ENABLE 1 2 3.3V _ RUN _ ENABLE SC10U6D3V5KX-1GP
RUN_ENABLE
10KR2J-3-GP
B
C4207 84.04800.D37 B
SCD01U50V2KX-1GP
+1.5V_RUN_CPU +1.5V_RUN 1.5V_RUN for VGA Comsumption

Peak current 7.39A
S3 Power Reduction
1 MAX Current 3000 mA
Design Current 2100 mA +1.5V_RUN_CPU Comsumption
DY
R4213
220R2J-L2-GP 2 +1.5V_S U S
+1.5V_RUN_CPU +1.5V_RUN
Peak current 3A
+1.5V_RUN for Mini-Card Comsumption

Peak current 1A
R4214 1 2 1 DY 2
0 R5J-5-GP
R4219 1 2
R4215
1 2
0R5J-5-GP
Total= 11.39A
0 R5J-5-GP R4220 DY 0R5J-5-GP
SIR460DP MAX 40A Rds(on) = 4.7m OHM

Rds(on) = 4.7mOhm
U4203 S3 Power Red uction
8 D COLAY
S 1
7 D S 2
6 D S 3
5 D G 4 <Core Design>
A . Q4206 C4208 A
2N7002E-1-GP R4227 SC10U 6 D3V5KX-1GP
SIR460DP-T1-GE3-GP
. 1 2 1.5V _RUN _ENABL E
. .
. 84.2N702.D31 Wistron Corporation
10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
C4210
SCD01U50V2KX-1GP Title
DIS uses 84.00460.037 SIR460DP Peak current=40A
PS _ S3CNTRL
UMA uses 84.07686.037 SI7686DP Peak current=35A Power Plane Enable
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
Batt Connecter
+VCHGR
PG4401
2 1 PC4402 PC4401
D BATT_SENSE SCD1U50V3KX-GP SC2200P50V2KX-2GP BATT1 D
GAP-CLOSE-PWR-3-GP 10
1
2
R4401 1 100R2J-2-GP PBAT_SMBCLK1 3
BAT_SCL
R4402 1 2 100R2J-2-GP PBAT_SMBDAT1 4
BAT_SDA
R4403 1 2 100R2J-2-GP PBAT_PRES1# 5
BAT_IN#
PR4401 6
+KBC_PWR 2 1 AFTP4401 1BAT _ALERT 7
8
470KR2J-2-GP 9
11
ALP-CON9-2-GP
20.81316.009
C
For actual location, need to be swap all pin C
Close to Batt Connector
AFTP4402 1 PBAT_PRES1# PD4401

AFTP4403 1 PBAT_SMBDAT1 PD4402 PD4403
B AFTP4404 1 PBAT_SMBCLK1 1 2 B
AFTP4405 1 +VCHGR 1 2 1 2
BAV99-8-GP
BAV99-8-GP BAV99-8-GP
+KBC_PWR
<Core Design>
A
Title
BATT CONN
A4
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = Charger modify +VCHGR

+SDC_IN +PWR_SRC
PU4502 PR4502 +VCHGR
8 D S 1 PU4503
+DC_IN_SS
7 D S 2 1 2 1 S D 8
6 D S 3 2 S D 7
D01R2512F-4-GP
5 D G 4 3 S D 6
4 G D 5
+DC_IN_SS
AO4407A-GP
AO4407A-GP
D Id=-12A PG4502
PG4503 D
PR4513_03
Qg=-25nC GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
Id=-12A
+DC_IN_SS
Rdson=10~38mohm PR4506
Qg=-25nC
470KR2J-2-GP
DY Rdson=10~38mohm
2 1
PR4507
0R2J-2-GP PR4524_03
PQ4501
3 4
BQ24745_ACOK 2 5
1 6 CHAGER_SRC
1 2
2N7002EDW-GP
PC4502
84.27002.F3F SCD1U50V3KX-GP
2 PR4511 1 CHAGER_SRC
PC4503 CHG _AGND
0R2J-2-GP PC4505
SCD1U50V3KX-GP BQ24745_DCIN BQ2 745
4 CSSP
_1 DY
22
DCIN CSSP
28 2
DY DY
BQ24745 _ACIN SCD1U50V3KX-GP
BQ24745_R E F
+KBC_PWR
2
ACIN
27 BQ24745_CSSN CHG_AGND DY DY
BQ24745_LDO CSSN BQ24745_ICOUT
11 26
VDDSMB ICOUT PR4517
C
PC4501 PR4512
25
0R3J-0-U-GP
BQ24745_BOOT1_1 2
BQ24745
_BST K
PD4501
A 1
CHG_ GND
2
Charger Current=1.4~3.6A C
DY
SCD1U10V2KX-4GP 0R2J-2-GP
2 1
BOOT
VDDP
21 BQ24745_LDO PC4511 modify +VCHGR
BQ24745_ACOK 13 SD103AWS-1-GP SCD1U50V3KX-GP
ACOK
CHG_AGND
ACAV_IN 24 BQ24745_ CHARGER_ UGATE
BAT _ SCL _ 1 UGATE PC4513 +VCHGR1 +VCHGR
BAT_SCL 2 1 10 1 2 PL4501
PG4507 GAP-CLOSE-PWR-3-GP SCL PC4512 SC3300P50V3 K X-1 G P PR4519
23 1 2 SCD1U50V3KX-GP DY B Q 24 74 5_ LX1 1 2 1 2
2009/ 0 8/04 PHASE 0R3J-0-U-GP PR4518 IND-5D6UH-43-GP D01R2512F-3-GP
BAT _ SDA _ 1 BQ24745_ PHASE_ GND
CHG_AGND DY BAT_SDA 2
PG4508
1
GAP-CLOSE-PWR-3-GP
9
SDA
20 BQ24745 _LGATE _ 1
1
PC4514
2
DY
LGATE
SC220P50V2JN-3GP
2
PR4501
1 14 19
2009/06/24 DY
AD_IA NC#14 PGND DY
0R2J-2-GP
18 BQ24745 _CSOP _ 1
CHG_AGND CSOP
17
BQ24745_VICM CSON
8
BQ24745_FBO VICM BQ24745_PR4505
PR4522
200KR2F-L-GP
1 2
6 CHG_AG N D 1 PR4523 2 BQ24745 _CSOP
BQ24745_EAI FBO 0R2J-2-GP
5 16
PC4522 BQ24745_EAO EAI NC#16
PR4526 4
EAO
1 SC2200P50V2KX-2GP BQ24 45 _ REF 3
PR4526_01 BQ24745_ CE 7 VREF
2 1 2 7K5R2F-1-GP
1 1 2 PR4528
PC4521 PR4527 CE
BQ24745_CSON
DY SC150P50 V2JN- GP
PC452
1 2 0R2J-2-GP
12
GND VFB
15 0R2J-2-GP
B BAT_SENSE 2 1 B
BATT_SENSE
DY PC4527 SC56P50V2JN-2GP DY PU4501
PC4526
BQ24745RHDR-GP DY
DY PR4529
DY PC4528
PC4529
2 1
DY DY
SCD01U50V2KX-1GP
SC1U6D3V2KX-GP 0R2J-2-GP
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
AC_IN#
PC4533
DY . Q4502
2N7002E-1-GP
.
.
. .
A ACAV_IN A
<Core Design>
Wistron Corporation
Title
CHARGER BQ24745
Custo m
Berry X00
5 4 3 2 1
A B C D E
+3.3V_ALW _2
51125_ VCLK
PC4603 PC4604
PR4602 SCD1U25V3KX-GP SCD1U25V3KX-GP
100KR2J-1-GP
51125_ENTRIP
51125_ ENTIP1
.
Q4601
2N7002E-1-GP .
.
PC4601 DY PR4601 PD4601 PD4602
. . 91KR2F-GP BAT54S-5-GP BAT54S-5-GP
4
84.2N702.D31 PQ4602
4
2N7002EDW -GP +15V_ALW +5V_PW R
84.27002.F3F
PG4605
3V_5V_EN
1 2 PD3903_ 2
51125_ ENTIP2 GAP-CLOSE-PW R-3-GP

PC4605
SC1U25V3KX-1-GP PC4606
PR4603 SCD1U25V3KX-GP
DY 100KR2F-L1-G P
PC4608
SCD1U25V3KX-GP
TPS51125 RT8205B
PR4622 DY ASM
+PW R_SRC +PW R_SRC

PR4622 +PW R_SRC
51125_EN 1 2
PC4612
820KR3J-GP PC4613
PC4609 PC4610 PC4611 TPS51125 RT8205B
PR4605 0R3J 4R7
DY
DY
T PS51125 +5V_PW R
D PR4604 0R3J
RT8205B
4R7
D PC4614 PC4616 PC4617
PG4613
+5V_ALW
PU4602 PU4603 DY 2 1
FDS888 0-NL-GP FDS888 0-NL-GP
PU4601 GAP-CLOSE-PW R
PG4614
Design Current =9.07A P C4615
SCD 1U25V3KX-GP PR4604 PR4605 SCD1U25V3KX- GP
Design Current = 8.48A 2 1
14.25A<OCP<16.84A 13.32A<OCP< 15.75A

4D7R3J-L1-GP 4D7R3J-L1-GP PC4618
G S GAP-CLOSE-PW R
S G
51125
2 1 51125_ VBST2_ 1 1 2 _VBS T 2 9 22 51125_ VBST1 1 2 51125_ VBST1_ 1 1 2 PG4615
VBST2 VBST1
2 1
+3.3V_ALW PL4601 51125_DRVH2 10 21 51125_DRVH1 +5V_PW R
DRVH2 DRVH1 PL4602
GAP-CLOSE-PW R
3 1 2 51125_LL2 11 20 51125_LL1 1 2 PG4616 3
LL2 LL1
IND-3D3UH-115-GP IND-2D2UH-46-GP-U 2 1
PTC4602
D 51125_ DRVL2 12
DRVL2 DRVL1
19 51125_ DRVL1
PC461 9 PTC4601
PR4606
D GAP-CLOSE-PW R
PG4617
DY PG4624 2D2R5F-2-GP DY PU4604 51125_ VO2 7
VO2 VO1
24 51125_ VO1 PU4605 DYPR4607 PG4626 PC4620 PTC4603 2 1
FDS 66 76AS-GP 2D2R5F-2-GP PTC4604
51125_ FB2 5 2 51125_ FB1 GAP-CLOSE-PW R
VFB2 VFB1
DY PG4618
2 1
1 2 51125_E N 3V_ 5V_ POK
DY820KR2F-GP 13
EN0 PGOOD
23
PR4608
G S GAP-CLOSE-PW R
PC4621
SC330P50V3KX-GP
S G 51125_VREF
51125_ENTIP2 6
ENTRIP2 ENTRIP1
1 51125_ ENTIP1
PC4622 2
PG4619
1
DY 3 15 SC560P50V-GP
VREF GND DY GAP-CLOSE-PW R
51125_ TONSEL 4 25 PG4620
TONSEL GND
2 1
PR4611
PR4610 14 18 51125_VCLK 0R2J-2-GP GAP-CLOSE-PW R
0R2J-2-GP SKIPSEL VCLK
51125_SKIPSEL DY PG4621
PR4609 DY PR4612 2 1
6K65R2F-GP 33KR2F-GP
TPS51125RGE R -GP 51125_FB1_ R GAP-CLOSE-PW R
51125_FB2_R 74.51125.0 7 3
PC4624 DY
PC4625 +5V_ALW 2 +3.3V_ALW SC18P50V2JN-1-GP
DY +3.3V_ALW _2
SC18P50V2JN-1-GP
PG4635
1 2
PR4614 PR4615 PR4616
PR4613
10KR2F-2-GP
51125_VREF 1
0R2J-2-GP
GAP-CLOSE-PW R-3-GP
Change to RT8205B 100KR2J-1-GP 21K5R2F-GP
PR4617
1
74.08205.B73 Close to VFB Pin (pin2)
+3.3V_ALW _2 DY 0R2J- 2-GP
3V_5V_POK
51125_VREF 2 PR4618
1
0R2J-2-GP PC4626 PC4627
Close to VFB Pin (pin5) PR4619 SC4D7U6D3V3KX-GP
DY
2
+3.3V_ALW _2 DY0R2J-2-GP
1 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L 2
PR4620 Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
1 O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
DY0R2J-2-GP O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L +3.3V_ALW _2 +3.3V_RTC_LDO L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 10.8mohm/11.8mohm Isat =16Arms 68.3R310.20C TPS51125 RT8205B PR4621
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L PR4614 DY ASM 1 2
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 PR4617 ASM DY
0R2J-2-GP
H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037
L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37
TPS51125:
TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND

GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND
Operating
Mode enable both enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
turn on
switcher channels
switcher
channels
RT8205B:
1 1
TONSEL CH1 CH2
GND 200kHz 250kHz
VREF 300kHz 375kHz
Bom
VREG3 365kHz 460kHz
VREG5 365kHz 460kHz
Wistron Corporation
Title
RT8205B _ 5V/3D3V
A2
Berry X00
A B C D E
5 4 3 2 1
+PW R_SRC
PM_DPRSLPVR
+PW R_SRC VR_CLKEN# PC4706 PC4703 PC4704 PC4705
IMVP_VR_ON
DY
H_VID[6..0]
PU4702
TC4702 TC4703 +3.3V_RUN
DY DY
UGATE1 +VCC_CORE
PL4701
D D
PHASE1 1 2
IND-D36UH-9-G P
PR4745
1K91R2F-1-GP PTC4703 PTC4702
PU4703 DY
DY
+3.3V_RUN LGATE1
PU4701
ISEN1
Design Current = 48A
PR4720 1
1K91R2F-1-GP +5V_ALW PR4756 10KR2F-2-GP 52.8A<OCP<67.2A
VSUM+ 1 2
PR4772 PR4767 3K65R3F-GP
1 2 62883_ PGOOD 1 30 BOOT2 1 B00T2_R VSUM- 1
IMVP_PW RGD PR4704 0R2J-2-GP PGOOD BOOT2 PR4742 1R2F-GP
1 62883_PSI# 2 29 UGATE2 2D2R3J-2-GP PR4770 ISEN2 1
PSI# PSI# UGATE2
PR4733 0R2J-2-GP 1 DY 2 PR4716 10KR2F-2-GP
1 2 62883_RBIAS 3 28 PHASE2 1 2 ISEN3 1 2
RBIAS PHASE2
NTC 470K close to H/S MOSFET of Phase1 PR4781 147KR2F-GP
H_PRO CHOT #_R
PC4710 4K02R2F-GP PR4738 10KR2F-2-GP
1 DY 2 4 27 SCD22U16V3KX-1-GP PR4751
H_PROCHOT# PR4771 PR4758 VR_TT# VSSP2 0R3J-0-U-GP
1 DY 2 6266A_NTC_R1 DY NTC-470K-1-GP 4K02R2F-GP 62883_NTC 5 ISL62883HRZ-T-GP 26 LGATE2 +PW R_SRC
NTC LGATE2
PR4774
4K02R2F-GP 1 DY 62883_VW 6 25 62883_ VCCP
SCD01U25V2KX-3GP VW VCCP
PC4737 1 2 62883_COMP 7 24 62883_ PW M3 PC4708 PC4732 PC4715 PC4713 PC4714 PC4712
PR4726 COMP PW M3/LGATE1#
8K06R2F-GP 62883_FB LGATE1
8
FB LGATE1
23 DY
1 ISEN3 9 22
ISEN3/FB2 VSSP1
C PC4719 PC4702 ISEN2 10 21 PHASE1 PU4704 C
SC1KP50V2KX-1GP ISEN2 PHASE1
PC4707 +1.05V_VTT
PR4744 41
GND
1 DY 1
PC4738 PR4723
0R2J-2-GP SC33P50V2JN-3GP 0R2J-2-GP
PR4786
DY UGATE1
ISEN3 62883_COMP_R ISEN1 PR4722
DY 100KR2F-L1-GP
UGATE2 +VCC_CORE
1 1 1 2 PL4702
PC4735 PC4740 PR4752 BOOT1 1 BOOT 1_PHASE1
SC22P50V2JN-4GP SC150P50V2JN-3GP 324KR2F-GP PC4736 SCD22U10V2KX-1GP 2D2R3J-2-GP PHASE2 1 2
IMVP_IMON IND-D36UH-9-GP
PR4754 0R2J-2-GP +5V_ALW
1 2 +PW R_SRC PR4776 PC4730 PTC4705 PTC4704
VSUM- SCD22U10V2KX-1GP PR4731 PC4734 PU4705
PC4716
1
PR4759
2 +5V_ALW 1 2 1 DY
1 62883_ FB_ VSEN1 1 1R2F-GP 0R2J-2-GP SC1U10V2KX-1GP PR4734
PR4714 BOOT3 1 6208_PHASE3
PR4712
5 62R2F-GP SC390 P 50V2KX-G P 2 PC4729 VSS_SENSE
1 2 SCD22U25V3KX-GP 2D2R3J-2-GP
PC4723
PU4706 SCD22U16V3KX-1-GP DY
2KR2F-3-GP LGATE2
VSUM+
2 7 PHASE3
PC4717 PC4741 PW M PHASE UGATE3
8
PC4721 PR4750 UGATE LGATE3
4
SC330P50V2KX-3GP 2K61R2F-1-GP LGATE ISEN2
6 1 2
PR4725 FCCM PR4780 10KR2F-2-GP
82D5R2F-1-GP PR4736 VSUM+ 1 2
PR4739 3K65R3F-GP
ISL6208CRZ-TGP-U VSUM- 1
VCC_SENSE PR4708 1R2F-GP
ISEN1 1
PC4711 PR4760 10KR2F-2-GP
SC330P50V2KX-3GP PC4742 PR4721 ISEN3 1 2
SCD01U25V2KX-3GP NTC-10K-26-GP PR4707 10KR2F-2-GP
VSS_SENSE +PW R_SRC
B
PR4748 B
1 2 VSUM-
PC4701 649R2F-GP
NTC 10K close to Choke of Phase1
SC1KP50V2KX-1GP PC4727 PC4725 PC4728 PC4726
PC4731
SCD1U25V3KX-GP
Intel support POC (Power On Configuration ). DY
+1.05V_VTT
PG4715 PU4707
1 2
PR473 7 PR4701 PR4709 PR4732 PR4713 PR470 5 PR476 9 PR4724 PR4753 GAP-CLOSE-PW R-3-GP
DY DY DY DY
UGATE3 +VCC_CORE
PL4703
PHASE3 1 2
H_ VID0 IND-D36UH-9-GP
H_ VID1
H_ VID2 PTC4706 PTC4707
H_ VID3 PU4708
H_ VID4 DY
H_VID5
H_ VID6
PM_DPRSLPVR
PSI#
PR471 5 PR4702 PR4768 PR4743 PR4727 PR471 0 PR470 6 PR4703 PR4777

DY
LGATE3
DY DY DY DY DY
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L ISEN3 1

PR4763 10KR2F-2-GP
Inductor: 0.36UH PCMC104T-R36MN1R05J Cyntec 1.05mohm/ 68.R3610.20C VSUM+ 1 2
A O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L PR4764 3K65R3F-GP A
O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L VSUM- 1

PR4747
2
1R2F-GP
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 ISEN1 1
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 PR4719 10KR2F-2-GP
ISEN2 1
PR4765 10KR2F-2-GP <Core Design>
Wistron Corporation
Title
ISL62883 _ CPU_ CORE

A2 Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
+PW R_SRC +PW R_SRC_VTT

TPS51218 for +1.05V_VTT
PG4901
1 2
GAP-CLOSE-PW R
PG4902
1 2
+PW R_SRC_VTT
GAP-CLOSE-PW R
PG4903
1 2
GAP-CLOSE-PW R
D PG4904 D
1 2
DY
GAP-CLOSE-PW R
PG4907
1 2 PU4902 PU4903
GAP-CLOSE-PW R
DIS(Arrandale 1.05V_VTT)
Design Current = 20.57A
30.79A<OCP<36.39A
1.5CPU_1.05VTT_PW RGD
PU4901 PC4908
PR4902 SCD1U25V3KX-GP
PR4901 1 11 2D2R3J-2-GP
51218_ VTT_TRIP PGOOD GND 51218_ VBST_ VTT 51218 VBST
_ VTT1_2 +1.05V_VTT
1 2 10 1 1
TRIP VBST PL4901
80K6R2F-GP 51218_ VTT_EN 3 9 51218_ DRVH_ VTT
51218_ VTT_VFB EN DRVH 51218_ SW_ VTT
4 8 1 2
51218_VTT_CCM VFB SW
1 5 7 +5V_ALW IND-D56UH-12-GP
RUNPW ROK CCM V5IN
PR4903 0R2J-2-GP 6 51218_ DRVL_ VTT
DRVL PC4910 PC4911 PTC4901 PTC4902
PC4909 PR4905
PR4904 TPS51218DSCR-GP-U SC1U10V2KX-1GP DY 2D2R5J-1-GP PG4916
DY
470KR2F-GP
PU4904 PU4905
1 2
DY VTT_SENSE
PR4906
10R2J-2-GP
PC4912
+3.3V_RUN +3.3V_ALW R1
DY
Vout=0.704V*(R1+R2)/R2
C C
PR4909
PR4908 100KR2J-1-GP
10KR2J-3-GP 51218 _VTT_ VFB
PQ4901
1 6
1.5CPU _ 1.05VTT_ PW RGD 2 5 H_ VTTPW RGD_ R

+1.05V_VTT
R2
3 4
PC4913
SCD1U25V3KX-GP
2N7002EDW -GP PR4911
84.27002.F3F 1KR2J-1-GP
H_ VTTPW RGD
H_VTTPW RGD
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
Frequency setting O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
470K -->290KHz H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
200K -->340KHz
100K -->380KHz
39K -->430KHz
B B
A A
<Core Design>
Wistron Corporation
Title
TPS51218 _+1.05V_ VTT

A2
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW 5 S3 Power Reduction
PR5001
5D1R3J-GP
+5V_ALW
+5V_ALW
PR5002
1.5CPU_1.05VTT_PWRGD
Modified net name 1 2
10KR2F-2-GP
TPS51116_VDD
+5V_ALW
PS_S3CNTRL
D D
1 2 PC5003 PR5016
SC1U10V2KX-1GP 100KR2J-1-GP
PC5002
+3.3V_RUN SC1KP50V2KX-1GP PD5001
+PWR_SRC_1D5V PR5015
DY RB551V-30-2GP
+1.5V_RUN_CPU 0R2J-2-GP
TPS51116_ VDD_ R 1.5V _ RUN_ CPU_ EN# PQ5002
PU5001 2N7002EDW-GP
PR5004
PR5017
20KR2F-L-GP 84.27002.F3F
PR5005 2 11.5V _RUN _CPU _EN 1 PQ5001
22 TPS51116_ VBST 1 2TPS51116 _VBST1 PMBS3904-1-GP
BST 4K7R2J-2-GP 0D75V_EN
RUNPWROK 13
PGD 0R3J-0-U-GP
PR5006 1 2 622KR2F-GP TPS51116_NC#12 12 21 TPS51116_ UGT
DY NC#12 DH PR5003 PC5004
1D5V_EN 1 DY SCD1U10V2KX-4GP
11
EN/PSV PM_SLP_S3# 0R2J-2-GP
2
DY
0D75V_EN 10 20 TPS51116_ PHS
VTTEN LX
RT: 23
+1.5V_SUS VTTIN
Non_ASM
TI: ASM PC5005 19 TPS51116_LGT
SC1U10V2KX-1GP DL
7
+5V_ALW NC#7
PR50081 1M1R2J-GP +PWR_SRC +PWR_SRC_1D5V
DY 2 TPS51116RGER-GP-U
1 18 PR5007 1 2 0R2J-2-GP 1D5V_EN PG5002
+1.5V_SUS PGND2 PGND1 PM_SLP_S4#
17 2 1
C PR50091 0R2J-2-GP TPS51116_TON PGND1 C
2 4
TON TPS51116_VDDQSNS GAP-CLOSE-PWR
8
VDDQS PC5006 PG5003
PC5007 24 9 TPS51116_VDDQSET DY SCD1U10V2KX-4GP 2 1
SC1KP50V2KX-1GP VTT FB
+0D75V_DDR_P DY 2
+5V_ALW PR5010 GAP-CLOSE-PWR
VTTS PG5004
6 1 2
VCCA DY +PWR_SRC_1D5V
2 1
0R2J-2-GP
GAP-CLOSE-PWR
PC5008 PG5006
+V_DDR_REF DY SC1U10V2KX-1GP 2 1
1 PR5011 2 GAP-CLOSE-PWR
0R0603-PAD DY
PU5002

PC5010 22.71A<OCP< 26.84A
+0D75V_DDR_P SCD033U16V3KX-GP
+0D75V_DDR_P +0.75V_DDR_VTT +1.5V_SUS

PG5001 TPS51116_UGT
PL5001
2 1
TPS51116_ VBST1 1 2 TPS51116_ PHS 1 2
B B
GAP-CLOSE-PWR
PG5016 PC5019 IND-1D5UH-34-GP
2 1 SCD1U25V3KX-GP
PU5003 PU5004
GAP-CLOSE-PWR PR5012 PTC5002 PTC5001
DY 2D2R5F-2-GP
DY
DY
TPS51116_LGT TPS51116_PHS_SET
State S3 S5 VDDR VTTREF VTT DY PC5022

S0 Hi Hi On On On SC330P50V3KX-GP
S3 Lo Hi On On Off(Hi-Z) TPS51116_VDDQSNS
S4/S5 Lo Lo Off Off Off DY

PR5013 PC5023
30KR2F-GP SC18P50V2JN-1-GP
TPS51116_VDDQSET
VDDQSET VDDQ (V) VTTREF and VTT NOTE

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PR5014 Close to VFB Pin (pin5)
30KR2F-GP
GND 2.5 VVDDQSNS/2 DDR
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 220U 2V EEFCX0D221ER 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
A H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 <Core Design> A
V5IN 1.8 VVDDQSNS/2 DDR2 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
Switching freq-->400KHz Wistron Corporation
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
TPS51116_+1.5V_SUS
Custom
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p8v
D
APL5930 for +1.8V_RUN D
+3.3V_ALW +1.8V_RUN_VIN +5V_ALW +1.8V_RUN_VIN
PG5107 PC5109 PC5113

2 1 PC5110
SC1U10V2KX-1GP DY
GAP-CLOSE-PW R
PG5106
2 1
Design Current =1.23A +1.8V_RUN_P +1.8V_RUN
GAP-CLOSE-PW R
PU5101
RUNPW ROK 1 21.8V _RUN _POK 7 POK VIN#5 5

PR5113 0R2J-2-GP 9 +1.8V_RUN_P PG5105
VIN#9
1 2
PM_SLP_S3# 1 2 1D8V _ RUN _ EN 8 EN VOUT#3 3
PR5109 0R2J-2-GP 4 GAP-CLOSE-PW R
VOUT#4 PG5108
PR5111 PC5108 PC5111 PC5112 1 2
2
FB DY GAP-CLOSE-PW R
C APL5930KAI-TRG-GP C
SO-8-P
DY
Vout=0.8V*(R1+R2)/R2
PR5110
13K3R2F-L1-GP
B B
A <Core Design> A
Wistron Corporation
Title
APL5930 _ +1.8V _ RUN

A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = CPU.GFX.Regulator
+PW R_SRC +VGFXCORE_PW R_SRC
PG5301
1 2
GAP-CLOSE-PW R
+3.3V_ALW PG5303
UMA 1 2
1
GFX_VR_EN GAP-CLOSE-PW R
PR5310 0R2J-2-GP
PG5305
1 2
51611_VREFF
GAP-CLOSE-PW R
+5V_ALW 51611_VREFF PG5308
UMA 1 2
D D
1 2 GAP-CLOSE-PW R
PR5311 124KR2F-GP PG5311
1 2
1 GAP-CLOSE-PW R
51611_VREFF PC5313 SC2D2U10V3KX-1GP +3.3V_RUN
UMA UMA
1 2 PC5314
SC68P50V2JN-1GP
UMA UMA UMA DY DY DY
1
PR5312
2
1K69R2F-2-GP
UMA
PR5319
UMA DY
+VGFXCORE_PW R_SRC
UMA PC5315
SCD22U10V2KX-1GP
PC5302 PC5303
UMA UMA
DY PC5304
PU5301 SCD1U25V2KX-GP
+5V_ALW Design Current =17.6A

PU5302
1 24 SI7686DP-T1-GP 27.2<OCP<32.15A
GND CLKEN#
51611_ CSP 2 23
CSP PGOOD
51611_ CSN PC5301
UMA
3 CSN MODE 22
+CPU_GFX_CORE
Close to VGA
51611_ GSNS
51611_ VSNS
4
GNDSNS UMA V5IN
21 UMA
1
SC2D2U10V3KX-1GP
DY
5
VSNS TPS51611RHBR-GP DRVL
20 PL5301
51611_THERM_R 51611_THERM 51611_ PHASE
1
PR5320
DY2K R2F -3-2GP PR5321
1
NT
2
100K-10-GP
6
THERM LL
19
2D2R3J-2-GP PC5316
1
IND-D56UH-12-GP
2
51611_VR_TT 51611_ BOOT 6236A_ BOOT_ C PR5324

PM_EXTTS#0_C 1 7
VR_TT# VBST
18 1
PR5323 UMA
1
SCD22U16V3KX-2-GP
UMA PTC5301
C PR5322 DY 0R2J-2-GP C
GFX_IMON 51611_ UGATE PG5323
8
IMON DRVH
17 UMA DY
PG5322 DY DY DY UMA UMA SE330U2VDM-L-GP
PU5303 PU5304
PR5325 PC5317 74.51611.073
1 0KR2F-2-GP
DY DY SC3300P5 0V2KX-1GP DY
DYPC5318
UMA
PRN5301
GFX_DPRSLPVR 5 4 51611_DPRSLP_1
6 3 51611_VID6
GFX_VID6 51611_VID5
GFX_VID5
7 UMA 2
51611_VID4
8 1
GFX_VID4
SRN0J-7-GP 51611_ LGATE
PRN5302
5 4 51611_VID3
GFX_VID3 51611_VID2
6 3
GFX_VID2 51611_VID1
GFX_VID1
7 UMA 2
51611_VID0
8 1
GFX_VID0
SRN0J-7-GP
Close to choke (L5301)

PR5327 PR5328
51611_ CSP 1UMA 2 51611_ CSP_ R 1 2 51611_ CSP_ G
UMA
330R2F-GP 24K9R2F-L-GP
PR5326
PC5320 UMA
UMA SC33P50V2JN-3GP
NTC-100K-10-GP
B PC5321 PR5330 B
UMA SCD022U50V3KX-GP 51611_CSP_CSN UMA 154KR2F-GP
UMA PC5322
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L SC33P50V2JN-3GP
UMA PR5331
43K2R2F-L-GP
I0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 PR5332
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 51611_ CSN 1 2 51611_ CSN_ R
UMA
330R2F-GP
PC5323
UMA
2 1
SC1KP50V2KX-1GP
X01-0713 51611_ GSNS
UMA PC5324
1
PR5333 0R2J-2-GP +VCC_CORE
UMA SC1KP50V2KX-1GP
51611_ VSNS
PC5325
PR5334
UMA 100R2F-L1-GP-U 2
UMA
1
PG5324 SC1KP50V2KX-1GP
1 2
VCC_AXG_SENSE
GAP-CLOSE-PW R-3-GP
PG5325
1 2
VSS_AXG_SENSE
GAP-CLOSE-PW R-3-GP
A A
PR5335
UMA 100R2F-L1-GP-U
<Core Design>
Wistron Corporation
Title
TPS51611_+GFX_CORE(UMA)
A2
Berry X00
5 4 3 2 1
SSID = VIDEO +3.3V_RUN_VGA
SSID = Inverter
+3.3V_RUN
DY
+3.3V_RUN INVERTER POWER
LVDS CONNECTOR
3.3V _ LCD _ RUN 1 2
R5404 0R2J-2-GP
1 2
R5407 0R2J-2-GP R5401
GFX_PW R_SRC DY10KR2J-3-GP
LCD1
48 100R2J-2-GP
R5402 1 2 LBKLT_CTL
41 50
1 +LCDVDD
LCD _ BRIGHTNESS
2
3
4 C5402
+PW R_SRC
5 Change Poly-fuse
42 6 SC1U6D3V2KX-GP R5405
7 3.3V _ LCD _ RUN DY100KR2J-1-GP GFX_PW R_SRC
8 LCD_BRIGHTNESS
9 BLON_OUT_C F5401
10 LCD_CBL_DET#_C 2 1
11 LCD _ TST _ C
12 LVDSB_TX2 POLYSW -1D1A24V-GP
43 13 1 2 C5406 C5407
LVDSB_TX2#
14 LCD _ DET _ G R5408 100KR2J-1-GP SC1KP50V2KX-1GP SCD1U50V3KX-GP
15 LVDSB_TX1 RN5401
16 LVDSB_TX1# BLON _ OUT _ C 1 8 BLON_OUT Main:69.50007.A41
17 LCD _ CBL _ DET# _ C 2 7
18 LCD _ TST _ C 3 6
LCD_CBL_DET# Second:69.50007.A31
LVDSB_TX0 LCD_TST
19 LVDSB_TX0# LCD _ DET _ G 4 5
44 20
21 SRN100J-4-GP
LVDSB_TXC
22 LVDSB_TXC#
23
24 LVDSA_TXC
25 R5409
LVDSA_TXC#
26 1 2
45 27 LVDSA_TX2
28 0R3J-0-U-GP
LVDSA_TX2#
29 USB_PN13
30 LVDSA_TX1
31 LVDSA_TX1#
32
33 LVDSA_TX0
46 34 LVDSA_TX0#
35
36
GPU_LVDS_DATA
GPU_LVDS_CLK
DY L-112UH-1-GP-U
37
38 USB_CAMERA# TR5401
39 USB _ CAMERA
40 +3.3V_CAMERA
47
49
51
USB_PP13 SSID = VIDEO
R5411
1 2
+3.3V_RUN
LCD POWER
IPEX-CONN40-2R-GP-U
0R3J-0-U-GP
+LCDVDD
For Camera GND
Q5401
20.F1093.040 1 D D 6
2 D D 5
3 G S 4
Close to LVDS connector
+15V_ALW 1 2 SI3456DDV-T1-GE3-GP
R5412 330KR2J-L1-GP
LVDSB _ TXC# 1
C5409 SCD1U25V2KX-GP R5416
LVDSB _ TXC 150R3J-L-GP
Camera Power LVDSA _ TXC#
2 DY 1
100KR2J-1-GP
LCD _ BRIGHTNESS R5406 Q5402
+3.3V_RUN +3.3V_CAMERA LVDSA_TXC 4 3 LCDVDD_1
R5414
LCD_TST_C
1 2 EC5406 EC5407 EC5408 EC5409 5 2
DY DY DY DY
0R3J-0-U-GP 6 1
EC5405 C5403 DY DY 2N7002EDW -GP

SCD1U16V2KX-3GP DY SC10U6D3V5MX-3GP
84.27002.F3F
LCDVDD_EN
+5V_ALW 1 2
R5415 100KR2J-1-GP
For EMI request Q5403
3 OUT FPVCC _ CTL3
D5401 3 LCDVCC _ EN 2 R1
IN 1 GND
BAT54C-U-GP R2
DDTC144EUA-7F-GP
LCD_TST_EN <Core Design>
Wistron Corporation
Title
LCD/Inverter Connector
A3
Berry X00
5 4 3 2 1
LVDS Channel A Panel BL brightness/Power En/BL En

RN5501
PCH_LVDSA_TX2# 5 4 LVDSA_TX2#
6 3 RN5502
PCH_LVDSA_TX2 LVDSA_TX2
PCH_LVDSA_TXC# 7 2 LVDSA_TXC# 5 4
PCH_LVDSA_TXC 8 1 LVDSA_TXC 6 3 PANEL_BLEN
PCH_VGA_BLEN
SRN0J-7-GP PCH_LCDVDD_EN
7 UMA 2 LCDVDD_EN
UMA PCH_LBKLT_CTL
8 1 LBKLT_CTL
D Impedance:85 ohm D
RN5503
Impedance:90 ohm SRN0J-7-GP
GPU_LVDSA_TX2# 4 5
GPU_LVDSA_TX2 3 6
2 7 RN5504
GPU_LVDSA_TXC#
GPU_LVDSA_TXC 1 8 5 4
VGA_BLEN
6 3
VGA_LBKLT_CTL
DIS SRN0J-7-GP 7 DIS 2
VGA_LCDVDD_EN
Impedance:100 ohm 8 1
RN5507 SRN0J-7-GP
PCH_LVDSA_TX0 6 3 LVDSA_TX0
PCH_LVDSA_TX1 8 1 LVDSA_TX1
UMASRN0J-7-GP
Impedance:85 ohm
4
RN5508
5
Impedance:90 ohm
GPU_LVDSA_TX0# LVDSA_TX0#
GPU_LVDSA_TX0 3 6 LVDSA_TX0
GPU_LVDSA_TX1# 2 7 LVDSA_TX1#
GPU_LVDSA_TX1 1 8 LVDSA_TX1
DISSRN0J-7-GP
Impedance:100 ohm
C C
LVDS Channel B
RN5505
PCH_LVDSB_TXC# 5 4 LVDSB_TXC#
PCH_LVDSB_TXC 6 3 LVDSB_TXC
PCH_LVDSB_TX0# 7 2 LVDSB_TX0#
PCH_LVDSB_TX0 8 1 LVDSB_TX0
UMA SRN0J-7-GP
Impedance:85 ohm
Impedance:90 ohm
RN5510
GPU_LVDSB_TXC# 4 5 LVDSB_TXC#
GPU_LVDSB_TXC 3 6 LVDSB_TXC
GPU_LVDSB_TX0# 2 7 LVDSB_TX0#
GPU_LVDSB_TX0 1 8 LVDSB_TX0
DISSRN0J-7-GP
B
Impedance:100 ohm B
RN5509
UMASRN0J-7-GP
Impedance:85 ohm
Impedance:90 ohm
RN5506
DIS SRN0J-7-GP
Impedance:100 ohm
A A
<Core Design>
Wistron Corporation
Title
LVDS_Switch
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
LVDS _ Switch
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR

+3.3V_RUN
HDMI CONN +3.3V_RUN
HDMI1
22
20 UMA R5709
R5702 R5701 1 HDMI_DATA2 20KR2J-L2-GP
DY 4K7R2J-2-GP
+3.3V_RUN 4K7R2J-2-GP 2
DY 3 HDMI_DATA2# HDMI_OE#
HDMI_DATA1
Impedance:100 ohm 4
5
C5717 C5716 C5715 C5714 C5701 6 HDMI_DATA1#
UMA UMA UMA UMA UMA 7 HDMI_DATA0
D 8
9 HDMI_DATA0# UMA . Q5701
2N7002E-1-GP
D
10 HDMI_CLK .
11 . .
. 84.2N702.D31
12 HDMI_CLK#
U5701
Close to HDMI Connector 13
14
15 DDC_CLK_HDMI +5V_RUN
SRN0J-6-GP RN5703 16 DDC _DATA _HDMI HPD_ HDMI_ CON
38 23 HDMI_LS_ TXC# 1 4 HDMI_CLK# 17
HDMI_PCH_CLK# IN_D1- OUT_D1- HDMI_LS_ TXC HDMI_ CLK
39 22 2
HDMI_PCH_CLK IN_D1+ OUT_D1+ UMA 3
5704
18
19
41 20 HDMI_LS_ TX0# S RN0J-6-GP
1 HDMI_DATA0# 21
HDMI_PCH_DATA0# IN_D2- OUT_D2- HDMI_LS_ TX0 HDMI_ DATA0
42 19 2 3 C5705
HDMI_PCH_DATA0 IN_D2+ OUT_D2+ UMA RN5706
23
SCD1U16V2KX-3GP
44 17 HDMI_LS_ TX1# S RN0J-6-GP
1 4 HDMI_DATA1# SKT-HDMI19P-69-GP
HDMI_PCH_DATA1# IN_D3- OUT_D3- HDMI_LS_ TX1 HDMI_ DATA1
45 16 2 3
HDMI_PCH_DATA1 IN_D3+ OUT_D3+ UMA RN5707
HDMI_PCH_DATA2#
47
IN_D4- OUT_D4-
14 HDMI_LS_TX2# S RN0J-6-GP
1 4 HDMI_DATA2# 22.10296.211
+3.3V_RUN 48 13 HDMI_LS_ TX2 2 HDMI_ DATA2 +3.3V_RUN_VGA
UMA 3
HDMI_PCH_DATA2 IN_D4+
UMA OUT_D4+
R5703 2 UMA 1 4K7R2J-2-GP HDMI_PC0 3 8

PC0 SDA PCH_HDMI_DATA
R5704 2 1 4K7R2J-2-GP HDMI_PC1 4 9 DIS
DY PC1 SCL
7
PCH_HDMI_CLK
HDMI_PCH_DET 1 2
HDMI _HPD_B
1 Q5702
R5705 HPD R5711 150KR2J-L1-GP PMBS3904-1-GP
HDMI_REXT
DIS
2 UMA 1 6
REXT HPD _ HDMI_ CON R5707
499R2F-2-GP 10 30
R5706 HDMI_OE# 25
RT_EN# HPD_SINK
29 DDC _ DATA_ HDMI DY 20KR2J-L2-GP R5710
HDMI_HPD_DET
OE# SDA_SINK
4K7R2J-2-GP UMA +3.3V_RUN 2 HDMI_DDC_EN
1 UMA 4K7R2J-2-GP 32 28 DDC _ CLK_ HDMI
R5708
DDC_EN SCL_SINK 200KR2J-L1-GP
DY
R5712 DIS
10KR2J-3-GP
Change from 5.1K to 4.7K. PS8101-GP
1st Parade 71.P8101.003

2nd Pericom 71.03411.B03
C C
HDMI DISCRETE/ UMA Co-lay Impedance:100 ohm +3.3V_RUN_VGA +5V_RUN
Close to Level Shift Close to HDMI Connector

RN5702
RN5708 SRN0J-6-GP R N5701
HDMI_PCH _ CLK# 2 3 HDMI_ CLK#_ R C 5706 1DIS S CD1U16V2KX-3GP HDMI_ CLK# +3.3V_RUN_VGA SRN2K2J-1-GP SRN1K5J-GP
HDMI_PCH _ CLK 1 DIS 4 HDMI_ CLK_ R C 5707 1DIS S CD1U16V2KX-3GP HDMI_ CLK DY
HDMI_PCH _ DATA0# HDMI_ DATA0#_ R C 5708 HDMI_ DATA0# +5V_RUN
U5702 5V Tolerance
2 3 1DIS 2 S CD1U16V2KX-3GP
HDMI_PCH _ DATA0 1 DIS 4 HDMI_ DATA0_ R C 5709 1DIS S CD1U16V2KX-3GP HDMI_ DATA0 1 2 GPU_HDMI_CLK
1OE 1A
7 5 GPU_HDMI_DATA
RN5709 SRN0J-6-GP 2OE 2A
8
DY
RN5710 SRN0J-6-GP VCC DDC _CLK_ HDMI
3
HDMI_PCH_DATA1# HDMI_DATA1#_R HDMI_DATA1# 1B DDC_DATA_HDMI
2 3 C 5713 1DIS 2 S CD1U16V2KX-3GP 4 6
HDMI_PCH _ DATA1 1 DIS 4 HDMI_ DATA1_ R C 5710 1DIS S CD1U16V2KX-3GP HDMI_ DATA1 GND 2B
HDMI_PCH _ DATA2# 2 3 HDMI_ DATA2#_ R C 5711 1DIS 2 S CD1U16V2KX-3GP HDMI_ DATA2# TSCBTD3305CPW R-GP
HDMI_PCH _ DATA2 1 DIS 4 HDMI_ DATA2_ R C 5712 1DIS 2 S CD1U16V2KX-3GP HDMI_ DATA2
RN5711 SRN0J-6-GP
RN5705
GPU _HDMI_ CLK 2 3
DIS
Impedance:100 ohm Impedance:100 ohm GPU _HDMI_ DATA 1 4
SRN0J-6-GP
HDMI_PLL_GND
DIS . Q5703
2N7002E-1-GP
B
.
.
B
. . 84.2N702.D31
+5V_RUN
R5714
DY 100KR2J-1-GP
A A
<Core Design>
Wistron Corporation
Title
HDMI Level Shifter/Connector

A2
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
ITP Connector
H_CPURST# use pull-up Resistor close
D D
ITP connector 500 mil ( max ),
others place near CPU side.
CPU ITP Connector

TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C C
SSID = Thermal
Fan Connector
B B
3 1
*Layout* 15 mil
FAN1
5
EMC2102_FAN_TACH 3
AFTP5801 1 2
EMC2102_FAN_DRIVE 1
4
AFTP5802 1 EMC2102 _ FAN _ TACH
FOX-CON3-6-GP-U
AFTP5803 1 EMC2102 _FAN _ DRIVE
D5801
C5801 RB551V-30-2GP
SC10U6D3V5MX-3GP
20.D0210.103
A <Core Design> A
Wistron Corporation
Title
ITP/Fan Connector
A3
Berry X00
5 4 3 2 1
SSID = SATA
SATA HDD Connector
+3.3V_RUN
HDD1
C5904 C5901
SC10U6D3V5MX-3GP DY DY SCD1U16V2KX-3GP P1 16
V33 16
P2 17
V33 17
P3 V33 18 18
+5V_RUN P7 V5
P8 V5
P9 V5
C5905 C5906
SC10U6D3V5MX-3GP SCD1U16V2KX-3GP P13 S1
V12 GND
P14 V12 GND S4
P15 V12 GND S7
GND P4
GND P5
SATA_TXP0 S2 A+ GND P6
SATA_TXN0 S3 A- GND P10
GND P12
SATA_RXP0_C SCD01U50V2KX-1GP 1 C5903 SATA _ RXP0 S6
SCD01U50V2KX-1GP
B+
SATA_RXN0_C 1 2 C5902 SATA _ RXN0 S5 B- DAS/DSS P11
SKT-SATA7P-15P-17-GP
62.10065.C71
ODD Connector
ODD1
8
NP1
S1
S2 SATA_TXP1
S3 SATA_TXN1 SATA_RX- and SATA_RX+ Trace
S4
S5 SATA _ RX1- _ C SCD01U50V2KX-1GP 1 2 C5907 SATA_RXN1_C
Length match within 20 mil
S6 SATA _ RX1+ _ C SCD01U50V2KX-1GP 1 2 C5908 SATA_RXP1_C
S7
+5V_RUN
P1
P2
P3
P4
P5 C5909 C5910
P6 SCD1U10V2KX-4GP SC10U6D3V5MX-3GP
NP2
9
SKT-SATA7P+6P-42-GP
62.10065.581 <Core Design>
Wistron Corporation
Title
HDD/ODD
A3
Berry X00
5 4 3 2 1
SSID = AUDIO
Speaker LINE1
Connector OUT
D D
SPK1
FOX-C ON4-19-GP
BLM18BD601SN1D-GP
1 AUD _ HP1 _ JD#
AUD_SPK_L- AUD_HP1_JD#
L6001 LINEOUT1
2 AUD _ HP1 _ JACK _ L2 1 2 AUD _ HP1_ JACK_ L1 6
AUD_SPK_L+ AUD_HP1_JACK_L2
3 5
AUD_SPK_R- AUD _ HP1 _ JACK_ R2
4 1 2 AUD _ HP1_ JACK_ R1 2
AUD_SPK_R+ AUD_HP1_JACK_R2 L6002 BLM18BD601SN1D-GP
4
EC6005 EC6006 1
SC1KP50V2KX-1GP SC1KP50V2KX-1GP 3
DY DY DY DY 20.F0711.004 7
SEC. 20.F0693 .004 JACK_AGND JACK_AGND JACK_AGND JACK_AGND

8
PHONE-JK383-GP
1 1 AUD _ HP1 _ JD#

AFTP6002 AFTP6003 600ohm 100MHz
AFTP6001
AFTP6005
AFTP6007
1
1
AUD _ SPK _ L-
AUD _ SPK _ L+
AUD _ SPK _ R-
AFTP6004
1 AUD _ HP1 _ JACK_ L1
AUD _ HP1 _ JACK_ R1

200mA 0.5ohm DC AFTP6006 1 22.10133.K31
1 1
AFTP6009 1 AUD _ SPK _ R+ AFTP6008
C C
JACK_AGND
MIC IN Internal
AUD_VREFOUT_B Microphone
MIC1 is in DIP
RN6001
SRN4K7J-8-GP 1 MIC1
INT_MIC_L_R
MICROPHONE-40-GP-U1
MICIN1 EC6009
SC1KP50V2KX-1GP
23.42143.001
8
B B
7
3
1
2 1 MIC _IN _ L _ C 4
MIC_IN_L
R6001 0R3J-0-U-GP
2
5
1 2 MIC_IN_R_C 6
MIC_IN_R
R6002 0R3J-0-U-GP
PHONE-JK383-GP
EXT_MIC_JD#
22.10133.K31
EC6011
EC6010
SC100P50V2JN-3GP 1 AFTP6010
1 MIC _IN _ L _ C
AFTP6011
1 MIC _IN _ R _ C
AFTP6012
1 EXT _ MIC _ JD# JACK_AGND JACK_AGND
AFTP6013
Close Jack
A <Core Design> A
width 15mil DY
2 1 1 2
R6004 0R2J-2-GP R6003 0R3 J -0-U-GP Wistron Corporation
Title
AUD_AGND JACK_AGND
Audio Jack
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH
+3.3V_RUN
+3.3V_RUN
C6202
D C6201 DY SCD1U16V2KX-3GP D
RN6201 SC10U6D3V5MX-3GP
SRN4K7J-10-GP
PCH _ SPI_ HOLD _ 0#
+3.3V_RUN
U6201
PCH _ SPI_ CS0# 1 8

PCH_SPI_CS0# CS# VCC
1 2 PCH_SPI_DI_R 2 7 PCH_SPI_HOLD_0#
PCH_SPI_DI SO NC#7
PCH_SPI_W P# 3 6 PCH_SPI_CLK
R6202 WP# SCK
4 GND SI 5 PCH_SPI_DO
15R2J-GP
EC6202 DY MX25L3205DM2I-12G-GP
SC4D7P50V2CN-1GP EC6203 DY DY EC6204
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
C C
+KBC_PW R
SPI FLASH ROM (256K byte) for KBC

+KBC_PW R
C6203
RN6202 SC10U6D3V5MX-3GP
SRN100KJ-5-GP
DY
EC _ SPI_ HOLD#
U6202 +KBC_PW R
EC_SPI_CS# 1 8
R6205 CS# VCC
EC_SPI_DI 1 2 0R2J-2-GP EC _ SPI _ DI_ R 2 SO HOLD# 7 EC _ SPI_ HOLD#
R6206 1 2 0R2J-2-GP EC _ SPI _ W P# 3 6
EC_SPI_W P#_R W P# SCLK EC_SPI_CLK
4 GND SI 5 EC_SPI_DO
EC6201 R6208 MX25L2005C-12G-GP

B SC4D7P50V2CN-1GP DY DY 100KR2J-1-GP EC6205 DY DY EC6206 B
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
+3.3V_RTC_LDO
U6203
SSID = RBATT
+RTC_CELL
2
+RTC_VCC
3 RTC1
R6210
1 RTC _ PW R 1 2 1 PW R
2
C6205 1KR2J-1-GP GND
NP1 NP1
SC1U6D3V2KX-GP SDMG0340LC7F-GP-U NP2 NP2
1
AFTP6203
A Width=20mils BAT-CON2-1-GP-U <Core Design> A
62.70001.011
Wistron Corporation
1 +RTC _ VCC Taipei Hsien 221, Taiwan, R.O.C.
AFTP6202
Title
Flash/RTC
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = USB
Close to I/O connector
IO Board USB Power
Support 2A
+5V_ALW +5V_USB1
U6301
at least 80 mil
D at least 80 mil 1 GND VOUT 8 D
Main RT9715BGF P/N:74.09715.B79 2
3
VIN VOUT
7
6
VIN VOUT
SEC G547F2P81U P/N: 74.00547.A79 C6301
USB_PW R_EN#
4 EN# FLG#
5
C6302
DY SC1U10V2KX-1GP
RT9715BGF-GP
USB_OC#8_9
CRT Board USB Power Close to CRT Board connector
C
Support 2A C
+5V_ALW +5V_USB2
U6302
at least 80 mil
at least 80 mil 1 GND VOUT 8
2 VIN VOUT 7
3 6
VIN VOUT
4 5
USB_PW R_EN# EN# FLG# C6304
SC1U10V2KX-1GP
DY RT9715BGF-GP
USB_OC#0_1
B B
<Core Design>
A A
Wistron Corporation
Title
USB Power SW
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4 Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
Power LED(White)
+5V_ALW
Q6602
E
PW RLED# _ C B
D C LED _ PW R 1 2 PW R _ LED _ B D
R6601 220R2J-L2-GP
EC6601
PDTA143ET-GP
1 2 POW ER _SW _ LED _ B
1
RN6601
4 W HITE_LED_BAT# DYSC220P50V2KX-3GP R6603 100R2J-2-GP
W HITE_LED#_KBC
2 3 SATA _ LED# _ C 84.00143.M11
SATA_LED#
SRN15KJ-3-GP
SATA HDD LED(White)

RN6602
1 4 AMBER_LED_BAT#
AMBER_LED#_KBC
2 3 PW RLED# _ C
PW RLED#
SRN15KJ-3-GP +5V_RUN
Q6601
E
SATA _ LED# _ C B R6604
C SATA _ LED _ R 2 1 SATA _ LED
330R2J-3-GP
PDTA143ET-GP
EC6604
DY SC220P50V2KX-3GP
84.00143.M11
C Battery LED1(White) C
+5V_ALW
Q6603
E LEDBD1
W HITE _ LED _ BAT# B R6602 7
C W HITE _ LED _ BAT 2 1 BAT _ W HITE
PW R _ LED _ B 1
330R2J-3-GP
PDTA143ET-GP
EC6602 SATA _ LED 2
DY SC220P50V2KX-3GP BAT _ W HITE
84.00143.M11 BAT_AMBER
3
4
5
6
Battery LED2(Amber)
8
ACES-CON6-13-GP
+5V_ALW
Q6604
E
AMBER _ LED _ BAT# B R6606
C AMBER _ LED _ BAT 1 2 BAT _ AMBER
330R2J-3-GP
PDTA143ET-GP
EC6603
B 84.00143.M11 DY SC220P50V2KX-3GP B
Power button LED(White)

1 2 PW RBTN1
KBC_PW RBTN#
R6605 100R2J-2-GP 5
KBC _ PW RBTN# _ C 2
+5V_ALW 3
POW ER _SW _ LED _ B 4
Q6605
6
E
1 2 PW R _ BTN _ LED# _ C B
PW R_BTN_LED#
R6607 15KR2J-1-GP C POW ER _SW _ LED _ R 1 DY 2 POW ER _ SW _ LED_ B ACES-CON4-10-GP-U
R6608 100R2J-2-GP
A
PDTA143ET-GP
20.K0320.004 <Core Design> A
84.00143.M11 Wistron Corporation

Title
LED Bard/Power Button

A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
D
Internal KeyBoard Connector TouchPad Connector
D
KB1 1 AFTP6801
31
1 KB_DET#
2 KROW 7 1
3 KROW 6 1 AFTP6802
4 KROW 4 1 AFTP6803 +5V_RUN
5 KROW 2 1 AFTP6804
6 KROW 5 1 AFTP6805 +5V_RUN
7 KROW 1 1 AFTP6806
8 KROW 3 1 AFTP6807
9 KROW 0 1 AFTP6808
10 KCOL5 1 AFTP6809
11 KCOL4 1 AFTP6810
12 KCOL7 1 AFTP6811 KROW [0..7] RN6801
13 KCOL6 1 AFTP6812 SRN10KJ-5-GP
14 KCOL8 1 AFTP6813
15 KCOL3 1 AFTP6814 TPAD1
KCOL[0..16]
16 KCOL1 1 AFTP6815 6
17 KCOL2 1 AFTP6816
18 KCOL0 1 AFTP6817 4
19 KCOL12 1 AFTP6818 3
TPCLK
C 20 KCOL16 1 AFTP6819 2 C
TPDATA
21 KCOL15 1 AFTP6821
22 KCOL13 1 AFTP6823 1
23 KCOL14 1 AFTP6822
24 KCOL9 1 AFTP6824 C6802 DY DY C6803 5
25 KCOL11 1 AFTP6825 SC33P50V2JN-3GP SC33P50V2JN-3GP
26 KCOL10 1 AFTP6826 1 ACES-CON4-10-GP-U
27 AFTP6827 AFTP6820
28
29
20.K0320.004
30 1
32 AFTP6828
1 +5V_RUN
ACES-CON30-3-GP AFTP6829 1 TPCLK
AFTP6830 1 TPDATA
AFTP6831
20.K0421.030
Sec. 20.K0259.030
B B
A <Core Design> A
Wistron Corporation
Title
Key Board/Touch Pad

A3
Berry X00
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
AFTP6901 1 +3.3V _ ALW
AFTP6902 1 LID _ CLOSE# _ 1
D D
C6903
+3.3V_ALW SCD1U6D3V2KX-GP
R6901 HALLSW1
DY 100KR2J-1-GP
2
VDD
1
LID_CLOSE# LID _ CLOSE# _ 1 VSS
LID_CLOSE# 2 1 3
R6902 OUT
0R2J-2-GP
C6902 S-5711ACDL-M3T1S-GP
DY SCD047U16V2KX-1-GP
AFTP6903 1
C C
B B
<Core Design>
A
Title
Hall Sensor
A4
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
DB1
1
2
LPC_LAD0
3
LPC_LAD1
4
LPC_LAD2
5
LPC_LAD3
LPC_LFRAME#
6
7
DY
PLT_RST#
8
9
PCLK_FWH
10
11
12
C MLX-CON10-7-GP C
20.D0183.110
B B
<Core Design>
A
Title
Dubug connector
A4
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Size
RESERVED
Document Number Rev
A4 Berry X00
5 4 3 2 1
5 4 2 1
BDBIOS.COM
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
RESERVED
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D Bluetooth Module conn. D
BT1
15
NP1
AFTP7301 1 BLUETOOTH _ DET# 1 2 BT _ ACT +3.3V_RUN
W LAN _ ACT 3 4
AFTP7302 1 BDC _ ON 5 6 USB _ PP5
BLUETOOTH _ EN 7 8 USB _ PN5
AFTP7304 1 BT _ LED 9 10
AFTP7305 1 BLUETOOTH _ GPIO3 11 12 C7301
AFTP7314 1 BLUETOOTH _ GPIO5 13 14 SC2D2U10V3KX-1GP
NP2
16
1 AFTP7313
HRS-CONN14D-GP
20.F0987.014
USB_PP5 AFTP7316 1 W LAN _ ACT

USB_PN5 AFTP7317 1 BLUETOOTH _ EN
BT _ ACT AFTP7315 1 BT _ ACT
BT_ACT
BLUETOOTH_EN BLUETOOTH _ EN AFTP7318 1 +3.3V _ RUN
W LAN _ ACT AFTP7319 1 USB _ PP5
W LAN_ACT
AFTP7320 1 USB _ PN5
C C
DY DY
B B
A <Core Design> A
Wistron Corporation
Title
Bluetooth
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Reserved
A4
Berry X00
5 4 3 2 1
5 4 3 2 1
IO Board CONN 80 pin
IOBD1
85 NP1
86 84
USB(ESATA) USB_PP9 2 1 SATA_TXN4

SATA(ESATA)
D D
USB_PN9 4 3 SATA_TXP4
6 5
WWAN USB SATA(ESATA)

USB_PP11 8 7 SATA_RXN4_C
USB_PN11 10 9 SATA_RXP4_C
12 11
USB1 USB_PN8 14 13
PCIE_TXP2
USB_PP8 16
18
15
17
PCIE_TXN2 WLAN PCIE
WLAN USB WLAN PCIE
USB_PP2 20 19 PCIE_RXP2
USB_PN2 22 21 PCIE_RXN2
24 23
E51_RXD 26 25 CLK_PCIE_W LAN
WLAN CLK
E51_TXD 28 27 CLK_PCIE_W LAN#
30 29
WWAN PCIE PCIE_RXP4 32 31 CLK_PCIE_LAN

LAN CLK
PCIE_RXN4 34 33 CLK_PCIE_LAN#
36 35
WWAN PCIE
PCIE_TXP4 38 37 CLK_PCIE_W W AN
WWAN CLK
PCIE_TXN4 40 39 CLK_PCIE_W W AN#
42 41
WWAN/WLAN SMBUS PCH_SMBDATA 44 43

PCH_SMBCLK 46 45 at least 80 mil
48 47 +5V_USB1
+DC_IN_SS 50 49 +5V_ALW
52 51
54 53 +3.3V_RUN
56 55
58 57
C 60 59 C
W IFI_RF_EN 62 61 +3.3V_ALW
W W AN_CLKREQ# 64 63 +1.5V_RUN
W W AN_RADIO_DIS# 66 65 AD_OFF
PSID_DISABLE# 68 67 PM_LAN_ENABLE
70 69 PLT_RST#
LAN PCIE PCIE_RXP3 72 71 W LAN_CLKREQ#

PCIE_RXN3 74 73 PCIE_W AKE#
76 75 BT_ACT
LAN PCIE
PCIE_TXP3 78 77 W LAN_ACT
PCIE_TXN3 80 79 PSID_EC
83 81
82 NP2
ACES-CONN80D-GP
20.F1009.080
B B
A <Core Design> A
Wistron Corporation
Title
Document Number
IO Board Connector
Size Rev
A3 Berry X00
5 4 3 2 1
5 4 3 2 1
CRT Board Connector

CRTBD1
21
1
at least 80 mil
2 +5V_USB2
3
4 +5V_RUN
5
USB3 PORT
6 USB_PN1
7 USB_PP1
8
USB2 PORT
9 USB_PN0
10 USB_PP0
11
D 12 CRT_RED D
CRT RGB
13 CRT_GREEN
14 CRT_BLUE
CRT H/VSYNC
15 CRT_HSYNC_CON
16 CRT _VSYNC _ CON
CRT SMBUS
17 CRT_DDCCLK_CON
18 CRT_DDCDATA_ CON
19
20
22
ACES-CON20-1-GP-U
20.F0772.020
SEC. 20.F1035.020
CRT RGB CRT Hsync & Vsync level shift Close to CRT Board CONN
Close to CRT Board CONN
Filter design on CRT Board
RN7706
RN7701 2 3
1 8 1 4
VGA_CRT_RED
2
3
7
6
CRT_RED
CRT_GREEN 3.3V Tolerance RN7703
SRN0J-6-GP SRN0J-6-GP RN7705
VGA_CRT_GREEN
4
DIS 5 CRT_BLUE
VGA_CRT_HSYNC 1 4 CRT_HSYNC _ IN CRT_ HSYNC_ OUT 4 1 CRT_ HSYNC_ CON
VGA_CRT_BLUE CRT_VSYNC _ OUT CRT_ VSYNC_ CON
2 3 3
SRN0J-7-GP
VGA_CRT_VSYNC DIS DY 2
SRN33J-5-GP-U
2
RN7702
PCH_CRT_HSYNC
PCH_CRT_VSYNC 1 UMA 4 CRT _VSYNC _IN +5V_RUN
1 8
PCH_CRT_RED
2
3
7
6
2.5V Tolerance? RN7704
SRN0J-6-GP
PCH_CRT_GREEN
4
UMA 5
C
PCH_CRT_BLUE DY C7702 C
U7701 SCD1U16V2KX-3GP
SRN0J-7-GP
TC7W T125FU-GP
DY
CRT DDCDATA & DDCCLK level shift

+3.3V_RUN
Pull High 5V Design on CRT Board
RN7707 +3.3V_RUN
UMA SRN2K2J-1-GP
Need Level Shift

Q7701
4 3 CRT _DDCDATA_ CON
PCH_CRT_DDCDATA
5 2
UMA
PCH_CRT_DDCCLK
6 1
2N7002EDW -GP
5V Tolerance 84. 27002. F3F
RN7709
2 3
VGA_CRT_DDCDATA
1 DIS 4 CRT_DDCCLK_CON
VGA_CRT_DDCCLK
SRN0J-6-GP
B B
A A
<Core Design>
Wistron Corporation
Title
CRT Board Connector

A2
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
Card Reader connector
+3.3V_RUN
CARDBD1
7
C 1 C
2
CLK_48M_CARD
3
USB_PN4 4
USB_PP4 5
6
8
MLX-CON6-21-GP
20.F1035.006
B B
<Core Design>
A
Title
CARD Reader CONN

A4
Berry X00
5 4 3 2 1
5 4 3 2 1
H1 H2 H3 H4 H5 H6 H7 H8 H9
HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP
D D
H10 CPU Thermal module hole GPU Thermal module hole

HOLE335R115-GP
HTML1 HTML2 HTML3 stand off
HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP HGPU1
STF237R117H83-1-GP HBT1
STF237R115H123-GP
C C
DY DY DY
EMI Reserve
+PWR_SRC +VGFXCORE_PWR_SRC
+PWR_SRC_VTT +PWR_SRC_1D5V
EC7901 EC7902 EC7904 EC7903 EC7905 EC7907 EC7909 EC7906

EC7911 EC7916
DY DY DY DY DY DY DY DY
B
DY DY B
EMI Reserve
SPR1
<Core Design>
SPRING-58-GP
A
DY Wistron Corporation A
Title
UNUSED PARTS/EMI Capacitors

A4
Berry X00
5 4 3 2 1
5 4 3 2 1
PEG_TXP[0..15] PEG_RXP[0..15]
VGA1A 1 OF 8
PEG_TXN[0..15] PEG_RXN[0..15]
CONFIGURATION STRAPS RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, 1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
DIS
PEG _ TXP0 AA38
PCIE_RX0P PCIE_TX0P
Y33 PEG _ C _ RXP0 C8001 1 2 SCD1U16V2KX-3GP PEG _ RXP0 PLATFORM
PEG _ TXN0 Y37 Y32 PEG _ C _ RXN0 C8002 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN0 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
PCIE_RX0N PCIE_TX0N SETTING
DIS Transmitter Power Savings Enable
PEG _ TXP1 Y35 W 33 PEG _ C _ RXP1 C8003 1 2 SCD1U16V2KX-3GP PEG _ RXP1 TX_PWRS_ENB GPIO0 X 1
D
PEG _ TXN1 PCIE_RX1P PCIE_TX1P 0: 50% Tx output swing 1: Full Tx output swing D
W 36 W 32 PEG _ C _ RXN1 C8004 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN1
PCIE_RX1N PCIE_TX1N
PCIE TRANSMITTER DE-EMPHASIS ENABLED
DIS TX_DEEMPH_EN GPIO1 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled X 1
PEG _ TXP2 W 38 U33 PEG _ C _ RXP2 C8005 1 SCD1U16V2KX-3GP PEG _ RXP2
PCIE_RX2P PCIE_TX2P
PEG _ TXN2 V37 PCIE_RX2N PCIE_TX2N U32 PEG _ C _ RXN2 C8006 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN2 0:Advertises the PCIe device as 2.5GT/s capable at power on.
BIF_GEN2_EN_A GPIO2 1:Advertises the PCIe device as 5.0GT/s capable at power on. 0 0
DIS
PEG _ TXP3 V35 U30 PEG _ C _ RXP3 C8008 1 2 SCD1U16V2KX-3GP PEG _ RXP3 optional input allow the system to request a fast
PEG _ TXN3 PCIE_RX3P PCIE_TX3P PEG _ C _ RXN3 C8007 1D
U36 PCIE_RX3N PCIE_TX3N U29 IS 2 SCD1U16V2KX-3GP PEG _ RXN3 GPIO5_AC_BATT GPIO5 ? 0
power reduction by setting GPIO5 to low.
DIS
PEG _ TXP4 U38 T33 PEG _ C _ RXP4 C8009 1 SCD1U16V2KX-3GP PEG _ RXP4 RESERVED GPIO8 RESERVED 0 0
PEG _ TXN4
PCIE_RX4P PCIE_TX4P PEG _ C _ RXN4 C8010 1D
T37 PCIE_RX4N PCIE_TX4N T32 IS 2 SCD1U16V2KX-3GP PEG _ RXN4
0:VGA Controller capacity enabled
DIS VGA_DIS GPIO9 1:The device won't be recognized as the system's VGA controller 0 0
PEG_TXP5 T35 T30 PEG_C_RXP5 C8011 1 SCD1U16V2KX-3GP PEG_RXP5
PCIE_RX5P PCIE_TX5P
PEG _ TXN5 R36 PCIE_RX5N PCIE_TX5N T29 PEG _ C _ RXN5 C8012 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN5 BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
ROMIDCFG[2:0] GPIO[13:11] BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
(256MB)
DIS
PEG _ TXP6 R38 P33 PEG _ C _ RXP6 C8013 1 2 SCD1U16V2KX-3GP PEG _ RXP6
PEG _ TXN6 PCIE_RX6P PCIE_TX6P PEG _ C _ RXN6 C8014 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN6
P37 PCIE_RX6N PCIE_TX6N P32 RESERVED GPIO21 RESERVED 0 0
DIS 0:Disable external BIOS ROM device
PEG _ TXP7 P35 PCIE_RX7P PCIE_TX7P P30 PEG _ C _ RXP7 C8016 1 2 SCD1U16V2KX-3GP PEG _ RXP7 BIOS_ROM_EN GPIO_22_ROMCSB 1:Enable external BIOS ROM device X 0
PEG _ TXN7 N36 P29 PEG _ C _ RXN7 C8015 1D IS 2 SCD1U16V2KX-3GP PEG _ RXN7
PCIE_RX7N PCIE_TX7N
VIP Device Strap Enable indicates to the software driver that it sense
DIS VIP_DEVICE_STRAP_EN V2SYNC X 0
PEG _ C _ RXP8 C8018 1
whether or not a VIP device is connected on the VIP Host interface.
PEG _ TXP8 N38 PCIE_RX8P PCIE_TX8P N33 2 SCD1U16V2KX-3GP PEG _ RXP8
C PEG _ TXN8 M37 N32 PEG _ C _ RXN8 C8017 1D 2 SCD1U16V2KX-3GP PEG _ RXN8 C
PCIE_RX8N PCIE_TX8N IS
RSVD H2SYNC RESERVED 0 0
DIS
PEG _ TXP9 M35 N30 PEG _ C _ RXP9 C8020 1 SCD1U16V2KX-3GP PEG _ RXP9
PEG _ TXN9
PCIE_RX9P PCIE_TX9P PEG _ C _ RXN9 C8019 1D
L36 PCIE_RX9N PCIE_TX9N N29 IS 2 SCD1U16V2KX-3GP PEG _ RXN9 RSVD GENERICC RESERVED 0 0
DIS
PEG _ TXP10 L38 L33 PEG_C_RXP10 C8021 1 SCD1U16V2KX-3GP PEG_RXP10 AUD[1] HSYNC X 1
PEG _ TXN10 PCIE_RX10P PCIE_TX10P PEG_C_RXN10 C8022 1DIS 2 SCD1U16V2KX-3GP PEG_RXN10
K37 PCIE_RX10N PCIE_TX10N L32 AUD[1:0]:11-Audio for both DisplayPort and HDMI
DIS AUD[0] VSYNC X 1
PEG_TXP11 K35 L30 PEG_C_RXP11 C8023 1 SCD1U16V2KX-3GP PEG_RXP11
PEG_TXN11 PCIE_RX11P PCIE_TX11P PEG_C_RXN11 C8024 1DIS 2 SCD1U16V2KX-3GP PEG_RXN11
J36 PCIE_RX11N PCIE_TX11N L29
DIS
PEG _ TXP12 J38 K33 PEG_C_RXP12 C8025 1 SCD1U16V2KX-3GP PEG_RXP12
H37 PCIE_RX12N PCIE_TX12N K32
+3.3V_RUN_VGA
DIS PIN STRAPS
PEG _ TXP13 H35 J33 PEG_C_RXP13 C8028 1 2 SCD1U16V2KX-3GP PEG_RXP13
G36 J32
PCIE_RX13N PCIE_TX13N
TX_PW RS_ENB
R8001 1
DY 2 3KR2J-2-GP
DIS DY
PEG _ TXP14 G38 K30 PEG_C_RXP14 C8030 1 2 SCD1U16V2KX-3GP PEG_RXP14 R8002 1 2 3KR2J-2-GP
PCIE_RX14P PCIE_TX14P TX_DEEMPH_EN
PEG _ TXN14 F37 K29 PEG_C_RXN14 C8029 1DIS 2 SCD1U16V2KX-3GP PEG_RXN14
PCIE_RX14N PCIE_TX14N
BIF_GEN2_EN_A
R8003 1
DY 2 10KR2J-3-GP
DIS DY
PEG _ TXP15 F35 H33 PEG_C_RXP15 C8032 1 SCD1U16V2KX-3GP PEG_RXP15 R8004 1 2 10KR2J-3-GP
PCIE_RX15P PCIE_TX15P GPIO8_ROMSO
PEG _ TXN15 E37 H32 PEG_C_RXN15 C8031 1DIS 2 SCD1U16V2KX-3GP PEG_RXN15
B PCIE_RX15N PCIE_TX15N
VGA_DIS
R8005 1
DY 2 10KR2J-3-GP B
CLOCK
CONFIG0
R8006 1
DIS 2 10KR2J-3-GP
CLK_PCIE_VGA AB35
AA36
PCIE_REFCLKP
CONFIG1
R8007 1
DY 2 10KR2J-3-GP
CLK_PCIE_VGA# PCIE_REFCLKN
CONFIG2
R8008 1
DY 2 10KR2J-3-GP
CALIBRATION R8017 DIS +1.0V_RUN_VGA
Y30 PCIE _ CALRP 1 2 R8009 1 2 10KR2J-3-GP
DIS
AJ21
AK21
NC#AJ21 PCIE_CALRP 1K27R2F-L-GP
VGA_CRT_VSYNC DIS
PW RGOOD NC#AK21
1 2 AH16 Y29 PCIE _ CALRN 1 2 R8010 1 2 10KR2J-3-GP
R8018 10KR2F-2-GP
PW RGOOD PCIE_CALRN R8019 2KR2F-3-GP
VGA_CRT_HSYNC DIS
DIS
1 R8020 2VGA_RST# AA30
PLT_RST#
0R2J-2-GP DY
PERST# R8012 1
DY 2 10KR2J-3-GP
VSYNC_DAC2
MADISON-PRO-2-GP R8013 1
DY 2 10KR2J-3-GP
HSYNC_DAC2
DY
DIS
DIS BIOS_ROM_EN
R8014
R8015
1
DY
2 10KR2J-3-GP
10KR2J-3-GP
PLTRST_DELAY#
1 2 GPIO5_AC_BATT 1 2
R8021 0R2J-2-GP
GPIO21_BB_EN
R8016 1
DY 2 10KR2J-3-GP
A <Core Design> A
Wistron Corporation
Title
GPU _ PCIE/STRAPPING(1/5)
A3 Berry X00
5 4 3 2 1
5 4 3 2 1
VGA1C 3 OF 8 VGA1D 4 OF 8
DDR2 DDR2 DDR2 DDR2
MDA[0..31] MDB[0..31]
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
MDA0 C37 G24 MDB0 C5 P8
DQA0_0/DQA_0 MAA0_0/MAA_0 MAA0 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB0
MDA1 C35 J23 MDB1 C3 T9
MDA2 A35 H24 MDB2 E3 P9
MDA3 E34 J24 MDB3 E1 N7
MDA4 G32 H26 MDB4 F1 N8
MDA5 D33 J26 MDB5 F3 N9
MDA6 F32 H21 MDB6 F5 U9
MDA7 E32 G21 MDB7 G4 U8
MDA8 D31 H19 MDB8 H5 Y9
D DQA0_8/DQA_8 MAA1_0/MAA_8 MAA8 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB8 D
MDA9 F30 H20 MDB9 H6 W9
MDA10 C30 L13 MDB10 J4 AC8
MDA11 A30 G16 MDB11 K6 AC9
MDA12 F28 J16 MDB12 K5 AA7
MDA13 C28 H16 MDB13 L4 AA8
DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 A_BA2 DQB0_13/DQB_13 MAB1_5/BA2 B_BA2
MDA14 A28 J17 MDB14 M6 Y8
DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 A_BA0 DQB0_14/DQB_14 MAB1_6/BA0 B_BA0
MDA15 E28 H17 MDB15 M1 AA9
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 A_BA1 DQB0_15/DQB_15 MAB1_7/BA1 B_BA1
MDA16 D27 MDB16 M3
MDA17 DQA0_16/DQA_16 MDB17 DQB0_16/DQB_16
F26 A32 DQMA0 M5 H3 DQMB0
DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQB0_17/DQB_17 WCKB0_0/DQMB_0
MDA18 C26 C32 MDB18 N4 H1
DQA0_18/DQA_18 WCKA0#_0/DQMA_1 DQMA1 DQB0_18/DQB_18 WCKB0#_0/DQMB_1 DQMB1
MDA19 A26 D23 MDB19 P6 T3
DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQMA2 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB2
MDA20 F24 E22 MDB20 P5 T5
MDA21 C24 C14 MDB21 R4 AE4
MDA22 A24 A14 MDB22 T6 AF5
MDA23 E24 E10 MDB23 T1 AK6
MDA24 C22 D9 MDB24 U4 AK5
MDA25 A22 MDB25 V6
MDA26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 MDB26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
F22 C34 QSAP_0 V1 F6 QSBP_0
MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0
D21 D29 QSAP_1 V3 K3 QSBP_1
DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1
MDA28 A20 D25 MDB28 Y6 P3
DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 QSAP_2 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSBP_2
MDA29 F20 E20 MDB29 Y1 V5
MDA30 D19 E16 MDB30 Y3 AB5
MDA31 E18 E12 MDB31 Y5 AH1
MDA[32..63] DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 QSAP_5 MDB[32..63] DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 QSBP_5
MDA32 C18 J10 MDB32 AA4 AJ9
MDA33 A18 D7 MDB33 AB6 AM5
MDA34 F18 MDB34 AB1
D17 A34 QSAN_0 AB3 G7 QSBN_0
DQA1_3/DQA_35 DDBIA0_0/QSA_0#/WDQSA_0 DQB1_3/DQB_35 DDBIB0_0/QSB_0#/WDQSB_0
MDA36 A16 E30 MDB36 AD6 K1
DQA1_4/DQA_36 DDBIA0_1/QSA_1#/WDQSA_1 QSAN_1 DQB1_4/DQB_36 DDBIB0_1/QSB_1#/WDQSB_1 QSBN_1
MDA37 F16 E26 MDB37 AD1 P1
MDA38 D15 C20 MDB38 AD3 W4
MDA39 E14 C16 MDB39 AD5 AC4
MDA40 F14 C12 MDB40 AF1 AH3
MDA41 D13 J11 MDB41 AF3 AJ8
MDA42 F12 F8 MDB42 AF6 AM3
MDA43 A12 MDB43 AG4
D11 J21 AH5 T7
MDA45 DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA0 MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB0
F10 G19 AH6 W7
DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1
C MDA46 A10 MDB46 AJ4 C
C10 H27 AK3 L9
DQA1_15/DQA_47 CLKA0 CLKA0 DQB1_15/DQB_47 CLKB0 CLKB0
MDA48 G13 G27 MDB48 AF8 L8
MDA49 DQA1_16/DQA_48 CLKA0# CLKA0# MDB49 DQB1_16/DQB_48 CLKB0# CLKB0#
H13 AF9
J13 J14 AG8 AD8
DQA1_18/DQA_50 CLKA1 CLKA1 DQB1_18/DQB_50 CLKB1 CLKB1
MDA51 H11 H14 MDB51 AG7 AD7
MDA52 DQA1_19/DQA_51 CLKA1# CLKA1# MDB52 DQB1_19/DQB_51 CLKB1# CLKB1#
G10 AK9
DQA1_20/DQA_52 DQB1_20/DQB_52
MDA53 G8 K23 MDB53 AL7 T10
MDA54 DQA1_21/DQA_53 RASA0# RASA0# MDB54 DQB1_21/DQB_53 RASB0# RASB0#
K9 K19 AM8 Y10
MDA55 DQA1_22/DQA_54 RASA1# RASA1# MDB55 DQB1_22/DQB_54 RASB1# RASB1#
K10 AM7
DQA1_23/DQA_55 DQB1_23/DQB_55
MDA56 G9 K20 MDB56 AK1 W 10
MDA57 DQA1_24/DQA_56 CASA0# CASA0# MDB57 DQB1_24/DQB_56 CASB0# CASB0#
A8 K17 AL4 AA10
DQA1_25/DQA_57 CASA1# CASA1# DQB1_25/DQB_57 CASB1# CASB1#
MDA58 C8 MDB58 AM6
E8 K24 AM1 P10
DQA1_27/DQA_59 CSA0#_0 CSA0#_0 DQB1_27/DQB_59 CSB0#_0 CSB0#_0
MDA60
MDA61
A6
DQA1_28/DQA_60 CSA0#_1
K27 Reserved for JTAG MDB60
MDB61
AN4
DQB1_28/DQB_60 CSB0#_1
L10
C6 AP3
E6 M13 AP1 AD10
DQA1_30/DQA_62 CSA1#_0 CSA1#_0 DQB1_30/DQB_62 CSB1#_0 CSB1#_0
MDA63 A5 K16 MDB63 AP5 AC10
DQA1_31/DQA_63 CSA1#_1 +3.3V_RUN_VGA DQB1_31/DQB_63 CSB1#_1
MVREFDA L18 K21 U10
MVREFDA CKEA0 CKEA0 CKEB0 CKEB0
MVREFSA L20 J20 MVREFDB Y12 AA11
MVREFSA CKEA1 CKEA1 MVREFSB MVREFDB CKEB1 CKEB1 +1.5V_RUN
AA12
MVREFSB
MEM _CALRN0 L27 K26 R8121 N10
MEM_CALRN0 WEA0# WEA0# WEB0# WEB0#
MEM _CALRN1 N12
MEM_CALRN1 WEA1#
L15
WEA1# DIS 10KR2J -3-GP
WEB1#
AB11
WEB1#
MEM _CALRN2 AG12
MEM_CALRN2 R_MEM_3
MEM _CALRP1 M12
MEM_CALRP1 MAA0_8
H23 MAA13
TEST _ EN AD28
TESTEN MAB0_8
T8 MAB13 DY R8102
2K2R2J-2-GP
MEM _CALRP0 M27 J19 W8
MEM_CALRP0 MAA1_8 MAB1_8
+1.5V_RUN
MEM _CALRP2 AH12
MEM_CALRP2
TP8101
1
TPAD14-GP
CLKTESTA AK10
CLKTESTB AL10
CLKTESTA DRAM _ RST
R_MEM_2 DIS
1 AH11 1 MEM_RST
CLKTESTB DRAM_RST#
DIS R8122 DY TP8102 TPAD14-GP R8103 680R2J-3-GP
1
243R2F-2-GP
2 MEM_CALRN0
R8104
10KR2J-3-GP
R8105
R_MEM_1 C_MEM
DIS MEM _CALRN1
10KR2J-3-GP DIS DIS C8103
SC68P50V2JN-1GP
1 2
243R2F-2-GP R8106 MADISON-PRO-2-GP
1
DIS
2 MEM_CALRN2
MADISON-PRO-2-GP
DIS
B
243R2F-2-GP
DIS
R8107
MEM
DIS For new version
B
R8110 1 2 _CALRP1
243R2F-2-GP
DIS MEM
_CALRP0
** This basic topology should be used for DRAM_RST for
R8111 1 2 DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
243R2F-2-GP
are an example only. The Series R and || Cap values
DIS MEM_CALRP2 will depend on the DRAM load and will have to be
R8112 1 2
243R2F-2-GP calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
+1.5V_RUN +1.5V_RUN +1.5V_RUN +1.5V_RUN
Designator For M97-M2 For Mannhatton
Ra R8113 Ra R8114 R8115 R8116

40D2R2F-GP
Madison 40D2R2F-GP
Ra 40D2R2F-GP
Ra 40D2R2F-GP R_MEM_1 10K 10K
Madison DIS DIS
MVREFDA MVREFSA MVREFDB MVREFSB R_MEM_2 0R/Short 680R
Mad ison Madi sonC8105 C8106 DIS
R8117 C8104 R8118 R8119 SCD1U10V2KX-4GP R8120 C8107 R_MEM_3 DNI DNI
Rb 100R2F-L1-GP-U
Rb 100R2F-L1-GP-U Rb 100R2F-L1-GP -U
Rb 100R2F-L1-GP-U
Madison Madison SCD1U10V2KX-4GP DIS DIS DIS SCD1U10V2KX-4GP
SCD1U10V2KX-4GP C_MEM 2.2nF 68pF
DDR3/GDDR3 Memory Stuff Option

A A
GDDR5 GDDR3 DDR3
MVDDQ 1.5V 1.8V/1.5V 1.5V <Core Design>
Ra 40.2R 40.2R 40.2R Wistron Corporation

Rb 100R 100R 100R Taipei Hsien 221, Taiwan, R.O.C.
Title
GPU Memory(2/5)
C Berry X00
5 4 3 2 1
5 4 3 2 1
VGA1B 2 OF 8
LVDS Interface
MEMORY ID Table TXCAP_DPA3P
TXCAM_DPA3N
AU24
AV23
HDMI_PCH_CLK
HDMI_PCH_CLK# 2
RN8203
3
7 OF 8
1 DIS 4
DVPDATA[0:3] Description TX0P_DPA2P
AT25 HDMI_PCH_DATA0
VGA1G
MUTI GFX AR24 HDMI_PCH_DATA0# SRN10KJ-5-GP
DPA TX0M_DPA2N
1000 DDR3 Samsung-K4W1G1646E-HC12 (800MHz) TX1P_DPA1P

AU26 HDMI_PCH_DATA1 LVDS CONTROL
AV25 HDMI_PCH_DATA1# AK27 VGA_LBKLT_CTL
TX1M_DPA1N VARY_BL
AJ27 VGA_LCDVDD_EN
DIGON
0000 DDR3 Hynix-H5TQ1G63BFR-12C (800MHz) AR8
DVPCNTL_MVP_0 TX2P_DPA0P
AT27 HDMI_PCH_DATA2
MEM_ID Control AU8
AP8
DVPCNTL_MVP_1 TX2M_DPA0N
AR26 HDMI_PCH_DATA2#
DVPCNTL_0
DVPDATA[0:3] Default:Pull down +1.8V_RUN_VGA
AW8
DVPCNTL_1 TXCBP_DPB3P
AR30
AR3 AT29 AK35 GPU_LVDSB_TXC
DVPCNTL_2 TXCBM_DPB3N TXCLK_UP_DP F3P
D R8207 1 Hynix2 10KR2J-3-GP MEM_ID0
AR1
AU1
DVPCLK
AV31
TXCLK_UN_DPF3N
AL36 GPU_LVDSB_TXC#
D
R8209 1 10KR2J-3-GP MEM_ID1 DVPDATA_0 TX3P_DPB2P
DY MEM_ID2
AU3
AW3
DVPDATA_1 DPB TX3M_DPB2N
AU30
TXOUT_U0P_DPF2P
AJ38
AK37
GPU_LVDSB_TX0
DVPDATA_2 TXOUT_U0N_DPF2N GPU_LVDSB_TX0#
TP8222 TPAD14-GP MEM_ID3 AP6 AR32
THERMTRIP _VGA TP8223 TPAD14-GP DVPDATA_3 TX4P_DPB1P
AW5 AT31 AH35 GPU_LVDSB_TX1
DVPDATA_4 TX4M_DPB1N TXOUT_U1P_DPF1P
AU5 AJ36 GPU_LVDSB_TX1#
DVPDATA_5 TXOUT_U1N_DPF1N
AR6 AT33
DVPDATA_6 TX5P_DPB0P
THERMTRIP_VGA# AW6 AU32 AG38 GPU_LVDSB_TX2
DVPDATA_7 TX5M_DPB0N TXOUT_U2P_DPF0P
DY R8208 AU6
AT7
DVPDATA_8
AU14
TXOUT_U2N_DPF0N
AH37 GPU_LVDSB_TX2#
10KR2J-3-GP DVPDATA_9 TXCCP_DPC3P
AV7 AV13 AF35
DVPDATA_10 TXCCM_DPC3N TXOUT_U3P
AN7 AG36
2N7002EDW -GP DVPDATA_11 TXOUT_U3N
Q8203
. Q8202 AV9
DVPDATA_12 TX0P_DPC2P
AT15
AT9 AR14
DI S .
2N7002E-1-GP
AR10
DVPDATA_13 TX0M_DPC2N LVTMDP
84.27002.F3F DIS .
. . 84.2N702.D31 AW10
DVPDATA_14 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 AV15 AP34 GPU_LVDSA_TXC
DVPDATA_16 TX1M_DPC1N TXCLK_LP_DPE3P
AP10 AR34 GPU_LVDSA_TXC#
DVPDATA_17 TXCLK_LN_DPE3N
AV11 AT17
DVPDATA_18 TX2P_DPC0P R8202 10KR2J-3-GP VGA _BLEN
H_THERMTRIP# AT11
DVPDATA_19 TX2M_DPC0N
AR16 1 DIS TXOUT_L0P_DPE2P
AW37 GPU_LVDSA_TX0
AR12 AU35 GPU_LVDSA_TX0#
+3.3V_RUN_VGA DVPDATA_20 TXOUT_L0N_DPE2N
AW12 AU20
DVPDATA_21 TXCDP_DPD3P
THERMTRIP_VGA_GATE AU12 AT19 AR37 GPU_LVDSA_TX1
DVPDATA_22 TXCDM_DPD3N TXOUT_L1P_DPE1P
AP12 AU39 GPU_LVDSA_TX1#
DVPDATA_23 TXOUT_L1N_DPE1N
AT21
TX3P_DPD2P
AR20 AP35 GPU_LVDSA_TX2
JTAG_ TRST#_ VGA RN8201 TX3M_DPD2N TXOUT_L2P_DPE0P
AR35 GPU_LVDSA_TX2#
TXOUT_L2N_DPE0N
DPD
For new version
DIS SRN4K7J-8-GP TX4P_DPD1P
AU22
AV21 AN36
TX4M_DPD1N TXOUT_L3P
AP37
I2C TXOUT_L3N
AT23
R8201 JTAG _TCK _ VGA RN8202 TX5P_DPD0P
AR22
TX5M_DPD0N
DIS I2C Bus for LVDS GPU_LVDS_CLK 4 1 GPU _LVDS_ CLK_ C AK26
SCL
3 2 GPU _LVDS_ DATA_ C AJ26
GPU_LVDS_DATA DIS SDA
10KR2J-3-GP
DY R8203
Straps MADISON-PRO-2-GP
10KR2J-3-GP
SRN0J-6-GP
GENERAL PURPOSE I/O R
R#
AD39
AD37
VGA_CRT_RED DIS
TX_PW RS_ENB AH20
GPIO_0 +1.8V_RUN_VGA
TX_DEEMPH_EN AH18 AE36 VGA_CRT_GREEN
GPIO_1 G AVDD
BIF_GEN2_EN_A AN16 AD35
GPIO_2 G# L8202 DIS
AH23
GPIO_3_SMBDATA (1.8V@65mA AVDD)
C AJ23 AF37 VGA_CRT_BLUE 1 2 C
GPIO_4_SMBCLK B
GPIO5_AC_BATT
GPIO6 _VGA
AH17
GPIO_5_AC_BATT DAC1 B#
AE38 +3.3V tolerant BLM15BD121SS1D-GP
C8203 C8204
1 AJ17 RN8204
TP8207 TPAD14-GP GPIO_6 VGA _ CRT_ BLUE C8201
+3.3V_RUN_VGA
VGA_BLEN AK17
GPIO_7_BLON HSYNC
AC36 VGA_CRT_HSYNC
VGA _ CRT_ GREEN
1 8
SC4D7U6D3V3KX-GP
DIS DIS DISS C1U6D3V2KX-GP
AJ13 AC38 2 7
GPIO8_ROMSO
VGA_DIS AH15
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC
VGA _ CRT_ RED 3
DIS 6
GPIO_9_ROMSI
AJ16
GPIO_10_ROMSCK GPU _RSET
DIS 4 5
CONFIG0 AK16 AB34 1
R8205 GPIO_11 RSET R8214 499R2F-2-GP SRN150F-1-GP
DIS CONFIG1
CONFIG2
AL16
AM16
GPIO_12
AD34 AVDD VDD1DI
10KR2J-3-GP VPIO14 _VGA GPIO_13 AVDD L8203 DIS
1 AM14
GPIO_14_HPD2 AVSSQ
AE34 (1.8V@100mA VDD1DI)
TP8208 TPAD14-GP AM13 1 2
PW RCNTL_0 GPIO_15_PW RCNTL_0
1 TPAD14-GP GPIO16 _SSIN AK14 AC33 VDD1DI BLM15BD121SS1D-GP
JTAG _ TMS_ VGA 1 TPAD14-GP GPIO17 _VGA GPIO_16_SSIN VDD1DI C8206 C8207
TP8203 AG30 AC34
GPIO_17_THERMAL_IN T VSS1DI
TP8213 1 TPAD14-GP GPIO18 _VGA AN14 C8202 DIS DIS
TP8209 THERMTRIP_VGA GPIO_18_HPD3 SC4D7U6D3V3KX-GP
AM17
GPIO_19_CTF DIS
AL13 AC30 SCD1U10V2KX-4GP
PW RCNTL_1 GPIO_20_PW RCNTL_1 R2
GPIO21_BB_EN AJ14 AC31
GPIO_21_BB_EN R2#
BIOS_ROM_EN AK13
GPIO_22_ROMCS#
PEG_CLKREQ# AN13 AD30
JTAG _ TRST#_ VGA GPIO_23_CLKREQ# G2
AM23 AD31
JTAG_TRST# G2#
R8204 TP8202 1 TPAD14-GP JTAG _TDI _VGA AN23
JTAG_TDI
JTAG SIGNAL OPTION CLK_VGA_27M_SS
1 DIS 2 JTAG _TCK _VGA
JTAG _ TMS_ VGA
AK23
AL24
JTAG_TCK B2
AF30
AF31
(1.8V@50mA VDD2DI)
JTAG_TMS B2#
Normal Debug 0R2J-2-GP TP8205 1 TPAD14-GP JTAG _TDO _VGA AM24
JTAG_TDO
Signal mode mode
TP8206 1 TPAD14-GP GEN _A AJ19
GENERICA
C8209 C8210
For new version no 27M TP8211
TP8218
1
1
TPAD14-GP
TPAD14-GP
GEN _B
GENERICC
AK19
AJ20
GENERICB C
AC32
AD32
DY DY SC1U6D3V2KX-GP
GENERICC Y
TESTEN "1"(PU) "1"(PU) TP8219 1 TPAD14-GP GENERICD
GENERICE _HPD4
AK20
GENERICD COMP
AF32
TP8212 1 TPAD14-GP AJ24
TP8220 GENERICF GENERICE_HPD4 DAC2
1 TPAD14-GP AH26
GENERICF
JTAG_TRST# "0"(PD) "1"(PU) TP8221 1 TPAD14-GP GENERICG AH24
GENERICG H2SYNC
AD29 HSYNC_DAC2
A2VDDQ
AC29 VSYNC_DAC2
V2SYNC
JTAG_TCK CLK "1"(PU) +1.8V_RUN_VGA

HDMI_HPD_DET AK24
HPD1 +1.8V_RUN_VGA
L8205 DIS (1.8V@1.5mA A2VDDQ)
AG31 1 2
VDD2DI
AG32 BLM15BD121SS1D-GP
VSS2DI
JTAG_TMS "1"(PU) "1"(PU) +3.3V_RUN_VGA C8212 C8213
PLACE VREFG DIVIDER AND CAP R8216 DIS DIS
DIS 499R2F-2-GP AG33 A2VDDQ
CLOSE TO ASIC A2VDD
B +1.8V_RUN_VGA DPLL_PVDD AD33 B
GPU _VREFG A2VDDQ
AH13
L8201 VREFG
DIS (1.8V@75mA DPLL_PVDD) A2VSSQ
AF33
1 2 DPLL_PVDD
BLM18PG471SN1D-GP R8217 C8217 DIS +3.3V_RUN_VGA
C8218 249R2F-GP R2SET
C8205 C8219
DIS DIS R2SET
AA29 1
R8218
2
715R2F-GP
(3.3V@130mA A2VDD)
DY AM32
DPLL_PVDD
SC4D7U6D3V3KX-GP DIS AN32
DPLL_PVSS
DIS C8215 C8216
DDC/AUX
DDC1CLK
AM26 VGA_CRT_DDCCLK DY DY
AN31
DPLL_VDDC DDC1DATA
AN26 VGA_CRT_DDCDATA DDC1 channel for CRT SCD1U10V2KX-4GP
AM27
+1.0V_RUN_VGA DPLL_VDDC XTALIN PLL/CLOCK AUX1P
(1.0V@125mA DPLL_VDDC) AV33
XTALIN AUX1N
AL27
XTALOUT AU34
DIS (1.1V@150mA DPLL_VDDC For M96/M92) XTALOUT
1 2 AM19 GPU_HDMI_CLK
DDC2CLK
L8207 BLM18PG471SN1D-G P
DDC2DATA
AL19 GPU_HDMI_DATA DDC2 channel for HDMI
CLK_VGA_27M_NSS AW34
C8221 C8222 XO_IN
AN20
C8220 AUX2P
SC4D7U6D3V3KX-GP
DY DIS DIS AW35
XO_IN2 AUX2N
AM20
VGA_THERMDA DDCCLK_AUX3P
AL30
AM30
DDC1/DDC2/DDC6 have 5V-tolerant
C8226 DDCDATA_AUX3N
SC470P50V2 JN-GP
DY AF29
DDCCLK_AUX4P
AL29
AM29
DPLUS THERMAL DDCDATA_AUX4N
VGA_THERMDC AG29
DMINUS
AN21
DDCCLK_AUX5P
AM21
TP8214 DDCDATA_AUX5N
1 TPAD14-GP FAN_PW M AK32 X8201
TS_FDO
AJ30 C8227
DDC6CLK
AL31 AJ31
+1.8V_RUN_VGA TSVDD TS_A DDC6DATA XTALIN
1 1 4
L8204 DIS
1 2
(1.8V@20mA TSVDD)
AJ32
DDCCLK_AUX7P
AK30
AK29
DY
TSVDD DDCDATA_AUX7N SC18P50V2JN-1-GP C8228
BLM15BD121SS1D-GP AJ33
TSVSS
2
DY 3 XTALOUT 1 2
DIS DIS C8225
C8223 DY C8224 MADISON-PRO-2-GP
A
SC4D7U6D3V3KX-GP SC1U6D3V2KX-G SCD1U10V2KX-4GP
DIS XTAL-27MHZ-85-GP
SC18P50V2JN-1-GP
DY A
<Core Design>
Clock Input Configuraiton -GDDR3/DDR3
a) 27MHz crystal connected to XTALIN or XTALOUT or Wistron Corporation
b) 27MHz (1.8V) oscillator connected to XTALIN or 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
A2
Berry X00
5 4 3 2 1
5 4 3 2 1
VGA1E 5 OF 8 +1.8V_RUN_VGA
+1.5V_RUN
For DDR3/GDDR5, MVDDQ = 1.5V MEM I/O
PCIE (1.8V@504mA PCIE_VDDR)
AC7 AA31
VDDR1 PCIE_VDDR
AD11 AA32
C8301 C8304 C8305 C8306 C8307 C8308 C8309 C8310 C8311 C8312 VDDR1 PCIE_VDDR C8313 C8314 C8315 C8316 C8317
AF7 AA33
VDDR1 PCIE_VDDR SC4D7U6D3V3KX-GP
AG10
VDDR1 PCIE_VDDR
AA34 DIS
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS AJ7
VDDR1 PCIE_VDDR
V28
DY DIS DY DIS
AK8 W29
VDDR1 PCIE_VDDR
AL9 W30
VDDR1 PCIE_VDDR +1.0V_RUN_VGA
G11 Y31
VDDR1 PCIE_VDDR
G14
VDDR1
G17
VDDR1 (1.0V@1920mA PCIE_VDDC)
G20 G30
C8318 C8319 C8320 C8321 C8322 C8323 C8324 C8325 C8326 C8327 VDDR1 PCIE_VDDC
G23 G31
VDDR1 PCIE_VDDC C8328 C8329 C8330 C8331 C8332 C8333 C8302 C8334
G26 H29
DIS DIS DIS VDDR1 PCIE_VDDC
DIS SC4D7U6D3V3KX-GP
DIS DIS DY DY DY DY DY G29
H10
VDDR1 PCIE_VDDC
H30
J29
J7
VDDR1 PCIE_VDDC
J30
DIS
D
J9
VDDR1 PCIE_VDDC
L28
DIS DIS DIS DIS DIS DIS D
VDDR1 PCIE_VDDC
K11 M28
VDDR1 PCIE_VDDC
K13 N28
VDDR1 PCIE_VDDC
K8 R28
VDDR1 PCIE_VDDC
L12 T28
VDDR1 PCIE_VDDC
C8303 C8335
L16
L21
VDDR1 PCIE_VDDC
U28
+VGA_CORE For UMA +VGA_CORE connect to GND
VDDR1
L23
VDDR1
L26 AA15
VDDR1 CORE VDDC
DIS DIS L7
M11
VDDR1 VDDC
AA17
AA20 C8336 C8337 C8338 C8339 C8340 C8341 C8342 C8343 C8344 C8345
VDDR1 VDDC SC1U6D3V2KX- GP R8301
N11 AA22
VDDR1 VDDC
P7 AA24
R11
VDDR1 VDDC
AA27
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS UMA 0R3J-0-U-GP
VDDR1 VDDC
U11 AB16
VDDR1 VDDC
U7 AB18
VDDR1 VDDC
Y11 AB21
VDDR1 VDDC
Y7 AB23
VDDR1 VDDC
AB26
+1.8V_RUN_VGA VDDC
AB28
VDDC C8346 C8347 C8348 C8349 C8350
AC17
VDDC
VDDC_CT LEVEL VDDC
AC20
AC22
DIS DIS DY DIS DI S SC1U6D3V2KX-GP
TRANSLATION VDDC
(1.8V@110mA VDD_CT) VDDC
AC24
1 2 AF26 AC27
L8301 DIS BLM15BD121SS1D-GP AF27
VDD_CT VDDC
AD18
C8351 C8352 C8353 C8354 C8355 VDD_CT VDDC
AG26 AD21
VDD_CT VDDC
DIS DIS DIS DIS AG27
VDD_CT VDDC
AD23
AD26
DIS VDDC
AF17
I/O VDDC
AF20
+3.3V_RUN_VGA VDDC C8356 C8357 C8358 C8359 C8360 C8361 C8362 C8363 C8364 C8365
AF23 AF22
VDDR3 VDDC
AF24 AG16
AG23
VDDR3 VDDC
AG18
DIS DY DIS COLAY
AG24
VDDR3 VDDC
AG21
DIS DIS DIS DIS DIS DIS
C8366 C8367 C8368 C8369 VDDR3 VDDC
AH22
VDDC
DIS VDDC
AH27
AF13 AH28
VDDR4 VDDC
DIS DIS DIS AF15
VDDR4 VDDC
M26
AG13 N24
VDDR4 VDDC
C AG15 N27 C
VDDR4 VDDC/BIF_VDDC C8370 C8371 C8373
R18
VDDC C8372
R21
VDDC
AD12 R23
AF11
VDDR4 VDDC
R26
DIS DIS DY DIS
VDDR4 VDDC
AF12 T17
VDDR4 VDDC
AG11 T20
VDDR4 VDDC
T22
VDDC
T24
C8374 VDDC
T27
SC1U6D3V2KX-GP C8375 VDDC/BIF_VDDC
U16
SCD1U10V2KX-4GP VDDC
M20 U18
NC_VDDRHA VDDC
DIS D IS M21
NC_VSSRHA VDDC
U21
U23
VDDC
U26
VDDC
V12 V17
U12
NC_VDDRHB
NC_VSSRHB
VDDC
VDDC
V20 VDDCI and VDDC should have seperate regulators with a merge option on PCB
V22
VDDC
V24
PCIE_PVDD
VDDC
VDDC
V27 For Madison and Park, VDDCI and VDDC can share one common regulator
Y16
PLL VDDC
(1.8V@40mA PCIE_PVDD) VDDC
Y18
1 2 AB37
L8302 DIS BLM15BD121SS1D-GP MPV18
PCIE_PVDD VDDC
Y21
Y23
C8377 C8378 VDDC
H7 Y26
C8376 MPV18 VDDC
DIS DIS H8
MPV18 VDDC
Y28
SC4D7U6D3V3KX-GP
DIS SPV10
SPV18 (GDDR3/DDR3 1.12V@4A VDDCI)
+VGA_CORE
+1.0V_RUN_VGA AM10 (GDDR5 1.12V@16A VDDCI)
L8303 SPV18
AA13
1
DIS
2 AN9
VDDCI
AB13
(120mA SPV10)
BLM18PG471SN1D-GP SPV10 VDDCI
AC12
C8380 C8381 VDDCI C8382 C8383 C8384 C8385 C8386 C8387 C8388
(For M96 SPV10 = VDDC) AN10
SPVSS VDDCI
AC15
C8379 SC1U6D3V2KX-GP
(For M97, Broadway, Madison and Park SPV10 = 1.0V) DIS DIS DIS VDDCI
AD13
AD16
DY DY DIS SC10U10V5KX-2GP
SC4D7U6D3V3KX-GP VDDCI
M15
DIS DIS DIS DIS
VDDCI
M16
VOLTAGE VDDCI
M18
SENESE VDDCI
M23
VDDCI
N13
FB
_VDDC VDDCI
M97, Broadway, Madison and Park only 1 AF28
FB_VDDC VDDCI
N15
B M96 do not support core vsense feature TP8301 TPAD14-GP N17 B
VDDCI
N20
FB
_VDDC I VDDCI
1 AG28 N22
TP8302 TPAD14-GP FB_VDDCI I SOLATED VDDCI
R12
C ORE I/O VDDCI
R13
FB
_GND VDDCI
1 AH29 R16
TP8303 FB_GND VDDCI
TPAD14-GP T12
VDDCI
T15
VDDCI
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair VDDCI
V15
Y13
VDDCI
MADISON-PRO-2-GP
M97, Broadway, Madison and Park only
DIS
SPV18
(1.8V@75mA SPV18)
NOTE1:
1
L8304 DIS 2
BLM15BD121SS1D-GP
Back Bias is not supported on M97, Broadway, Madison and Park
C8389 C8390 C8391
DIS SCD1U10V2KX-4GP For the M96 Back Bias circuitry, refer to REF134
SC4D7U6D3V3KX-GP DIS DIS
NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
(M97, Broadway and Madison: 1.8V@150mA MPV18) If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
(Park: 1.8V@75mA MPV18)
MPV18
L8305 NOTE4:
DIS
2
1
BLM18PG471SN1D-GP
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
C8393 C8396
C8392 DIS SCD1U10V2KX-4GP
A SC4D7U6D3V3KX-GP DIS DIS A
<Core Design>
Wistron Corporation
Title
GPU_POWER(4/5)
A2
Berry X00
Date: Thursday, October 22, 2009 S heet 83 of 92
5 4 3 2 1
5 4 3 2 1
VGA1F 6 OF 8
VGA1H 8 OF 8
AB39 A3 DPA_VDD18
PCIE_VSS GND DPB_VDD18 DP C/D POWER DP A/B POWER
E39 A37
PCIE_VSS GND
F34 AA16
PCIE_VSS GND
F39 AA18 AP20 AN24
PCIE_VSS GND +1.0V_RUN_VGA DPC_VDD18 DPA_VDD18
G33 AA2 AP21 AP24
PCIE_VSS GND DPC_VDD18 DPA_VDD18 +1.0V_RUN_VGA
G34
PCIE_VSS GND
AA21 DNI for M96/M92
H31 AA23 DPA_VDD10
PCIE_VSS GND L8403
H34
PCIE_VSS GND
AA26 (1.0V@110mA DPC_VDD10) (1.0V@110mA DPA_VDD10) DIS
H39 AA28 AP13 AP31 1 2 +1.8V_RUN_VGA DPA_VDD18
PCIE_VSS GND DPC_VDD10 DPA_VDD10 BLM15BD121SS1D-GP
J31 AA6 AT13 AP32
PCIE_VSS GND DPC_VDD10 DPA_VDD10 C8402 C8403
J34 AB12 C8405
PCIE_VSS GND SC10U6D3V5KX-1GP L8402
K31 AB15 DIS DIS DIS (1.8V@130mA DPA_VDD18)
K34
PCIE_VSS GND
AB17 AN17 AN27 1
DIS2
PCIE_VSS GND DPC_VSSR DPA_VSSR BLM15BD121SS1D-GP
K39 AB20 AP16 AP27
PCIE_VSS GND DPC_VSSR DPA_VSSR C8407
D L31 AB22 AP17 AP28 D
PCIE_VSS GND DPC_VSSR DPA_VSSR C8406 C8408
L34
PCIE_VSS GND
AB24 AW14
DPC_VSSR DPA_VSSR
AW24 DIS DIS
M34 AB27 AW16 AW26 SC4D7U6D3V3KX-GP DIS SCD1U10V2KX-4GP
PCIE_VSS GND DPC_VSSR DPA_VSSR
M39 AC11
PCIE_VSS GND DPD_VDD18 DPB_VDD18
N31 AC13
PCIE_VSS GND DPB_VDD18
N34 AC16
PCIE_VSS GND +1.0V_RUN_VGA
P31 AC18 AP22 AP25
PCIE_VSS GND DPD_VDD18 DPB_VDD18
P34 AC2 AP23 AP26
PCIE_VSS GND DPD_VDD18 DPB_VDD18 +1.0V_RUN_VGA
P39
PCIE_VSS GND
AC21 DIS (1.8V@130mA DPB_VDD18)
R34 AC23 1
PCIE_VSS GND
T31 AC26 (1.0V@110mA DPD_VDD10) R8402 0R2J-2-GP
PCIE_VSS GND
T34
PCIE_VSS GND
AC28 AP14
DPD_VDD10 DPB_VDD10
AN33 (1.0V@110mA DPB_VDD10) DY C8410
T39 AC6 AP15 AP33 C8409 DY DIS C8411
PCIE_VSS GND DPD_VDD10 DPB_VDD10 SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP
U31 AD15
PCIE_VSS GND
U34 AD17
PCIE_VSS GND
V34 AD20
PCIE_VSS GND
V39 AD22 AN19 AN29
PCIE_VSS GND DPD_VSSR DPB_VSSR
W31 AD24 AP18 AP29
W34 AD27 AP19 AP30
Y34 AD9 AW20 AW30
PCIE_VSS GND DPD_VSSR DPB_VSSR +1.8V_RUN_VGA
Y39 AE2 AW22 AW32
PCIE_VSS GND DPD_VSSR DPB_VSSR DPA_PVDD
AE6
GND L8404
AF10 (1.8V@20mA DPA_PVDD)
GND
AF16 DP mode R8401 DIS R8404 1
DIS 2
GND DPCD_CALR DPAB_CALR
BLM15BD121SS1D-GP
AF18 (1.8V@130mA DPE_VDD18) 1 2 AW18 AW28 1 2
GND DPCD_CALR DPAB_CALR
GND AF21 +1.8V_RUN_VGA 150R2F-1-GP 150R2F-1-GP C8412

GND LVDS mode DPE_VDD18 C8413
AG17
GND
F15
GND GND
AG2 DIS L8401 (1.8V@200mA DPE_VDD18) DP E/F POWER DP PLL POWER
DIS DIS DIS C8414
F17 AG20 1 2 AH34 AU28 DIS SC4D7U6D3V3KX-GP DPD_VDD18
GND GND BLM18PG471SN1D-GP DPE_VDD18 DPA_PVDD
F19 AG22 AJ34 AV27
GND GND C8401 C8418 DPE_VDD18 DPA_PVSS
F21 AG6
GND GND SC4D7U6D3V3KX-GP C8419
F23
GND GND
AG9
LVDS mode
DIS DIS DIS SCD1U10V2KX-4GP
DIS (1.8V@130mA DPD_VDD18)
F25
GND GND
AH21 (1.8V@20mA DPB_PVDD) 1 2
F27 AJ10 (1.0V@120mA DPE_VDD10) AL33 AV29 R8405 0R2J-2-GP
GND GND DPE_VDD10 DPB_PVDD
F29 AJ11 DP mode DPE_VDD10 AM33 AR28 DY C8421 Madison
GND GND DPE_VDD10 DPB_PVSS
F31 AJ2 (1.0V@110mA DPE_VDD10) C8415
GND GND SC4D7U6D3V3KX-GP C8422
F33
GND GND
AJ28 DY
F7 AJ6 +1.0V_RUN_VGA (1.8V@20mA DPC_PVDD) SCD1U10V2KX-4GP
GND GND L8408
F9 AK11 AN34 AU18
G2
GND GND
AK31 1
DIS 2 AP39
DPE_VSSR DPC_PVDD
AV17
GND GND BLM15BD121SS1D-GP DPE_VSSR DPC_PVSS
G6 AK7 AR39
GND GND C8404 C8424 C8425 DPE_VSSR
C H9 AL11 AU37 C
GND GND DPE_VSSR
J2
GND GND
AL14 SC4D7U6D3V3KX-GP DIS DIS (1.8V@20mA DPD_PVDD)
J27
GND GND
AL17
DP mode
DISSCD1U10V2KX-4GP DPD_PVDD
AV19
J6 AL2 AR18
GND GND DPD_PVSS
J8
GND GND
AL20 (1.8V@130mA DPF_VDD18)
K14 AL21 LVDS mode AF34 DPF_PVDD
GND GND/PX_EN DPF_VDD18 DPF_VDD18
K7
GND GND
AL23 (1.8V@200mA DPF_VDD18) AG34
DPF_VDD18 (1.8V@20mA DPE_PVDD)
L11 AL26 AM37
GND GND +1.8V_RUN_VGA DPE_PVDD
L17 AL32 AN38
GND GND L8405 DIS DPE_PVSS
L2 AL6
GND GND
L22 AL8 1 2 AK33
GND GND DPF_VDD10 L8406
L24 AM11 BLM18PG471SN1D-GP AK34
L6
GND GND
AM31 C8423 C8427 DPF_VDD10
AL38
(1.8V@20mA DPF_PVDD)
1
DIS 2
GND GND SC4D7U6D3V3KX-GP C8428 DPF_PVDD BLM15BD121SS1D-GP
M17 AM9 DIS AM3 5
GND GND DPF_PVSS
M22
GND GND
AN11 DIS DISS CD1U10V2KX-4GP C8429 C8430
C8416
M24
GND GND
AN2 AF39
DPF_VSSR DIS DIS DIS
N16 AN30 LVDS mode AH39 SC4D7U6D3V3KX-GP
GND GND DPF_VDD10 DPF_VSSR
N18
GND GND
AN6 (1.0V@120mA DPF_VDD10) AK39
DPF_VSSR
N2 AN8 DP mode AL34
GND GND DPF_VSSR
N21 AP11 (1.0V@110mA DPF_VDD10) AM34
GND GND DPF_VSSR
N23 AP7
GND GND +1.0V_RUN_VGA
N26 AP9
GND GND L8407
N6 AR5
R15
GND GND
B11 1
DIS 2 AM39
GND GND BLM15BD121SS1D-GP DPEF_CALR
R17 B13
GND GND C8426 C8433 C8434
R2 B15
GND GND SC4D7U6D3V3KX-GP MADISON-PRO-2-GP
R20
GND GND
B17 DIS DIS
R22 B19 DIS
R24
R27
GND
GND
GND
GND
GND
GND
B21
B23
DIS
R6 B25
GND GND R8406
T11 B27
GND GND 150R2F-1-GP
T13
GND GND
B29 DIS
T16 B31
GND GND
T18 B33
GND GND
T21 B7
GND GND
T23 B9
GND GND
T26 C1
GND GND
U15 C39
GND GND
U17 E35
GND GND
U2 E5
B GND GND B
U20
GND GND
F11 For M97/M96, DPF_VDD18 can be shared with DPE_VDD18
U22 F13
GND GND
U24
GND For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
U27
GND
U6
GND
V11
GND
V16
GND
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
V18
GND
V21
GND
V23
GND
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
V26
GND
W2
GND
W6
GND For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
Y15
GND
Y17
GND
Y20
GND
Y22 A39 VSS_ MECH1 TPAD14-GP1 TP8401
GND VSS_MECH
Y24 AW1 VSS_ MECH2 TPAD14-GP1 TP8402
GND VSS_MECH VSS
_MEC H 3 TPAD14-GP1
TP8403
Y27 AW39
GND VSS_MECH
U13
GND
V13
GND
MADISON-PRO-2-GP
DIS
A A
<Core Design>
Wistron Corporation
Title
GPU _ DPPWR/GND(5/5)
A2 Berry X00
Date: Tuesday , October 20 , 2009 S heet 84 of 92
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM1 VRAM2
MDA[0..31] MDA[0..31]
K8 E3 MDA3 K8 E3 MDA29
VDD DQL0 MDA7 VDD DQL0 MDA24
K2 F7 K2 F7
C8508 C8509 C8512 C8511 C8513 VDD DQL1 MDA1 VDD DQL1 MDA30
N1 F2 C8515 C8520 N1 F2
R9 F8 R9 F8
B2
VDD DQL4
H3 DY B2
VDD DQL4
H3
Madis
Madioson
n MadisonMadisoMadisoMadis
n MoadisonMadis on D9
VDD DQL5
H8 MDA4 Madison Madiso nMadis o n MadisoMadison
n Madison D9
VDD DQL5
H8 MDA27
D MDA0 MDA25 D
G7 G2 Madison G7 G2
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 N9
VDD MDA20 VDD MDA8
D7 D7
DQU0 MDA19 DQU0 MDA14
A8 C3 A8 C3
VDDQ DQU1 MDA23 VDDQ DQU1 MDA9
A1 C8 A1 C8
C8502 C8505 C1 C2 C8521 C8522 C1 C2
C9 A7 C9 A7
Madison Madiso n D2
VDDQ DQU5
A2 D2
VDDQ DQU5
A2
E9 B8 MDA21 MadisonMadison E9 B8 MDA13
VDDQ DQU6 MDA17 VDDQ DQU6
F1 A3 F1 A3 MDA11
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 QSAP_2 H2 C7 QSAP_1
VDDQ DQSU VDDQ DQSU
B7 QSAN_2 B7 QSAN_1
VRAM1_VREF DQSU# VRAM2_ VREF DQSU#
H1 H1
VREFDQ VREFDQ
VRAM2_VREF M8 F3 QSAP_0 VRAM1_ VREF M8 F3 QSAP_3
VREFCA DQSL VRAM VREFCA DQSL
1 2 VRAM_ ZQ1 L8 G3 QSAN_0 1 2 _ZQ2 L8 G3 QSAN_3
R8503 243R2F-2-GP ZQ DQSL# R8504 243R2F-2-GP ZQ DQSL#
Madison Madison
K1 ODTA0 K1 ODTA0
ODT ODT
MAA0 N3 MAA0 N3
A0 A0
MAA1 P7 MAA1 P7
A1 A1
MAA2 P3 L2 CSA0#_0 MAA2 P3 L2 CSA0#_0
A2 CS# A2 CS#
MAA3 N2 T2 MEM_RST MAA3 N2 T2 MEM_RST
A3 RESET# A3 RESET#
MAA4 P8 MAA4 P8
A4 A4
MAA5 P2 MAA5 P2
A5 A5
MAA6 R8 T7 MAA6 R8 T7
A6 NC#T7 A6 NC#T7
MAA7 R2 L9 MAA7 R2 L9
A7 NC#L9 A7 NC#L9
MAA8 T8 L1 MAA8 T8 L1
A8 NC#L1 A8 NC#L1
MAA9 R3 J9 MAA9 R3 J9
A9 NC#J9 A9 NC#J9
C MAA10 L7 J1 MAA10 L7 J1 C
A10/AP NC#J1 A10/AP NC#J1
MAA11 R7 MAA11 R7
A11 A11
MAA12 N7 MAA12 N7
A12/BC# A12/BC#
MAA13 T3 J8 MAA13 T3 J8
A13 VSS A13 VSS
M7 M1 M7 M1
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
A_BA0 M2 P9 A_BA0 M2 P9
BA0 VSS BA0 VSS
A_BA1 N8 G8 A_BA1 N8 G8
BA1 VSS BA1 VSS
A_BA2 M3 B3 A_BA2 M3 B3
BA2 VSS BA2 VSS
20090902 VSS
T1
A9
VSS
T1
A9
VSS VSS
CLKA0 J7 T9 CLKA0 J7 T9
CK VSS CK VSS
CLKA0# K7 E1 CLKA0# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
CKEA0 K9 CKEA0 K9
CKE CKE
G1 G1
R8508 R8507 VSSQ VSSQ
F9 F9
56R2J-4-GP VSSQ VSSQ
DQMA2 D3 E8 DQMA1 D3 E8
DMU VSSQ DMU VSSQ
Madison56R2J-4-GP M adison DQMA0 E7
DML VSSQ
E2 DQMA3 E7
DML VSSQ
E2
D8 D8
VSSQ VSSQ
D1 D1
VSSQ VSSQ
GPU _ CLKA0 _ T WEA0# L3 B9 WEA0# L3 B9
W E# VSSQ W E# VSSQ
CASA0# K3 B1 CASA0# K3 B1
CAS# VSSQ CAS# VSSQ
RASA0# J3 G9 RASA0# J3 G9
C8503 RAS# VSSQ RAS# VSSQ
Madison
SCD01U50V2KX-1GP K4W1G1646E-HC12-GP K4W1G1646E-HC12-GP
B
Madison 20090902
Madison B
20090902
+1.5V_RUN
+1.5V_RUN
R8513
R8510 2K1R2F-GP
2K1R2F-GP
Madison
Madison
VRAM2_VREF
VRAM1_VREF
C8506
C8504 R8512 MadisonSCD1U16V2ZY-2GP
R8511 2K1R2F-GP
2K1R2F-GP
MadisonSCD1U16V2ZY-2GP
Madison
Madison
A A
<Core Design>
Wistron Corporation
Title
Size
GPU-VRAM1,2 (1/4) Rev
Document Number
Custom Berry X00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM3 VRAM4
MDA[32..63] MDA[32..63]
K8 E3 MDA36 K8 E3 MDA61
K2 F7 K2 F7
N1 F2 N1 F2
R9 F8 R9 F8
B2
VDD DQL3
H3 MDA32 DY B2
VDD DQL3
H3 MDA59
VDD DQL4 VDD DQL4
MadisoMadison
n n MadisoMadiso
MadisoMadison n Madison
n Madison D9
VDD DQL5
H8 MDA34 MadisonMadison
Madiso
Madison
n MadisonMadison
Madison D9
VDD DQL5
H8 MDA56
G7 G2 MDA35 G7 G2 MDA62
R1 H7 R1 H7
VDD DQL7 VDD DQL7
N9 N9
VDD MDA46 VDD MDA50
D7 D7
D DQU0 MDA43 DQU0 MDA55 D
A8 C3 A8 C3
A1 C8 A1 C8
VDDQ DQU2 MDA40 C8617 C8619 VDDQ DQU2 MDA52
C8606 C1 C2 C1 C2
C8608 C9 A7 C9 A7
D2
VDDQ DQU5
A2 Madison Madis on D2
VDDQ DQU5
A2
Madison Madis on E9 B8 MDA47 E9 B8 MDA51
VDDQ DQU6 MDA42 VDDQ DQU6
F1 A3 F1 A3 MDA53
VDDQ DQU7 VDDQ DQU7
H9 H9
VDDQ VDDQ
H2 C7 QSAP_5 H2 C7 QSAP_6
VDDQ DQSU VDDQ DQSU
B7 QSAN_5 B7 QSAN_6
VRAM3_VREF DQSU# VRAM4_VREF DQSU#
H1 H1
VREFDQ VREFDQ
VRAM4_VREF M8 F3 QSAP_4 VRAM3_ VREF M8 F3 QSAP_7
VRAM VREFCA DQSL VREFCA DQSL
1 2 _ZQ3 L8 G3 QSAN_4 1 2
VRAM
_ZQ4 L8 G3 QSAN_7
R8603 Madison 243R2F-2-GP ZQ DQSL# R8604 Madison 243R2F-2-GP ZQ DQSL#
K1 ODTA1 K1 ODTA1
ODT ODT
MAA0 N3 MAA0 N3
A0 A0
MAA1 P7 MAA1 P7
A1 A1
MAA2 P3 L2 CSA1#_0 MAA2 P3 L2 CSA1#_0
A2 CS# A2 CS#
MAA3 N2 T2 MEM_RST MAA3 N2 T2 MEM_RST
A3 RESET# A3 RESET#
MAA4 P8 MAA4 P8
A4 A4
MAA5 P2 MAA5 P2
A5 A5
MAA6 R8 T7 MAA6 R8 T7
A6 NC#T7 A6 NC#T7
MAA7 R2 L9 MAA7 R2 L9
A7 NC#L9 A7 NC#L9
MAA8 T8 L1 MAA8 T8 L1
A8 NC#L1 A8 NC#L1
MAA9 R3 J9 MAA9 R3 J9
A9 NC#J9 A9 NC#J9
MAA10 L7 J1 MAA10 L7 J1
A10/AP NC#J1 A10/AP NC#J1
MAA11 R7 MAA11 R7
A11 A11
MAA12 N7 MAA12 N7
A12/BC# A12/BC#
MAA13 T3 J8 MAA13 T3 J8
A13 VSS A13 VSS
C M7 M1 M7 M1 C
NC#M7 VSS NC#M7 VSS
M9 M9
VSS VSS
J2 J2
VSS VSS
A_BA0 M2 P9 A_BA0 M2 P9
BA0 VSS BA0 VSS
A_BA1 N8 G8 A_BA1 N8 G8
BA1 VSS BA1 VSS
A_BA2 M3 B3 A_BA2 M3 B3
BA2 VSS BA2 VSS
T1 T1
VSS VSS
A9 A9
VSS VSS
CLKA1 J7 T9 CLKA1 J7 T9
CK VSS CK VSS
CLKA1# K7 E1 CLKA1# K7 E1
CK# VSS CK# VSS
P1 P1
VSS VSS
CKEA1 K9 CKEA1 K9
CKE CKE
G1 G1
R8607 VSSQ VSSQ
F9 F9
VSSQ VSSQ
56R2J-4-GP R8608 DQMA5 D3 E8 DQMA6 D3 E8
DMU VSSQ DMU VSSQ
Madison 56R2J-4-GP DQMA4 E7 E2 DQMA7 E7 E2
DML VSSQ DML VSSQ
Ma d ison VSSQ
D8
VSSQ
D8
D1 D1
GPU _ CLKA1 _ T VSSQ VSSQ
WEA1# L3 B9 WEA1# L3 B9
W E# VSSQ W E# VSSQ
CASA1# K3 B1 CASA1# K3 B1
CAS# VSSQ CAS# VSSQ
RASA1# J3 G9 RASA1# J3 G9
RAS# VSSQ RAS# VSSQ
C8603 Madison
SCD01U50V2KX-1GP K4W1G1646E-HC12-GP K4W1G1646E-HC12-GP
Madison Madison
20090902 20090902
B
20090902 +1.5V_RUN
B
+1.5V_RUN
R8605
2K1R2F-GP
R8601 Madison
2K1R2F-GP
Madison
VRAM4_VREF
VRAM3_VREF
C8605
R8606 MadisonSCD1U16V2ZY-2GP
C8601 2K1R2F-GP
R8602 MadisonSCD1U16V2ZY-2GP Madison
2K1R2F-GP
Madison
A A
<Core Design>
Wistron Corporation
Title
Size
GPU-VRAM3 ,4 (2/4) Rev
Document Number
Custo m
Berry X00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM5 VRAM6
MDB[0..31] MDB[0..31]
K8 E3 MDB14 K8 E3 MDB16
VDD DQL0 MDB13 VDD DQL0 MDB18
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 MDB12 N1 F2 MDB20
VDD DQL2 MDB15
VDD DQL2 MDB19
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 MDB11 DY B2 H3 MDB22
VDD DQL4 MDB8
VDD DQL4 MDB17
D9 H8 D9 H8
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDB10 R1 H7 MDB21
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D D7 MDB26 D7 MDB1 D
DQU0 MDB27
DQU0 MDB5
A8 C3 A8 C3
VDDQ DQU1 MDB30 VDDQ DQU1 MDB2
A1 VDDQ DQU2 C8 A1 VDDQ DQU2 C8
C8706 C1 C2 MDB24 C8718 C8719 C1 C2 MDB4
C8708 VDDQ DQU3 MDB31
VDDQ DQU3 MDB3
C9 VDDQ DQU4 A7 C9 VDDQ DQU4 A7
D2 A2 MDB25 D2 A2 MDB7
VDDQ DQU5 MDB29
VDDQ DQU5 MDB0
E9 B8 E9 B8
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ C7 QSBP_3 H2 VDDQ C7 QSBP_0
DQSU DQSU
DQSU# B7 QSBN_3 DQSU# B7 QSBN_0
VRAM5 _ VREF H1 VRAM6 _ VREF H1
VRAM6 _ VREF VREFDQ VRAM5 _ VREF VREFDQ
M8 VREFCA DQSL F3 QSBP_1 M8 VREFCA DQSL F3 QSBP_2
1 2 VRAM _ ZQ5 L8 G3 QSBN_1 1 2 VRAM _ ZQ6 L8 G3 QSBN_2
R8704 243R2F-2-GP
ZQ DQSL# R8706 243R2F-2-GP
ZQ DQSL#
DIS DIS
ODT K1 ODTB0 ODT K1 ODTB0
MAB0 N3 A0 MAB0 N3 A0
MAB1 P7 A1 MAB1 P7 A1
MAB2 P3 A2 CS# L2 CSB0#_0 MAB2 P3 A2 CS# L2 CSB0#_0
MAB3 N2 A3 RESET# T2 MEM_RST MAB3 N2 A3 RESET# T2 MEM_RST
MAB5 P2 MAB5 P2
A5 A5
MAB6 R8 A6 NC#T7 T7 MAB6 R8 A6 NC#T7 T7
MAB7 R2 A7 NC#L9 L9 MAB7 R2 A7 NC#L9 L9
MAB8 T8 A8 NC#L1 L1 MAB8 T8 A8 NC#L1 L1
MAB9 R3 A9 NC#J9 J9 MAB9 R3 A9 NC#J9 J9
MAB10 L7 A10/AP NC#J1 J1 MAB10 L7 A10/AP NC#J1 J1
MAB11 R7 A11 MAB11 R7 A11
MAB12 N7 A12/BC# MAB12 N7 A12/BC#
C T3 J8 T3 J8 C
MAB13 A13 VSS MAB13 A13 VSS
M7 NC#M7 M1 M7 NC#M7 M1
VSS VSS
M9 M9
VSS VSS
VSS J2 VSS J2
B_BA0 M2 BA0 VSS P9 B_BA0 M2 BA0 VSS P9
B_BA1 N8 BA1 VSS G8 B_BA1 N8 BA1 VSS G8
20090902 B_BA2 M3 BA2 VSS B3
T1
B_BA2 M3 BA2 VSS B3
T1
VSS VSS
VSS A9 VSS A9
CLKB0 J7 CK VSS T9 CLKB0 J7 CK VSS T9
CLKB0# K7 CK# VSS E1 CLKB0# K7 CK# VSS E1
VSS P1 VSS P1
CKEB0 K9 CKE CKEB0 K9 CKE
R8707 R8708 G1 G1
56R2J-4-GP 56R2J-4-GP
VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS DQMB3 D3 DMU VSSQ E8 DQMB0 D3 DMU VSSQ E8
DQMB1 E7 DML E2 DQMB2 E7 DML E2
VSSQ VSSQ
D8 D8
GPU _ CLKB0 _ T
VSSQ VSSQ
VSSQ D1 VSSQ D1
W EB0# L3 W E# VSSQ B9 W EB0# L3 W E# VSSQ B9
CASB0# K3 CAS# VSSQ B1 CASB0# K3 CAS# VSSQ B1
C8703 DIS J3 G9 J3 G9
RASB0# RAS# VSSQ RASB0# RAS# VSSQ
SCD01U50V2KX-1GP
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
DIS DIS
B 20090902 B
20090902
+1.5V_RUN +1.5V_RUN
R8701 R8703
2K1R2F-GP 2K1R2F-GP
DIS DIS
VRAM5 _ VREF VRAM6 _ VREF
C8701 C8705
R8702 R8705
2K1R2F-GP SCD1U16V2ZY-2GP 2K1R2F-GP SCD1U16V2ZY-2GP
DIS DIS DIS DIS
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN +1.5V_RUN
VRAM7 VRAM8
MDB[32..63] MDB[32..63]
K8 E3 MDB40 K8 E3 MDB53
VDD DQL0 MDB43
VDD DQL0 MDB51
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 MDB47 N1 F2 MDB55
VDD DQL2 MDB44
VDD DQL2 MDB49
R9 F8 R9 F8
B2 VDD DQL4 H3 DY DY DY B2 VDD DQL4 H3
D9 H8 MDB45 D9 H8 MDB48
VDD DQL5 MDB42
VDD DQL5 MDB52
G7 VDD DQL6 G2 G7 VDD DQL6 G2
D R1 H7 MDB46 R1 H7 MDB50 D
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDB36 D7 MDB61
DQU0 MDB35
DQU0 MDB62
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 MDB39 A1 C8 MDB58
C8806 C8807 VDDQ DQU2 MDB32 C8817 C8818 VDDQ DQU2 MDB59
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 MDB37 C9 A7 MDB63
DIS DIS D2 VDDQ DQU5 A2 DIS DIS D2 VDDQ DQU5 A2
E9 B8 MDB38 E9 B8 MDB57
F1 DQU7 A3 F1 DQU7 A3
VDDQ VDDQ
H9 VDDQ H9 VDDQ
H2 VDDQ C7 QSBP_4 H2 VDDQ C7 QSBP_7
DQSU DQSU
DQSU# B7 QSBN_4 DQSU# B7 QSBN_7
VRAM7 _ VREF H1 VRAM8 _ VREF H1
VRAM8 _ VREF VREFDQ VRAM7 _ VREF VREFDQ
M8 VREFCA DQSL F3 QSBP_5 M8 VREFCA DQSL F3 QSBP_6
1 2 VRAM_ZQ7 L8 G3 QSBN_5 1 2 VRAM_ZQ8 L8 G3 QSBN_6
R8803 243R2F-2-GP
ZQ DQSL# R8804 243R2F-2-GP
ZQ DQSL#
DIS DIS
ODT K1 ODTB1 ODT K1 ODTB1
MAB0 N3 A0 MAB0 N3 A0
MAB2 P3 A2 CS# L2 CSB1#_0 MAB2 P3 A2 CS# L2 CSB1#_0
MAB3 N2 RESET# T2 MEM_RST MAB3 N2 RESET# T2 MEM_RST
A3 A3
MAB6 R8 A6 NC#T7 T7 MAB6 R8 A6 NC#T7 T7
MAB7 R2 A7 NC#L9 L9 MAB7 R2 A7 NC#L9 L9
MAB8 T8 A8 NC#L1 L1 MAB8 T8 A8 NC#L1 L1
MAB9 R3 A9 NC#J9 J9 MAB9 R3 A9 NC#J9 J9
MAB10 L7 A10/AP NC#J1 J1 MAB10 L7 A10/AP NC#J1 J1
C R7 R7 C
MAB11 A11 MAB11 A11
MAB12 N7 A12/BC# MAB12 N7 A12/BC#
MAB13 T3 J8 MAB13 T3 J8
A13 VSS A13 VSS
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VSS M9 VSS M9
VSS J2 VSS J2
B_BA0 M2 BA0 VSS P9 B_BA0 M2 BA0 VSS P9
20090902 B_BA1 N8
M3
BA1 VSS
G8
B3
B_BA1 N8
M3
BA1 VSS
G8
B3
B_BA2 BA2 VSS B_BA2 BA2 VSS
VSS T1 VSS T1
VSS A9 VSS A9
CLKB1 J7 CK VSS T9 CLKB1 J7 CK VSS T9
CLKB1# K7 CK# E1 CLKB1# K7 CK# E1
VSS VSS
VSS P1 VSS P1
CKEB1 K9 CKE CKEB1 K9 CKE
R8807 R8808 G1 G1
56R2J-4-GP 56R2J-4-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS DQMB4 D3 E8 DQMB7 D3 E8
DMU VSSQ DMU VSSQ
DQMB5 E7 DML VSSQ E2 DQMB6 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
GPU _ CLKB1 _ T D1 D1
VSSQ VSSQ
W EB1# L3 W E# VSSQ B9 W EB1# L3 W E# VSSQ B9
CASB1# K3 B1 CASB1# K3 B1
C8803 CAS# VSSQ CAS# VSSQ
DIS RASB1# J3 RAS# VSSQ G9 RASB1# J3 RAS# VSSQ G9
SCD01U50V2KX-1GP
K4W 1G1646E-HC12-GP K4W 1G1646E-HC12-GP
B DIS DIS B
20090902 20090902
+1.5V_RUN +1.5V_RUN
R8801 R8805
2K1R2F-GP 2K1R2F-GP
DIS DIS
VRAM7 _ VREF VRAM8 _ VREF
C8801 C8804
R8802 R8806
2K1R2F-GP SCD1U16V2ZY-2G P 2K1R2F-GP SCD1U16V2ZY-2GP
DIS DIS DIS DIS
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3
Berry X00
5 4 3 2 1
5 4 3 2 1
SSID = Video.PWR.Regulator RT8208BGQW for +VGA_CORE
D D
+PW R_SRC
DY DY
DIS DIS DIS
+5V_ALW
PU8902 Vout=0.75V*(R1+R2)/R2
SI7686DP-T1-GP
PR8910 DIS Design Current = 21.94A

PC8908 +GFX _ CORE _ TON 1 DIS 2
24.14A<OCP< 28.53A
DIS
SC1U10V2KX-1GP 249KR2F-GP
PU8901
PR8902
PC8906
+GFX_CORE_B OOT_C
+VGA_CORE
PR8903 16 13 +GFX_CORE_BOO2 DIS 1 1 DIS2
TON BOOT 1R3J-L1-GP
2 DIS 1 9 PL8901
10R2F-L-GP VDDP +GFX _ CORE _ UGATE SCD1U25V3KX-G P
UGATE 12
+GFX _ CORE _ VDD 2 11 +GFX _ CORE_ PHASE 1 2
VDD PHASE +GFX _ CORE _ LGATE IND-D56UH-12-GP
LGATE 8
DIS
DIS 4 7 PTC8901
RUNPW ROK PGOOD G0 PW RCNTL_0
C 1 2+GFX _C O RE _CS 10 3 +GFX _ CORE _ FB PU8903 PU8904 DY PR8906 PTC8902 PTC8903 C
PR8905 6K34R2F-GP CS DIS FB
14 2D2R5F-2-GP
G1 PW RCNTL_1
5 PW RCNTL _ 1#
+GFX _ CORE _ EN _ R 15
D1
6 PW RCNTL _ 0# DY DY D IS
DIS
PC8904
EM/DEM D0
DIS
SC1U10V2KX-1GP 17 1 +GFX _ CORE _ VOUT DIS D IS
GND VOUT
RT8208BGQW -GP
+GFX _ CORE _ VOUT
DY DY
RT8208B:74.08208.A73 DY PC8910
PR8908
10KR2F-2-GP
DIS
PR8921 1 DY 2 0R2J-2-GP
GFX_CORE_EN
PR8920 1 2 10KR2J-3-GP +GFX _CORE _ EN _ R
PM_SLP_S3# DIS
+GFX _ CORE _ FB
PC8912
SCD1U6D3V2KX-GP
PR8909 PR8911 PR8912
DIS 150KR2F-L-GP 49K9R2F-L-GP 49K9R2F-L-GP
DIS DIS
B B
PWRCNTL_0 PWRCNTL_1 +VGA_CORE

H H 0.9V
L H 0.95V
H L 1.05V
L L 1.1V
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

A
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D <Core Design> A
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L

H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 Wistron Corporation
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
RT8208B _ +VGA _ CORE

A3
Arsenal DJ1 Discrete X00
5 4 3 2 1
5 4 3 2 1
APL5930 for +1.8V_RUN_VGA
+1.8V_RUN_VGA_P +1.8V_RUN_VGA
PG9002
1 2
+3.3V_RUN +1.8V_RUN_VGA_VIN +5V_RUN +1.8V_RUN_VGA_VIN
GAP-CLOSE-PW R
PG9003
1 2
D D
PG9001 PC9002 PC9003 PC9004
2 1
SC1U10V2KX-1GP
DIS DY GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG9004
DIS
2 1
+5V_ALW GAP-CLOSE-PW R
Design Current =1.13A
PU9001
RUNPW ROK 7 5
POK VIN#5
R9006 9 +1.8V_RUN_VGA_P
VIN#9
DIS 100KR2J-1-GP
DIS 1.8V_VGA_RUN_EN_C
1.8V_VGA_RUN_EN 1 8 3
EN VOUT#3
PR9002 0R2J-2-GP 4
VOUT#4
Vo=0.8*(1+(R1/R2)) PC9001 DIS PR9003
PC9005 PC9006
DIS
PC9007
DY FB
2 DY
DIS
APL5930KAI-TRG-GP
DIS
SO-8-P
PQ9001 +1.8V_RUN_VGA
DIS 2N7002EDW -GP
84.27002.F3F
DIS Vout=0.8V*(R1+R2)/R2 PR9006
13K3R2F-L1-GP
1 .8V _ DIS 1
R9005
2
10R2J-2-GP
DIS
1.8V _ VGA _ RUN_ EN

C C
+3.3V_RUN_VGA APL5930KAI for +1.0V_RUN_VGA

1
DIS +5V_ALW +1.5V_SUS
R9001 0R2J-2-GP
+3.3V_RUN_VGA
Q9001
PC9008 PC9009 PC9010
+3.3V_RUN S
DY D DIS DY
SI2301CDS-T1-GE3-GP SC1U10V2KX-1GP DIS
Id: 2A
R9002
DY Rds: 0.15ohm
100KR2J-1-GP +3.3V_ALW
3.3V _ ALW _ 1 PU9002

+1.0V_RUN_VGA
Design Current: 1.51A
R9007 7 5
RUNPW ROK POK VIN#5
DIS 100KR2J-1-GP
VIN#9
9 +1.0V_RUN_VGA
Q9002 R9004
DY 100R2J-2-GP 1
DIS 2
1.0V_RUN_VGA_EN_C
8 3
2N7002EDW -GP 1.0V_RUN_VGA_EN EN VOUT#3
PR9007 0R2J-2-GP
DY VOUT#4
4
PC9014
84.27002.F3F PC9011 DIS PR9009 PC9012 PC9013
DY FB
2 DIS DIS DY
DIS
3.3V _ RUN _ VGA _ 1 APL5930KAI-TRG-GP
B B
SO-8-P
3.3V_RUN_VGA_EN
PQ9002
DIS 2N7002EDW -GP
5930 _ 1. 0VRUN _ FB
84.27002.F3F +1.0V_RUN_VGA
1 .0V _ DIS 1
DIS
2 Vout=0.8V*(R1+R2)/R2 PR9011
R9010 10R2J-2-GP 32K4R2F-1-GP

DIS
1.0V _ RUN _ VGA_ EN
A A
<Core Design>
Wistron Corporation
Title
DISCRETE VGA POWER

C Berry X00
5 4 3 2 1
5 4 3 2 1
D15 Intel-Power Up Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1
T1
PCH_RTCRST#
PCH_RTCRST#
+PWR_SRC
+PWR_SRC T2
T2
+3.3V_RTC_LDO
+3.3V_RTC_LDO
T3 KBC GPIO36 control
D
S5_ENABLE
Press Power button D
KBC_PWRBTN_EC# KBC_PWRBTN_EC# GPIO3
T4
+5V_ALW EC_ENABLE# (GPIO51) keep low
T5 T3
+KBC_PWR
+3.3V_ALW T4 KBC GPIO36 control
T6
S5_ENABLE
+5VALW_PCH_VCC5REFSUS T5
+5V_ALW
T6 +5V_ALW & +3.3V_ALW need meet 0.7V difference
+15V_ALW T7
T8 TPS51125 to KBC GPIO46 +3.3V_ALW
T7 +5V_ALW & +3.3V_ALW need meet 0.7V difference
3V_5V_POK
PCH to KBC GPI94 +5VALW_PCH_VCC5REFSUS
SUS_PWR_DN_ACK T9
KBC GPIO43 to PCH +15V_ALW T8
T10 T9 TPS51125 to KBC GPIO46
PCH_RSMRST#(EC Delay 40ms) >10ms
T11 PCH to KBC GPIO00 3V_5V_POK
T10 KBC GPO84 to PCH
PCH_SUSCLK_KBC
PM_PWRBTN#
PCH to KBC GPI94
AC_PRESENT_EC T12 <200ms
SUS_PWR_DN_ACK T11
KBC GPIO43 to PCH
PCH_RSMRST# T12 >10ms
T13
PCH to KBC GPIO01
Press Power button
PCH_SUSCLK_KBC
AC KBC_PWRBTN_EC# KBC_PWRBTN_EC# GPIO3
3V_5V_POK
T13 KBC GPO84 to PCH DC PCH_SUSCLK_KBC
AC PM_PWRBTN# T14
PM_SLP_S4#
AC PM_PWRBTN# T15
T14 PM_SLP_S3# >30us
T16 KBC GPO16 to LAN
PM_LAN_ENABLE
PM_SLP_S4# T 17
T15
+3.3V_LAN
PM_SLP_S3# >30us
C
T16 KBC GPO16 to LAN C
+1.5V_SUS T18
PM_LAN_ENABLE
T 17
+V_DDR_REF(0.9V) T19
+3.3V_LAN +5V_RUN & +3.3V_RUN need meet 0.7V difference
+5V_RUN T20
+1.5V_SUS T18
+3.3V_RUN T21
+V_DDR_REF(0.9V) T19 T 22
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
+5V_RUN T20
+1.5V_RUN T23 H_PWRGD
+3.3V_RUN T21 T25 >1ms
T 22
+1.8V_RUN T24
+5VS_PCH_VCC5REF KBC GPIO71 to RT8208B
GFX_CORE_EN(Discrete only) T26
+1.5V_RUN T23 H_PWRGD
T25 >1ms T 27
+VGA_CORE(Discrete only)
+1.8V_RUN T24 T28 KBC GPIO30 to APL5930
KBC GPIO71 to RT8208B
1.0V_RUN_VGA_EN(Discrete only)
GFX_CORE_EN(Discrete only) T26
T29
T 27 +1.0V_RUN_VGA(Discrete only)
+VGA_CORE(Discrete only) T 30 KBC GPIO66 to APL5930
T28 KBC GPIO30 to APL5930
1.8V_VGA_RUN_EN(Discrete only)
1.0V_RUN_VGA_EN(Discrete only)
T31
T29 +1.8V_RUN_VGA(Discrete only)
+1.0V_RUN_VGA(Discrete only) T32 KBC GPI95
T 30 KBC GPIO66 to APL5930 +3.3V_RUN_VGA_EN(Discrete only)-->DY reserved
1.8V_VGA_RUN_EN(Discrete only) T33
T31 +3.3V_RUN_VGA(Discrete only) -->Reserved for sequence
+1.8V_RUN_VGA(Discrete only)
T 32 KBC GPI95
+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved RUNPWROK T34
T33
T35
+3.3V_RUN_VGA(Discrete only) -->Reserved for sequence +1.05V_VTT
TPS51218 to KBC GPI34
T36
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)
RUNPWROK T34
T37
T35 +0.75V_DDR_VTT
+1.05V_VTT
B TPS51218 to KBC GPI34 B
T36 H_VTTPWRGD T38
1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)
T37
+0.75V_DDR_VTT
H_VTTPWRGD T38
+1.05V_VTT
T39
CPU to TPS51611
GFX_VR_EN(UMA only)
+1.05V_VTT
T39 T40 UMA GFX CORE Power
CPU to TPS51611 +CPU_GFX_CORE(UMA only)
GFX_VR_EN(UMA only)
T40 UMA GFX CORE Power
+CPU_GFX_CORE(UMA only)
1.5CPU_1.05VTT_PWRGD
T41 ( >99ms )
KBC GPO53 to ISL62883
IMVP_VR_ON
1.5CPU_1.05VTT_PWRGD T42
T41 ( >99ms )
KBC GPO53 to ISL62883 +VCC_CORE <3ms CPU CORE Power
IMVP_VR_ON
T42 CLK_CPU_BCLK
CPU CORE Power CLKIN_BCLK(from CK505) stable
+VCC_CORE <3ms
43 >1ms ISL62883 to CLOCKGEN
CLK_CPU_BCLK
CLKIN_BCLK(from CK505) stable CK_PWRGD
ISL62884 to KBC GPO14
T44 >1ms
43 >1ms ISL62883 to CLOCKGEN IMVP_PWRGD T45
CK_PWRGD 1.5CPU_1.05VTT_PWRGD Delay 10m s
ISL62884 to KBC GPO14 T46 >5ms
T44 >1ms
IMVP_PWRGD T45 KBC GPIO47 to PCH
1.5CPU_1.05VTT_PWRGD Delay 10m s PM_PWROK 3ms< T47 <20ms
T46 >5ms
T48 >1ms
KBC GPIO47 to PCH +1.5V_RUN_CPU T49 >100ns
PM_PWROK 3ms< T47 <20ms PM_DRAM_PWRGD (for S3 Reduction)
T48 >1ms
+1.5V_RUN_CPU T49 >100ns
H_VTTPWRGD
A PM_DRAM_PWRGD (for S3 Reduction) T50 >1ms A
PM_PWROK
H_VTTPWRGD T51 >1ms
T50 >1ms
+VCC_CORE
PM_PWROK 0.05ms< T52 <650ms
T51 >1ms
H_PWRGD
+VCC_CORE
T53 KBC LRESET#
0.05ms< T52 <650m s PLT_RST# >1ms
T54 KBC GPIO45
H_PWRGD <Core Design>
T53 KBC LRESET# PLTRST_DELAY#
T55
PLT_RST# >1ms Wistron Corporation
T54 H_CPURST# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R. O.C.
PLTRST_DELAY#
T55 Title
H_CPURST# Power Sequence
A1
Berry X00
Date: Tuesday , October 20 , 2009 Sheet 91 of 92
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Change History
A3
Berry X00
5 4 3 2 1

Berry DG15 Discrete/UMA Schematics Document Arrandale Intel PCH 2009-10-12 REV: X00

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Berry DG15 Discrete/UMA Schematics Document Arrandale Intel PCH 2009-10-12 REV: X00

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5 4 3 2 1

Berry DG15 Discrete/UMA Schematics Document

UMA:UMA platform installed

PCB P/N : 48.4HH01.0SA

DDR3 Revision : 09909-SA SYSTEM DC/DC

PCI/PCI BRIDGE SYSTEM DC/DC

2CH SPEAKER Wistron Corporation

ISL62883 TPS51218 TPS51611

RT9715BGF AO4468 RT9715BGF AO4468 PA102FMG

+5V_USB1 +5V_RUN +5V_USB2 +3.3V_RUN +3.3V_RUN_VGA +3.3V_LAN

+1.8V_RUN_VGA +LCDVDD +3.3V_RUN_CARD +1.2V_LOM

Regulator LDO Switch

Power Block Diagram

PCH_ SMB _CLK

SDA SMBus address:12

SDVO_CTRLDATA PCH_ HDMI_ DATA

SRN2K2J-1-GP Minicard GPIO73/SCL2 KBC_SCL1

CRT_DDC_DATA PCH_ CRT _DDCDATA

DDC2CLK VGA _ CRT _DDCCLK

DDC2DATA VGA _ CRT _DDCDATA

+3.3V_RUN DIS +5V_RUN

CRT_ DDCDATA_ CON

SMBUS Block Diagram

Thermal Block Diagram Audio Block Diagram

Place near CPU

DP3 EMC2102_ DP3

PCH Strapping Processor Strapping

GPIO33 Default: Do not pull low.

PCIE Routing USB Table SATA Table

LANE6 RESERVED 7 HM55 no support

13 CAMERA Table of Content

4 6 CLK _ VGA _ 27M _ NSS_ R 4 DIS 1 RN701 CLK_VGA_27M_NSS

C712 82.30005.901 C713

Clock Generator SLG8SP585

PEG_ICOMPI B26 PEG _IRCOMP _ R R801 1 2 49D9R2F-GP

FDI_TX5 PEG_TX#1 M35 _ _ DIS1 C815 SCD1U16V2KX-3GP PEG _ TXN14

FDI_TX7 PEG_TX#3 M30 _ _ DIS1 C813 SCD1U16V2KX-3GP PEG _ TXN12

PEG_TX#4 L31 _ _ DIS1 2 C812 SCD1U16V2KX-3GP PEG _ TXN11

FDI_FSYNC0 PEG_TX#5 K32 _ _ DIS1 2 C811 SCD1U16V2KX-3GP PEG _ TXN10

FDI_FSYNC1 PEG_TX#6 M29 _ _ DIS1 C810 SCD1U16V2KX-3GP PEG _ TXN9

FDI_INT PEG_TX#8 K29 _ _ DIS1 C808 SCD1U16V2KX-3GP PEG _ TXN7

PEG_TX#9 H30 _ _ DIS1 C807 SCD1U16V2KX-3GP PEG _ TXN6

FDI_LSYNC0 PEG_TX#10 H29 _ _ DIS1 C806 SCD1U16V2KX-3GP PEG _ TXN5

FDI_LSYNC1 PEG_TX#11 F29 _ _ DIS1 2 C805 SCD1U16V2KX-3GP PEG _ TXN4

PEG_TX#12 E28 _ _ DIS1 2 C804 SCD1U16V2KX-3GP PEG _ TXN3

PEG_TX#13 D29 _ _ DIS1 2 C803 SCD1U16V2KX-3GP PEG _ TXN2

PEG_TX2 M32 _ _ DIS1 C830 SCD1U16V2KX-3GP PEG _ TXP13

PEG_TX3 L30 _ _ DIS1 C829 SCD1U16V2KX-3GP PEG _ TXP12

PEG_TX4 M31 DIS1 2 C828 SCD1U16V2KX-3GP PEG_TXP11

PEG_TX6 M28 _ _ DIS1 2 C826 SCD1U16V2KX-3GP PEG _ TXP9

PEG_TX7 H31 _ _ DIS1 C825 SCD1U16V2KX-3GP PEG _ TXP8

PEG_TX8 K28 _ _ DIS1 C824 SCD1U16V2KX-3GP PEG _ TXP7

PEG_TX9 G30 _ _ DIS1 C823 SCD1U16V2KX-3GP PEG _ TXP6

PEG_TX10 G29 _ _ DIS1 2 C822 SCD1U16V2KX-3GP PEG _ TXP5

PEG_TX12 E27 _ _ DIS1 2 C820 SCD1U16V2KX-3GP PEG _ TXP3

PEG_TX13 D28 _ _ DIS1 2 C819 SCD1U16V2KX-3GP PEG _ TXP2

PEG_TX14 C27 _ _ DIS1 C818 SCD1U16V2KX-3GP PEG _ TXP1

PEG_TX15 C25 _ _ DIS1 2 C817 SCD1U16V2KX-3GP PEG _ TXP0

H_THERMTRIP# AK15 RN904

AN28 XDP _ TCLK SM _ RCOMP _ 1 R914 1 2 24D9R2F-L-GP

For EMI PLT_RST# 1 2 PLT _ RST# _ R AL14 RSTIN# SM _ DRAMRST#

EC906 EC905 EC904 EC903 EC902 EC901 U901

SSID = CPU CPU1D 4 OF 9