Programmable Logic Controller

A programmable logic controller (PLC) is a specialized

computer used to control machines and process.

It uses a programmable memory to store instructions

and execute specific functions that include On/Off control,
timing, counting, sequencing, arithmetic, and data handling.
PLC System
Discrete Input
A discrete input also referred as digital input is an input that is
either ON or OFF are connected to the PLC digital input. In the
ON condition it is referred to as logic 1 or a logic high and in the
OFF condition maybe referred to as logic o or logic low.

Normally Open Pushbutton

Normally Closed Pushbutton

Normally Open switch

Normally Closed switch

Normally Open contact

Normally closed contact

Analog Input
An analog input is an input signal that has a continuous
signal. Typical inputs may vary from 0 to 20mA, 4 to 20mA
or 0 to10V. Below, a level transmitter monitors the level of
liquid in the tank. Depending on the level Tx, the signal to the
PLC can either increase or decrease as the level increases
or decreases.
Level Transmitter IN

PLC
Analog
Tank Input
Module
Digital Output

A discrete output is either in an ON or OFF condition. Solenoids,

contactors coils, lamps are example of devices connected to the
Discrete or digital outputs. Below, the lamp can be turned ON or
OFF by the PLC output it is connected to.
OUT

PLC
Lamp
Digital
Output
Module
Analog Output

An analog output is an output signal that has a continuous

signal. Typical outputs may vary from 0 to 20mA, 4 to 20mA
or 0 to10V.
Electric to pneumatic transducer

OUT
E Supply air
PLC 0 to 10V P

Analog
Output
Module
Pneumatic control valve
LadderDiagram
❑ Primary programming language for PLCs.
❑ Other programming methodsinclude:
➢ Function block diagrams(FBDs)
➢ Structured text (ST)
➢ Instruction List(IL)
➢ Sequential function charts(SFCs)
❑Visual and Graphical language unlike textual high-level, such as C, C++, Java…
❑ Derived form relay logic diagrams
❑ Primitive Logic Operations
❖ OR
❖ AND
❖ NOT
 LadderDiagram
Terminologies
❑ Power Rails -Pair ofvertical lines
❑ Rungs -Horizontal lines
❑ Contacts A, B, C, D… arranged on
rungs
❑ Note in PLCLadder Logic: Rungs

➢ No Real Power Flow (like in

relay ladder)
➢ There must be continuous
path through the contacts to
energize the output

Power Rails
Binary InputDevices

Device One/ZeroInterpretation

Limit switch Contact/no contact

Photodetector Contact/no contact

Pushbutton switch On/off

Timer On/off

Control relay Contact/no contact

Circuit breaker Contact/no contact

Binary OutputDevices

Device One/Zero Interpretation

Motor On/off

Alarm buzzer On/off

Lights On/off

Controlrelay Contact/no contact

Valves Closed/open

Clutch Engaged/not engaged

Solenoid Energised/not energised

Anatomy of LadderDiagram

o
Anatomy of LadderDiagram
❑ Input instructions are entered on the left
❑ Output instructions are entered on the right
❑ The power rails simulate the power supply lines
➢ L1and L2 for AC circuits and +24V and ground for DC circuits
❑ Most PLCs allow more than one output per rung
❑ The processor (or “controller”) scans ladder rungs from top-to-bottom
and from left-to-right.
➢ The basic sequence is alteredwhenever jump or subroutine
instructions are executed.
I/O address format for the SLC family of PLCs.
Program Scan
During each program scan cycle, the processor
reads all the inputs, takes these values, and
energizes or de-energizes the outputs according to
the user program.
The time it takes to complete a scan cycle is a
measure of how fast the controller can react to
changes in inputs.

If a controller has to react to

an input signal that
changes states twice during
the scan time, it is possible
that the PLC will never be
able to detect this change.
The scan time is a function of:
• The speed of the processor module
• The length of the ladder program
• The type of instructions executed
• The actual ladder true/false conditions

The PLC computes the scan time each

time the END instruction is executed.

Typical scan time data include the

maximum scan time and the last scan time.
Scan process applied to a single rung program.
Timers and Counters
Timers

◼ Timers are used to delay actions

❑ Keep an output on for a specified time after an input turns off
❑ Keep an output off for a specified time before it turns on

◼ Timing functions are vital in PLC applications

❑ Cycle times are critical in many processes

◼ Many PLCs use block-type timers and counters

❑ Compliance with IEC 61131-3 standards
 Block-Type Timer
Example

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Above Timer is labeled T4:0

Timer Attributes
Time Base:
◼ Timers are typically programmed with several different time bases

❑ 1 second, 0.1 second, 0.01 second, 0.001 second

❑ Suppose time base is set to 0.1 and Delay increments is set to 50 →
timer has 5 seconds delay (0.1 x 50)
 Block-Type Timer
Example

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Preset Attribute:
◼ Preset value is the number of time increments timer must count
before changing the state of the output
❑ Time Delay = Preset value x Time Base ( refer to previous example)
❑ Preset can be constant or a variable
Block-Type Timer
Example
TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Accum Attribute:
◼ [Rockwell] Timers have one input. When the input transits from low
to high, the timer will begin timing (Accum value)
❑ Timers that do not lose their accumulated time when the enable input line
transitions to low again are known as Retentive Timers
❑ Retentive Timers continue to maintain accumulated time and increment
the time when the input line goes to high again
❑ Non-retentive Timers lose the accumulated time whenever the enable
input transitions to low
◼ The accumulated time resets to zero
Timer Block
Numbering System
TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Above Timer is calledT4:0

T File Type (Timer)

4 File Number of the Timer
Timer T4:0 : Delimiter
0 Element (The actual timer number)
 Block-Type Timer
Example

TON
I:2 TIMER ON DELAY EN
Timer T4:0
Time Base 0.1
Preset 50 DN
Accum 0

Timer On (TON) Delay

Timer On Delay Instruction:

◼ Turns an output on after a Timer has been on for a preset time
interval
❑ TON starts accumulating time when rung becomes true
❑ Continue accumulating until one of the following occurs:
◼ Accumulated (Accum) value equals preset value
◼ The rung conditions becomes false
Block-Type Timer
Status Bits (EN, DN, TT)

Timer Status bits can be used in ladder logic

Bit Set When Remains Set Till

Timer done Accumulated value is Rung conditions go false
equal to or greater than the
Bit (bit 13
preset value
or DN)
Timer Timing Rung conditions are true Rung conditions go false or
and the accumulated value when the done bit is set
bit (bit 14 or
is less than the preset
TT) value
Timer enable Rung conditions are true Rung conditions go false
bit (bit 15 or
EN)
Using Status Bits in Ladder Logic EN
Bit

Timer Enabled bit can be used in ladder logic

◼ Consider timer T4:0 from the example:
❑ The Timer Enable (EN) bit is set immediately when the rung
goes true. It stays set until the rung goes false
◼ The EN bit indicates that the timer T4:0 is enabled

❑ The EN bit from any timer can be used for logic:

◼ T4:0/EN could be used as a contact in a ladder
Using Status Bits in Ladder Logic TT Bit

Timer Timing (TT) bit can be used in ladder

logic
◼ Consider timer T4:0 from the example:
❑ The Timer Timing (TT) bit is set when the rung goes true. It stays
set until the rung goes false or the Timer Done (DN) bit is set (i.e.,
when accumulated value equals preset value)

◼ The TT bit from any timer can be used for logic:

❑ T4:0/TT could be used as a contact in a ladder

Using Status Bits in Ladder Logic DN Bit

Timer Done bit can be used in ladder logic

◼ Consider timer T4:0 from the example:
❑ The Timer Done (DN) bit is not set until the accumulated value is
equal to the preset value. It stays set until the rung goes false
◼ When DN bit is set, it indicates Timing operation is complete

◼ The DN bit from any timer can be used for logic:

❑ T4:0/DN could be used as a contact in a ladder

Using Other Bits in Ladder Logic
Preset (PRE)
◼ PRE can be used in ladder logic
❑ T4:0.PRE would access the preset value of T4:0
◼ Note, PRE value is an integer

◼ Accumulated Value (ACC)

❑ T4:0.ACC would access the accumulated value of timer T4:0

◼ Time Bases are available in 1 second intervals, 0.01 and 0.001

second intervals
Time Base Potential Time Range
❑ Potential time ranges:
1 Second To 32,767 intervals (up to
9.1 hrs)
0.01 Second To 32,767 intervals (up to
5.5 minutes)
0.001 Second To 32,767 intervals (up to
0.546 minutes)
What if a longer time is needed?
Memory Storage
Timers

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits
EN TT DN Internal Use 0 T4:0
Preset Value 1 T4:0.PRE
Accumulated Value 2 T4:0.ACC

◼ Current status of timer bits (EN, TT and DN) stored in first 16 bits
◼ PRE value is held in the second 16 bit of timer storage
◼ Third 16 bit holds accumulated value of timer
TON Timer
Ladder Diagram
TON
I:2 TIMER OFF DELAY EN
Timer T4:0
Time Base 1.0
Preset 180 DN
3
Accum 0
T4:0
O:5

TT 1

T4:0
O:5

2
DN

◼ When input I:2/3 is true → timer begins to increment the accumulated value of TON Timer
T4:0 in 1 second intervals
◼ The TT bit is used in rung 2 to turn on Output O:5/1, while the timer is timing (ACC <PRE)
◼ The DN bit of timer 4:0 is used in rung 3 to turn an output O:5/2 when the timer is done
timing (ACC = PRE)
❑ Note: the Preset for this timer is 180 → The timer will have to accumulate 180 1-second intervals to time
out
❑ Note: This is a non-retentive timer: If Input I:2/3 goes low before 180 is reached, the accumulated value
is reset to zero
Timer OFF Delay
TOF
Timer OF (TOF) -Delay
Used to turn an output On or OFF after rung has
been off for a desired time
1. TOF starts to accumulate time when the rung becomes false

2. It continues to accumulate time until the accumulated value

equals the preset value or the rung becomes true

3. The timer enable bit (EN bit 15) is set when the rung becomes
true. It is reset when the rung becomes false and ACC < PRE or
the DN bit is reset (ACC = PRE)

4. The done bit (DN bit 13) is reset when the ACC value is equal to
the PRE value. The DN bit is set when the rung becomes true
Timer Off Delay
TOF Bits

Bit Set When Remains Set Till

Timer done Rung conditions are true Rung conditions go false

and the accumulated value
Bit (bit 13
is greater than or equal to
or DN) the preset value
Timer Timing Rung conditions are false Rung conditions go true or
and the accumulated value when the done bit is reset
bit (bit 14 or
is less than the preset
TT) value
Timer enable Rung conditions are true Rung conditions go false
bit (bit 15 or
EN)
Ladder Logic
TOF Timer TOF
I:2 TIMER OFF DELAY EN
Timer T4:0
Time Base 1.0
Preset 180 DN
3
Acc 0
T4:0
This output is energized while the timer is timing O:5

TT 1

T4:0
This output is energized when the timer is done timing O:5

DN 2

Input I:2/3 is used to enable the timer

◼ When input I:2/3 transitions from true to false → The ACC value is incremented
as long as the input stays false and ACC ≤ PRE
◼ The TT bit for timer T4:0 (T4:0/TT) is used to turn output O:5/1 on while timer is
timing
◼ The DN bit of timer 4:0 (T4:0/DN) is used to turn on output O:5/2 when the timer
has completed the timing (ACC = PRE)
Retentive Timer On
RTO
RTO Instruction:
◼ Used to turn an output On after a set time period

1. The RTO timer is an accumulating timer. It retains the ACC

value even if the rung goes false

◼ To zero the ACC value, use a reset (RES) instruction in another rung with
the same address as the RTO

2. The status bits can be used as contacts in the ladder diagram

Retentive Timer On
Status Bits

Bit Set When Remains Set Till

Timer done Accumulated value The appropriate
≥ preset value RES Instruction is
Bit (bit 13
enabled
or DN)
Timer Timing Rung conditions are true Rung conditions go false
and the accumulated value or when the done bit is set
bit (bit 14 or
< preset value
TT)

Timer enable Rung conditions are true Rung conditions go false

bit (bit 15 or
EN)
Timers
◼ Delay = Time base x Preset
◼ On Timer
◼ Off Timer
◼ Retentive timer
Memory Storage
Timers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits
EN TT DN Internal Use 0 T4:0
Preset Value 1 T4:0.PRE
Accumulated Value 2 T4:0.ACC

◼ Timer
◼ Time base
◼ Preset
◼ Accumulator
 TON TOFF RTO

Bit Set When Remains Set Till Set When Remains Set Till Set When Remains Set Till

Timer done Bit (bit 13 or DN) Accumulated value ≥ preset value Rung conditions go false Rung conditions are true Rung conditions go false Accumulated value The appropriate RES
and the accumulated value ≥ preset value Instruction is enabled
≥ preset value

Timer Timing bit (bit 14 or TT) Rung conditions are true and the Rung conditions go false or Rung conditions are false Rung conditions go true Rung conditions are Rung conditions go false
accumulated value < preset when the done bit is set and the accumulated value or when the done bit is true and the or when the done bit is set
value is less than the preset reset accumulated value
value < preset value

Timer enable bit (bit 15 or EN) Rung conditions are true Rung conditions go false Rung conditions are true Rung conditions go false Rung conditions are true Rung conditions go false
 Cascading Timers

◼ When Application requires longer

time delays than a single timer can
provide
❑ Use multiple timers
◼ When the first timer times out, it becomes
an input to start the second timer timing

Two timers are used to extend the time delay

◼ The first timer output, T4:0/DN, acts as input to second timer
❑ When Input I:2.0 becomes true, timer 1 begins to count to 32,767 seconds (the limit of the timers)
◼ When it gets to 32,767 seconds, output T4:0/DN turns on
◼ This energizes timer T4:1
◼ Timer T4:1 times to 7233 seconds (its preset value)
❑ T4:1/DN turns on
Counters
◼ Counting is critical in industrial applications
❑ Suppose 24 bottles go into a case
❑ Then the 24th bottle must be sensed by the PLC and the case is sealed
◼ Primary Counter Types
❑ UP Counters - PLC sense how many finished products leaving
the machine
❑ Down Counters- PLC sense how many parts are left

❑ Up/Down Counters - PLC monitors an automated storage

system to track how many are coming and how many are
leaving to determine total number in stock
❑ Choice used depend on the task
 Counters
Attributes
◼ Counters usually use low-to-high transition from an input to trigger the
counting action
◼ Counters count the number of low-to-high transitions on the input
line
◼ Counters also have a reset instruction to clear the accumulated count
Accessing Counter Values

Addressing C5:0

To use the Done Bit: C5:4.DN

To use the Preset Value C5:4.PRE

To use the Accumulated Value C5:4.ACC

Memory Storage
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Element
CU DN OV Internal Use 0 C5:0
Preset Value 1 C5:0.PRE
Accumulated Value 2 C5:0.ACC
 CTU Counter Bits
Bit Set When Remains Set Till

Count-up Overflow bit (bit 12 or OV) Accumulated value wraps around to -32,768 A RES instruction that has same address as the
(from CTU instruction is executed or the count is
+32,767) and continues up from there towards decremented less than or equal to
zero +32,767 with a CTD instruction

Done bit The accumulated value is The accumulated value becomes less than
(bit 13 or DN) => the preset value the preset value

Count-up enable bit (bit 15 or CU) Rung conditions are true Rung conditions go false or a RES instruction
that has the same address as the CTU
instruction is enabled
Count-Up Counter
Ladder Diagram

Input I:2/3 is used to enable the counter

◼ Each time I:2/3 makes a low-to-high transition, the counter ACC value gets incremented by1
◼ The DN bit is set when the ACC value ≥ the Preset value
◼ The DN bit of C5:0 (C5:0/DN) is used to turn on O:5/1 when ACC ≥ Preset value The OV bit of C5:0
(C5:0/OV) is used to set O:5/2 when <What happens>?
 Count-Up Counter
Ladder Diagram

The OV bit of C5:0 (C5:0/OV) is used to set O:5/2

if the count reaches +32,767
Bit 1 of contact I:2/1 is set to true(1) this causes the RES instruction to reset CTU C5:0’s ACC value (i.e., “accum”) to zero
Count-Down Counter
Ladder Diagram
Input I:2/3 is used to enable the counter
Each time input I:2/3 makes a 0 1 transition, the counter ACC value gets decremented by1
The DN bit is set when the ACC value ≥ the Preset value
The DN bit of C5:0 (C5:0/DN) is used to turn output O:3/1 on when Accum ≥ Preset value The UN bit of C5:0 (C5:0/UN) is used
to set OUTPUT O:3/2 ON when the ACC value underflows (-32,768)
Input I:2/1 is used to reset the C5:0’s ACC value to zero
 CTU Counter Bits
Bit Set When Remains Set
Till
Count-up Accumulated value A RES instruction
wraps around to -32,768 that has same
Overflow bit (bit
(from address as the
12 or OV) +32,767) and continues up CTU instruction is
from there towards zero executed or the
count is
decremented less
than or equal to
+32,767
CTD Counter Bits
with a CTD
instruction Bit Set When Remains Set Till
Done bit The accumulated value is The
(bit 13 or DN) => the preset value accumulated Count-down Underflow bit Accumulated value wraps A RES instruction that has
value becomes around to +32,768 (from: same address as the CTD
less than the (bit 11 or UN)
-32,767) and continues instruction is executed or
preset value counting from there the count is incremented
Count-up enable bit Rung conditions are true Rung conditions go greater than or equal to
(bit 15 or CU) false or a RES +32,767 with a
instruction that has CTU instruction
the same address as
the CTU instruction Done bit The accumulated value is The accumulated value
is enabled (bit 13 or DN) ≥ the preset value becomes less than the
preset value
Count-down enable bit (bit Rung conditions are true Rung conditions go false or
14 or CD) a RES instruction that has
the same address as the
CTDinstruction is enabled
Memory Storage
CTU and CTD Counter Bits
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Element
CU CD DN OV UN Internal Use 0 C5:0
Preset Value 1 C5:0.PRE
Accumulated Value 2 C5:0.ACC
Tutorial _Timer and Counters
Programmable Logic Controllers by Frank D Petruzula Fourth Edition
• Chapter 7 Problems
Q8, Q12,Q14 (page 146-148)
• Chapter 8
Q9,Q13,Q14 (page 174-175)