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G3 G3 --> S5 S5 S0 S3 S0 S4/S5 S4(S5)-->G3 G3

DC_IN DC_IN+

DCBATOUT DCBATOUT
A A

+ECVCC +ECVCC

EC[I] ECRST#
ECRST#

EC[O]ALW_ON T01 (Min. 5 ms)

ALW_ON

+3VALW/+5VALW +3VALW/+5VALW

Power
EC[I]ALW_PWRGD Switch ALW_PWRGD
Press

EC[I]PWRSW#
PWRSW#
T02 T05
(700ms) (50ms)
EC[O]PWRBTN# (From EC to PCH) T04
(150ms) PWRBTN#
T03
(5ms) For battery mode(ACIN_EC inactive):
EC[O]PM_RSMRST# (From EC to PCH) PM_RSMRST# follow ACIN_EC
PCH will wait for 4-5 seconds before de-asserting SLP_S5# & PM_SLP_S5# &PM_SLP_S4#) PM_RSMRST#
Ta (max.110ms)
EC[I]PM_SLP_S5# (From PCH to EC) PM_SLP_S5#

T8 (Min 30us)
B EC[I]PM_SLP_S4# (From PCH to EC) PM_SLP_S4# B

T9 (Min 30us)
EC[I]PM_SLP_S3# (From PCH to EC) PM_SLP_S3#
T06(1ms) T17(1ms)
EC[O]SUS_ON SUS_ON

+3VSUS/+5VSUS +3V_SUS/+5V_SUS

+1_5VSUS/DDRDIMM_VREF (0V to1.5V ->Max.2ms for DDR3) +1_5VSUS/DDRDIMM_VREF(DDR2)

(~0.3ms)Td
EC[I]SUS_PWRGD SUS_PWRGD

T07(1ms)
EC[O]RUN_ON T16 (5ms)

+3VRUN/+5VRUN

T08(5ms)
EC[O]RUN_ON1 T15(2ms)

PEX_VDD/NV_VDD/+1_05VRUN/+1_5VRUN/+1_1V_VTT/+1_8VRUN/+0_75VRUN
T09 (5ms)
(~1.8ms) Te
EC[I]RUN_PWRGD (From +1_1V_VTT VR PGOOD to EC)
C C

VTTPWRGOOD (TO CPU) Repeat Previous Repeat Previous

T16
(Delay Min 99ms)
S0 Sequence S3 Sequence
EC[O]IMVP_VR_ON (From EC to IMVP6) T13(1ms)

VHCORE

CLK_PWRGD T18(From 10 to 100us )

EC[I]IMVP_OK

CLK_CPU_BCLK (From Clock Gen TO CPU)

T24( Min 1ms )

EC[O]IMVP_PWRGD ( Form EC to PCH) T12(1ms)

T20( From 3ms to 20ms )

SYS_PWROK/PWROK/MEPWROK/LAN_RST# T21
( Min 5ms )

D D
BCLK, SRCCLK, PCICLK
Running

T23
T22( Min 100ns ) ( Min 1ms )
PM_DRAM_PWRGD (Form PCH to CPU)

T24 ( Min 1ms )

H_CPUPWRGD (From PCH to CPU) T25 ( From 1ms to 100ms )
( Min 1ms ) T26

PLT_RST# (From PCH to CPU) T32 (Min 1ms)

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