Ultra Low capacitance measurements in multilevel metallisation CMOS by using a
built-in Electron-meter
B. Froment, F. Paillardet, M. Bely, J. Cluzel*,E. Granger, M. Haond, and L. Dugoujon
Centre Commun CNET/ST Microelectronics, 850 rue J. Monnet, BP 16,38926 Crolles Cedex France
Ph: +33 4 76 92 68 34, Fax: +33 4 76 92 68 14, e-mail: benoit.froment@st.com
*CEALETI, 17 rue des Martyrs, 38000 Grenoble, France
Abstract
In this paper a new interconnect capacitance measurement
method with a sub-attoFarad (<lO-'*F) resolution is presented.
We have developed a SPD (Single Pattern Driver) which
allows to obtain directly all the coupling terms for a system of
several interconnect electrodes. A very good fit is obtained
between measurements and simulation for a state-of-the-art
0.18pm CMOS process with low-k. Moreover, we
demonstrate that this SPD can be used for process
characterisation and monitoring, and extraction tool
validation.
Introduction
The state-of-the-art CBCM method [ 11 can not give the cross-
coupling capacitance C12 between 2 electrodes (Fig. 1).
Indeed the superposition theorem can not be applied when
boundary conditions are different. Moreover, the mismatch
between the 2 CBCM branches of 0.lfF(measured in [2]) and
charge injection [3], limit the resolution. Therefore, a new
driver (based on a modified Berkeley circuit) without
mismatch and allowing all the coupling capacitance
extractions, needed to be implemented. We first give an
overview of the SPD method principle, before discussing
about the limitation of drivers based on the CBCM method.
Then results are commented, followed by the possible
applications of the SPD.
Method
In order to extract the capacitance Cij between the nets i & j,
the idea is to use a 3 step superposition method on only one
pattern (Fig.2) with the SPD (Fig.3) circuit. During the first
step Vli and Vzi are non-overlapping pulses, and all the other
gates receive Vdd. The other PMOSbi (OGkGn) are off, in
order to have no current in the other branches. The NMOSbi
are on, to make sure that the other electrode potentials are
grounded. The whole current Ii, except a negligible leakage
current (in the other branches), flows through the PMOSi. It
charges Cij, Z. Ck (Wa, k#ij), and the branchi MOS
parasitic capacitance Cpar.i. The PMOSi switches off, the
NMOSi on, and Cij, Z CL are discharged to the ground. Ii is
then integrated during several periods.
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During the second step, gate roles are reversed: Vlk=V2k=Vdd
(k#j), Vlj and VY are the non-overlapping pulses. Then the
sum of Cji=Cij, Cj, (O&Gn, k A j ) and Cp,j is measured
(Fig.2).
For the last step, the non-overlapping signals are on each side:
VIi=Vl, and V2i=Vzj. The current flows through both
branches: ZCs, Z Cj, (O&<n, k+i,j), Cpw,i, and Cw.j are
charged. COis not charged, since the potential Vdd at the end
of the charge phase is the same on each side of Cij. Finally the
combination of Ii, Ij, and Iij (Fig.2) gives COby the formula:
cij=(ii+Ij-Iij)/(vdd*fr2). Since each i j branch is used an even
number of times, the mismatch terms are subtracted, and the
resolution is improved.
An additional n+l branch allows to obtain all the capacitive
metal-substrate terms Ci0 (Fig.3). Indeed, since the left branch
has no load, the only capacitance measured is Cpar,n+l.
Assuming that the mismatch between CBCM branches is
negligible, it comes: Cpar.i-Cpar.n+l.Then Ci0 can be extracted
with the Cij knowledge. Thus n(n+1)/2 steps are required for
capacitance extraction, plus one step to obtain the metal-
substrate terms.
Method validation
The linearity between 11+12-112 and frequency is excellent
(Fig.4). Measurement repeatability of I1 shows a very good
ratio o/m=0.003% (Fig.5). The driver offset, COff,defined by
the parasitic coupling capacitance between 2 empty branches
(CofrO.05aF ATLAS simulation), is too small compared to
the precision of the Keithley238 which gives 0.5 aF. A
C=O.IaF capacitor charged with v ~ = 1 . 8 V ,carries a charge
Q=C.Va, which is around 1 electron. This means that the
SPD is able to detect the amount of charges on the capacitor
to within one electron. However, this theoretical resolution is
limited by the precision of the extern measurement system.
Charge injection
The CBCM driver types are limited by charge injection. The
Cz discharge (Fig.6) depends on C and the pulse rise time rt
[3], since C2 has not enough time to flow entirely through the
channel to the current meter. A small amount of
supplementary charge remains on C. The same problem
occurs for the NMOS (Fig.7). Finally the real average current
IEDM 99-897
is: I,,I=(Cp,+C).(Vdd+GV"+GVp).f, which can be rewritten: Conclusion
I~e~=(c,,.=ffec).v,d.f, where Cpu,eff=g(C,rt)is an effective
parasitic capacitance function of C and rt (Fig.8). If C-Cp,,,ff,, We have demonstrated the improvements obtained with a
this effect alters a lot the resolution. However, concerning the SPD: a 140 (0.1fF/O.O007fF) factor gain in the resolution, and
best resolution determination, since the branchi charges the the possibility to extract all the coupling matrix for n
load C=Cio+Cijin the first step, and C=Cio in the third step, interconnect electrodes. This makes the SPD a powerful tocd
and that Cij<<Cio, Cp,.eff remains constant, and parasitic to characterise and monitor the process, validate and calibrate
capacitance is eliminated by subtraction: g(Cio+Ci,,rt)- design extraction tools, at a very small silicon area cost.
g(Cio,rt)-Cij.Xp,,ff/X -0.005*C~<e C, (Fig. 8).
Acknowledgments
Accuracy evaluation
The authors express their thanks to A. Margain, N. Bicaii.,
To be sure that the measurement has a meaning for very low C.Lair, and to the GRESSI teams for simulation training
capacitance values, patterns (Fig.9) with different number of (G.Lecarva1, P. Rivallin, R. Klein) and measurement
crossing lines (OSfF/cross, CLEVER simulation), and resources providing (Pierre Bichon).
fringing capacitance have been measured (Fig.lO). The idea is
to use 2 parallel 17pm space metal lines, with a 2.8aF/pm References
lineic capacitance (CLEVER simulation). The line length
increase will increase the capacitance of a very small [ I ] J.C.Chen. et al. Proc. IEEE, ICMTS 97
[2] B.Froment, et al. IlTC Roc. 99, p.224
quantum, according to the formula C=Cedgc.effcci+Clineic*L. The [3] Je-hum Shieh, et al. IEEE Sol. State. Cif, apr 87
straight lines confirm the measurement goodness. Moreover,
the slope values are in perfect agreement with simulation: Reference pattern Targeted pattern
0.48fF/cross, 2.77aF/pm. Fig. 10 gives the smallest
capacitance detectable: 0.7aF for a 0.26pm line increase. This
means that the amount of charges on the load is known to
within 8 electrons.

Process characterisation

Two 135pm-long parallel fringe metal2/metal3 (width 0.4p,

space 0 . 3 2 ~ )have been measured and cleaved. Measurement
and ATLAS simulation are in perfect agreement (Fig.ll), 0 AI = (c%? + Clo- c ' ? O ) . v d d . f # C I .Vdd.f
~
except for the substrate term obtained to within the MOS Fig.1: The light electrodes receive Vm, whereas the dark ones are at the
mismatch. ground. Electrical field lines are modified by the presence of a 2* electrode.
Because of the excellent SPD resolution, a small area It implies that C'IO* CIO.Then AI=W is not proportional to C12 that can not
capacitance load can be measured. A 6 electrodes be obtained.
configuration with superposed interdigited combs (20*140p2)
measured with SPD, is compared to traditional combs ( lmm2)
used for intra-capacitance study (Table 1). SPD allows a
measurement with less dispersion since IMD, space, and
metal thickness do not vary on a 140pm length. Thus it
becomes possible to extract intra-dielectric constant with the
help of simulation with higher accuracy (Fig. 12), since
elementary dimensions are known with certitude. The
permittivity monitoring is also possible with the help of
Kelvin resistance measurement (Fig.13) which gives the width
(and the space, since the pitch is constant) and the metal
thickness. The space and metal height knowledge gives k
thanks to a formula obtained by simulated DOE. Moreover,
IMD thickness is extracted (Fig.14b) from capacitance
measurement (Fig. 14a) by an analytical formula. The use of
narrow plate allows to be closer to the design metal density Iij = [
&i .V&I.f
and to extract a 'realistic' IMD.
Fig. 2: 3 step superposition method for CIJextraction among n electrodes. Z
Cik and Cjk e h h a t e d by subtraction.

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Fig. 3: SPD circuit with n electrodes. The additional n+l branch allows to Fig. 4: Il+Iz-I,z vs frequency. The excellent linearity verify the relation:
extract the metal substrate capacitances. 1,+Iz-I1*= 2,C,,.V,.f.

Initial state
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I i Current (pA)
Fig. 5: 11 measurement repeatability: 100 values for a 5fF load measured at Fig. 6: Charge injection during PMOS switch: C1 and C2 are discharged to
lOMHz with a lOns rise time for the pulses. the current meter and to the load capacitance C.

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C load capacitance ( f q
Fig. 7: Switching charge injection in the NMOS after the capacitive load C Fig. 8: ELDO simulation of Cpar.eff vs C. The difference between 2 branches
discharge. In the initial state Vg = Vdd, in the final state Vg=O. with 2 different loads C and C', will alter the resolution by the term :
g(C,rt)-g(C'*fl).

37.2.3
IEDM 99-899
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Cross number Fringe length rising (pm)
- 10: Capacitance vs line length increase. C=C~,+CU,W~*L
Fie. 9: CaDacitance vs cross number. The linearitv confirms the measurement Fig. ~
is verified. The
accuracy. Moreover, the 0.48F/cross slope agrees with the O S f F simulation. smallest meaningfuldetectable quantity is 0.7aF.

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Dielectric constant k
Fig. 11: Comparison m&urement/simulation (ATLAS) on a 4 electrodes Fig. 12: HSQ (FOX)dielectric constant extraction: intersection between SPI)
system, for all coupling capacitance. measurement and ATLAS simulation for a 120pm dual fringe. Error on SEM
measurement and Teos permittivityis also implemented.Finally k=3 f 0.1,
I Cross-coupling I SPD Capacimeter I 1
apacitance (aF/prn] m I m I d
0 1
=men-,
Kelvin resistance
M2
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. _I 1.8
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cepadtancsmeaar-
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Fig. 13: Structure for dielectric constant monitoring. The Metal height (H)and Table 1: Mean and std. dev. of the cross-couplingcapacitance vs different
width (w) are extracted from the resistance measurements on a large line, and measurement systems. No thermic budget influence can be seen on the
a narrow line of same height, respectively. The space s is equal to pitch minus capacitance evolution vs metal level.
w. Since oxide thickness under and above metal3 is much bigger than s, small

--
IMD variations have no influence on the cross coupling capacitance. Thus, all
parameters are known to extract k with a formula obtained by a DOE.
w, = 10 pm w,= 5 pm
1111

llpL

111 = 111

Fig. 14b: Comparison real (SEM) oxide thicknesdextracted thickness by a

length system.)ummy metals maintain the same low-k thickness on the formula determined by a DOE.In the simulations low-k thickness is assumed
plates, and simulate a metal density similar to a mil circuit. to be constant on the considered patterns (across the whole wafer).

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