VERILOG HDL based FPGA design
Gary Gannot and Michiel Ligthart
Exemplar Logic, Inc.
2550 Ninth Street, Suite 101
Berkeley, Ca. 94710
(510) 849 0937
Abstract
This paper presents a logic synthesis system for
Field Programmable Gate Arrays (FPGAs) based
on the Verilog HDL. It describes aspects of syn-
thesis and optimization specific to FPGAs, in
contrast to CMOS gate-arrays. Particular atten-
tion is paid to architecture specific optimization ,
both on Register Transfer and Logic Level. The
concept of the design methodology is proven by
a real-world implementation of an actual design.
Introduction
At the end of the previous decade, Verilog HDL
was rapidly becoming the design language of
choice for many CMOS gate array starts. This de-
velopment was driven by an excellent simulator
and a wide availability of many vendor- certified
simulation libraries. The adaptation of an RTL
subset of Verilog HDL by Synopsys as its origi-
nal high-level synthesis language accelerated the
usefulness of the language.
Unfortunately, the HDL paradigm that proved to
be so useful for CMOS gate array design, was
lacking in support for the design of FPGAs. Not
only were no simulation libraries available from
the different vendors, but synthesis tools based on
gate-array optimization performed poorly when
optimizing for different FPGA architectures.
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language entry could easily cost more than
$ lOOk for simulation, high-level synthesis, and
logic synthesis tools. Such a cost may seem rea-
sonable for CMOS gate-arrays, where designers
are already facing high NRE costs, and can am-
ortize tools over several projects, but is prohibi-
tive for average FPGA design.
This paper discusses a design methodology for
FPGAs based on the Verilog HDL, including be-
havioral simulation, synthesis, and back annota-
tion for gate-level simulation. Within the thread
of the flow, we will focus on the specifics of
FPGA synthesis, in contrast with traditional gate-
array synthesis.
FPGA architectures
Field Programmable Gate Arrays (FPGAs), con-
trary to traditional gate arrays, comprise a wide
variety of building blocks, or cells. Xilinx’ Con-
figurable Logic Block (CLB, see figure l), for
instance, contains programmable Look-Up Ta-
bles and storage registers. The 4000 architecture
implements any function of up to five inputs, and
some functions of up to nine inputs. In this sense,
a 5-input XOR function is as expensive in area
and delay as a 2-input NAND. This is in contrast
with ASIC transistor counts when implementing
thesc same functions.
 FUNCTION

m
CONTROL

FUNCTION o o -xa

>
- EC
RO
K
(CLOCK) I\ 1
X

Figure 1. Simplified Block Diagram of XC4000 Configurable Logic Block.

completely different basic cell (see figure 2).
Based on a multiplexor architecture, the Act2 c-
module implements as diverse gates as 2-input
AND gates, as well as AND-OR gates with five
inputs with the same area and delay penalty.
As a final example, the Altera MAX family (fig-
ure 3) is representative of the so-called complex
PLDs. The basic structure is the Logic Array
Block (LAB), which consist of a macrocell array,
an expander product term array, and an do control
block. The LAB implements 16 functions of up to
30 product terms.
regular and-or decomposition, and fanin-limited
decomposition for LCA design. And-or decom-
position processes a complex equation, and rep-
resents it as a tree of and gates and or gates only.
The tree representation is then mapped into an
LCA by merging gates with less then four fanins,
and splitting gates with more than four fanins.
For instance,
X = (A*(B+C))+(B*D)+(E*F*G*H*I)
after and-or decomposition would be as follows:

The differences in cell granularity among differ-

X = Tl+T2+T3
ent FPGAs make it a challenge both for human
designers and for automated synthesis tools to de-
sign circuits in an optimal fashion for every T1 =A*T4
architecture. For random logic, synthesis can use T2 = B*D
architecture specific optimization algorithms. To T3 = E*F*G*H*I
stick with the three technologies discussed be- T4 = B+C
fore, one can use fanin-limited optimization for
Xilinx, mux-based optimization for Actel, and
Next, as T3 has more than four inputs, it is split
cube-limited optimization for Altera [ 13.
into two functions :

As an example, consider the differences between

T3 = E*F*G*TS
 Figure 2. Combinational and sequential configurations of the Act2 cell.

T5 = H*I
X = Tl+(T2*E)
Now the design is in AND/OR format, the Xilinx T1 = A*(B+C)+(B*D)
physical place and route software can be used to T2 = F*G*H*I
place the design into physical CLBs. This pro-
cess is referred to as "partitioning" by Xilinx,
Since the three expressions share no common in-
a l t h o u g h " p a c k i n g " is the m o r e f a v o r a b l e
puts, an optimal solution has been achieved.
terminology. In this example, T5 or T3 cannot be
merged because of fan-in limitations. T I may be
combined with X, but it would be better to com- The Actel logic module consists of three 2-to-1
bine T1 with T4 and X with T2. This gives the multiplexors and one 2-input OR gate. As such,
following partitioning into four CLBs: the Actel technology is often classified as a fine-
grain FPGA, and can be optimized and mapped
using traditional gate-array techniques [2]. How-
X = Tl+(B*D)+T3
ever, since the basic logic module is created from
T I = A*(B+C) multiplexors, mux-based optimization and bool-
T3 = E*F*G*TS ean mapping techniques are much more effective.
T5 = H*I
Consider the function:
The best partitioning for this example, however is
not the best solution overall. The initial logic de- f = a*b + !b*c + d
composition given to the place and route strongly
affects the final solution. A fanin-limited decom-
where ! symbolizes the boolean negation.
position, which is based on the knowledge that
the number of inputs only limits the logic to be Using the property:
implemented, yields a much better partioning into
three CLBs: d = (b + !b) d

88
 to I/O Block

Programmable 16 Expander
Interconnect Product Terms
SignaIs

Figure 3. Simplified Block Diagram of Altera Max7000 Macrocell.

sometimes in different aspect ratios.) Hard and

and substituting this into f, we obtain:
f = b * ( a + d) + !b * (c + d )
In a similar fashion:
a+d = a+!a*d = a*l+!a*d
c+d = c + ! c * ~= ~ * l + ! c * d
Substituting (4) and ( 5 ) into (3) gives:
soft macros are especially popular to implement
arithmetic and relational logic, including addi-
tion, subtraction, incrementation, and
(3)
comparisons. The optimization techniques de-
scribed previously, however, operate only on the
Boolean gate level, and are not capable of resyn-
thesizing larger structures, like n-bit adders, as a
(4) structure in itself. In fact, once the n-bit adder is
implemented in a certain way, no synthesis tool
(5) will change its basic structure, say from carry rip-
ple into carry look ahead.
a b

pre-defined, teqhnology-specific hard and soft C

macros that can be utilized by advanced synthe-

sis systems. (Hard macros differ from soft macros Figure 4. Decomposition into Actel technology.
in the fact that they are pre laid out and routed,

89
 VERILOG HDL
I
parser
random ~
I optimization
v
netlist
Figure 5. Module Generation dataflow.
From the discussion above, it is obvious that im-
plementing structured logic functionality in an
FPGA differs drastically from technology to
technology. As an example, 16-bit addition in the
Xilinx 4000 family is best implemented using
hard macros exploiting the architecture's fast car-
ry chain, but these hard macros do not exist in the
3000/3100 family. Actel, on the other hand, has a
vast variety of full-adder cells that can be config-
ured in carry-look ahead or ripple carry adders.
Not only target architecture, but area vcrsus de-
lay trade-offs can also play an important role in
how to implement structured logic. To stay with
the adder example, a 16-bit implementation in
Act 1 can be done in 24 modules as a carry-ripple,
or in 78 modules as a carry-select adder for ap-
proximately half the delay.
In a schematic entry methodology, the designer
can .always utilize the foundry-provided hard and
soft macros by interconnecting them in the sche-
____-- -~ modgen
I
I library
matic drawing. He or she can even design propri-
etary macros and use those where appropriate.
The drawback, besides using the schematic entry,
is that the designer has to be familiar with the tar-
get technology and should know in detail when to
use which macro. From a Verilog HDL perspec-
tive, these macros can be utilized using module
instantiation with hardwired connectivity. For in-
stance, when addition is required in the Xilinx
4000 family, the designer can instantiate the
ADSU8H for an 8-bit implementation or the
ADSU16H for a 16-bit implementation:
adsu8h g 0 (.a( busa),. b( busb),.add(pwr),
s(sum),.ofl(ofl));
~~
where the actual module is described without a
body:
module adsu8h (a, b, add, s, ofl);
input [7:0] a, b;
90
 Figure 6. The Mancala Game implemented in FPGAs and mounted on an Aptix Field Programmable
Circuit Board.

input add; wants to see the ’+’ operator implemented by the

output [7:0] s; ADSU8H hard macro, but cannot enforce this as
output 0fl; Verilog does not allow overloading of any oper-
ator or function.
endmodule

The solution is one where designers can refer to

However, this removes the higher level of ab-
libraries where certain operators are defined in
straction that the Verilog HDL was supposed to
terms of a target technology. Such a library could
provide and essentially reduces Verilog design to
contain n-bit adders, subtractors, accumulators,
textual schematic capture. But at the same time, it
and other datapath operators. The synthesis tool
is the only way to assure the utilization of the
chooses from this library the preferred implemen-
fast-carry chain in this particular architecture.As-
tation of an operator, depending on size and
suming that the overflow signal (ofl) is not re-
well-defined attributes. Such a library, which is
quired in this implementation, a typical Verilog
statement to achieve addition would have been referred to as a module generation library, can be
defined in many different ways.
sum = busa + busb ;
Figure 5 shows the general flow of data in a mod-
ule generation environment. After the Verilog
For the 4000 architecture, the designer
code is successfully parsed, it is passed on

91
to an inference engine that matches supported op-
erators like addition with preferred implementa-
tions in the module generation library. Matching
is performed on three levels:
- name of the module generator
each operator has an identifying name,
e.g. ’modgen-add’ for ’+’.
- generic value ’size’
module generators can be defined for
any size in the natural range.
- number of ports
the number of ports is defined by the
module generator and its size.
Other generics, for instance for area and delay
trade-offs, can be defined as well, but are not
mandatory for a match [3].
Pilot design
The concept of Verilog HDL based FPGA design
as described in this paper has been tested and im-
plemented with a real-world design. The Mancala
Game is a tradional African board game, that has
been emulated in hardware.
The Verilog description is approximately 700
lines, and has been synthesized into different
FPGAs. The printed circuit board implementation,
as shown in figure 6, contains three identical im-
plementations of the game in an Actel 1280,
Altera Flex, and a Xilinx 4008 device.
The pilot design illustrates another interesting as-
pect of device-specific FPGA synthesis. The
Mancala game requires 24 seven-segment dis-
plays, which at four i/o pins each consume 96
device pins. In order to save i/o pins on the FP-
GAS, the data for the seven-segment displays
were multiplexed on a high-impedance output
bus using the verilog assignment to ’z’:
92
assign bincount-bus = bindselect[ I] ?
bincountl : 8’bz;
The high-impedance assignment synthesized fine
in the Xilinx technology, where it resulted in a
total of 96 three-state buffers. Actel’s anti-fuse
technology nor Altera’s FLEX 8000, however,
support internal three-state buffers.Hence, to ac-
comodate the assign statement an automatic con-
version into multiplexed logic was performed.
The finalized design occupied 175 CLBs plus 96
3-state buffers (xilinx 4000), 893 modules (act2),
and 680 LCs (flex 8000). Figure 6 shows how the
devices are mounted on an Aptix Field Program-
mable Circuit Board.
Conclusions
This paper has discussed aspects of a Verilog
HDL based FPGA design flow. It has shown that
the Verilog HDL language itself is applicable to
FPGA design, but that dedicated tools especially
for synthesis are required to obtain feasible
results. The approach taken has been validated
with the synthesis of a Verilog HDL description
of the Mancala game in actual hardware.
References
[ 11 ’ELSS: A Logic Synthesis Tool for FPGAs’,
R.P Ranauro and M.M. Ligthart, proceedings of
the 4th annual IEEE Asic conference and Exhibit,
1991, pp.13.2.1-13.2.4.
[2] ’Technology Mapping in MIS’, E. Detjens, G.
Gannot et..al., proceedings of the ICCAD, 1987,
pp.1 16-119.
[3] ’Module Generation for VHDL synthesis’,
R.W. Dekker and M.M. Ligthart, proceedings of
the VIUF spring conference, 1993.