College of Engineering, Pune

Dept. of Electronics and Telecommunication Engineering

Course : Digital System Design ( SY E & Tc)

Year : 2020-21

Assignment No 5 :

Topics : Mux, Decoders and Adders

Q 1. Implement the following multiple output combinational logic circuit using a
4-line to 16-line decoder:

Q2. The inputs to a digital circuit shown in figure is are the external signals A, B and
C. Assume complements of A, B and C are NOT available. The +5 volts power supply
(logic l) and the ground (logic 0) are also available.

a. Write down the output function X in its cannonical SOP and POS forms.
b. Implement the DIGITAL CIRCUIT (one with output as X) using ONLY 2 to 1
multiplexers. The 2:1 mux is shown in the figure left, where S is the data select line,
D0 and D1 are the input data lines and Y is the output line. The function table is also
given for the multiplexer on left.
(Hint : See how basic gates are implemented using 2:1 mux and use that concept here.
There is no limitation on using number of 2:1 muxes)
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Q3. In the following circuit X is given by expression = ?

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Q4. Considering X and Y as inputs and Difference(D) and Borrow(B) as the outputs
implement a 1-bit half-subtractor using 2:1 multiplexer.
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Q5. Consider the circuit shown in the figure below:

The input lines (A0 A1 A2 A3) are feed with data 0010. The output to the circuit is
used to light 4 LED’s connected on different streets. The streets are named as street-
1, street-2, street-3 and street-4. Assuming all gates and decoder have no
propagation delay, the street which will be illuminated for the applied input is
_______.
(Enter the street number. E.g.: enter 1 for street-1)
(Explaination is mandatory here)
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Q6. If the logical expressions of the outputs in the circuits shown in Figures A and
B are same, then select the correct combination of signals to be connected to
the inputs of multiplexer (i.e. I0, I1, I2, I3) using the codes given below the
Figures.

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Q7.

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Q 8.

I3

I0

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Q9.

The blue dots represents the

connections made to 1 or 0
logic

X0 or D0 which you use..!

(Note : the OR gate connected to S2 is having only 1 input C and other floated.)
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Q10. Draw the circuit of BCD Adder using two IC7483 and some basic gates. Explain
its working in detail with one example of A = 9 and B = 8, where A and B are assumed
to be 4 bit inputs to IC.
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Q11. Design a Decimal to Gray ENCODER. The circuit will have 0-9 (i.e 10 inputs)
each for a decimal number. If pin 1 is HIGH, i.e. Decimal input is 1 given then output
must be gray equivalent of 1. Draw TT and the gates based circuit.

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Q12. Consider a two-level logic implementation of the look-ahead carry generator. Assume
that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates
can have any number of inputs. The number of AND gates and OR gates needed to implement
the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are
respectively:

(A) 6, 3
(B) 10, 4
(C) 6, 4
(D) 10, 5

(Hint : Use the basic equations for Ci+1 and don’t forget to REuse the expressions which you
have generated in previous stages. Your answer must be optimized one.)
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