The flip-flops in the register have

asynchronous clear inputs that are connected to a

on clear signal, ClrN. The bubble
the clear inputs indicates that a
at
logic 0 is required
lear the flip-flops. ClrN 1is normally 1, and if it is changed momentarily to 0, the Q
of all four will flip-flops become 0.
outputs

As discussed in Section 11.8, gating the clock with another signal can cause timing
hlems, If flip-flops with clock enable are available, the register can be designed as shown
p r o b i

in Figure 12-1(6). The load signal is connected to all four CE inputs. When Load = 0, the
dlock is disabled and the register holds its data. When Load is 1, the clock is enabled, and
the data applied to the D inputs will be loaded into the flip-flops, following the falling edge
of the clock. Figure 12-1(c) shows a symbol for the 4-bit register using bus notation for the
D inputs and Q outputs. A group of wires that perform a common function is often referred
to as a bus. A heavy line is used to represent a bus,
and a slash with a number beside it
indicates the number of bits in the bus.
data between registers is a common operation in digital systemns.
Transferring
can be transferred from the output of one of
two registers into
Figure 12-2 shows how data
a third register using tri-state
buffers. If En 1 and Load 1, the output of register A is
=
=

A will be stored in Q after the rising

enabled onto the tri-state bus and the data in register the
clock. If En 0 and Load 1, the output of register B will be enabled onto
=

edge of the =

t-state bus and stored in Q after

the rising edge of the clock.

Tri-State Bus

Register FF
A
Register A =
En-
Flip-fiops Aj and A2
FF
FF
Register B = Register
Flip-flops Bj and Ba2

FF FF
Repister
Register Q =
Flip-flops Q1 and Q2
CIk
FF

Between Registers
Transfer Learning
2014
Data O Cengage
FIGURE 12-2:
 Registers and Counters 641
Serial in

Serial out
(SO)

Shift H
lk

(a) Flip-flop connections

Cock

(b) Timing diagram

FIGURE 12-7: Right-Shift Register

Cengage Learning 2014
If we connect the serial output to the serial input, as shown by the dashed line, the
end-around shift. If the initial contents of the
esulting cyclic shift register performs an
is 1011. After a second pulse, the state is
egister is 0111, after one clock cycle the contents
the register to the initial 0111 state.
91, then 1110, and the fourth pulse returns
or more flip-fiops are available in integrated circuit form.
Shift registers with 4, 8, data is
serial-in, serial-out shift register. Serial in means that
8-bit
Eure 12-8 illustrates an
the flip-flops cannot be loaded in parallel.
bit at a time, and
cd into the first flip-flop one
last fiip-flop and the outputs from the
4i out means that data can only
be read out of the
circuit. The inputs to the first
otherp-fiops
flip-flops connected to
terminals of the integrated it is
1, a l is shifted into the register when
are not
if Si
=

R SI. Thus.
=SI and
=

O are S
Figure pical timing diagram.
12-9 shows a typica timing diagram.
clocked, and if SI
C a , and =
0, a 0 is shifted in.
Parallel-in implies
4-bit parallel-in. parallel-out shirt register.
Figure 12-10(a) shows a
time, and parallel-out implies that all bits can
same
l four bits can be loaded at the two control inputs, shift enable (Sh)
two control
shift register has
read Out at the s a m e
time. The
I or L =
register causes the
0), clocking the register cau
I (and L
=

load enable (L). If Sh =

while the data in flip-flops Q. Oo,. flip-flops 03 O

a ,d the first fiip-fiop.
register will cause the
locking the shift register
into
to be shifted
p u t (S) 0 and L 1, clocking =

If Sh
=

are shifted shifted right.

 3ro SEM B.E - Analog and Digital Electronics

CP

a,
0001 0011 0111 1111 Data in register
0000

Note: For bits 1010 do necessary changes.

can be applied for serial addition. (07M)
with ncat diagram How shift Register
. b. Explain
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1) Shift register is used Parallel to
as
serial converter, which converts the
parallel data into serial data. It is utilized
at the transmitter section after Analog to
Digital Converter ADC block.

2) Shift register is used asSerial to

parallel converter, which converts the
serial data into parallel data. It is utilized
at the receiver section before Digital to
Analog Converter DAC block.

3) Shift register along with some

additional gates generate the sequence
of zeros and ones. Hence, it is used as
sequence generator.

4) Shift registers are also used as

counters. There are two types of counters
based on the type of output from right
most D flip-flop is connected to the
serial input. Those are Ring counter and
Johnson Ring counter. 6:11 pm
Asynchronous inputs on a flip-flop have
control over the outputs (Q and not-Q)
regardless of clock input status.
These inputs are called the preset (PRE)
and clear (CLR). The preset input drives
the flip-flop to a set state while the clear
input drives it to a reset state. 6:12 pm

Preset clear output

0 0 not allowed
0 1
0 1
1 1 no change 6:12 pm
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 644 Digital Electronics

Figure 12-12(a) shows a 3-bit shift register with the O, nutut nom the laat i
nop Ted back into the D input of the tirst tlip-flop. Ir the initial atale ot the regialor i
000, the initial value of D, is 1. so ater the first eloek pulae, the regiater slate ia
100. Successive states are shown on the transition graph of ligure 12-1241) When

CL

LLoad H
Sh (Shift)
D. D.Da
(

01 0

o)i i1

FIGURE 12-11: Timing Diagram for Shift Register

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(MM0)
D (001) (1000) (010)

CLK-
(o11) (110) (101)
(111
(a) Flip-flop ponnections (b) Tnsition graph

FIGURE 12-12: Shift Register with Inverted Feedbaok

Cengug 1eurntng 1014
the register is in state 001, D, is 0, and the next register state is 000. Then, successive clock
pulses take the register around the loop again. Note that states 010 and 101 are not in the
main loop. If the register is in state 010, then a shift pulsc takes it to 101 and vice vers,
therefore. we have a secondary loop on the transition graph.
A circuit that cycles throughfixed scquence of states is called a munter. A
a
shi
register with inverted feedback (Figure 12-12) is called a Johnon emanter on a twisterd ring
counter. If the feedback is not inverted (e.g., Q, connected to 1, in Figure 12 12). the shi
register counter is called a ring counter