ECE/Exam Cell/002

SCHOOL OF ELECTRICAL & COMMUNICATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VTU R 2015
ASSIGNMENT – I
2021-22
B.Tech. - ECE
Course Category: Programme Core
Course Code/Course Title: 1151EC115/ VLSI Design Max.Marks : 5
Semester: Winter
Achievable Course Outcomes
Describe the design hierarchy and CMOS fabrication K2
CO1
techniques
Describe the logic design , circuit design and physical K2
CO2
design of CMOS transistors

Mark
Questions CO s
S.No.
Compare CMOS inverter gate instances for designing a CO1 5
vtu12006
1. buffer .
2 Design a 2:1 Multiplexer using Behavioral modeling CO1 5
Verilog code. vtu12041

3 Design D Latch using behavioral modeling and mention the CO1 5 vtu12291
timing report
4 Design the Flip flop using transmission gate using CO1 5
VIVADO software vtu12426

5 Write the gate level HDL program for 4:1 mux. CO1 5 vtu13989

6 Simulate the CMOS inverter operation and show the VLSI CO1 5 vtu13998
design flow of generating bit file.
7 Draw the Mind map of VLSI in real time applications CO1 5 vtu14004
based on technology.
8 Design 4 bit counter using VIVADO tool and compare the CO1 5 vtu15359
timing specifications.
9 Design a Logic Calculator using VLSI CO1 5 vtu15367

10 A Smarter Toll Gate using mux based design CO1 5 vtu15371

11 Monitoring of Temperature System using VLSI CO1 5 vtu15379

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 ECE/Exam Cell/002

SCHOOL OF ELECTRICAL & COMMUNICATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VTU R 2015
12 Five digit Seven segment LED display CO1 5 vtu15383

13 Design a door lock logic using Vivado CO1 5 vtu15550

14 Design a RTL schematic for 4 bit Shift register using CO1 5 vtu15552
ivado.
15 Design a 1 bit SRAM Cell using Microwind CO1 5 vtu15553

16 Design a Full adder using Vivado and specify the synthesis CO1 5 vtu15562
report.
17 Compare the timing report for designing full adder and CO1 5 vtu16025
with 2 half adder instances.
18 In Verilog code what does “timescale 1 ns/ 1 ps” signifies? CO1 5
Discuss the test bench waveform for D Latch in specified vtu16036
time units.
19 Write a test bench waveform for 4:2 encoder CO1 5 vtu16038

20 Simulate a Real-time clock using VLSI CO1 5 vtu16049

21 Write a test bench waveform for real time counter CO1 5 vtu16740

22 Design a 2:1 mux using transmission gate and analyze its CO1 5 vtu16933
synthesis and timing.
23 Design 4 bit flip flop using NAND gate instances and CO1 5
simulate its performance. vtu16966

24 Design a 1 bit memory cell for read and write operation CO1 5 vtu16967
and explain with timing diagram.
25 Design a 2 bit flip flop for read and write operation and CO1 vtu16987
explain with timing diagram .
26 Write the HDL coding for priority encoder and show the CO2 5 vtu17009
design constraints in FPGA architecture.
27 Implement the physical design of the same in basis board . CO2 5 vtu17046
Discuss its area estimation
Draw the diagrams for the interface of CMOS logic design with CO2 5 vtu17106
28 physical design with justification for adder architecture.
29 Design the verilog coding in behavioral model for flip-flop CO2 5
and discuss its floor planning in FPGA architecture vtu17137

30 Design the verilog coding in behavioral model for CO2 5 vtu17151

latches .discuss its floor planning in FPGA architecture.
31 Draw the diagrams for the interface of CMOS logic design with CO2 5 vtu17198
justification for Full adder with HA architecture

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 ECE/Exam Cell/002

SCHOOL OF ELECTRICAL & COMMUNICATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VTU R 2015
32 Discuss the RTL synthesis , floor planning , pitch CO2 5
matching , area estimation for the logic design 2 input vtu17199
NAND gate.
33 Discuss the RTL synthesis , floor planning , pitch CO2 5
matching , area estimation for the logic design 2 input vtu17243
NOR gate.
34 Discuss the floor planning , pitch matching , area CO2 5 vtu17281
estimation for the logic design 4 :1Mux.
35 Discuss the logic design for the logic design 4 :1Muxusing CO2 5 vtu17478
Vivado
36 Discuss the logic design for the logic design D latch using CO2 5 vtu17501
Vivado
37 Discuss the Physical design for the logic design D latch CO2 5 vtu17502
using Vivado
38 Discuss the logic design and circuit design for the logic CO2 5 vtu17510
design for D Flip flop using transmission gate
39 Simulate the Priority encoder and explain with its physical CO2 5 vtu17585
design.
40 Simulate the logic and circuit design for half subtractor . CO2 5 vtu17768

41 Simulate the y= A’+BC+DE and vErify its physical design CO2 5 vtu17773

42 Simulate the 4:2 encoder and explain with its physical CO2 5 vtu17919
design
43 Discuss the logic, circuit design and physical design of CO2 5 vtu17926
CMOS inverter.
44 Discuss the logic, circuit design and physical design of CO2 5 vtu17957
CMOS inverter .
45 Compare the CMOS inverter with gate model , RTL model CO2 5
and behavioural modeling and analyse its circuit design vtu17958
performance.
46 Compare the CMOS inverter with gate model , RTL model CO2 5
and behavioural modeling for D latch using Vivado and vtu18005
anlyse its logic design.
47 Simulate the priority encoder and explain with its physical CO2 5 vtu18035
design
48 Simulate the mux based design for magnitude comparator CO2 5 vtu18137
and explain its logic design
49 Simulate the mux based design for equality detector and CO2 5 vtu18142
explain its logic design
50 Simulate the mux based design for equality detector and CO2 5 vtu18144
explain its circuit design. and

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 ECE/Exam Cell/002

SCHOOL OF ELECTRICAL & COMMUNICATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VTU R 2015
18816

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