GENERAL VLSI SYSTEM

COMPONENTS
Dr. Mohammed M. Farag
Faculty of Engineering - Alexandria University 2013

Multiplexers

Gate-level NAND 2:1 multiplexor.

Multiplexor using switch logic.

Gate-level 4:1 MUX A 4:1 MUX using instanced 2:1 devices.

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Faculty of Engineering - Alexandria University 2013

Multiplexers (2)

4:1 MUX using nFET pass transistors.

Simple 4:1 pass-FET MUX layout.

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Faculty of Engineering - Alexandria University 2013

Multiplexers (3)

Split-array 4:1 MUX for full-rail output.

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Faculty of Engineering - Alexandria University 2013

Multiplexers (4)

A vector 2:1 MUX.

Single-bit cell tiling for an 8-bit 2:1 MUX.

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Faculty of Engineering - Alexandria University 2013

Decoders

An active-high 2/4 decoder.

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Faculty of Engineering - Alexandria University 2013

Decoders (2)

Active low 2/4 decoder.

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Faculty of Engineering - Alexandria University 2013

Comparators

a 4-bit equality detector.

8-bit equality detector.

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Faculty of Engineering - Alexandria University 2013

Comparators (2)

4-bit magnitude comparator logic.

Comparator output summary.

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Faculty of Engineering - Alexandria University 2013

Comparators (3)

Comp 8 logic diagram.

Additional logic for A_EQ_B

and Enable features.

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Faculty of Engineering - Alexandria University 2013

Comparators (4)

8-bit comparator system.

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Faculty of Engineering - Alexandria University 2013

Encoders

Symbol for priority encoder Function table for an 8-bit priority

encoder.

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Faculty of Engineering - Alexandria University 2013

Encoders (2)

Logic diagram for the priority encoder.

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Faculty of Engineering - Alexandria University 2013

Encoders (3)

Q0 and Q1 circuits for the 8-bit priority

encoder.
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Faculty of Engineering - Alexandria University 2013

Rotators and Shifters

General rotator.

A 4-bit rotate-right network.

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Faculty of Engineering - Alexandria University 2013

Rotators and Shifters (2)

Left-rotate switching array.

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 Faculty of Engineering - Alexandria University 2013

Rotators and Shifters (3)

An 8 X 4 barrel shifter. FET-array barrel shifter.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops

D-latch.
CMOS circuit for a D-latch.

Gated D-latch with Enable control.

AOI CMOS gate for D-latch with Enable.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (2)

Closed-loop inverter configurations.

Operation of a bistable circuit.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (3)

Adding an input node to the bistable circuit.

D-latch using oppositely phased switches.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (4)

Operation of the D-latch.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (5)

C2MOS-based D-latch circuits.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (6)

Master-slave D-type flip-flop.

Edge-triggered DFF symbols.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (7)

Alternate circuitry for the master-slave DFF.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (8)

DFF circuits with assert-low Clear and

Clear/Set controls.
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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (9)

DFF modified to a TFF circuit using feedback.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (10)

D-type flip-flop with Load control.

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Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (11)

CMOS master-slave FF
with Load control.

Operation of the CMOS DFF with load control.

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Faculty of Engineering - Alexandria University 2013

Registers

Construction of an n-bit register.

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Faculty of Engineering - Alexandria University 2013

Registers (2)

One-bit static multiport register circuit.

An n-bit static multiport register.

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