Module4

Chapter

4
Control Unit Design

Syllabus
Hardwired control unit: State table method, Delay element methods, Microprogrammed control unit
Micro instruction-format, Sequencing and execution, Micro operations, Examples of microprograms.

Chapter Contents
4.1 CPU Architecture and Register Organization

4.2 Basic Instruction Cycle

4. Instruction, Micro-instructions and Micro-operations: Interpretation and

Sequencing
4.4 Control Unit: Hardwired Control Unit Design Methods
4.5 Control Unit: Soft Wired (Micro programmed) Control Unit Design Methods
Concepts of Nano Programming
4.6
 Control Unit Desi
4-2 DLCO&A (Sem. Comp./ MU)
DLCO&A (Sem. l /Comp./MU) It consists
of PIPO (Parallel
in parallel out)
register as It acceptS operands from memory Control Unit Design
4.1 CPU Architecture and Register
MU: May 16
shown in Fig. 4.1.2.
result of arithmetic and
or
register. It
Organization: This section is also called
ac
as
SCratch
scratch pad
pad memory. It
stores
register or memory.
logic operations in
Fetch cycle Execute cycle
of memory.
University Questions
stores data
and addresS

affects the rOvides status of resuit to the

flag
Sart instruction
Fetch next Execute
instrucion Hal
organization within the CPu. The register
organization
length register shows status of result. register. Flag
Q.1 Describe the register program, the execution time of program andof
Fig. 4.2.1: Basic instruction cycle
(May 16,10 Marks) simplification of the program.
ALU looks after the branching decisions
Fig. 4.2.1 shows the basic instruction
Fig. 4.1.1 shows the architecture of microprocessor. cycle.
To achieve better performance, the numberr 4.1.3 Interrupt Control: Comprises of the fetch and
executes cycle in a loop
This architecture is divided in different groups
as f to
execute huge number of
should be large. instructions, until
registers
follows This block accepts ditterentinterrupt request inputs. reaches the halt
The architecture of microcomputer depends instruction.
1. Registers upon When valid interrupt request is
a The fetch
the number and type of the registers used present it cycle comprises
control logic to take action in response toinforms
of the following
Arithmetic and logic unit in operations:
microprocessor. each
. Interrupt control. It consists 8-bit registers or 16 bit registers.
signal. Program Counter (PC) holds address of next
Anthmetio 4.1.4 Timing and Control Unit : instruction to fetch; hence the CPU
Accumulator WorSrking
4.1.1 Register Section fetches instruction from
(Processor)
This is a control section of memory location
The register section varies trom
microprocessor
microprocessor made up pointed to by PC. This is done by providing the
tto of synchronous sequential logic circuit. value of the PC to the MAR and
microprocessor. thegiving
It controls all internal and external circuits. Read control signal the memory. On this the
to
The registers are used to store the data and address
It operates with reference to clock memory provides the value in the given
Stack
Interrupt These registers are classified as signal. address (which is the instruction) to MBR.
Timing and POinter
olook circuits circuit This accepts information from
Program . Temporary registers instruction decoder 2. The PC value has to be incremented to
COunter and generates microsteps to point
2. General purpose registers perform it. to the next instruction
(Sometimes the value of
Fig. 4.1.1: General architecture of a microprocessor In addition to this, the block PC may have be
completely changed in case of
3. Special purpose registers. accepts clock inputs,
performs sequencing and
synchronising operations.
some special instructions called as branching
The instructions).
Inputs synchronization is required for communication 3. The instruction is loaded into Instruction
between microprocessor and
peripheral devices. Register (IR) from the MBR.
D6 To implement this it uses
different status and control Finally the processor
interprets or decodes the
signals. instruction. The processor
performs required
The basic operations in the execute cycle.
operation of a
microprocessor is regulated
CLK by this unit. In the execute ycle the operation asked to be
Q7 It performed by the instruction is done. It may
synchronizes all the data transfers.
This unit takes
comprise of one or more of the following
appropriate actions in response to operations
Outputs external control signals.
Fig. 4.1.2:8 bit Transfer of data between processor and
4.1.2 register 4.2
Arithmetic and Logical Unit Basic Instruction Cycle:_ memory or between processor and 1O module.
This section Processing of data like some arithmetic or
processes data i.e. it performs arithmetic and he instruction cycle is a representation of the states
It
performs arithmetic operations logical logical operations on data.
etc.
like addition, subtraction and operations. that the
computer or the microprocessor performs Change of the sequence of operation i.e.
logical operations 3.

The ALU is not

available to the user. Its word
like ANDing., ORing, EX-OnRing when
executing an instruction. branching instructions.
The ALU is controlled length depends upon the ne
instruction cycle comprises
by timing and control width of an internal data
of two main steps to | 4.2.1 Interrupt Cycle:
circuits. bus. oe
followed to execute the instruction, namely the
n
Fetch and execute are not the only two states in the
operation in the fetch cycle and the execution
instruction cycle.
Tech Knowledge
Operation during the execute cycle.
cations
PubT
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DCa tions
 Comp./MU) 4-5 Control Unit Design
DLCO&A (Sem.
Control Unit Design address
are some states drawn to the state "Instruction
4.2.3, there on the he one that goes
4-4
then it fetchee
then fetches the
nen In
s o m e on the lower side. next instruction;and the o n e
that
is
present

side, while calculation" for the

then i n0er
forms
interrupt
pending for vector
no
address calculation"
,

If interrupt
the "Operand
MO) else if
on the upper side are the operations goes to
DLCO&A
(Sem. Il/Comp./ instruction ones
cycie
the following operations:
The
are external instructions.
more
state i.e.
Interrupt

o t current progra out on the Duses or erations, wherein the

There is one
of
interrupt

the
execution carried Vector instructions those instructions
are
the concept Suspend level are the operations
ones at the
lower the
will see
we current program the data on which
ofthe .hile Operation is same but the
subsection

n this context
cycle. Save the the CPU or internal operations. of data
ried out inside
are block
is to be performed in a huge
the interrupt
in short and
can
modules operation
which I/0 execution.

by interr from the "Instruction

instruction cycle begins
mechanism
address of or an array of data.
is a to start
Interrupt
PC value The
Set the is already
of processing.
interrupt service
as wherein the address of the instruction
state, second case, the
normal sequence called
interrupt from
dn
routine
also calculation" Hence in the
of some
request handler
is a small
routine
address operation is already
because service
calculated the value of the PC is and decoded i.e. the
instruction is
be or fetched
Interrupt
can Interrupt a
routine. on
device.
executed, servicesth
next to be performed
device to
service that particular which
when
know, and the operation is
VO control
program updated.
some
data or
or gives block of data.
may take
interrupting source.

h i s service instruction is fetched, which requires the

Then the set or
one
interrupt
service routine (ISR)and After completing the operation on

operation.
operation
in
4
Process the
operation
on the buses CPU to the next operand
unexpected operands, the returns
also because
of some
then. fetched is then decoded. Until this calculates and
t may
the CPU itselt. continue execution of The instruction address calculation state, wherein it
execution by context a n d
the program Restore the
state, it is
the fetch cycle.
earlier is
added to the interrupted program.
fetches the next operand.
cycle as
discussed
the operand address is the result and
Interrupt the execute cycle, stores
basic
instruction cycle with In Then it performs the operation,
instruction cycle. the complete and the operands are fetched from the until all the
-Thus calculated for the next set of operand,
checks for interrupt, be as
shown in the Fig. 4.2.2. again
the processor can calculated address.
During this cycle Interrupts completed.
the same.
operands in the array are

and if present and

enabled services
Interupt cycle to fetch the operands, we require the buses. Instruction, Micro-instructions and
=xecute cycle
Again 4.3
if more operands are Micro-operations: Interpretation
Fetch cycle After fetching the operand,
instructions, then the
Interrupts required for multiple operand and Sequencing :
disabled calculate the operand address ie.
next state is again May 19, Dec.19
MU: May 15, May 16, Dec. 16, Dec.18,
Gheck fof
Execute interrupt the address of the next operand.
Fetchnext
Start instruction instruction Interupts Pprocese interrupt
all the operands are fetched, the data University Questions execution.
Once
sequencing and
enablec
microinstruction
out as per the operation Q.1 Explain
carried
operation is (May 15, 7 Marks)
indicated in the instruction. instruction
microinstructions to execute a n
the address of Q. 2 Explain
Halt Now for the result storage again MOVIR1), R2.
(May 16, 6 Marks)
result is stored in the
Fig. 4.2.2: Complete basic instruction cycle operand is calculated and the micro instruction sequencing and
Q.3 Explain
ana
specified location of the memory. execution.
(Dec. 16, 10 Marks)
enabled
will notice in Fig. 4.2.2, the interrupts are checked for, after the execute cycle and processed if the calculation
microprogram for
of multiple operands again
You ? Write
in case
Q. 4 What is Microprogram
exist; else, it fetches the next instruction. continues until
dnd storage process for the operand ollowing operations
The detailed instruction cycle is shown in Fig. 4.2.3. all the operands are stored. M Register R1 and Memory
ADD R1, result storeat
wherein the first stepP location M are added and
Ope NOW begins the interrupt cycle,
ton Operand Register R1.
IS to check the presence of enabled interrupt.
Sore an

seen in the
MUL R1, R2 Register R1 and Register R2
is then the next state as
Multiple there none, are multiple and result store at Register R1
operands Multiple instruction address
ig. 4.2.3 is the calculation of next
(Dec.18, May 19,Dec.19,10 Marks)
GSuiis

e. executes the next sequential instruction.

Instruction Instructon Op
Operaton add Operand in section 4.2 is showwn
of the CPU
addre83 Data
then seen
enabled
the interrupt is present and
address ternupt
The structure
alouiauo BCOOin9 calculation peraton Interrupt case
in earlier
as discussed in details in Fig. 4.3.1.
Instruction complete No
servicing of the s a m e is done
Return for string
Ovector data nerrupt
in this section. This structure has a speciality that all the control
aie
tnere
notice that signals are shown in it
Fig. 4.2.3:Detailed instruction the you will also
Fig. 4.2.3,
n

cycle of the previous instruction. TechKnowledge

paths from the end P ubIlcations

TechKnouledge
ons
PubIca
 ontrol
Cont Unit Design DLCO&A(Sem.II1/ Comp. / MU)
4-7
4-6
DLCO&A (Sem. Ill / Comp. / MU) The set of registers RO to Rn (the value of Note,
the control unit is an e Control Unit Design
of instructions.
CPU) for genera
in the CPU) part of the This also
Programs are executed
as a sequence on the registers CPU; hence the design can vary rom completes the entire fetch
operation the
As seen in the previous sections of this chapter,
each
depends
purpose operations. processor.
processor to instruction.
or
t
that make up
instruction consists of a series steps of
4.3.2 Execute Cycle
an instruction decoder for deco: In the first t-state, the address of the
the instruction cycle ie. fetch, decode,
etc. There is also ng the instruction to
of a smaller
stored in theinstruction register
and in
executed is given to the MAR register from the
tach of these steps is, in turn, made up
instructions
Execute cycle
as discussed can be of
various types
PC register.
series of steps called micro-operations or micro provides the micro-Instructions or the
turn control erform this
Dased the operation to be
on
performed in the
instructions. signals for the
resources inside and outside tha r
To ert
operation the control
signals given instruction and the location of the operand.
are PCout and MARin
these W e wil see some
signals issued to perform The ALU also gets the control signals from
Control are
this examples
in this subsection.
micro-operations and micro-instructions are these This will make the PC register give out its data
decoder indicating the operation to be perfomed
the MAR register accept this data.
and The frst example we will take for the execution ot a
control signals AND etc. direct addressed operand. In this case the address of
like Add, Sub, and
Fig. 4.3.1 shows the structure of the CPU
with these Also the memory is ndicated to perform a read the operand is
The ALU also has an extra input called as Cn e. the directly given in the instruction.
micro-instructions or the control signals. operation from memory hence the signal "Read".
t invoves different operations in various t-states as
also shows those already seen in carry input as required for adder. To increment the value of PC, the various
t registers as
operations shown in Table 4.3.2
assuming the instruction ADD
section 4.2 like PC, MAR, MBR, etc. To execute any instruction as seen earlier it is to be are performed on ALU signals ie. Clear R,
Y, Set C
There are some registers like the register Y to divided into three cycles viz. fetch, execute and Add, Z Table 4.3.2 : Microinstructions for thee execute
shown in
cycle of direct
provide one of the operand to the ALU as The Y register is cleared and the carry flag is set.
interrupt cycles. addressed mode of operand access
the Fig. 4.3.1
Now when the ALU is said to perform
Internal External The execute cycle will differ based on the operation the "ADD Operation Microinstructions
control control
operation it will add the contents of the
sgna signal to be carried out in the instruction, but the fetch and Yregister, T1 IRMAR IRaaladdress). MAR Read,
interrupt cycle will be common for all the cycles. carry flag and the contents of the internal data bus. Clear C
tt Us
Addr
Instruction decoder MAR Let us see the micro-instructions to be given for each The contents of the internal data bus
MaRin
are nothing but T2 MMBR Rlout Y Wait for memory
n of these cycles. the value given out by the PC register. read cycle
MDAn Data bus

nstruction register MDR 4.3.1 Fetch Cycle Hence the PC is added with 1' i.e. the carry flag and
T3 MBRout Add. Z,
aDR
MOout
hence incremented value of PC is given to the Z MBR +R1>R1
Fetch cycle is concerned to fetch (i.e. read from T4 Zout
OU R1in
register.
memory) the instruction. In this case of direct addressing mode, the address of
PC
Our
- I n the second clock
pulse the CPU has to wait for the the memory operand is in the instruction itself.
ACCin It involves
ACC following operations
in different t-states memory operation, but in the same time it can
ACCu Y reg t+state is a time state and is equal to one clod
This instruction as we have seen in the fetch cycle
CLR ransfer the result in register
SETT Temp Tn pulse) and hence the mentioned microinstructionsin
Z register to the PC reaches the IR register.
Fo in With the control
signals namely Zout and PLin Hence the IR register is given a signal to give out the
Table 4.3.1.
ADD CLAC This could not be done in the previous t-state, as two address part and the MAR register to accept this
Table4.3.1: Microinstructions for the fetch cycle data cannot be given simultaneously on the data buS, address input value by giving the control signals
OR 4in SET C n out Operation Microinstructions else it will get mixed up. TRoutladdres) and MAR
iSP.
n T1 PC- MAR Only one data can be given on the data bus in any At the same time, since the memory is to be read
SP PCout MARin. Read, Clear y,
CIock
Set Cin Add, Zin pulse, but as many as required can accept the from the control signal is given to the memory i.e.
T2 M MBR data. "Read".
Fig. 4.3.1: Data path out PCn Wait for memory tetc
structure with control signals In final t-state, the contents received trom the
Another register is the PC-PC+1 cycle Also the carry flag is cleared to get ready for the
store the result
Z register, which is used to
nemory ie. the instruction is transferred to ts addition operation.
given by the ALU. T3 MBR> IR
A "temp" register or the temporary MBRoutRin COrrect place i.e. the instruction register.
Since the instruction expects addition of the register
some temporary data. register to store AS Seen in the table, three clock pulses or t-states are
S done by the control signals namely MBKout RI' and the data at memory location with address
equired for the fetch and IRin
X, the contents ofregister "R1'aretransferred tothe
cycle.
TechPubilcations
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Tech Kn0wleds
PUDIICations
 Control Unit Desigrn
Comp./ MU) 4-9
DLCO8A
(Sem.
microprogram for
the
instruction: ADD R N
Write
Control Unit Design of this
o f this
control
c ontro unit can be done in two 2. a
Microinstructions

esign
de sign

of the e
Microinstructions of the
execute
xecu oycle of an
The Hardwired Control Unit and T-state Operation
ways namely PCout. MARin. Read
4.3.3:
operand
instruction Microprogrammed Control Unit.t 1 PC M A R
Set Cin, Add,
Zn

iMU
Table
addressed Clear y,
(Sem.Iil/Comp
indirect
the subsequent for
Microinstructions in
ALD

two methods
tor any these Wait
DLCOSA operands
will see Zout. PCin.
M - MBR
is one
ofthe Operation
memory fetch cycle
Y egister,
which
IRunladdress), MARn. Read| sections.
P C -PC+1
Signais
control T1 IR MAR Clear Cn
of Microprograms:
operation. the

this transfer
operation
4.3.4
Examples
T3 | MBR- IR MBRout
IRin
for memo
Wait
MU: Dec. 18, May 19
pertorm

R1u Y CLRC

given are RIst and Y

second
t-state,
the
data

T2 M MBR read cycle

4 R3 X R3out: X
of the available

ADD, Zn
the end will be University QuestionsS R out
AISO Dy memory
R ALUU
from the
requirad MBR(address).
MAR Write microprogram for
Zout Rain
operand microprogram
T3 MBRMAR What is
in the MBR register.
MBR
which is
Read a.1 2>Rs
contents of the following operations. Assumption enabled intr
the
the third t-state Check for intr
Memory
acaress
In with the R1 and
location Wait for memory read cyce
ADD R1, M: Register pending
of memory
ALU IS 1.
and the 14|M- MBR
content
ne
data bus M are added and result store at CLRX, SETC, SPout.
on the
intermal
MBR Add, location
piaced
operation
indicated to perform
the
addítion

MT5
BR R1 R 1
Register R1. SUB, Zin
of the Y register
and tne
Zat. R1 MUL R1, R2 Register R1 and Register R2 Zout. SPin, MARin
t adds the contents

and the
resut is T6 2. T8 SP-SP-1
of the
intermal data
bus,
are multiple and result store at Register R1. PCout. MDRin. W R I T E
contents
4.3.3 Interrupt cycle: T9 PC>MDR
given to the Z register.
tor any pending
(Dec.18, May 19, 10 Marks) Wait for mem a c c e s s
to send
the data
trom the
to pertorm the test T10 MDR [SP
An extra t-state is required It is concerned the instructioon
earier two data instruction execution Write a microprograms for T11 PCIS Raddr PCin IS Raddr out
the register R1
as seen
at the end of every
Z register to interupts
the data bus in
MOV R Ra
simuitaneously on and if an interrupt occurs instruction
cannot be given
Write a microprogram for the
the same t-state. micro-operations for various
Operation Microlnstructions MOV R. IRJ OR LOAD R. R
location with the
t invotves the
different
T-state
of
And the contents memory
shown in Table 4.3.4. Read. Clear
Operation Microinstructions
t-states as PC M A R PCo. MAR.
on the data bus in the T1 T-state
address X are already put
Here you will notice a special register used called s

y.Set Ca. Add, Zn T1 PCMAR PCout. MARin. Read

third t-state
transter the the stack pointer (SP). which always points to the top Clear y, Set Cin. Add, Zn
The fourth tstate is thus required to
M MBR Zout. PCn. Wait for memory Zout. PCin. Wait for
T2 T2 M MBR
data from register Z to register Rl using the signals of the stackk
memory fetch cycle
of he P C - PC 1 fetch cycle P C P C +1
This stack is used to store the return address
RL
Another exeate cyce we wi be stucying in this intermupted program. r3 MBRo. IRn
13 MBRIR
MBRot. IRn
MBR1R Ra out. MARn. READ
sub-section is for the indirect addressed operand. Table 4.3.4: Microinstructions for the interrupt yde RMAR

in this case the address given in the instruction is thee

4
R Ri oRa 5 Mem MDR Wait for mem access
memory location that contains the address of the
Operation Microinstructions
5 Check for intr
Assumpton enabled intr
MDR RR MDRu Rn
Check for intr Assumption enabled intr
operara. T1 SP-SP -1 SPadaddress). Decrement. pending pending
Table 433 shows te mico-operations required forT2SP MAR CLRX, SETC. SPout.
ZMAR SP CLRX, SETC, SPa. SUB,
sudh an eyecute yce tor an erampie instructon
pr PCaretun address). MER
SUB, Zin
-MBR
ADD RL M T8 SP-SP-1 Zout. SPn. MARn
Table 43.3 shos the cotro signais to be given Wrte T5
SPSP-1 Zoa. SPa. MAR PC> MDR
T9 PCout. MDRn. WRITE
eracty simlar to that of the Table 432, with minor4 a SR address PC ISR address out. ne
PC MDR PCat. MORe. WRITTE T10 MDR[SP Wait for mem access
diffeence ie the valiue received
memory read is e operard address ard
in the MBR on first a0dress). Wat for memo 8
T11 PCIS Ressr PCin IS Raddrout
be given back to the
hence is to MDR[SPI Wait for mem access
4. Write a microprogram for the instruction:
wTte c y c
memory to fetch the actua
erend. ne
Control PC-IS Raddr PC IS Raddr out ADD R IR
signals are to be generated US
control unit
Terhmmlede
Tec k
DLC8A (Sem 1 Comp MU
A-10 Controf Urit Des OLCO8A (Sem lii/ Comp MU
Tstate Operatlon Mieroinetructions
Tstate Operation Microlnstr
T10 MDR SP Wait for mem
Ttate
Operatton
MAR P MAR Read Clea access
PC 1S Raddr out 6 MOR ALu Microlnstrucions
y.t Add Z T11 PCISRaddr AOR 2 ADO 1

R,+451
MMBR Emn. PL. Waif for memory 6 Write a microprogtam tor the instruction
T12
7 2 R
PCP 1 fetch cycte ADD R, 45H Zat Rn
T3 MBRIR 8 Check for intr
MBR. IR
T4 R MAR
T-state Operation
Microlnstructions Assumption enabled intr
pending
MAR,. READ, CLRC T1 PC MAR
PCot MARn, Read state 3ymboit
Merm MOR Wait for men accest Clear y. Set Cin,
Add, Z
CLRX SETC. SP operations
M MBR
SUB PG AAP
T MDR AL MD Rw Z, ADD T2
Zout PCn Wait
o T9 SP-SP-1
PCPC +1 memory fetch cycle ZoutSP. MAR ,CLT SETC
X R mernMOR
iat s
ZR T3 MBR IR MBRou. Rn T10 PC »MDR PCo MDR in,
WRITE
T4 RyX MDR
Check fo intr Axsumption enabled intr Rout n. CLRC T11 MDRSPI Wait for mem
access 4
pending T5 IRdata ALU Raddr -» MAR
IRout ADD, Zn T12 PC+IS Raddr PMAR EAD
CLRX, SETC. SPoun. PCin IS Raddr out
SUB T6 ZR Zout Rg in 5
8. Write mem MDR

T7 Check for intr

a
microprogram for the instruction ADDX,
SP$P-1 Assumption enabled intr Y Temp
Zot. SPn. MARn T-4tate
pending Operation
T10 PCMDR
PCoa, MDR. WRITE T1
Microlnstructlon MDRMAR MDRMAR READ
CLRX, SETC, SPa PC MAR
T11 MOR [SP
Wait for mem access
PCout MAR READ mem- MDR Wat r meah accass
SUB, 2 CLRT, STC, ADD, Z
T12 PC MDR- ALU
IS Raddr PC IS Raddr
out
8 SP-SP-1 Zout. SPin. MARin 12
memMDR
MDRADD Z
Wait for mem access T9 ZX
S Wnte a
mcroprogram for the instruction T9 PCMDR PCout, MDRin, WRITE PC-PC+1
ADD R, (R,I T10
out PCn 8 Check for intr
A3SumpDcn anacd
MDRSP] Wait for 3
MDR IR
tate
9perstion Microinstructions T11
mem access
MDRoutRin pending
1 PCMAR | PCIS Raddr T4 CLRX SETC SP
PCaM MARn Read, PCin IS Raddr out YMAR Yout MAR READ. SUB. 2
Clesr y, Set Cn, Add, Zn 7. Write
2 MMBR
a

ADD R, 145H)
microprogram for the instruction: CLRC T9 SP- SP 1
Zou SPMAR
Lost. PCn Wait 5
for mem MDR PCMOR
PCPC+1 memory fetch cycle Wait for mem accesS
T10

PCMDR WRITE
T-state Operation
3 MBRIR Microinstructions T11 MDR SP]
MBR, IRn
T1
X»Temp Xoul in Wa er mem a c c
4 memMDR PCMAR T12
Walt tor mem
access PCout MARn Read. 6
MDR ALU MDRut: 2in. ADD
PC S Raddr PCS Rador out
5 MDR ALU Clear y, Set Cin. Add,
MDRu Z ADD Zn ZX
Write a
microprogram for the
instructon MUL R
Z R T2
M-MBR Zout Xn R2
kout PCin Wait for 8
Check for intr
17 Check tor intr
Assumption enabled intr PC-PC+1 memory fetch cycle Assumption enabled intr
T-state Operation
pending 3 pending Microinstructios
CLRX, SETC, SPoun.
MBRIR MBRoui, IRin CLRX, SETC, SPau PCMARR
SUB,2 T4 IR addr MAR PCosa MAR Read
IRut MAR. D, CLRC SUB, ZIm Crear
T8 SP- SP-1 TS RX
y. Set Co, Add
Zou. SPin. MAR Ra out in
9 SP-Sp-1 Zout. SPin, MARn
T9 M-MBR Za PCm
PCMDR Wat or
PCBu, MDRin, WRITE T5 mem >MDR T10 PC MDR PCout, MDRn, WRITE memcry teh oycie
Wait for mem acc859 PCPC1

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PUDIICatiga Tech&neutedge
 DLCO&A (Sem. !ll/ Comp. i MU) Control Unit Desi
Tstate
2. In Operating system:
DLCO&A (Sem. Ill /
Operation Microinstructlons
Microprograms can be used to
Comp. AU)
3 MBR- IR MBRt. IRn the primitives of operating system. implement some of Tt is used to
generate a set of
control signals. It is fixed sequences
sequ of4-13
4
R This simplifies operation system variety ofstandard" implemented
digital logic using any of a
R utXnCLRC also improves the performance of
implementat The major advantages of circuits.
ntroi Unit Design
the Inputs
RALU Rot MUL, Z, system. operating higher speed of operation hardwired control uni State
units re 2 ..... Outputs
T6 ZR 3. In High-Level Language support: required for
implementation
and
and smaller space
S.S S
R3in IC (Integrated Circuit), on
silicon wafer
ince the ie. the
components
7 Check for intr In High-Level language various sub required are lesser.
Assumption enabled intr
be
functions
implemented ususingand
data types can
pending The only disadvantage is that
microprogramming. design modifications
CLRX SETC. SPout
are
slightly difficult. to the S S1 S2
This makes compilation into
SUB, in
language from possible.
an
efficient ma
machine
The use of
hardwired control unit is
S. -O
T8 SP-SP-1
the RISC designs. majorly found in Fig. 4.4.1:State
(b) Moore Type
Zout. SPm, MARn In Micro diagnostics: tables for a
There are different methods 4.4.2 finite-state machine
T9 to
implement hardwired Delay Element
PC MDR
PCoun. MDRn. WRITE Microprogramming can be used tfor
detection
control unit
This method is
Method
isolation monitoring and repair of State table method.
T10 MDR ISP] Wait for mem access system errors, ie. D-flipfiops. implemented using delay elements
This known as micro
diagnostics and they Delay-Element method. A
flipflop
T11
PCIS Raddr PCn IS Raddr out enhance system maintenance. significant 3.
Sequence counter method.
is made to
give output iogic
specific event or in a t-state in
1 ater the
4.3.5
Applications of Microprogramming :
In User Tailoring 4. PLA method. Outputs of these sequence and the
flipflops are used to
4.4.1 control signals or generate
MU :May 14, May 15 By using RAM for
implementing control memory State Table Method: the
operations that require a micro-instructions i.e two
(CM), it is possible to tailor the delay of 1 t-state between
University Questions machine to different In this method state transition them are
separated by D flipfiop between
Q.1 What are applications. made and hence a
for each
instruction is
a
them.
applications of Fig. 4.4.2 shows this
microprogramming ?
InEmulation This state table is
state table is
obtained. impiementation.
(May14, May 15, 3Marks) Emulation refers to the use of a
then combine to
form a
Input
Applications set state table,
where all the instructions instruction
ofMicroprogramming one machine to
execute programs
microprograms on are considered (OPCODE) HOP
for another machine. originally written next state is
as
inputs and according to this the
1. In realization of being determined.
control unit This is used Each state with a S,| CLK D-fiip
Tiop
rol
widely as an aid for users in set of
microinstructions to be Signais
2. in
operating system from one migrating ISSued to various
computer to another. well as external components of the processor as P

4.4 Control Unit: Hardwired control signals.

3. In high-level
language support
Unit Design Methods: Control This state table is
then Output
4. In microdiagnostics and
combinational
implemented using flip-flops Fig. 4.4.2: Use of D
circuit to flip flop asa delay element
MU: May 14, May 15, Dec. control signals. generate different between two
5. In
15, Dec. 16, May 17, De sets of control
signals
user
tailoring University Questions An
example state table
nput

6. In emulation
Q.1 Describe hardwire Fig. 4.4.1. implementation is shown in
HOP
control unit and spec
Fig. 4.3.2: Applications of
advantages. D-flip
nputs CLK
Microprogramming May 14, Daec. 15, State fiop
The
applications of microprogramming Q.2 Dec. 16, May 17, 10 Maro 22
are Explain with
diagram
functioning of Output
S,O2S,2O,2
1. Contro
In Realization of control unit Control unit Sgnals
Q.3 Explain (May 15, 8 Marks) S21 O2,1 S22Oz,2 S O
Microprogramming is
used
widely now diferent technique for design of contr CLK
D-ilip
tlop
implementing the control unit for of computer.
of
computers. he (Dec. 18,1o MarksJ HOP
hardwired control unit is viewed
an
combinational logic circuit.
as a
se LS,S 1. On. 1Sn 2 On,2 Sn Onm Fig. 4.4.3:Use of OR gate in delay element method of
hardwired control unit
Fig. 4.4.1(a) : Mealy
TechKnau
uDCa
ECRKnowledge
'0ns
DLCo&A (Sem. ill/ Comp. / MO) 4-14 ntrol Unit Des
The signals that activate the same control signal are The OR gates outputs are the Outputs of
ORed together ie. if a PLA and are used as control signals in the Overall DLCO&A (Sem. I1 / Comp. / MU
signal has to be activated from
the outputs of the inputs to the AND array is from varinemie the individual
multiple flipflops then an OR gate Is onents of the -15
used as shown in signals generated and the output of the OR ontrol external devices.
Fig. 4.4.3.
given as control signals to various array is processor and the
In case if a decision is to be made then
implemented using a lf-Then-Else circuit i.e. two AND
it is components
processor as well as the external control of the equ Status
If a
microoinstruction
is
Control Unit Design
required. signals Sarting and bre
Starinncer
1lags C C Ca encoded as given
gates coupled to a OR
Fig. 4.4.4.
gate. This is shown in Fig. 44.6 shows the implementation of
address generator)

Condition
C G C C A belo
the PLA A A
method of implementation of control unit. o0 1 o
CLK ontrol addresg Then the
PLA control
rogiøtonjuO] on
execution of
information 0100110 indicates that
signals C, C and C, above
will be
microinstruction,
control
Control
ANDArray OR nemon Address field activated.
Yes Array contains the address of
A= 1 A 0
microinstruction. the net

Fig. 4.4.4:
Implementation of If-Then-Else in delay element Mioro-Instructionreglstor hus, after
execution of the above
next
instruction to be executed instruction, thne
method of hardwired control unit Control step lags and is one which is at
4.4.3 Ountor Ondon cod09 Control address 010. the
Sequence Counter Method slgnals
Decoder
he control
In this method, Fig. 4.4.6:PLA technique field tells the
multiple clock signals are derived be activated control signais which are
to
4.5 and the address
from the master clock
using a standard counter Control Unit: Soft Wired (Micro Control slgnals Control address of the next field provide the
slgnals
decoder approach as shown in the
Fig. 4,4.5. programmed) Control Unit Design
within CPO to
system bus
In Wilkie's
microinstruction
to be
executed.
Fig. 4.5.1: Micro control, control
These signals are
applied to the combinational Methods : MU: May 14 4.5.1 Wilkie's
programmed control unit program logic array.
memory is organized as a
portion of the circuit.
As
University Questions Microprogrammed Control Unit The Control
Memory Access Register (CMAR) can be
shown in Fig. 4.4.5, the counter
keeps on Q.1 Explain with diagram MU: Dec. 14 loaded from an external
incrementingand generating different functioning University Questions source
(instruction register)
The counts are decoded
counts.
Microprogrammed Control Unit. (May 14, 8 Marks) Q.1 Explain Wilkie's Engine (Hardwired
as well as from the address fieid of
using a decoder and the Micro Control Unit) in microinstruction.
decoder outputs are given to various programmed control unit generates control detail.
control signals in the CPU.
as components signals based on the microinstructions stored in a First working model of a
(Dec. 14,10 Marks) A machine instruction
typically provides the starting
Begin special memory called as the control memory. unit was micro-programmed
proposed by Wilkie's
control address of a
micro-program
in control
in 1952. memory
D- Enabs CE In the above On the basis of
-

Each instruction
points to a corresponding location design, a
microinstruction has two
starting address from instruction
End
Modulo-k
in the control major components: register, decoder activates one of the eight
Counter
memory that loads the control signals 1. lines. output
in the control Control field 2. Address field
Clock register. -This activated line, in turn,
Rosot The control Co C C2 Co--1Bn-2 o generates controi signals
register is then read by a sequencing Control fleld *-Address fleld
and the address of the next
microinstruction to be
1/k
Enable
logic that issues the control executed.
EN
Dooodor
signals in a proper Flg. 4.5.2:A typical mlcroinstructlon
sequence. This address is once again fed to the
CMAR res:ilting
(CMAR)
The in activation of another control line and
Clock implementation of the micro
programmed address field.
penod 1O,comos
hon
shown in the Fig. 4.5.1. This cycle is repeated till the execution of the
I Q2 comos
and 80 on instruction is achieved.
O, O2 The Instruction Register
Fig. 4.4.5: Sequential (IR), Status flag a For example, as shown below, if the machine
counter method of hardwired
control unit Implementation
Condition codes are
read by the sequencer
tio lo true instruction under execution causes the decoder to
4.4.4 PLA Method: generates the address of the Dncodet omkton

control me have an entry address for a machine instruction in

In this method location for the e IR. control memory at line 000.
PLA
(Programmable Logic Array) is
a
corresponding instruction
in
used to This address is
generate the control signals. PLA is an array
of AND gates at input and the OR
stored in the Control address regi
The decoder activates the lines in the sequence given
that selects one of the locations in the control below
gates at output. dros9 h
The inputs are to be given to the memory having the corresponding control signals. Control signal Address of next
AND gates, which LIne activated
can be connected to the
specific OR gates as generated microlnstruction
These control the
000 Co. Cz. Ca. Cs 001
required. signals are
to
given Coniml ulkd C. C 010
microinstruction register, decoded and
i v e n to
001
then Fig. 4.5.3 : Wilkes control
ech Knowledg
o n s

Tech Know
P DCa
 Control Urt esiu
DLCOSA (Sem. INComp. / MU) -10
Minroirofarn nirn
Control algnal Address of next
LIne actlvated vanesontr
generated microlnatruction
010 Co. Ci C 011 Micsoprogrnin risriay
011 C, Ca. C emmmet
On execution of microlnstruction at adelres 011,
acddress of the next microlnstruction depends on the Microinsirutioi (eister
external condition. ere

If the condition is true then the addross 101 will be

selectod else the acddress 110 will be selected. Nanoinstructiiri risriry

4.5.2 Comparlson botwoon Hardwirod and

Micro-programmod Control: Nanoinstriaion rogistar

Attributo
Hardwlred Mlcro-programmod Flg, 4.6.1:Nano programming
Control Control

The nanoinstruction memory

contairns the actua
Speed Fast Slow wide,
micro-instructions which is very
Cost of More Cheaper
implementation
Implementation
approach
Sequentlal
clrcult
Programming Reviow Questions
Flexiblity Not flexlble, Flexlble, new Explain fetch cycle with the corresponding
machine Instructions
Q. 1
diffcult to
can easlly be added. mlcro-program
modify for new
Describe the register organization within the CPU
Q.2
Instructlon.
Ablity to handle Difficult Easler Q.3 Explain microinstruction sequencing and execution

Write short notes on microinstructions to execute a

Complex Q. 4
instruction MOV [R1, R2.
instructions
Design process Complicatod Systematic . 5 Explain microinstruction sequencing and execution
Decoding and Complex Easy Q. 6 What are applications of microprogramming?
sequencing Q. 7 Write short note on state table method of control unit
logic design
Applications RISC p CisC p Q.8 Explain the sequence counter method of hardwires
Instruction set Small Large control unit.
size Q, 9 Explain with block diagram the micro-programmes
Control memory Absent Present control unit.
Less More s
Chip area Q. 10 Describe hardwired control unit and specify
required advantages
4.6 Concepts of Nano Programming: Q. 11 Explain with diagram functioning of hardmire
MU May 14, Doc. 14, May 15, Dec.16 Control unit
a. 12 Describe hardwire control unit and speciy
Univorsity Questions
advantages.
Q. 1 Explaln concepts of nanoprogramming.
(May14, Dec. 14, May 15, Dec. 16,6 Marke)
Q. 13 Explain with diagram functioning9
Fig.of 4.6.1 explains the Microprogrammed Control Unit.
The following block diagram
flow in a nanoprogram concept, Q. 14 Explain Wilkie's microprogrammed control unit
a.15 Explain Wilkie's Engine (Hardwired Control Unit)"
(control ROM) is much
The microprogram memory detail
contains pointers to the actual
narrower because it Q. 16 Explain concepts of nanoprogramming
microinstructions.
a. 17 Write short notes
The microinstruction register
contains a short pointer
on
nano-programming
that to the nanoinstruction memory.
points
Tech1 Kaawledge
ECatit5s
 Chapter

Memory Organization

r=an ~~:: ,:ct~::~•o;·~:~~--;: ..:::=:.•::~::•:::~ :-le~:I:::,~~-

'
5

characteristic, Cache memory : Concept, Locality of reference, Design problems based on mapping
I techniques, Cache coherence and write policies, Interleaved and associative memory.
~':«½i. - ~'®,\"1$.i

5.1 Introduction to Memory and Memory 5.6 Cache Memory : Concept, Architecture (L1. L2, LS)
Parameters and Cache Consistency

5.2 Memory Hierarchy Classifications of 5.7 Cache tv1apping Techniques

Primary and Secondary Memories

5.3 Types of RAM and ROM 5.8 Interleaved and Associative Memory

5.4 ROM (Read Only Memory) 5.9 Virtual Memory

5.5 Allocation Policies

 Memory Orga .
- -·
'Ille ) ~ ~ == ~ = =5~·l2== = ==== ==== ====
==a: ~~~~ n1za1ion
=
5.1
I !,.
- _:'Y'~!D~L~C~O~&A~_i(~S,:e~m~. !_!11.!, . /~M~U,!.
m~p:;_,
i ~C~o~
if pLCO&A (Sem. Ill/ Comp. 1 MU)
Introdu ction to Memor y and (c) External : This is no rmally removab le O .
r 111 ttu al Hence access t ime depends O .
Memor y Parame ters : memory and hence access is slower. n 1ocat1on
location. and Previous
2. Capacity : Memory Organization
For example magnetic or optical disk.
fflilN4tiiM--i't4111·1,Li It is measu red in terms of the Word size
and the Let take the same example th - The- Ph>1'ica1 .
Q.1 number of words. at a Pers matenal using ' ,t,· h the memory is
What are characteristics of memory devices ? listen to the third stanza of th f on Wants to made can b,, dif! ' ,c
. e OUrth son (a) - ,ere:,1 li<E :
Word size is the size of each location. Number of then he can directly reach to th g on a co Semiconductor :
(May 14, 8 Marks) '
e fourth
Q. 2 words is the number of locations . thereafte r he has to access th song, but .
List different memory organization characteristics . Memory can be
e stanzas of h
sequentia lly tp rea ch to the third t e song i.e. !Cs fo • ll'lade •JSing S€m:-:onductor materi al
(Dec. 15, 5 Marks) 3. Unit of transfer : stanza. ' r e-,ample RAM.
Q. 3 (b) Magnetic :
Describe the characteristics of memory. (c) Random access :
This refers to the size of the data that is transferred
Memory can also be .
(May 16, Dec. 16, 10 Marks) in one clock cycle. It main ly depends on the data bus · In case of · random access i d. . . mace using magnetic read and
n IV1dua1 add resses write
When a memory is taken
I Charticterl allca
of Memory Syatem
I size. identify locations exactly. mechanism. for example magnetic disk and
magnetic tape.
then there are variou s
The data as discussed earlier may be internal or Hence the access t ime is independ (c) Optical :
characte rist ics r+! 1. Location
I .
previous access. For example RAM.
ent of location or
of th is external and according ly will be the data to be
memory that are
H ii CPU
transferred in one clock pulse :
- Optical m• mories . .
i.e. memones that use ootical
In case of a RAM, any location to be -
consider ed . 7 b . lntemal accessed can be methods to read and Write have become fa;,,ous
(a) Internal : It is related to the communi cation of . directly reach ed to without going th th
- The characte ristics of
7 c , &tL>mal
locations sequentia lly.
rough the ese days, for example CO and DVD.
data with the memory directly accessible . It is
memory are based ~ 2. Ca.ia cJty (d) There are some other methods using which data was
on usually governed by data bus width. (d) Associative access :
~ 3. un:1of lnlnsler S!ored in early days like Bubble and Hologram.
the following :
(b) External : This is the data commun ication with Physical characteristics :
~ a . lnlemal I · Here th~ . da,t f _is ')i:icated, by ·a comparison with 7.
the external removabl e memory or virtual
b. External

M_ 4. Acce ss rnelhod
J memory. It is usually a block which is much
contents of a portion· .ol tlie·stored .d~ia(addre ss).
- The physical characteristic of memory is also an
Hen'ce the. access ,_time is· i ndependent of location or important aspect to be considered .
larger than a word.
I. a. S~Quential access previous access. For example .cache. - This indudes the volatility, power consumption,
4. Access method :
H b .Dlred acce ss erasable/ not erasable, etc.
In case of cache memory, each location has a tag
'-i c. Random occcss ~ There are various methods of accessing the memory 8. Organisation :
associated with it, and to reach to the required
"'."""l based on the memory organ ization. . . .,
-{ d Associative location the tags are to be compared with the - It 1s not that -always the •memory will be organized
r+f 5. Performance These methods are listed below w ith examples : location to be accessed. sequentially.
-~ • Acr.essti- Q (a) Sequential access :
- There are some other types of memory organization
There are technique s used to reach to the required
b~ Memory cyclo ti~
The sequential access means start from the tagged location at a faster speed. like interleaved memory, etc. Interleaved memory is
t-+'f 6. Physical type beginning and read through in order until the byte 5. Perform ance : used in microprocessor 8086.
~ aml~ nductor
I
to be read is reached. 5.1.1 Bytes and Bits :
The performa nce of the memory depends on its
.- b. Magnetic
Hence the access time depends on location of speed of operation or the data transfer rate. The byte is a unit of digital information that mostly
~ C. Optical
data and previous location accessed . consists of eight bits.
The data tra nsfe~ rate is the rate at which the data is
,-.i 7. Physl~l ~ ;a~ ris ~
For Example, magnetic tape. If one wants to listen to transferre d . The speed of operation depends on two _ Infact, a byte was the number of bits used to encode
8. Organisation
. L the third stanza of the fourth song stored in an audio things : a sing le character of text in a computer and for this
Fig. 5.1.1 : Characteristics of memory system reason it has become the basic addressable element
cassette, he has to go through the entire first song (a) Access time :
1. Location : second and the third song, and then t he first stanza, . . t he add ress and getting in many computer architectures.
The t .ime between prov1d1ng
second stanza of the third song and then reaches to The size of the byte has been hardware dependent
The memory can be located in one of the following : the valid data from ~emory is called as its access
the third stanza of that song . and no definition exists.
(a) CPU : This includes CPU registers and on-chip time i.e. the address to data time.
(b) Direct access : of eight bits is also
cache memory. • The fact .,s that standard
(b) Memory cycle time : permitting the values from
f two
Here individual blocks have unique address and the ry to "recover convenient power o
(b) Internal : This includes the memory that the The t ime that is required for the memo two
access is done by jumping to vicinity plus sequential . e between 0 to 255 for one byte.
processo r can directly access. _before next access i.e. the t im
search.
addresse s is called as memory cycle time.
"•, Ted1Kno111 led~:
~ u t>IIC a tlCI
P
 Memory Organization
5-5
7 ..,_ pl.co&A (Sem , ill /Comp. / MU)

1zatlon l(a) shows the structure of a DRAM 11 . operation, the select line must
Similarly to r th e vmte
_.....,_,_._.----==M=e=nn=o=iry~O;,;rg~a~n· Fi9 · 5·3· ce .
1. be ena bled by making it logic '1' and the Read /
0 ,he ddress line selects the particular lo ca 10n it
__,,,.,..,...- - - - s tlie memory hierarchy based a
- ena bieS the MOSFET that connects the ca . ' to
pac,tor Write line must be logic ·o·.
to be read
v~• 1P!;,·~/M
1l~C~o~n~
~D~L~C~O;:&~A~(S:;e~n1!;,·,!.!I11 :::;,:;;;U)r.,- - ,,,eani119 was
n- - to t11e processor.
Fig. S.2.1 show n the the data bUS and hence if the data is Thus the data from the in put line w ill be stored in the
. as discussed are the closest to gets the data to be read·, Wh'II e .'1f
O l the data line .
SI·mpl''
• With 1so/J EC aoooo-13, this cornrn c1oseness
. on flip -flop.
use varia The registers
d i,ence are the fastest wh ile off-I·the t e ata is to be written the data is to be given
codified in a formal standard. . bleS d
h I
he data line and w ill be written on the capac't Table 5.3.1 shows the differences between the SRAM
P . ,.,,o,i·ke,omagnetic tape are the farthest and al'•
- M•"1 ,,,.. o< "'''""~' . If le of . .ts.
e1gl1t bi t Address line or.
so and DRAM.
representable in eight bits or rnu ,p storage '
t. ns of Table 5.3.1
5.2 Memory
Primary and S-~ ~
HierarchY : c1assiflca i_o .
ry .M,em~:- - the slowest.
The list of memories from closest to the processor to
the farthest is given as below :
Sr.- ORAM
- •·••-"'- Transistor Storage SRAM
capacitorT ,No:
Registers Continuous refreShing
1. No refreshing required.
th 1.
&if§t-W•¥ ➔ ft•l
Q . 1 Explain in details Memory HierarchY wi 2.
Ll cache
Ground
required (disadvantage) .
14 6 L2 cache Bit time
examples. (M 8 Y • Marks) 3. B 2. It is faster for accessing It is slower in accessing
th Main memory (a) oRAM cell structure
a . 2 Describe the memory hierarchy in e computer I 4. SELECT / Address line data. data.
system. (Dec, 18, oec, 19, 5 Marks) J Magnetic disk
th 5. It takes more space on It takes Jess space on chip
Memory hierarchy explains that the nearer e 3.
Optical chip as more number of as less number of
memory to the processor, faster is its access. 6.
Tape. components are required components are required
But costlier the memory becomes as it goes closer to 7.
To have a large faster memory is very costly and per bit. per bit
the processor. hence the different memory at different levels gives Hence is cheaper.
The following sequence is in faster to slower or 4. Hence is also costly.
costlier to cheaper memory : the memory hierarchy. Bit density is more.
5. Bit density is lesser.
l. Reg isters i.e. inside the CPU. How does this memory hierarchy give faster
6. The bit is stored in a flip- The bit is stored as a
2. Internal memory that includes one or more operation and some other terms like cache etc. will flop. charged or discharged
levels of cache and the main memory. Internal Read / Write capacitor.
be understood in the subsequent sections.
memory is always RAM. SRAM for cache and (b) SRAM cell structure
Types of RAM and ROM : 7. SRAM is mainly used or DRAM is mainly used or
DRAM for main memory. The differences Fig. 5.3.1
5.3 selected for cache selected for semiconductor
between the SRAM and DRAM will be seen in a On the other hand, the SRAM has each cell made of
5.3.1 SRAM and DRAM : main memory.
later section in this chapter. This is also called a flip-flop, thus requires more components as memory.
RAM (Random Access Memory) is called so because
as the primary memory. compared to the DRAM cell . 5.3.2 Types of Memory :
External memory or removable memory any memory location in this IC can be accessed on the silicon wafer,
Hence it occupies more space
3. We will also see how to place the memory in
includes the hard disk, CDs, DVDs etc. This is randomly. and is costlier.
the secondary memory. There are two types of RAM. namely, SRAM (Static different locations in the system.
- Thus it is also costlier. But the advantage is that it
To begin with we will revise the different types of
RAM) and DRAM (Dynamic RAM). doesn't require any refreshing and is also very fast
memory that can be interfaced w ith the processor.
SRAM is made up of flip flops while the DRAM is compare to DRAM.
The different types of memories used with
made up of capacitors. ' Fig . 5.3.l(b) shows the structure of the DRAM cell.
processors are EPROM (Erasable Programmable Read
Since DRAM is ma d e using
· capacitors,
. . requires
1t . less - The flip-flop is used to store the data. Only Memory) and RAM (Random Access Memory).
number of components to make a one bit cell, hence - Th ere ·1s a AND gate at the output of the flip-flop,
5.3.2.1 Memory Map, Structure and its
also requires less space on the silicon wafer. · be enabled by the select line (that works as
wh·ic h will
Requirements :
Thus it is also comparatively
. cheaper. But it is slower an address line) and the Read / Write operation The read / write memories consist of an array of
than SRAM ' because capacitors r.equ ire time for (when data has to be read) when it is logic 'l'. registers wherein each register has a unique address.
· and discharging.
ch arging I Fig. 5.3.2 shows the block diagram of a memory
- Th us when both i.e. the select line and the Read
Also the capa c,tors
. .
hence need to
.
b e
loose charge in some time and
recha rged according to the data,
~ . be
I'ines are 'l ', the output of the flip-flop will device.
..r,
~
Tedi Knowled9i
P 11b l lCat1ons
Fig. 5.2.1 : Memory hierarchy available on the data line.
this 1s called as refreshing the DRAM.
 Memo ryo
rqani~ar
. , oLCO&A (Sem . Ill / Comp _I MU)

V DLCO&A {Sem. Ill I Comp. I MU)

5-6
,--
= Slzeo fm~
'On
Number of address lines ory In
N : number of registers required bytes
~ rganization
M : word length . - fj
64 ----- -
CE
Addresses

Chip enable ~ lelors11s l

Example : 1-;::::- i _ ----: ___ __JI
~

7 128----------- 1 CS -OE • _;;; .

Output enable
~
OE
- 8 data ~

lf a memory is having 13 address lines and 13 256 -----------

rs / memory location s 0 0 -0 7
1 X I
-
~

lines. then number of registe 9 512 ------- - Outputs

= 8192 word length = M bit = 8 bit
13 0
= 2• = 2 110 1024 ., 1-;;--- --

I~o
PGM Program
- The number of add ress lines of a microp
rocessor ~

11 2048 _, 2; - - 1 I
~
N.C. No connect
depends on the size of the memory. 4096 ., 4 ~
~
·12
Data Inputs Fig. 5.3.3(b)

r-
8192 ., B ~
l ! ! !p+-@ 13
·14 16384 " 1s;- -
Table 5.3.3 : RAM !Cs Ex. 5.3.1 : lntert
- ace 4 KB of EPROM with star-"ng address
~
Input Buller O+- ~ cs from OOOoH
Memory size and 2 KB of RAM W11h starting

j 15 32768 ., 3 ; ; - IC No. Type

address followed by EPROM
Address
input

A o - .=
~
i£
N, M
Memo,y

Output Buffer l>+--R Dp+- -

16

5.3.3 Memory Chip Size and Numbers

:
65536 "

--
64--;-- 6116

6264

21 14
SRAM

SRAM
2k x B

Bk X B
Sofn. :

Note : Let us assume the

processor has i 6 address fines.
Step 1 · T tal EPROM required = 4 kB
' o
i i i J Table 5.3.2 : EPROM !Cs available ln the market
,.,:-,:...,
Vee
SRAM 1kx4
Chip size available = 4 kB (assume ) OC 2732)

Data outputs IC Memory size A_ddrelis:•· :> ·Nu~ tii~ 4 kB

data
·_.r
,.... "/ _'.· •,,~Inf ': - A12 ·2 . 27 m- :. No. of chips required =4k8 =1
number 26
Fig. 5.3.2 : Block diagram of a memory device A7 3 CS 2 A,
2716 . 2 k x ~ . ·., , ··>·~:24~· :th··
......:.:._•
,.. 4 25 Aa A,
Vee
Chip 1 : Starting address = 0000H
Numb er of address lines
required
Size of memory in
bytes 2732 4k x 8 24
- A, 5
-- -24 Ag
A,,
A, 3· A.,
23
22
Aa
Chip size = 4kB = OFFFH

2 Bk x 8
- A,
A,
6 23
~
A,
A,
4 21 WE'
(Actually 4 kB = 1000H, but here we have
1 2764 28 7 22
20 !)!
2

3
4

8
27128

27256
16 k x 8

32 k x 8
28

28
A,
A,
Ao
110,
8

10
6264
21
20
19
1107
~.
A,o A,
A,
Ao
6

8
8116
19 A,o
18 ~
17 vo,
Ending Address = OFFFH
EPROM
OOOOH
taken OOOOH to OFFFH)

11 110.
18 110, 9 18 vo,
4 16 27512 64 k x B 28 ChlP 1
110, 12 1105
17 110, :10 • vo, OFFFH
15
5 32 110, 13 - , ;.1e 110, l/02 l/0, RAM 1000H
11 . •1~ Chip1
GND ONO
14 .~ '_. . ._1/i. 1103 _1 2,;, .'_13 l/03 1iF~H
,,..,,.A ... ;-;, .i,,J\·.--,

.,
"'
·, t _~-l ·- ~ ~-/;l 'i t~'.'.~
<(
:fl Fig. 5.3.4 : Pin configuration
.;
,._ ;g "',._"'
"',._ !;; ;:: 27128
A,s
"' "' Vpp
"' "'
.,...
Table 5.3.4
Vpp Vee " Ve·c ; Vcc • -V/;1;,, ' ~ •; i.•·

A,2 A,2 A12 ~ . ,J5mj ' .~,,.~'.-1:i*;; :·;. Truth Table fo_r 6264
A, A,
A7
As
A7
As As As
A7
As
A13
As
Vee
As
Vee
As
N.C. ·A13 : Ai a
- As As ·As ,
~

WE
-'--
·.c:s1 . ·C:S2 ·oe.
--"- - - _Mode
As As As As As Ag Ag Ag Ag .

A:i
A, A,
As
A4
A:i
A,
~
A,
Ari ~
""Ai1 ""
"vpp
~
A11 A11
or ~ ; or ·
A11 {',;•; ·· ~
X 1 X X Not selected Step 2 : Total RAM required = 2 kB
Chip size available = 2 kB {assume) OC 6216)
0 p X X 0 X (Power down)
~ A2 ~ ~ A2 A10 A10 A10 A10 A10 A10 :; 2 kB
A, A1 A, A, A1 :. No of chips required = kB = 1
.Ao Ao Ao Ao Ao
CE
o,
--~ ~ CE c:e· ct
o · O'f';c - 1 0 1 1 Output disable 2
·o, ·0 7 o7 7 EPROM + 1..
Oo OoOoOo Oo Os o.;: ' 1 0 0 Read Chip 1 : Starting address= ending address of
o, 01 o, 0 1 .' Ps Os · Os Q6 i >--. 1

-
01 ~ l·= _lOOOH
= OFFFH
. 02 02 02 02 0 2,
05 0
s . -Os ., o~ · o5_ ;.~v 0 0 1 Write
o, 1
Chip size = 2 kB = 07FFH
;_GND. •GND. :GND GND GN~
03 :.;.< ~4 ?~., .,
?4 1_-~--.-'.,---.4~:_'.::3 < f_,_oo·_•_·s~-~-~
._ 3 ,. -:,,03;. :; 9~ . ,,"' ·,
--•.;_t__:..
0 0 1 0 Write
:. Ending address = 17FFH

---------------.:__:_:~=~:::.___ __ __ __8-=--'rec11Kna -----------=--- == == --- --- --~- ..:.:_::,_....::...--- -----;_ij•~yecfl~l('90~•i~u~1if

:...---< Fig. 5.3.3(a) : Pin configuration
'if# PUii ii tat t ons

111I•,:
V purtllt at lO
 s11m Ill / vim / MIJ V,

(hip Ill- , nFF~<i

En<i ln".J addre1i ~ lHF ►'

: f otal AAM requ ired ~ R kB

r (11tlf 1MLI 9!11P 2 Chip 11le available • 4 •8 I I( ~l /1 '
V OlCO~>- '''" Ill A,, ] A,o 8 ~8
A,r
SltP 1
M•m"'ry ~•11
l Att
Au An
0 0
No of chip~ required =tta =l

[
p •~OhH"•P'
SA · n<><\011
~A•OJ'rlH I
i~
J
~

~
(I

~
(!__ J
, I,
0 0 0 0 0 0
cnlP ·
1 Chip size = 4 ~B , 0FFFH
,
, starting address = EPROM ending addrm • 1 _ 1,HH • l , 2'l',;,,

0
0
0 0 ·. Ending address = 2FFFH
➔
)', )' • 0
I , - 0 1 . Starting address = Previous ending + l = 2FFFH • 1 = llf.Jlh
1 &A • l(){l()H '[;_ cnlP 2 .
I RA!IA ehlP Chip size = 4 kB = 0FF•H
£1' - 171'fH i 0
Ending address = 3FFFH
\ -Y~
Full d<!Codlng 1oq1<
... ------"-
"'M hp 1l1P • 2kB
n >ROM t11,,,.1z• • dk6 3nd IV' C I A and cons1de1 ,pr,,a n,n, I n address
RAM - 2 kB = 2u
sr,,allei ch1P size ::::> ·
1ines
A
11 II
.
- to A for decoding.

SK Of EPROM and B KB of ou,

St•P 3
. Memory map :
A15 ~. ~, ~J ~,· A,o A, A, A. .. A. >-, JI.;
--,., - .
N~l-tl lowP• 11 3od•e» l111e•, e A.. to 11' ; ; ~ :;; ;

~
')

.
"""'
- - · 1 the five 5 3 2 • Interface 0 0 0 0 I) IJ
Hl'fl(~ ;.3l d<!COO<!' 11 ,e<iuirtd Hen((>
E
circ eh~ S IWO· E~. , • · using ,KB de\liCIIS,
PROM
_
EPROM SA= 0000H
0 1 1 1 : 1
. ' '
bib 3~ ,,,own en nu!'rt1ory rnap chip 1 EA= 0FFFH
Soln.:
po»11)1i,t1• 1 ()()()OOI> and OOOOlb thu> it require• Yr Not• : Let ua ,saume the processor has 16 address lines.
1
OOOOH -Yo '.) )
and y o utpUI> of t he S32 d.code RAM ha> ooo!Ob J :)

CJ
EPROM 0 () ~
0 0 0
Chlp 1 OFFFH EPROM SA= 1000H
0 0
, .
and "~""" ,1 reQuirt, Y: output of tM decode,
Step 4 , Flntl 1mp1<1m1nc.tton :
EPR0M
1000H
chip 2 EA= 1FFFH
1 1 1 ; 1 1 l
' '
Chip2 1FFFH '
r. - To EAAOMQt1pi
2000H
y,

-
'j
.,, Vi RAM ~ C
.
J j

□
To RAM Oflt>1 Chip 1 0 0 0 0 0
r, 0 0
6$2 fa - RAM
2FFFH
3000H
RAM SA= 2000H
1 1 , , 1
, 1 1 '.

___
1
Chlp2 chip 1 EA=2FFFH
3FFFH
,_ ...
f,- -Y, :; ;
: ~ l)

.
0 0

□
0 0 0 0
Fig. P. 5.3.1 0
RAM SA= 3000H
1 t
, 1 1 l 1

-
1 1 1
chip 2 EA= 3FFFH
-Y, y,: while
---
-·-
~-w..•""
6Moatal!Mii
Step 1 : Total EPROM required = 8 kB
Chip size availa ble = 4 kB (IC 2732)
Full decoding logic :

- EPROM chip size = 4kB and RAM chip size = 4 kB.

case}
-
EPROM cruo al"e h.lS Ot'OOo. th..; rt r~.;•res
EFROM .:ti•P r:wo ~a, iJOOlb. t ~ tt requ,res y,
soon.
and

~ · ,'J ~~\lcho 1

.. same in this ~
8 Smaller chip size (Both are A,.s-
i.:: EP~~2
kB -- 2
No of chips requi red = 4kB ~ r,, 'v.M ""'P 1
= 4 kB = i1
2

Chip 1 : Starting eddress = 0000H - :. Neglect lower 12 address lines i.e. A.i to A., and
>--, .. - ' -~
_.. "
.__ T,• 'i,\McNp2

Ai:,-
Chip size = 4 kB = 0FFFH consider remaining address lines i.e. At: to Ai, for

Ending address = 0FFFH decoding.

Ai. : -
-v;!
- .
th
Chip 2 .· Start·ing add ress = Previous ending + l - Hence 4:16 decoder is required. Hence circle e foui' Flg. P. 5.3.l
TtdlK-l1q e
0FFFH + 1 = l0OOH bits as shown in the memory map.
Fig. P. S.3.l(i)
 ~•, , co&A (Sem. Iii/ Comp. / MU) 5-11
f Memory Organization

-
0~
Memory Organi,latiori
........ ? ; : o r / map :
51eP 3 . A1s A1• Au Au Ai, A,o As At A-, Ao A,. A, Ao

I:
As A, A,
a
J
0 0
V DLCO&A (Sem. 111 / ComP / MU) R01,1chip1 0 a a a a 0 0 0 0 0 0
Ao-A,s ;: , ooooH 0 0
Step 4 : Final implementatlon : _ _ _ ___, E}. • 1fffH

to· y, .
RP,M Chtp1
0 0 0 0 0 a 0 a a 0 0 0 a 0
SA• 2000H 0 0
Efo, 2fffH
t1,crop!008S..°"'
,,ith 16-bll
address tines and Y2
8-bil data HneS

wiR
ioRD 4:16
Deooder
iOWR
OE
EPROM _
2732 ~ y
Fig. P. 5.3.3

n:
Step 4 : Final implementatio,----,,,-,- - .....

•Mlcroprooessor. p===::=:=::::;~:::::::~= :::> Do- D7

with 16-blt
-address lines and.
~ 8-bit data lines

Fig. P. S.3.2(a)
i.;M::::R.::Dc.__~O~E ,_Ao'-"n Do-~
· 2784
Ex. 5.3.3 : Interface 8 KB EPROM and 4 KB RAM to a processor with 16-bit address and 8-bit data bus.

Soln.:
Step 1 : Total EPROM required = 8 KB
ciE ..--"'"---".._ _
Chip size = 8 KB (Assume) ~-An Do-~ ·
'9232
No of chips = 1
we
Chip 1 : Starting Address = 00OOH
Chip size = 8 KB ⇒ lF H Fig. P. S.3.3(a)

Ending Address = lFFF H

Step 2 : Total RAM required = 4 KB Soln.:

Chip size = 4 KB(Assume)
No. of chips = 1
Chip 1 : Starting Address = 2000H
Chip size = 4 KB
. · Ending Address = 2FFFH
A computer system needs 512 bytes of RAM Assuming that the processor has 10 address lines to
Ex, 5.3.4:
and 512 by1es of ROM. RAM chip available is - interface 1KB memory (5128 + 512B)
of capacity 128 by1es and ROM chip available
is of 512 by1es. Draw memory address map tor Step 1 : Total EPROM required= 512 B
Chip size = 5128
⇒ 0FFFH
a computer system and also draw a
Number of chips required = 1
. . TldlKnniledgi
connection structure. ., PUD II C II t 10n S

'91 TecUno11ttdli
V P u b 11c .1ti o l'ls
 Memory
1f DLCO&A (Sem. III / Comp. I MU)
-----------------~=~~~!:!!:!.
V DLCO&A (Sem. Ill /Comp. I MU) 5-12

Chip 1 : Starting address = 0000H

= 027FH + l = 0280
128B ⇒ 007FH
~ ---- S-13
Chip size .Absolute (full) decoding logic :
Chip size 5128 ⇒ 0lFFH EPROM chip size = 512B While RAM . . Memory Organization
End ing address 02FFH . chip size - 12 Thus small h" .
0lFFH . th - 88.
Ending address address Imes 1.e, A to A6• Now sine
0
Starting address = Previous ending + l -_ 0oH .e ree address I"1 er c ip size = 1288 - 2'
Step 2 : Total RAM required = 5128 nes are remaining - · Therefore neglect lower 7
Chip 3 : 03 The remaining lines Le. A to 1,. •11 . , we need a 3 8 decoder·
Chip size = 128B ⇒ 007FH 7 ''9 W1 be inputs t 0 th
e decode r, as shown by circles in m
Ch ip size available = 1288 lmpl.ementatlon :
~
.
step 4 : Final
:. Total number of chips required = 4
Ending address = 037FH . ~
Chip 4 : Starting address = Previous en ding + l = H
Chip 1 : Starting address = Previous ending + 1 = 0200H 0380
Chip size 128B ⇒ 007FH
Chip size 1288 ⇒ 007FH
027FH Ending address 03FFH
Ending address

Chip 2 : Starting address - Previous ending + 1

Step 3 : Memory map :
.· ....... :..;:-,.,,
A, Aa '·A1 A,,"
]:',:~;:~·f~f;:- ·_·,·;,.L.;

~)
EPROMchip 1 0 O 0 0 '~ddies,,Jines a~\; , .. cs p

(:
SA= 0000H 0 0 0
,._,. B'bll diita·rines( .

-Yo -Y,- -Y2- · -Y,

EA= 01FFH
t~(il" ..
RAM chip2

Y,
SA= 0200H

EA= 027FH [; 0
Q :) 0 0 0 0 0 0 0 _cs. Ys

RAM chip 1

Ys
SA= 0280H

EA= 02FFH C :] 0
0 0 0 0 0 0 0
Ag
··-s
Ys

To EPROM chip

D
RAM chip2 Ae
SA= 0300H
0 0 0 0 RAM
EA= 037FH
0 0 0 we \':, ·-,. ~ Y1
0 ~t

Ys

□
RAM chip 3 SA= 0380H
0 0 0 0 0 0
EA= 03FFH Fig. P. 5.3.4(a)
1
Y1

Ag
-5,4
ROM (Read Only Memory) :
- Thus the application of ROM is for virtual or
secondary memories like hard disks, external storage
like CD / DVD and floppy disks etc.

.,;. We will see different types of ROM in the subsequent

2r-- - - , To EPROM chip
sub-section and thereafter some ROM memories
3'• r----c; .;;;,
used in computers like magnetic disk, CD, DVD etc.
Yf·r---- To RAM Chip 1
ROM or the read only memory is quite cheaper 5.4.1 Types of ROM:
,----- To RAM Chip 2
,---~ - To RAM Chip 3 compared to RAM and is mainly used for

---.;.;.;..... " - - --ToRAMChlp4

implementation of the secondary or the virtual
There are various types of ROM available based on
whether or not it can be re-written; they are called as
memory. ROM, PROM, EPROM and EEPROM.
 l
Memory Or _
• DLCO&A (Sem. Ill / Comp. I MU) 5-14
• • DLCO&A (Sem . 111 / Comp_/MU)
sequence of binary, in this case from "O V
These types of memories wi ll be studied in this to - 1
section. 11•. The aluminium substrat s
as there are three bit address. e Was used -15

There are some more ROM s available these days like The OR array (on the right hand in Fig. 5 4
· -1) coll\
es
1.
2.
Improved surface un·f . earlier but now I
I
Increase reliability 1orm ty 9 ass 1s us~
•u because
01
th --:::-:---Me::::~l!;~!:!:,:~~
e following .
mory Organization
flash memory, OTP etc. with programmable lin k, the ones to be ret .
aIned 3. Reduction in surface d
be retained while the remaining fused or O Can efects and
The ROM is a memory wherein. the user cannot write Pened 4. Better stiffness and h read/write err
s ockfda ors
anyth ing. Hence whenever a memory address is giv mage resistance.
. . en to th
Read
The data to be stored in the ROM is to be given to address lines (a, b and c In Fig . S.4.1) the s _ e curren1
Pec1fied
MR
the ROM manufacturer, who writes this data on the location will be selected and according to th
e fused senso, II
ROM and provides the same. links, the data will be available on the OR
9ates
output lines.
The PROM (Programmab le Read Only Memory) or
also sometimes referred to as OTP (One Time The EPROM (Erasable Programmab le Read
. Only
Programmab le) memory, as it can be written onto Memory) although extinct today and is repla ced by
2
only once. EEPROM or E PROM, but it used to be th e only
erasable memory available earlier.
When manufacture d, it is blank, once written on it. it
cannot be re-written. In case of EPROM the data written can be erased by

There are diodes that are used to store data, and keeping the EPROM IC in the UV box, as the UV rays

they are fused or kept as it is to store the data in erase the previously written data on the EPROM. R900fding
rnediun
them.
The EPROM as discussed earlier are these days . Fig. 5.4.2 : Read-Write mechanism
_
The reading and writing mechanism of th e magnetic
The internal diagram of the PROM is shown in replace with EEPROM (Electrically Erasable . .
memory Is shown in the Fig. 5 3_
·.4_ The data is also stored in a special manner such that
Fig. 5.4.1. Programmable Read Only Memory). first the data is stored in the first track of first platter
b C Writing and read ing of data is done with the help of (upper and lower sides) and then in the first track of
r{ r{ ,; + Predellned link
+ Programmable link
The EEPROMs are erased by giving an extra supply
voltage.
a conductive coil called as head.

The head may be sin9le for both read and write

the second platter(upper and lower sides), then of
the third (upper and lower sides) and so on. This is
Address 0 J &'
L.:.,I 5.4.2 Magnetic Memory : operations or separate ones. shown in the Fig. 5.4.3(b).
Add'9ss , r,:---
L.:.,I During read/write operation, head is stationary while
Sectois Tracks

Add,ess 2 r,:--- Magnetic disks are very cheap and widely used as the platter (disk) rotates.
3 -17'
L.:.,I
f
a:
external storage and as hard disks. Write operation is done by passing current through
L.:.,I 0
coil that p(oduces magnetic field and then the puls.es

I
,.,-:-,. as hard disks, they are called as
Address 4
~ When used
are sent to head.
Address 5 '&"
L.:.,I
Winchester Disk.
r,:--- Thus the magnetic pattern i.e. NS (North-South) or
Address 6
"-"-' Initially magnetic tapes were used for storage.
r,:--- SN (South-North) is recorded on surface below.
Address 7
. L.:.,I .. .n A Magnetic tapes are used even today in some places
Read operation is done by magnetic field moving
la b lb C le
V..)'\~)'()
because of its low cost and ease of data storage.
-
Predefined ANO array
6 6 6 relative to coil that produces current.
When huge amount of data is to be stored, magnetic According to the magnetic pattern the data is read
Fig. 5.4 .1 : PROM
tape is used. by the head.
·s in a special
1
The AND array is used as address lines and the OR I
The organization of data on the Patter
Let us see the construction of these magnetic
array as data lines. manner with concentric circles called as tracks as (a) Data organiution on a disk
memories.
'th shown in Fig. S.4.3(a). Fig. S.4.3 contd...
The AND array (on the left in Fig. 5.4.1) comes as The magnetic disk substrate is coated wi
Further the tracks are divided into sectors.
predefined connections as shown in the Fig. 5.4.1 in magnetisable material.
 ~r~• co&A (Sem . JJI / Comp. / MU)
Memory Organizat1
.on -.,_ DL 5-17
the co- ROM the data stored as pits and Memory Organization
~ In Iands as shown in .
. k . single platter, while a hard disk hese pits and lands are read by reflect·
~ ~ ~ f . . . mg laser. The CD h
Fig. 5.4.6(a).
_ A floPPY d' k is multi platter as shown in veioCltY across a track IS required as against the as a constant packing density hence constant linear
if OLCO&A (Sem. 111 i comP• I MU) winchester is the . 5 4 .6(a) shows that the CD is made
constant angula 1 . .
r ve oc,ty ,n case of magnetic discs.
o rtve Physic.el and Logical orgari1zatfon Fi 9· 5.4J(b). head for each side . Fig, · . material
protective . like
. acrylic.
. up of three layers' namely the polycarbonate plastic, aluminium and the
of the mulr 1
this case one ip e
- In unted to form a head stack assembl
I rters are mo y, rhe Iaser beam. . incident on the highly refl ective
. substance l'k 1 I •. .
Pa Winchester hard disk because it w sased on this time gap, the optical disk read . e a um,nium, returns back in some amount of t,me.
H.. d 1 er can realize that ther
• called as as .
He4d 2 - It is d b IBM in Winchester (USA). case ifit is a land it will take more time to t
deveiope Yunit with Protective re urn while less t·ime ·ine case
was a land or a pit
.. - a pit as seen in the Fig . 5.4.6(a).
1f ,t Is
the platters and the heads fl In
It is a sea led . . y acrylic
- d r/ layer of air as dis k spins.
on boun a
. ver/ small head to d isk gap making 't
AISO, there IS • • I
- b t Winchester hard disk 1s cheap and the
more ro us .
fastest external storage.
There is gap be~een the two sectors as well as p~
_sector ,,., tracks as shown in Fig . 5.4.3(a). Aluminium
be~een ,,. 0 Polycarbonate
(b) Data organization on multiple platters The disk moves at constant angular velocity and plastic

•.' l'' ~ '

Fig, 5.4.3 hence the data is read at the same speed, may ·be-the
th
Thus when reading from one track of a platter, e innermost track or the outermost track.
nd th 0th Laser transmit/
head mechanism may not be moved a e er Each data stored on the disk is stored in a s_pecial receive
head will s:tart reading from the same track of manner with seme -lD· infor-matioA as shewn in· the Fig. 5.4.6(a) : Construction of CD
The data format on a CD-ROM is shown in the Fig. 5.4.6(b). Initially a data OOH is stored, followed by 10 bytes of
another platter. Fig, 5.4.4.
FFH and again a OOH, called as the synchronous 12 bytes.
The next is the 4 bytes ID (!Dentity) about the time required for this data to be played (in MINutes and seconds),

the sector in which the data is placed and the mode. There are three modes :

1. Mode 0 indicates blank data field

Mode 1 indicates 2048 byte data + error correction
2.
Mode 2 indicates 2336 byte data and no correction data
Fig. 5.4.4 : Data storage format In magnetic memory 3.
Thus the remaining two fields contain data and error correction code (ECC) as defined by the mode bits.

5..4.3 Optical Memory :

The memory devices like Compact Disc (CD) and Digital Versatile Disc or Digital Video Disc (DVD) use the optical '". i~;&i: q•~'\j~~,~j;~·~~
method to read the data written on them. :;.;;y 288 bytes
The following sub-sections discuss about the CD and the DVD data storage and reading. 2048 bytes
· L-ECC
4 bytes · - Data
12 bytes . ID .
Devices for Opllcal Memory
SYNC

A. CD-ROM · 2352 bytes

B. DVD
Fig. _ _6(b) : Data format on CD
54
Fig. 5.4.5 : Devices for optical memory

A. CO-ROM : B. DVD·• . · DVD has multiple layers and hence very high capacity.

CD-ROM was originally built for aud'io and was of the ca acity f The maJor
. difference
. .
between a CD and DVD is that a . h t the DVD has more denser data storage mechanism
. O . . · .
The construction of the CD wa h p GSOMbytes giving over 70 minutes audio. A . h espect to CD IS t a
aluminium. s sue that it used po Iycarbonate coating with highly reflective coat. usuallY nother major difference in a DVD wit r d 4 ]G per'layer of a DVD.
Which results in the data storage capacity of aro,tui~n~~- ~~~::.,.::::.:~.:..:..:.......-------;._;..;,r:Hll;;;;Kn::o:w:;-,..
• Puo1tc,1t1ons :;:,::i
 Memory Organization , co&A (Sem. Ill / Comp. / MU)
1) DLCO&A (Sem. Ill / Comp. I MU)
5-18 -.._ if_ DL. -=....,..__ 5-19
~ d :idually by tasks fragmentation 9
· le layer as weII as multiple layers. in I enerally
_ .
There are DVDs available wit. h sing DVD ens when memory blocks have been -
Memory Organization
. haPP a11 ocated Partition numb .
Fig. 5.4.7 shows the constructional d1'ff erences of a CD and an d
are freed randomly. er
2 o1 size 500 K is assigned to Pl
Label~ 212
(size = K). It is the first partition that ·can
This results in splitting of partition memory into small accommodate Pl.
Protective layer - non- continuous fragments.
(acrylic) - Partition number 5 of size 600 K is assigned to
There are 3 memory allocation policies :
Reflective layer P2 (size = 417 KJ. It is the first empty partition that
(aluminum) _ eest fit : can accommodate P2.
1
Polycart>onate substrate
(plastic) In this case the smallest available fragment is P3 is assigned to p~rtition 3.
searched and the required data is stored in that - P4 cannot be executed.
fragment.
Processes Size :' Memory utilization = Memory utilized
Total memory
I' Pl ,. 2t2K The smallest fragment searched for should be
P2 417K Memory utilized by Pl, P2 and P3
greater than of equal to the size of data to be stored.
P3 112K Total memory
' P4 .4~6K ; 2_ Worst fit : 212 K + 417 K + ill K
1700 K
In this case the largest available block is used to
741
store the data. 1700 = 0.436
3. Next fit :
ii) Best-fit:
t In this case immediate next empty block of a size
Partition No. Addresses
(a) CD-ROM - capacity 682 MB equal to or greater than the size of data, to be stored
Polycarbonate substrate, side 2
is searched sequentially and the required data is
Semlreflective layer, side 2
stored there.
Polycarbonate layer, side 2
Ex. 5.5.1 : Given the memory partitions oI size 100 K,
Fully reflective layer, side 2
500 K, 200 K, 300 K and 600 K (in order}. How
Fully reflective layer, side 1
would each of the first fit, best-fit, worst fit
Polycarbonate layer, side 1 algorithms place the processE!S of 212 K,
417 K, 112 K and 426 K (in order} ? Which (S9.5)Fig. P, 5.5.l(a)
Semlreflective layer, side 1
Laser focuses on pits in one layer
on one side at a time. Disk must algorithm makes the most efficient use of - Partition no. 4 of size 300 K is allocated to Pl (212 K).
Polycarbonate substrate, side 1
be flipped to read other side. memory? It is the smallest free partition that can accommodate
(b) DVD-ROM, double-sided, dual-layer - capacity 17 GB Soln.: Pl.
Fig. 5.4.7: Construction of (a) CD and (b) DVD q First-flt :
Partition no. 2 of size 500 K is allocated to P2 of size

As seen in Fig. S.4.7(b), the double sided, two layers

DVD, has a reflective and semi-reflective layers on intensity beam is reflected by the highly reflective
t:,5,: \~;~/
P2 .• 417K \
417 K. It is the smallest free partition that can
accommodate P2.
both the sides. substance. Similarly, partition no.3 is allocated to P3 and the
P3 ·-:" -112K :.
Hence in this case, the laser beam and receiver have
to be on both the sides of the disc.
Thus giving a mechanism to read the data written on
th th
>P.~, .ic, ~'.:f?.~_1(\' partition no. s is allocated to P4.
Memory utilized by Pl, P2, P3 and P4
bo e layers of each of the side.
Memory utilization = Total memory
Also there have to be two types of beam with low 5.5
and high intensity, the low intensity beam is reflected
Allocation Policies : 212 K + 417 K + 112 K + 426 K
1700K
· by the semi-reflective substance, while the high Partitioning ref . .. . or/
. ers to logical d1v1s1on of the mem 1167 K = 0.686
into subparts so that they can be accessed
t
Partition No.
Addresses 1700K

(59.S)Fig. P. 5.5.l
,e Ttd1Kno11l'4?~
V Pu£Jllcat1D
 • DLCO&A (Sem . Ill/ Comp. / MU) 5-20
-
Worst-Flt: 5.6.1 Cache Operation : if pLCO&A (Sem . III /Comp. I MU)
The cache controller uses the add . 5-21
i processor to determ ine if a co
~b Y the
~--r-=,.,:.j100K
2
. . PY of the re Memory Organization
information 1s already in the c h quested p~ncil>les of l..oca11ty
1---.----1 600 K . ac e memo Reference
3 cache miss occurs as the cache m . ry. But a
~'--,-,=~600K emory Is empty_
4 The cache controller initiates a m
3, emory react I
1 - -.....---1 1' 100 K fetch the requested informar eye e to
5 ron from DRAM
..__ _ ___, 1700 K memory. This will consume some w • Fig. 5,6,2 · Tw - - -
art states. 1 . o COmpo,..,nts of loality of referonco
1s1.s1Flg. P. 5.5.l(b) 4. The information from DRAM mem . · Temporal loca11ty :
. ory 1s sent to the (a)
The largest free partition no.5 of size 600 K is processor. It as also copied into the h
allocated to Pl (212 K). cac e memory Since the programs have loops, the same
Fig. 5.6.1
and the cache controller updates its ct· instructions are required frequently, i.e. the
P2 (size 417 K) is assigned to partition no.2. Partition 1. •rectory to
Implementation of cache memory subsystem is an reflect the presence of the new info . programs tend to use the most recently used
no. 2 is the largest free partition and it can rmatron. The information again and again.
attempt to ach ieve almost all accesses with zero Wait information being sent is not J·ust th .
accommodate P2. e required
state while accessing memory, but with an (b) If for a long time a information in cache is not
instruction, but a block (line) of data is sent to the
P3 (size 112 K) is assigned to partition no.4. Partition acceptable system cost. used, then it is less likely to be used again.
cache. No performance gain is achieved due to
no. 4 is the largest free partition. 2. (c) This is known as the principle of temporal
The cache controller maintains a directory to keep a absence of information in cache memory. locality.
P4 cannot be executed as there is no free partition track of the information and it has copied into the
that can accommodate P4. cache memory. s. After executing the first instruction, the processor's 2. Spatial locality :

M T . Memory utilized by Pl, P2, P3 3. prefetched requests a series of memory read bus (a) Programs and the data accessed by the
emery ut1 1zat1on = Total memory When the processor initiates a memory read bus
cycles to fetch the remaining instructions in program processor mostly reside in consecutive
cycle, the cache controller checks the directory to
212 K + 417 K + 112 K loop. But since an entire line was brought earlier, memory locations.
determine if it has a copy of the requested
1700 K
information in cache memory. most of the required instructions will be in cache and (b) This means that processor is likely to need
741
1700 = 0.436 4. hence resulting in faster access and performance code or data that are close to locations already
If the copy is present, the cache controller reads the
information from the cache, sends it to the gain. If the cache is sufficiently large, all instructions accessed.
5.6 Cache Memory : Concept, in the program loop can become resident in cache
processors data bus, and asserts the processor's (c) This is known as the Principle of Spatial
Architecture (L 1, L2, L3) and Cache memory.
ready signal. This is called as READ HIT. locality.
Consistency :
5. If the cache controller determines that it does not 3. The performance gains are realized by the use of
6. The program has loop instruction to jump to the
have a copy of the requested information in its cache memory subsystem are because of most of the
Un1vers1ty Questions beginning of the loop start over again. The processor
cache, the information is now read from main memory accesses that require zero wait states due to
\0...1' -',• WhaL°a~e ·e lements ."of . cache then requires the same program again.
principles of locality.
memory (DRAM). This is known as READ MISS and
7· When the processor requests f or the first instruction
causes wait states due to slow access time of DRAM. S.6.3 Cache Perfonmance :
.rn the loop, cache controller ·detects the presence of
6. 1. Performance of cache subsystems depends on
The requested information is from the DRAM given
the instruction in the cache memo ry and hence the frequency of cache hits, usually termed as
to the processor. The information is also copied into
. h zerO wait states.
provides it to the processor wrt hit rate.
the cache memory by cache controller and it updates Cache Hits
% HIT RATE
x
100 %
its directory to track the information stored in cache S.6.2 Principles of Locality of Reference : Total Memory Accesses
memory.
. term used to
h 2. If a program req uires a small area. of memory
h
l. locality of reference rs t e n . t s of loops1 then maximum cac e
Assume the cache memory is in the and cons1s
empty, . . Of rograms that ru
explain the characterrS t lCS P ry hits are possible.
beginning (after reset) .
Before going to the cache of Pentium processor, we . consecutive memo 'f the program has non-
in relatively small loops rn 3. the other han d' ' .
will see some basics of the cache like its operation, The following sequence takes place : On . n accesses will result in
looping code, ma y
advantage, principles ·o f locality of reference, cache 1. Th rvcle to locations. ·ses of
e processor performs a memory read ~, • ciple compn cache misses.
architectures, write policies etc. 2. The locality of reference prrn
fetch the first instruction from memory.

TedlKnOII I,•,
p u ti II c at
,.... two com onents :

•
 - ,,, (Sern. Ill I Comp. I MU) 5-23 Memory Organization
Memory Organizauon hen the processor initiates a bus access
Causes of cac he consistency problems :
( cache controller as well as main memory'
5.22 . dvantage is t hat two bus ma t detects the bus access address. 1. ,,y of 1,ne
When the CO"' · . cache. no longer matches
1n
r1,e maJor a s ers
te simultaneously. One proces
if DLC0&A (Sem. 111 /comp. / MU)
s run in loops and
(d)
can opera .
k through cache while another b
Sor
(C)
fhe cache controller sits aside and monitors the content s of r1ne stored .1n memory, there is loss of
accesses Ioo us each processor memory request to determine cache consistency. It can be either due to cache line
Fortunately. most program f cac I,e hit h as oMA can access the system b
4. master sue us if the cache contains the copy of the re quested being updated while the memory line i s not, or t he
hence a high percentage o
is possible. information. memory line being updated while the cache line is
(BS _ 95%) is experienced. ion devices, a look-t hrough cache
various other If it is a cache hit, the cache controller
To expanS not
Besides locality of reference . (e) controller is like a system pro cessor. (d)
5. to cache hit rates like terminatesthe bus cycle by instructing
factors contribute memory . mernor}' writes, look-through cache 2. In each of these instances the stale data mu st be
memory subsystem to ignore the request. If it
Cache's architecture, Size of cache ounng updated. It can be a result of cache write hit and
(0 .d s zero wait state operation (using is a cache miss, the bus cycle completes in
and Cache memory organization. prOVI e . .
posted writes) for write m isses. normal fashion from memory (and wait states hence the caches write policy has to handle this

5.6.4 Cache Architectures : are required). problem for the first case.
t
Two basic architectures are found in today's syS ems: Advantages : 3. For the second case the coherency problem is due to
It reduces the system and memory bus Advantages :
Look-th rough cache design (a) (a) Cache miss cycles complete faster in Look some other bus master changing the data in
1. utilization, leaving them available for use by
Aside Cache as the bus cycle is already in memory. This change is to be updated in cache line
2. Look-aside cache design. other bus mast er. progress to memory and hence no look up by the cache controller, hence t he cache cont rol ler
Cache Archltactures It allows bus concurrency, where both the penalty is incurred.
(b) has to monitor the system bus.
processor and another bus master can perform Simplicity of designs because only one address
1. Look-through cache designs (b)
bus cycles at the same time. is to be monitored by cache controller form 5.6.6 Write Policy :
2. Look-aside cache designs processor and not from 1/0 devices.
(c) It also completes write operations in zero wait 1. When the write hit occurs, the cache memory is
Lower cost of implementation due to their
(C) updated and it contains the latest data wh ile
Fig. 5.6.3 : Two basic cache architectures states using posted writes.
simplicity.
1. Look-through cache designs :
memory contains stale data.
Disadvantages : Disadvantages :
(a) The processor requ ires system bus utilization 2. Such a cache line is called as dirty or 'modified'
(a) In the event that the memory request is a
for its every access, to access both cache because it has no longer mirrors of its corresponding
cache miss, the lookup process delays the
request to memory. This delay is called as subsystem and memory. line in memory.
3. In order to correct this cache consistency problem,
lookup penalty.
(b) Concurrent operations are not possible as all the corresponding memory line must be updated to
(b) It is more complex, costly and difficult to reflect the change made in the cache; else another
masters reside on the same bus.
design and implement. bus master may get stale data if it reads from these
S.6.5 Cache Consistency (Also Known as
2. Look-aside cache designs : Cache Coherency) : lines.
Fig. 5.6.4 Three write policies are used to prevent this type of
4.
consistency problem: Write-through, Buffered or
The performance of systems incorporating
(a)

Look Through Cache is typically higher than

that of systems incorporating Look Aside
r•:~;,i,,
Un1vers1ty Questions

"/. ,,fi;i{:
ti:il';;:11,i;
a, 5;7p~¢;[1l'ii'~iir!(1};
posted write-through and Write-back.

Write Polley
Cache.

(b) Data from ma1 ·n memory (DRAM) is not 1. In orde r t o work properly for the cache subsystems, A. Write-through cache design
transferred to the processo r using. system bus th e CPU and the other bus masters must be getting
B. Buffered or posted
write-through designs
hence
. system bus is free for oth er bus masters themot .
s updated copy of the requested information.
(li ke
. DMAC) to access them •
ain memory. 2· There d . C. Write-back cache designs
are several cases wherein the data store in
This system isolates the processor's lo
(c) Fig. 5.6.5
Ib
from the system bu h ca us (a) • ma in memory may be altered whereas
cache or in
s ence achieving bus In this case th e processor is directly connect•d Fig. 5.6.6 : Write policy
en__cy::.:._._ _ __ __
_____c_o_n_cu_r_r_ the du PI'icate copy remains unchanged.
to the syste m b us or memory bus. .THIIK110111l•d1i
• PuDllcat1ons

u~ Ted1Kno11Jl•dti
p 11 r,11c a ti on s
 if. oLco&A (Sem . Ill/ Comp. / MU)
Memory Orga .
0
"""-.::·• eus Master/Cache lnteracr10
t1 n
..,,, DLCO&A (Sem . Ill / Comp. I MU)
~•~••t~~~~ :!!~.!J:.~ ~ ~; ! / . . - - -- - -~5-~2!4- ~ -
The write -through
::::~n1ia
- : : ~ - : : : : ; ~ : : :operations use . -_ 5.6.7 cache Coherency : n for
1. b us. Hence When e1the . r
A. W rite-Through Cache Designs : system or memory Reads fron, Memory Organization
h · · Write When another device in syst rT>eniory (With '
In th is w ri te pol icy, the data is passed to t e through to memory is in progress, bus · 1.
1. • master en, uses the bu 1. When th Wlile-back cache) :
are prevented from accessing memory. s it must become bus master ses, e bus master reao f
m emory immed iately, so t hat t he memory has system tha s rom memory in a
But actual cache consistency problem t~ a Write-bac•
the updated data. occurs 2. In case of look-through c h from a 1• " cache, it may read
2. ac e design ,ne C!lntai .
2. Even on wri te hit operation, the cache only when the bus master reads f ' th e lnr- , n,ng ~ le data i.e. the
. ran, a cache controller is requested f ~uon has been u a .
location in memory that 1s stale. The freq or bus· Whil ·1 pd ted •n <:ache but not in
controller updates the line in the cache and . uency case of look-aside cache de . ' e n memory.
the correspond ing line in memory, and hence of this type of occurrence IS very less. In fact sign, the processo
is requested for same. In both ' 2. To detect th.
ensuring t hat consistency is maintained the memory line is likely to be updated cases HOLD ch ts coherer-cy probl!,m, write-back
many and
HLPA 1.ogic ls .u.sed . ca es must also snoop reads from memory.
between cache and memory. t imes by the processor before another b
Us
3. Very simple and effective implementation. master reads from that particular line. 3. Jn .s.o me cas.es, .the requ t · 3. The system can be designed to bade-off the
es is to b.e given to
bus arbiter li ke 8289. bus master and y,.;.e the cache line to
4. But poor performance due to slow main 3. As a result the write-through and buffered ....
write-through designs, update memory each memory, before rel.easing back off and
memory w ri tes operation. Since bus masters can write to and
. read from allowing the read continue.
5. Also it doesn 't allow bus concurrency. time a memory write is performed, although memory, cache consistency problems
may happen C. W-"'-t
the need for such action may not be required '"" o main memory (With write-bacl< cache) :
B. Buffered or Posted Write-Through Designs : under three circumstances.
1.
immediately. Candltlons for Consistence This problem occurs when another bus master
1. It has an advantage of providing zero wait
Occurrence of Problem is performing a memory write to a line
state write operation for cache hits as well as c. Write-Back Cache Designs :
containing stale data. The bus master updates
cache misses. 1. Write-back designs improve the overall system A. Writes to memory
one or more locations in memory that are also
When a write occurs, buffered write through (with write-through cache)
2. performance by updating a line in main contained within the cache.
caches tricks the processor into thinking that memory only when necessary, thereby keeping B. Reads from memory
(with write-back cache) 2. Even if the cache line is not capable of data
the i nformation was written to memory in zero thesystem bus free for use by other
C. Write to main memory snarfing, it could invalidate that cache line.
wait states. In fact. the write to main memory processors and bus masters and hence
(with write-back cache) causing a mistake.
has not been performed yet ensuring bus concurrency.
Rg. 5.6.7: Conditions for consistence occurrence of problem 3. Since the line has been maliced 'modified', it
3. The look-through cache controller stores the 2. The memory is updated only when :
indicates that some or all of the information in
entir e write operation in a buffer, and writes to A. Writes to memory (with write-through cache) :
(a) Another bus master initiates a read operation the line is more current than the
the main memory later. Hence the processor
from a memory line that contains stale data. 1. When the bus masters write through memory, corresponding data in the memory.
need not perform slow write operation with
wait states and hence doesn't impact (b) Another bus master initiates a write operation they update locations that may also be cached 4. The memory write being performed by another
processor's performance. This is assuming that from a memory line that contains stale data. by the ,:ache ·controller. bus master will update some item within the
the posted write buffer is only one transaction (c) The cache line that contains modified memory line. By invalidating the li ne in cache it
2. In these cases, memory is updated and the line
deep. information is about to be overwritten in order would quite probably discard some data that is
in the cache becomes stale. Hence cache
4. But, if there are two back-to-back memory to store a line newly acquired from memory i.e. more current than that within the memory line.
controller must monitor the memory writes to
write bus cycles, the cache controller will insert during line replacement. If the cache permits the bus master to
avoid this coherency problems. When the write 5.
wait states into second bus cycle until the first 3. Cache controller marks the cache lines as complete the write, and then flushes the cache
write to memory has actually been completed. is detected, the cache line is invali dated
th line to memory, the data just written by the
'modified' in the cache directory when e
The bus controller will then post the second because it will contain stale data after th e write
processor updates them. Hence when read by bus master may be over-written by stale data
the cache
bus cycle and assert the processor's ready line. to memory completes. Hence
another master or written into the memory, in the cache line. The correct action would be
But since processor typically writes only one ·tis st
controller has to monitor the sy em bus to
the cache subsystem checks whether
1 to back-off the bus master, before it is able to
write operation, the memory writes are 0
find out what the other bus ma ster is doing ~ complete the write to memory.
completed in zero wait states. marked as 'modified' in cache. ·t ther master 1s
is the system bus. So that I ano ntroller then seizes the bus and
5. With this policy, another bus master is not 4. They design of such contra II er
cache . ory the cache The cac he Co
6. write to update this stale
th updating a line of the main mem ' .
permitted to use the bus until the write- COMPUCATED to implement because ey 01 performs a memory
rite has to invalidate this line. This monitoring . memory In the cache
through is completed, thereby ensuring that must MAKE DECISIONS on when to w line in the mam ·
ensure the system bus is called as snooping. i,TldllMal.....
the bus master will receive the latest 'modified' lines back to memory to
information from memo consistency.
 1 ._,,. -
. , , DLco&A (Sem . Ill / Comp. I MU)
Memory Organ·1 I/'_
Types of Replacement p alleles
~-~~~~~~.!!!:~~;J.~L.-
~ · DLCO&A (Sem. Ill / Comp. I MU) Cache controllers ::::=::~~~~:
----,.,;5~-2~6--;:~~=:--- handle this . ~zati0n
(c) situation Memory Organization
directory, the cache line is now invalidated differently depe nd ing on how they are repla ced first Th . .
th the 1 •• us tne line which has stayed
because the bus master will update e designed. ongest 1n th h
2. ~ir~t i~ First Out (FIFO) e cac e is replaced.
3.
memoiy cache line immediately after th e line is Invalidate the line in cache that Least frequenu . .
ff 1. . Would 3. Least frequently used wh· h . Y USed · In this case the line
flushed. The cache then removes back-o therv.iise contain stale data. The ne-.. . ic 1s used f h
o . . . " tune re or t e least number of times is
that this particular line 1s requested b 4. Random
I
Paced first.
signal, permitting the bus master to reinitiate
. . Y the
the memoiy write operation. When the bus processor, it will result in cache miss, forcing 4. Random : In th'
is case randomly any line is
Fig. 5.6.9 : Types of replacement polices -._'.'.:Placed.
master completes the write to memo!)', the cache subsystem to read from memory.
1. Least Recently used (LRU) . 1 h' Ex. 5.6.1 : - : - - - - - - - - - - - -
memoiy line will contain the most updated
2. Sn arf the data : The cache controller sn oops . . . n t is case the Assume that memory consists of three frames
line which 1s least recently used .
data. the bus during another bus master's Write . . is replaced nd
a during execution of a program. following
with the new line. Thus the line wh· h
operation and if a snoop hit is detected, it Will ic has not pages are referenced in the sequence :
5.6.8 Bus Snooping/Snarfing :
been used for longest time is repla d .
captur,e (snarf) the data from the system bus .
new line.
ce with the 23215245325
1. Bus snooping is the method used by cache while it's being written to memory by the bus
controller to monitor memoiy accesses Show th at behaviour of the page replacement
master. In this way, both the memory and 2. .
First in first out (FIFO) : In this ca set he line
using FIFO strategy.
performed by other bus master.
cache lines will have the updated data. which was brou ht into the cache fi1rst .1s
2. The cache controller monitors, or snoops the
soln. :
system bus when another bus master is 2. Memory read by another bus master :
performing an access to memoiy so as to (a) Only i'f the cache subsystems use write-back
maintain cache consistency. policy, they must snoop the system bus during

3. A line that is accessed from
also resident in the cache, it is referred to as
snoop hit In such cases either cache or
memoiy line may contain stale data
There are two possibilities that may
to snoop the bus.
Possibilities that Create
S~Bus
memoiy and is memoiy reads initiated by other bus master.
(b) The ca,che controller snoops memory reads by
another bus master to determine if the line
being read from his being updated in cache,
create the need but memory has a stale data (i.e. the cached
location is marked as 'modified').
Page fault
(c) If yes, this would result in snoop read hit to a
'modified' line. Hence the cache controller (co 5.48) Fig, P. 5.6.1 : Behaviour of page replacement uoing FIFO

1. Memoiy writes by another bus master ;

must force the bus master attempting the Ex. 5,6.2: Find out page fault for following string using LRU and FIFO method. 6 0 12 0 30 4 2 30 32 1 20 15
memory read to suspend the bus cycle until it (Consider page frame size = 3)
i) Invalidate the line has updated memory. Soln. :
(d) Once the memory line has been updated by - Page address stream
•) Snarf the data

FIO§~
the cache controller, the bus master is allowed
: 2. Memory read by -.:olher!s maste] to complete its memory read operation.
(e) Alternatively the cache controller may find a
Fig. 5.6.8 : Possibilities that create snoop bus
snoop hit and instruct the system memo,Y not
1. Memory writes by another bus master : to supply the data and instead it will supply

~"§
the th e data from the cache.
(a) Assume that the cache controller has given
5·6·9 ReplaciJment Algorithms :
control of the system bus to the OMA

controller so that it may transfer a block of - Replacement algorithm is required to replace a line
data from a disk controller into memoiy. from the cache memory with the new line as
discussed earlier.
(b) the OMA controller will alter
It is possible that
There are · ·1 ble The
the contents of memoiy lines that have already Vanous replacement polices ava1 a ·
been copied into the cache. widely used ones are LRU FIFO LFU and random as - Page faults are indicated by 'F'.
- - - - - - - - - - - - - - - - - ~ - - d ~ i s c u s s e d below : ' '
--
~
•~ TedlKJ..ldf.
pu b llotlO
 ◄ t ~~~n
,..------------.,;5~-2~9- =~-- ----.! :=l.2
o&A (Sem . If!/ Comp . I MU)

Memory Organization
if_ ot..C.
. Y-:-•
Memory Organizatio

virtual memo!' .
so~-.
1
~flLI : etc. y, internal and external cache memory
5-28 The page address stream formed b
Y 1 7 3 8 5 4
ee frames. 3 4 ~7 - Let .us see the vanous
1MU)
a capacity of thr . usillQ FIFO, LRU and OPT. 4 J_}-4 0
_,,,,.- 0 0
0 3 3 3 4 5
4 • parameters to be consid ered
• DLCO&A (Sem. 111 I ComP- 4 4 4
. in which M1 has ·nd the page hit d
4 ,-- 7 1 1 1 8 8 ,-.. uring the rf

Ex. 5.
v4
L---
7
..'..7--f-:---J-::-i-:;----r--~~T:-Cr-8+
1...--- 1- - -
L....--
3 3 3 7 7 7 5
M M M
5 5 5 -
3J 3
8~...::3~.:
7
I pe ormance analysis.
Parame1en Considered
for Performance Analysis
I
Sol ";MMM MMMHMHH ...j 1. A·,e,-ag;, cost (C i
1
Time 2
Addnt•• apace
2
2
% H it = 14 X lQQ : 14.3 % r-+12.Hij ratio (H)
FIFO <-- 12
= =85.7 % ...j 3. Averag;, ;access-~ ( l;:.)
<-- % Miss 14 x 100
4j 4 . Efficiency (rJ

~~
, FIFO :
2
0 7 3 8 5 4 5 3 4 7 Fig. 5.6.10 : Param~ers considen,d for ~ analysis
4 7 3

ffi ~;
0 0 3 3 3 4 4 4 4 4
4 0

'""B ITT ITT§~~ ffi

4 4 1. Average cost (C) = c, S1 + C. S2
8 8 8 8 3 3 3 S1 + S,
- 7 7 7
3 7 7 7 555557
3 3 where, C1 and C2 are the costs per bit of memory 1
H H
(faster memory) and memory 2 (slower m emory)
2

"8 ITT§ ITT~~ mffi ITT~~~

% Hit = 14 x 100 = 14.3 % respectively.

12 S1 and S2 are the sizes of memory 1 and memory 2

% Miss = x 100 = 85.7 %
0
4 respectively.
Hit Hit OPT :
Hit Hit 3. 2. Hit Ratio (H) = N1 N, N
Hit + l
Hit
1 7 3 8 5 4 5 3 4 7
4 7 3 0
1 1 5 5 5 5 5 5 where N 1 is number of hits and N 2 is number o
4 4 4 0 1 1
7 7 7 8 8 4 4 4 4 4 misses.
Ex.'5-6.4 :. , Find oui page tauti for following string us_ing ·
3 2 7 7 7
0 0
·. ·LRU method. Consider page tram~ ~ize = 3 3 3 3 3 3 3 3 1
3 3 3 3. Average access time ( tA ) = H t_.1 + (1 - H) tA2
0 3 2
.7012°030 42303212 0,17,0i ., , 3
H H H H H
-M i#lll&fflfi 2 0 3 2 where tAl and t "2 are the ti me taken to access
5
Soln. : 2 F % Hit = 14 X 100 = 35.7 % memory 1 (faster memory) and memory 2 (slower
3
P~ges-access'ed , Frames memory) respectively.
2 3 2 9
%Miss = X 100 = 64.3 %
7 7 - - F 14 tA = H t Al + (1 - H) t "2
0 0 2
0 7 0 - 2
5·6-10 Cost and Performa nce Measurement = H t,u + (1 - HJ (tAl + t s)
0
1 7 0 1 of Two Level Memory· Hierarchy :
7 0 7 F tA2 = t,u + t s = t_.,_ + (1 - H) t 5
1
1 1 ■ •-
0 1 F where
2 2

0 2 0 1
0 0

0
7
7
1mm1§J6 ~
r--

-.
Q 'f .
ir
.. ·.f'JW¥Jn•nt--
~. . ~".: •,; ,,..,.
,·: ~-, ., .-
. . •· "'•>'· <
. -'·. .• .•
·".:...,
. .:~._.:
4,
Efficiency (11) = t
3 2 0 3 F
·· E~plair't L~ '.pag~.repl~ce~ent pcilic.y .with suiia~\~.. t,.,
0 2 0 3 ;pit, :\-~~: exa/r,p(e:i._ ,/: .; ,.: ; .,;-<•;:" (Dec..1~; 10 Maik~i• = H tA l + (1 - H) tA2
4 4 0 3 F Any two level memory has to be analysed with its 1
-
I · t = H + (1-H) r
2 4 0 2 F ( Perform ancecharacteris tics as per the fol owing se
~ t .
•
of charactenstics.
3 4 3 2 F
- where r
= .E =speed Ratio
·····,:,if:t:'.;:i~ftllvi ... The d"ff
cache
I erent group. of twos level memories can be
. nd
tAl
iJ Ted1Kno111ledgii
~ Pu.bllc.at,oo s
memory and main memory, main memory a
 Memo ry Organization
,,-
~.
w,_ DL
co&A (Sem . Ill /Com p.I MU)
each
5-31
Memory Organization
this case to search a line from the th e line field
e memory,
with the ta of the address specified by th selects the particular line, whose tag is to be
In g
.. bits specif y one memo ry block t comp ared
. e processor
o ·
ost significant s The advan tages of direct mapp ing
are :
V DLCO&A (Sem. Ill I Comp. I MU) - M
hich the cac
he line corres ponds .
Simpl e imple menta tion 2. lnex ~n .
5.7 Cache Mapping Techniques : - w rt into a cache line field r and a tag 1.
ing are :
ent algorithm disad vanta ge of direct mapp
The MSBs are sp I The
and replacem . -
Mapping function ost significant) if a progra accesses 2 blocks that
. f the main memory . Fixed locati on for. given block hence
rom ~0 (m divided
m map to the same line repeatedly, cache
togeth er decides where a line . Let cache be of 64kBy te that 1s _
misses are very high.
example . . ,.
can reside in the cache. f bytes hence cache 1s 16k (2 ) lines of
· Direct mapping,
into blocks o
4 fully Associative Mapping :
The differe nt mapping functions are
. . 5,1, 2
Set associative load into any 1•Ine of cache.
. mapping and 4 bytes.
that this case a main memo ry block can
Fully Associative main memo ry size be 16MB ytes In
s as tag and word.
mapping. And let t h e There are only two fields in the addres
. 24 bit address lines (22•=1 6M). . .
memory from where th e 1.ine h as been copied into the cache memo ry.
5.7.1 Direct Mapping Technique: requires The tag uniqu ely identi fies block of
_
·it<·) Line (r) (14 bits) Word (w) (2
bits)
• searching gets expensive
b
Tag (s - r) (8 ·' T search a partic ular. data the tag of every line ·IS t o b e examined for a match. Thus cache
ry can map to _ o .
Jn this case each block of main memo word
4 bit address is divide d as 2 bit in terms of time requir ed .
Hence t he 2 s
only one cache line. fier i.e. cache is 16k (2'') lines of 4 bytes.
'fi (4 tiyte block) 22 bit block identi is divided into blocks of 4 bytes hence
Jl, where i is ' Example : Let cache be of 64k byte that
A given block maps to any llne (I mod identI Ier
(:22' = 16M).
bit tag 14 bit slot or line (16K lines ':
2'•) bytes that requires 24 bit address lines
of the main memo ry to be mapped And let the main memo ry size be 16M
the line numb er 22 bit tag stored with each 4-wor d block
th e cache Fig. _7_1 shows the organ izatio n of
Direct Mappi ng Structure for this example considered :
and j is the total numbe r of lines in
5 The assoc iative Mapp ing Address

memo ry. Cache . of data.

s the data from in cache to check for least significant
2 bits of address identi fy which word is
The address is divide d into three parts
i.e. the word Fig. 5.7.1 shows the metho d the acces comp are tag field with tag entry
mapp ing techn ique
selector, line selector and the tag. the cache implem enting direct requir ed from 4-wor d data block.

Least signifi cant w bits identify unique

word of a I Tag (22 bits) IWord (2 bits) I
Cache mapping is shown in the Fig. 5.7.2.
particu lar line The organ izatio n of Fully Associative
s+w

~ t. ,
Tag :. Line Word
Cache

Tag Data }
Main memory

. } Bo
Memory address
.,. · ... Tag· ; Word
Cache
Main memor y

.
~
}
Ba

w
Lo
'
3
'
s .' .'
'
s- r
''
~

''
''
'
''
''
'
'' w .''' ''
'
''
'' '' '
' ' ''' ''
s-r ''' ''' ' ''
' '
' '' ' '
''' '''
'' '' w
' ''
'
''
'
w
'

'''
i! :• '' '
I
' (hit In cache)
,_ ___ _ _ _ _ _t '
'
i}
'
i •

Lm .. 1

- ---- --.: :::' .·=::____J

;j~
; ; o11Jled
(miss in cache)
(miss in cache) Flg.S,,7, . .2 ~ - - - - - - - - - ; ~
_
;; vVi ;Ted1Kn 9i
PuDll c.ltlo n ~

Fig, 5.7.1

V
V
Ted1Kno1111•t~
puD1 l car 1011
 " - Dl.co&A (Sem . III I Comp. I MU) 5-33 Memory Organization
Memory Organlzauon
Fi;
,;;,,---- s.7.3 shows an example of TWO Way Set 256 blocks = r,
Associative Cache Organ ization. - )~;-
lrr-.,.-c,-blta - -(2.
WMd ~ )]
- ·Btta

V DLCO&A (Sem. 111 / Comp I MU) . ·11 are : . .

in case of Direct •
mapping) repeatedly The advantages of Set Associative Mapping are :
Fig. P. 5.7.2 : Address format for HSOClatfw mapping
The advantages of Associative MaPP' g to th e same 1ine ' _ If a program accesses 2 blocks that map to the
1
blocks (that would n,ap same set repeatedly, cache misses will not 5.8 Interleaved and Associative
If a program accesses 2 Memory:
1. occur because they would go into different
cache misses will not occur.
. - e Mapping are : Jines of the set.
1 5.8.1 Associative Memory :
The disadvantages of Associ a ,v arisons of tag .
2. No t very comp Iex because of just 2, 4 or 8 MU May 15 Dec 15
complex design for many parallel comp
1. . f arallel compa ra tor. parallel comparisons.
Expensive due to implementation o p Un1vcrsrty Qucsr1r1n~
2. _ Not much expensive again because of simple
1 3 Q. 1 W h a t - ~ memo,y-? ~ 1 5 , -4 Marius)
5 ·7 · 3 Set Associative Mapping : . number o f -in es · im plementation.
. r of sets Each set contains a Q. 2 Explain -- - aAOCi111W and ~ cache
In this case cache is divided into a
.
numbe
.
· . . the line number of the ma in memory to be
et (i mod j), where 1 1s -;,-;71 ~,_- >:A;~~k ~J ~;i ~Jl ; ~ ~he' cirYs1s1s:iM mapping.t~-
(Oec. 15, 1.0 Mail<s)

A given block maps to any line '" a given

.. I
5

b r of sets in the cache memory. . . e mapping i.e. a given block can be in one of
bi~cl<~ ' ~1~ dedd ri:' 4.,:~.~
set,s.,,TJie.' main In associative m emory any stared item can be
mapped and J ,s the tota num e memory .,,conJajri~,j096 , blocks '.;each .128 accessed by using the contents of the item.
. .
11
d as 2 way associa11v ~o~ds of i~ .bit ie~Ul~:: ';- , ,'. . .

~J~~~;=,~-- :'.~"
For example, if there are 2 lines per sel 11 is ca e The subfield chosen to address the memory is callerl

2 lines in only one set.

s .. w

Main memory
.f
• 2, . - How,,- m~riy.t.bitiif:are:, th~re,.itJ•,-cache
the key.
Items stored in an associative memory can be viewed
as having the two field fonnat :
;. memory ~ set'.~;1i~

~-8
\ (lag,

EE
d}~
-: :_:~:.ti~Jdi>. 1 -· -i ..• /.1: Wi#n ■ ~tmi; ·- KEY, DATA
Where KEY is the stored address and DATA is the
Sein. :
s-d

' '
Seto ! ! 1. Main memory size = 4096 blocks x 128 word = i1 x
2
information to be
Associative searching
accessed
is based on s;multar,eou.s
27 = 219

~----1-----<'--"-•-d,,.,," --__ ~ i·I '

Thus main memory address lines required is equal to

19.
matching of the key to be searched witn the stored
key associated with each lin e of data
A word is retrieved based on a portion c f its C!lrrtems
. . ~ 2. Cache memory has 64 blocks divided in 4 block sets,
thus each set has 16 blocks. Hence 16 = 2'; 4 address
rather t han its address.
Kev Da!a
Sel 1 j j lines for set Key
Each block has 128 words; hence 128 = 2', 7 address
I :
' lines for word field
l~ I - - - - - - - -• Remaining Jines i.e. 19 - 4 - 7 = 8 address lines for

--_-• _ __J
(miss in cache) _ _ _ _ _ _ _·_··_- -_-_
tag
r------ -_.,..-- --i
Tag (7 bits) Set (4 bits) Word (7 bits)
Fig. 5.7.3 (co s.H )Flg. S.8.1 : A key to be SHrched is matched
rd5 simultaneously

i~.
Example : Ex. 5.7.2; Consider .a--~che memory of 16 wo · Each
each of the 2 sets hence 13 bits to select a set MU May 16 May 19
Let cache be of 64kByte that is divided into blocks of , block consists of 4 . words. SiZe of the main 5.8.2 Interleaved Memory :
(213 =8K) and remaining (24 _ 13 _ 2 = 9) bits for tag.
4 bytes hence cache is 16k (2'•, lines of 4 bytes. n:iemory 256 Bi~ks- Draw associative
· . · ORD size:
And let the main memory size be lGMBytes that Tag (S bits) Set (13 bits) Word (2 bits) mapping and calculate TAG and W .
requires 24 bit address lines (2" = lGM).
. he
.• ,.•$id"*60
In this case th e set field is used to determine cac
. address Soln.:
For this example for set associative mapping .. ve
set to look i n an d compare t ag fi eld t o see if we ,.a
. . . TedlKHwled.p
structure : 2 bits for one of the 4 word s, BK lines in
a hit. 4word = 22
- --
....
. ~ D~
- ~'Y" L~ 'g
~ om
C~O~&~A~(~S~e;m=.~lt~I C~
4 Memory Or,1 an12atlon
~)~=====~5f·3~~-:-:-:: ~ ~ : : : : : :: : ::~-~
~U
~p-~1~M - ......... ~ ~ "oLCO&A (Sem . fff I Com . I Mu
-
r Q, 2 Expl1ln'Memory lnltr1Hvlng Technl(IUH. l , G, lO, 14 , 18 ... Add resses to memory modul o
2
Mi 18, 11 Marki 3, 7, 11, 15, 19 .. , Addresses to memory module 3
l-½ru,r Otr an!Ullon
Interleaved memory Implements the concept of Consider a main memory formed with m " 2'
accessing more words in single memory access cycle. memory modules, each contain ing w 2'' Words of

Memory can be partit ioned Into N sepa rate memory memory cells.

modules. The total memory capac1'ty Is m · w = 2• ' b Words.

Thus N accesses can be carried out to the memory Fig. S.8.2(a) shows memory format for memory
simultaneously. Interleaving.

Once presented with a memory address, each Interleaving spreads contiguous memory locations
memory module returns one word per cycle. across m modules horizontally.

It is possible to present different addresses to This implies that the low-order a bits of the memory
different memory modules so that parallel access to address are used to identify the memory module.
multiple words can be done simultaneously or in a
pipelined fashion. The high-order b bits are used to address a word

The maximum processor bandwidth in Interleaved inside a module.

memory can be equal to the number of modules i.e. Same word address is applied to all memory
N words per cycle. modules simultaneously.

A module address decoder is used to distribute (b) Eight-way low-order Interleaving (absolut add
To achieve the address interleaving consecutive • ross shown In uct, memory word)
addresses are distributed among the N interleaved module addresses. Fig. 5.8.2 : Interleaved memory

modules. Access of the m modules can be overlapped in a 5.9 Virtual Memory :

For example, if we have consecutive addresses and 4 pipelined fashion.
1
interleaved memory modules then O'h, 4th, 8th, ... I61 115Mif8•MEM%Mi•N,-ue ,g1=1
addresses will be assigned to the first memory For this purpose, the memory cycle is subdivided into Un1vers1ty Questions Da1a Bus

module and so on. m sub cycles.

0, 4, 8, 12, 16 ... Addresses to memory module 0 An eight-way interleaved memory is shown in

1, 5, 9, 13, 17 ... Addresses to memory module 1 Fig. 5.8.2{b).

Data Bos

Fig. 5.9.1.: Connection of extemal or vlrtuol memory

to the processor

V1 . the applications
.rtua1 memory is a concept w herein - . from
The data requ1.red by the application is brought
'" blocks
Memory Data the externaI Slow memory to main memory
· memory by the mechanism called as
Buffer are made to feel that a huge main (also called. as pages )
(f . . t rfaced to the
ast semiconductor memory) 1s in e . Paging. .
Processor, whereas actually a smal I a
mount of main now we can say that the entire memory
Hence th system looks something as
(a) Low-order m-way Interleaving (the C-acc (typically slow system interfaced to e
e55 memory scheme) memory and a huge external memory
Fig, 5.8.2(Contd ...) shown in Fig. 5.9.1.
ROM like magnetic d isk) is interfaced.
 ~
~
..•!•t•~~~:! 5-36
;,;~---- ----~~~ ~---M ,;: n~
..,o,.ry.;,_o;;rg~a~
.e..m · if_ oLco&A (Sem. Ill / Comp_ 1 MU)
,~ ~;..!!~~~ ~ ~:!L.-- -==---;
'Y' DLCO&A (Sem . Ill / Comp. / MU)

The CPU or the p rocesso r is co nnected to t he fa st If t he page requ ired by the p ro c essor is not in the
memory i.e . cache m emory o r SRAM which is then . memory the page fault (sim ilar to cache miss) .
main '
connect ed to t he m ain memo ry o r DRAM and then
Write Short Memory Organization
occu rs and t he requ ired page is loaded into the main notes on L1 L2
Q. 13 nd
to t h e virtua l m emory or the external m emory. Exp1 . · a l3 cache memory.
memo ry by a special routine called as page fault . ainvariO(Jg hig!,
5
inteneav~ '""'-~- Peed memories such as
The m emory managem ent un it (MMU) co nnected to ro utine. - .. .,,,.,. and cacnes
Q. 14 Oesc, .
the p rocesso r co nve rts t he vi rtual ad d ress to the
os ibe What are the f
This technique is called as Demand Paging i.e. the Q. 15 eatures of cache design ?
p hysical add r ess and ta ke care of bringing the pages }osr1 What are the features cf cache .
page is brought from the external memory to the Q. 1s Wh memory design ?·
(b lock o f data) to the ma in m em ory fro m t he extern al at are the P<in ."'-
ma in memory only w hen required , o..,,. of k>:ality of reference ?
memo ry. Q, 17
Calculate nufrber
5.9.1 Paging Mechanism or the Memory A Translationa l Look aside Buffer (TLB) is ss the p=a - of Page faults and page hits for
-.,. replacement P<>li • F
Manageme nt Unit : •fol ► Wh imp lemented in the memory management system, }ssr, LRU fo · oes IFO. Optimal and
r Qrven reference string, 7. o. 1. 2. o 3 a 4
230 3 2 ' .. ·
w hich reduces the memory access time, by '. , , , , 1, 2. 0, 1. 7, o, 1 (assuming three frame
Urnvers,ty Quc,s t,on s size).
tran sl ating t he li near to p hys ical address w ithout 18
Q. 1 Explain page address translation with respect to Fig. 5.9.4 Q. Write a short note on lock through and lock aside
undergoing the pag ing mechan ism.
Virtual memory and further explain. cache ari:hitectures.
R99)$
L:::~-~,r ---"""' logical address
The structu re of memory management w ith TLB is as 1
(Dec. 19, 10 Marks) Q. 9 EXplain in detail cache coherence.
show n in Fig . 5.9.3. Address translation
Hit mechanism 20
The memory management unit or the paging unit is Q. Explain in details Cache Coherency.

responsible to convert the v irtual or the linear Q. 21 Calculate the hit and miss using '<a.~ous page
address to physical address.
replacement poricies LRU. OPT. FIFO for fuilowing
Fig . 5.9.2 shows how the address translation takes sequence (page frame size 3) 4. 7, 3, a. 1, 7. 3. 8 , 5.
place. 4, 5, 3, 4, 7. State which one is best for above
example?
The address given by the processor i.e. the linear or ',. Page .:,
--, directory_:. Q. 22 What is cache cohell!ncy ?
virtua l add ress, is broken into the page number and Fig. 5.9.5

the word number in that page. Q. 23 Explain different write policies.

Virtual address Fig. 5.9.3 : Translation Look aside Buffer
Q. 24 List and explain different replacement policies.
As shown in the Fig. 5.9.3, TLB is placed parallel with Q, 1 Q. 25 Explain LRU page replacement po! cy with suitable
What are the characteristics of memory devices ?
the pag ing mechan ism and hence if the TLB gives a example.
Q. 2 Describe the characteristics of memory.
hit, the paging mechan ism doesn't perform the List and explain the characteristics of memory. Q. 26 List and explain the different performance
Q. 3
pag ing mechanism characteristics of two level memory.
address translation, else the Q, 4
Explain in details memory hierarchy wilh examples.
·. Page Table( performs the address translation . Q, 5 Q . 27 Write a short note on direct mapping technique.
Explain memory hierarchy.
-Base Register
Segmentation : Explain fully associative mapping technique.
5.9.2 Q, 5 Q, 28
Compare SRAM and ORAM.
Page table . examp le two way set associative
Explain with
' '~ "' , ~- , ;,l~a\' ;;;?, Q, 7
Q. 29
Fig . 5.9.2 : Paging mechanism llJ.ii@MW+iMii•isU-:.' ~---. .. . ., .. . . . /!'/!;:·,• Interface 8 KB EPROM and 4 KB RAM to a mapping technique.

The page number is checked for its presence in the .Q. 1 De~cribe meir\~ry' ~;e~i~tio·~:i~-~~~-A~i~f;• o.a
processor with 16-bit address and S-bit data bus.
Q. 30
t ssociative cache consists of 64 blocks
A block se a ts The main memory contains
how addr.e ss tran'si~tion•-is Cpert:o r.med,,Jrii: ~11'\!1-~ . What are the types of ROM ?
d. 'ded in 4 block se •
main memory by comparing the entry for each page
in the page table.
- ·m,i'~o}f,,.i :- _,. /S::c.···yfo~ ~t;~?f&M41#1 Q, g . a netic as well as
IVI
4096 blocks, eac
h 128 words of 16 bit length.

Explain various types of ROM · M 9 there in main memory

1. How many bits are
Segmentation refers to logical division of the main optical.
If the page is present the w ord required is read from address ?
memory so as to give modular storage mechanism Q. 10
the page in the main memory. Explain the different allocation policies. bits are there in cache memory
and multitasking . 2. How many t and word fields) ?
Q. 11
What are elements of cache design
? Explain in
address (tag, se w TtdlKnowlffl•
y 1>utillc~t1o~s
detail.
v
~
TecllKnowled~~
P obll CJtlO
 •
•

a. 31
DLC O&A (Sem . 111 / Com p. / MU)

Writ e short notes on inter1eav

ed memory and
5-38

a. 38
- Merf 'oq

Explain vJrW al memory with referen<;

(H3a "l12.at.,

e t') rnerror/
~
asso ciative mem ory. hierarchy , segments and pages.

a . 32 Wha t is asso ciative memory ? a. Explain in deta ils virtu al memory. segm
39 entation ar,1
pagi ng .
a . 33 Exp lain setassociative and associative cache
map ping techniqu es. a. 40 What is virtu al memory ?

Q . 34 Exp lain the interleaved memory. a. 41 What is TLB ? Expl ain wor1<ing -Of TLB
.
0 . 35 Exp lain the pag ing mechani sm. a. 42 Explain virtual memory.
0 . 36 Wha t is the use of translational look a. 43 What is segmenta tion ?
aside buffer ?
0 . 37 Wha t is virtual mem ory ?

:lUO

I
I
1

- - - - -- - - - - - -·- - - - - - - -
- -- - - -- -- -- ~ --.-.- ,-tdl-l-UI;;; ;;
PlJlJI I C , t. 10 (\~