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Bala Kumar Mano
FPGA Programming A VLSI Student · 4y Follow 5 more Spaces
What is the design flow in VLSI?
Hardware Description Upvote 5 more good pieces
A Design Flow in VLSI is the sequence of processes/steps involved in the of content
Languages (HDL)
making of an Integrated Circuit.
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The design flow for a digital IC and an analog IC is completely different. And also
for an FPGA based digital design, the flow is different from that of an ASIC. Add 3 credentials about
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Digital IC Design Flow - Semi-custom Standard Cell based ASIC Design study
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Majority of the designs follow this design flow only. Here, the basic building Answer a question
Field Programmable
Gate Arrays (FPGAs) blocks of a digital design such as combinational logic gates (NOT, AND, OR,
NAND, AND-OR-INVERT, OR-AND-INVERT, multiplexers, adders), sequential cells Spaces to follow
ASIC Design (Flip-flops, Scan flip-flops, latches) and special cells (tie cells, delay cells, filler
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cells) are custom designed (like analog design), verified, characterized and later
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Verilog used for the design of larger circuits. This pre-designed and pre-verified library of
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Step 1: Design Specification Here you will get everything
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Questions The specification for an IC to be designed may come from a customer A who has
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Step 2: Architectural Design
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architecture for the design. By architecture I mean something like this. practice,Electrical…
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Then the detailed specifications for each of the sub-blocks are also derived from
the top-level specifications.
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Step 3: RTL Design 3
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Now the RTL Design team comes into the picture and the partitioned designed is
conversation.
given to them. The sub-blocks are designed by RTL designers by using a HDL
such as Verilog/SystemVerilog. The whole design is modeled at a higher level of
abstraction using mixed style of modelling (behavioral, data-flow and structural). New message

Step 4: Functional Verification

The functional verification happens in parallel with the RTL design where the
verification team develops the verification environment using a HVL such as
SystemVerilog. In simple words, the code to check whether the RTL Design code
does its functionality correctly is developed by the verification engineers. Once
the RTL design is complete, the design is verified for correct functionality by
functional verification. In case of any errors, the design code is corrected and re-
verified.

Step 5: Logic Synthesis

Logic Synthesis is the process of conversion the RTL code into gate-level netlist.
The RTL design code once verified to be sufficiently bug-free and functioning as
per the requirement, it is given to a logic synthesizer CAD tool which converts the
code into a list of ports, standard cells, their pins and the interconnections
between them (gate-level netlist). Any pre-synthesized or custom designed
macros are also included with the RTL code.

Step 6: Design-For-Test

This step makes certain changes to the obtained netlist from the synthesis tool
which will later aid in applying tests to verify the hardware.

Step 7: Logical Equivalency Checking

We have a RTL code which is verified to the required extent during functional
verification. We also have a gate-level netlist which is yet to be verified and DFT
has made some changes to our netlist as well. To again perform functional
verification for this netlist is a tiresome task. So a better and faster method where
the RTL code and gate-level netlist are compared by reducing both of them to
boolean equations and equating them to verify the gate-level netlist is
performed. This is logical equivalency checking and if both prove to be equal
then our gate-level netlist is good to go.

Step 8: Pre-layout Static Timing Analysis

Since our functionality is verified, now it’s time to verify if the design operates at
the required speed. This step exhaustively checks every timing path in the design
for any setup and hold violations when the clock operates at the specified
frequency. In case of any violations, it has be fixed before the design signs off to
the back-end. Front-end part of the design ends here.

Step 9: Floor Planning and Power Planning

The required area of the chip die, the core area within the die where it is
permitted to place the synthesized design, area for blockages where no cell
should be place etc are determined in floor planning. In the Power Planning, how
the power (VDD and GND) is to be routed to the whole design is decided.

Step 10: Placement

Now, the actual locations of the instances of the standard cells to be placed in
the core area of the die is determined for the entire design.
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Step 11: Clock-Tree Synthesis

The primary goal of this step is to ensure that the active edge of the clock signal
reaches every flip-flop in the design at the same instant.

Step 12: Global Routing

The global routing determines the paths through which the cells are to be
connected on a 2D plane.
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Step 13: Detailed Routing 3
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The detailed routing determines the exact path the interconnections take
conversation.
through a 3D space through various metal layers and vias along the path chosen
by global routing.
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Step 14: Physical Verification and RC Extraction

The placed and routed design is checked for the presence of any Design Rule
violations (DRC - If the layout meets every design rule given by the foundry for
the given technology), Layout Vs Schematic (LVS) mis-matches, Electrical Rule
violations (ERC), XOR check, Antenna Check etc. The RC parasitics for all the
components in the design are extracted.

Step 14: Post Layout Static Timing Analysis

Now, with all the parasitics extracted and the actual clock parameters, wire and
cell delays known, the STA is performed and the design is again verified for
timing correctness exhaustively. It is to be noted that STA is usually performed at
several stages during the back-end design flow which is consolidated as a single
step here. Back-end design ends here.

Step 15: GDSII generation

The GDSII (Graphic Database System for Information Interchange) is a format

which is understood and used by the foundry for fabrication of an IC. After the
back-end flow, the GDSII stream is generated from the final layout and taped out
to the foundry.

Step 16: Post-Silicon Validation and Testing

Once the chips are manufactured, each of the chips is again tested for presence
or absence of any possible faults during the fabrication process. The chips are
validated against the specifications given by the customer whether all the specs
are met or not. The chips which turn out to be fault-free and meeting all the
specs, come to the market.
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